hw/arm/exynos4210.c

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include "hw/boards.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/arm/arm.h"
  28 #include "hw/loader.h"
  29 #include "hw/arm/exynos4210.h"
  30 #include "hw/usb/hcd-ehci.h"
  31
  32 #define EXYNOS4210_CHIPID_ADDR         0x10000000
  33
  34 /* PWM */
  35 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  36
  37 /* RTC */
  38 #define EXYNOS4210_RTC_BASE_ADDR       0x10070000
  39
  40 /* MCT */
  41 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  42
  43 /* I2C */
  44 #define EXYNOS4210_I2C_SHIFT           0x00010000
  45 #define EXYNOS4210_I2C_BASE_ADDR       0x13860000
  46 /* Interrupt Group of External Interrupt Combiner for I2C */
  47 #define EXYNOS4210_I2C_INTG            27
  48 #define EXYNOS4210_HDMI_INTG           16
  49
  50 /* UART's definitions */
  51 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  52 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  53 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  54 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  55 #define EXYNOS4210_UART0_FIFO_SIZE     256
  56 #define EXYNOS4210_UART1_FIFO_SIZE     64
  57 #define EXYNOS4210_UART2_FIFO_SIZE     16
  58 #define EXYNOS4210_UART3_FIFO_SIZE     16
  59 /* Interrupt Group of External Interrupt Combiner for UART */
  60 #define EXYNOS4210_UART_INT_GRP        26
  61
  62 /* External GIC */
  63 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  64 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  65
  66 /* Combiner */
  67 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  68 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  69
  70 /* PMU SFR base address */
  71 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  72
  73 /* Display controllers (FIMD) */
  74 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  75
  76 /* EHCI */
  77 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
  78
  79 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  80                                     0x09, 0x00, 0x00, 0x00 };
  81
  82 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
  83                                                unsigned size)
  84 {
  85     assert(offset < sizeof(chipid_and_omr));
  86     return chipid_and_omr[offset];
  87 }
  88
  89 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
  90                                             uint64_t value, unsigned size)
  91 {
  92     return;
  93 }
  94
  95 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
  96     .read = exynos4210_chipid_and_omr_read,
  97     .write = exynos4210_chipid_and_omr_write,
  98     .endianness = DEVICE_NATIVE_ENDIAN,
  99     .impl = {
 100         .max_access_size = 1,
 101     }
 102 };
 103
 104 void exynos4210_write_secondary(ARMCPU *cpu,
 105         const struct arm_boot_info *info)
 106 {
 107     int n;
 108     uint32_t smpboot[] = {
 109         0xe59f3034, /* ldr r3, External gic_cpu_if */
 110         0xe59f2034, /* ldr r2, Internal gic_cpu_if */
 111         0xe59f0034, /* ldr r0, startaddr */
 112         0xe3a01001, /* mov r1, #1 */
 113         0xe5821000, /* str r1, [r2] */
 114         0xe5831000, /* str r1, [r3] */
 115         0xe3a010ff, /* mov r1, #0xff */
 116         0xe5821004, /* str r1, [r2, #4] */
 117         0xe5831004, /* str r1, [r3, #4] */
 118         0xf57ff04f, /* dsb */
 119         0xe320f003, /* wfi */
 120         0xe5901000, /* ldr     r1, [r0] */
 121         0xe1110001, /* tst     r1, r1 */
 122         0x0afffffb, /* beq     <wfi> */
 123         0xe12fff11, /* bx      r1 */
 124         EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
 125         0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
 126         0           /* bootreg: Boot register address is held here */
 127     };
 128     smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
 129     smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
 130     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
 131         smpboot[n] = tswap32(smpboot[n]);
 132     }
 133     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
 134                        info->smp_loader_start);
 135 }
 136
 137 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
 138         unsigned long ram_size)
 139 {
 140     int i, n;
 141     Exynos4210State *s = g_new(Exynos4210State, 1);
 142     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
 143     unsigned long mem_size;
 144     DeviceState *dev;
 145     SysBusDevice *busdev;
 146     ObjectClass *cpu_oc;
 147
 148     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
 149     assert(cpu_oc);
 150
 151     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 152         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 153         Error *err = NULL;
 154
 155         /* By default A9 CPUs have EL3 enabled.  This board does not currently
 156          * support EL3 so the CPU EL3 property is disabled before realization.
 157          */
 158         if (object_property_find(cpuobj, "has_el3", NULL)) {
 159             object_property_set_bool(cpuobj, false, "has_el3", &err);
 160             if (err) {
 161                 error_report_err(err);
 162                 exit(1);
 163             }
 164         }
 165
 166         s->cpu[n] = ARM_CPU(cpuobj);
 167         object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
 168                                 "reset-cbar", &error_abort);
 169         object_property_set_bool(cpuobj, true, "realized", &err);
 170         if (err) {
 171             error_report_err(err);
 172             exit(1);
 173         }
 174     }
 175
 176     /*** IRQs ***/
 177
 178     s->irq_table = exynos4210_init_irq(&s->irqs);
 179
 180     /* IRQ Gate */
 181     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
 182         dev = qdev_create(NULL, "exynos4210.irq_gate");
 183         qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
 184         qdev_init_nofail(dev);
 185         /* Get IRQ Gate input in gate_irq */
 186         for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 187             gate_irq[i][n] = qdev_get_gpio_in(dev, n);
 188         }
 189         busdev = SYS_BUS_DEVICE(dev);
 190
 191         /* Connect IRQ Gate output to CPU's IRQ line */
 192         sysbus_connect_irq(busdev, 0,
 193                            qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
 194     }
 195
 196     /* Private memory region and Internal GIC */
 197     dev = qdev_create(NULL, "a9mpcore_priv");
 198     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 199     qdev_init_nofail(dev);
 200     busdev = SYS_BUS_DEVICE(dev);
 201     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 202     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 203         sysbus_connect_irq(busdev, n, gate_irq[n][0]);
 204     }
 205     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 206         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 207     }
 208
 209     /* Cache controller */
 210     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 211
 212     /* External GIC */
 213     dev = qdev_create(NULL, "exynos4210.gic");
 214     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 215     qdev_init_nofail(dev);
 216     busdev = SYS_BUS_DEVICE(dev);
 217     /* Map CPU interface */
 218     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 219     /* Map Distributer interface */
 220     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 221     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 222         sysbus_connect_irq(busdev, n, gate_irq[n][1]);
 223     }
 224     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 225         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 226     }
 227
 228     /* Internal Interrupt Combiner */
 229     dev = qdev_create(NULL, "exynos4210.combiner");
 230     qdev_init_nofail(dev);
 231     busdev = SYS_BUS_DEVICE(dev);
 232     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 233         sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 234     }
 235     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 236     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 237
 238     /* External Interrupt Combiner */
 239     dev = qdev_create(NULL, "exynos4210.combiner");
 240     qdev_prop_set_uint32(dev, "external", 1);
 241     qdev_init_nofail(dev);
 242     busdev = SYS_BUS_DEVICE(dev);
 243     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 244         sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 245     }
 246     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 247     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 248
 249     /* Initialize board IRQs. */
 250     exynos4210_init_board_irqs(&s->irqs);
 251
 252     /*** Memory ***/
 253
 254     /* Chip-ID and OMR */
 255     memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
 256         NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
 257     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 258                                 &s->chipid_mem);
 259
 260     /* Internal ROM */
 261     memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
 262                            EXYNOS4210_IROM_SIZE, &error_fatal);
 263     vmstate_register_ram_global(&s->irom_mem);
 264     memory_region_set_readonly(&s->irom_mem, true);
 265     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 266                                 &s->irom_mem);
 267     /* mirror of iROM */
 268     memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
 269                              &s->irom_mem,
 270                              0,
 271                              EXYNOS4210_IROM_SIZE);
 272     memory_region_set_readonly(&s->irom_alias_mem, true);
 273     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 274                                 &s->irom_alias_mem);
 275
 276     /* Internal RAM */
 277     memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
 278                            EXYNOS4210_IRAM_SIZE, &error_fatal);
 279     vmstate_register_ram_global(&s->iram_mem);
 280     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 281                                 &s->iram_mem);
 282
 283     /* DRAM */
 284     mem_size = ram_size;
 285     if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 286         memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
 287                 mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
 288         vmstate_register_ram_global(&s->dram1_mem);
 289         memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 290                 &s->dram1_mem);
 291         mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 292     }
 293     memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
 294                            &error_fatal);
 295     vmstate_register_ram_global(&s->dram0_mem);
 296     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 297             &s->dram0_mem);
 298
 299    /* PMU.
 300     * The only reason of existence at the moment is that secondary CPU boot
 301     * loader uses PMU INFORM5 register as a holding pen.
 302     */
 303     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 304
 305     /* PWM */
 306     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 307                           s->irq_table[exynos4210_get_irq(22, 0)],
 308                           s->irq_table[exynos4210_get_irq(22, 1)],
 309                           s->irq_table[exynos4210_get_irq(22, 2)],
 310                           s->irq_table[exynos4210_get_irq(22, 3)],
 311                           s->irq_table[exynos4210_get_irq(22, 4)],
 312                           NULL);
 313     /* RTC */
 314     sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
 315                           s->irq_table[exynos4210_get_irq(23, 0)],
 316                           s->irq_table[exynos4210_get_irq(23, 1)],
 317                           NULL);
 318
 319     /* Multi Core Timer */
 320     dev = qdev_create(NULL, "exynos4210.mct");
 321     qdev_init_nofail(dev);
 322     busdev = SYS_BUS_DEVICE(dev);
 323     for (n = 0; n < 4; n++) {
 324         /* Connect global timer interrupts to Combiner gpio_in */
 325         sysbus_connect_irq(busdev, n,
 326                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 327     }
 328     /* Connect local timer interrupts to Combiner gpio_in */
 329     sysbus_connect_irq(busdev, 4,
 330             s->irq_table[exynos4210_get_irq(51, 0)]);
 331     sysbus_connect_irq(busdev, 5,
 332             s->irq_table[exynos4210_get_irq(35, 3)]);
 333     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 334
 335     /*** I2C ***/
 336     for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
 337         uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
 338         qemu_irq i2c_irq;
 339
 340         if (n < 8) {
 341             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
 342         } else {
 343             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
 344         }
 345
 346         dev = qdev_create(NULL, "exynos4210.i2c");
 347         qdev_init_nofail(dev);
 348         busdev = SYS_BUS_DEVICE(dev);
 349         sysbus_connect_irq(busdev, 0, i2c_irq);
 350         sysbus_mmio_map(busdev, 0, addr);
 351         s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 352     }
 353
 354
 355     /*** UARTs ***/
 356     exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 357                            EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 358                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 359
 360     exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 361                            EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 362                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 363
 364     exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 365                            EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 366                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 367
 368     exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 369                            EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 370                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 371
 372     /*** Display controller (FIMD) ***/
 373     sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 374             s->irq_table[exynos4210_get_irq(11, 0)],
 375             s->irq_table[exynos4210_get_irq(11, 1)],
 376             s->irq_table[exynos4210_get_irq(11, 2)],
 377             NULL);
 378
 379     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
 380             s->irq_table[exynos4210_get_irq(28, 3)]);
 381
 382     return s;
 383 }