1 /* Support for generating ACPI tables and passing them to Guests
3 * ARM virt ACPI generation
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
9 * Author: Michael S. Tsirkin <mst@redhat.com>
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
33 #include "hw/core/cpu.h"
34 #include "target/arm/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/generic_event_device.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/pci/pcie_host.h"
46 #include "hw/pci/pci.h"
47 #include "hw/pci/pci_bus.h"
48 #include "hw/pci-host/gpex.h"
49 #include "hw/arm/virt.h"
50 #include "hw/mem/nvdimm.h"
51 #include "hw/platform-bus.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "sysemu/tpm.h"
56 #include "migration/vmstate.h"
57 #include "hw/acpi/ghes.h"
58 #include "hw/acpi/viot.h"
60 #define ARM_SPI_BASE 32
62 #define ACPI_BUILD_TABLE_SIZE 0x20000
64 static void acpi_dsdt_add_cpus(Aml
*scope
, VirtMachineState
*vms
)
66 MachineState
*ms
= MACHINE(vms
);
69 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
70 Aml
*dev
= aml_device("C%.03X", i
);
71 aml_append(dev
, aml_name_decl("_HID", aml_string("ACPI0007")));
72 aml_append(dev
, aml_name_decl("_UID", aml_int(i
)));
73 aml_append(scope
, dev
);
77 static void acpi_dsdt_add_uart(Aml
*scope
, const MemMapEntry
*uart_memmap
,
80 Aml
*dev
= aml_device("COM0");
81 aml_append(dev
, aml_name_decl("_HID", aml_string("ARMH0011")));
82 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
84 Aml
*crs
= aml_resource_template();
85 aml_append(crs
, aml_memory32_fixed(uart_memmap
->base
,
86 uart_memmap
->size
, AML_READ_WRITE
));
88 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
89 AML_EXCLUSIVE
, &uart_irq
, 1));
90 aml_append(dev
, aml_name_decl("_CRS", crs
));
92 aml_append(scope
, dev
);
95 static void acpi_dsdt_add_fw_cfg(Aml
*scope
, const MemMapEntry
*fw_cfg_memmap
)
97 Aml
*dev
= aml_device("FWCF");
98 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
99 /* device present, functioning, decoding, not shown in UI */
100 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
101 aml_append(dev
, aml_name_decl("_CCA", aml_int(1)));
103 Aml
*crs
= aml_resource_template();
104 aml_append(crs
, aml_memory32_fixed(fw_cfg_memmap
->base
,
105 fw_cfg_memmap
->size
, AML_READ_WRITE
));
106 aml_append(dev
, aml_name_decl("_CRS", crs
));
107 aml_append(scope
, dev
);
110 static void acpi_dsdt_add_flash(Aml
*scope
, const MemMapEntry
*flash_memmap
)
113 hwaddr base
= flash_memmap
->base
;
114 hwaddr size
= flash_memmap
->size
/ 2;
116 dev
= aml_device("FLS0");
117 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0015")));
118 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
120 crs
= aml_resource_template();
121 aml_append(crs
, aml_memory32_fixed(base
, size
, AML_READ_WRITE
));
122 aml_append(dev
, aml_name_decl("_CRS", crs
));
123 aml_append(scope
, dev
);
125 dev
= aml_device("FLS1");
126 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0015")));
127 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
128 crs
= aml_resource_template();
129 aml_append(crs
, aml_memory32_fixed(base
+ size
, size
, AML_READ_WRITE
));
130 aml_append(dev
, aml_name_decl("_CRS", crs
));
131 aml_append(scope
, dev
);
134 static void acpi_dsdt_add_virtio(Aml
*scope
,
135 const MemMapEntry
*virtio_mmio_memmap
,
136 uint32_t mmio_irq
, int num
)
138 hwaddr base
= virtio_mmio_memmap
->base
;
139 hwaddr size
= virtio_mmio_memmap
->size
;
142 for (i
= 0; i
< num
; i
++) {
143 uint32_t irq
= mmio_irq
+ i
;
144 Aml
*dev
= aml_device("VR%02u", i
);
145 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0005")));
146 aml_append(dev
, aml_name_decl("_UID", aml_int(i
)));
147 aml_append(dev
, aml_name_decl("_CCA", aml_int(1)));
149 Aml
*crs
= aml_resource_template();
150 aml_append(crs
, aml_memory32_fixed(base
, size
, AML_READ_WRITE
));
152 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
153 AML_EXCLUSIVE
, &irq
, 1));
154 aml_append(dev
, aml_name_decl("_CRS", crs
));
155 aml_append(scope
, dev
);
160 static void acpi_dsdt_add_pci(Aml
*scope
, const MemMapEntry
*memmap
,
161 uint32_t irq
, VirtMachineState
*vms
)
163 int ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
164 struct GPEXConfig cfg
= {
165 .mmio32
= memmap
[VIRT_PCIE_MMIO
],
166 .pio
= memmap
[VIRT_PCIE_PIO
],
167 .ecam
= memmap
[ecam_id
],
172 if (vms
->highmem_mmio
) {
173 cfg
.mmio64
= memmap
[VIRT_HIGH_PCIE_MMIO
];
176 acpi_dsdt_add_gpex(scope
, &cfg
);
179 static void acpi_dsdt_add_gpio(Aml
*scope
, const MemMapEntry
*gpio_memmap
,
182 Aml
*dev
= aml_device("GPO0");
183 aml_append(dev
, aml_name_decl("_HID", aml_string("ARMH0061")));
184 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
186 Aml
*crs
= aml_resource_template();
187 aml_append(crs
, aml_memory32_fixed(gpio_memmap
->base
, gpio_memmap
->size
,
189 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
190 AML_EXCLUSIVE
, &gpio_irq
, 1));
191 aml_append(dev
, aml_name_decl("_CRS", crs
));
193 Aml
*aei
= aml_resource_template();
194 /* Pin 3 for power button */
195 const uint32_t pin_list
[1] = {3};
196 aml_append(aei
, aml_gpio_int(AML_CONSUMER
, AML_EDGE
, AML_ACTIVE_HIGH
,
197 AML_EXCLUSIVE
, AML_PULL_UP
, 0, pin_list
, 1,
199 aml_append(dev
, aml_name_decl("_AEI", aei
));
201 /* _E03 is handle for power button */
202 Aml
*method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
203 aml_append(method
, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE
),
205 aml_append(dev
, method
);
206 aml_append(scope
, dev
);
210 static void acpi_dsdt_add_tpm(Aml
*scope
, VirtMachineState
*vms
)
212 PlatformBusDevice
*pbus
= PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
);
213 hwaddr pbus_base
= vms
->memmap
[VIRT_PLATFORM_BUS
].base
;
214 SysBusDevice
*sbdev
= SYS_BUS_DEVICE(tpm_find());
215 MemoryRegion
*sbdev_mr
;
222 tpm_base
= platform_bus_get_mmio_addr(pbus
, sbdev
, 0);
223 assert(tpm_base
!= -1);
225 tpm_base
+= pbus_base
;
227 sbdev_mr
= sysbus_mmio_get_region(sbdev
, 0);
229 Aml
*dev
= aml_device("TPM0");
230 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
231 aml_append(dev
, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
232 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
234 Aml
*crs
= aml_resource_template();
236 aml_memory32_fixed(tpm_base
,
237 (uint32_t)memory_region_size(sbdev_mr
),
239 aml_append(dev
, aml_name_decl("_CRS", crs
));
240 aml_append(scope
, dev
);
244 #define ID_MAPPING_ENTRY_SIZE 20
245 #define SMMU_V3_ENTRY_SIZE 68
246 #define ROOT_COMPLEX_ENTRY_SIZE 36
247 #define IORT_NODE_OFFSET 48
249 static void build_iort_id_mapping(GArray
*table_data
, uint32_t input_base
,
250 uint32_t id_count
, uint32_t out_ref
)
252 /* Table 4 ID mapping format */
253 build_append_int_noprefix(table_data
, input_base
, 4); /* Input base */
254 build_append_int_noprefix(table_data
, id_count
, 4); /* Number of IDs */
255 build_append_int_noprefix(table_data
, input_base
, 4); /* Output base */
256 build_append_int_noprefix(table_data
, out_ref
, 4); /* Output Reference */
258 build_append_int_noprefix(table_data
, 0 /* Single mapping (disabled) */, 4);
261 struct AcpiIortIdMapping
{
265 typedef struct AcpiIortIdMapping AcpiIortIdMapping
;
267 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
269 iort_host_bridges(Object
*obj
, void *opaque
)
271 GArray
*idmap_blob
= opaque
;
273 if (object_dynamic_cast(obj
, TYPE_PCI_HOST_BRIDGE
)) {
274 PCIBus
*bus
= PCI_HOST_BRIDGE(obj
)->bus
;
276 if (bus
&& !pci_bus_bypass_iommu(bus
)) {
277 int min_bus
, max_bus
;
279 pci_bus_range(bus
, &min_bus
, &max_bus
);
281 AcpiIortIdMapping idmap
= {
282 .input_base
= min_bus
<< 8,
283 .id_count
= (max_bus
- min_bus
+ 1) << 8,
285 g_array_append_val(idmap_blob
, idmap
);
292 static int iort_idmap_compare(gconstpointer a
, gconstpointer b
)
294 AcpiIortIdMapping
*idmap_a
= (AcpiIortIdMapping
*)a
;
295 AcpiIortIdMapping
*idmap_b
= (AcpiIortIdMapping
*)b
;
297 return idmap_a
->input_base
- idmap_b
->input_base
;
301 * Input Output Remapping Table (IORT)
302 * Conforms to "IO Remapping Table System Software on ARM Platforms",
303 * Document number: ARM DEN 0049E.b, Feb 2021
306 build_iort(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
308 int i
, nb_nodes
, rc_mapping_count
;
309 const uint32_t iort_node_offset
= IORT_NODE_OFFSET
;
310 size_t node_size
, smmu_offset
= 0;
311 AcpiIortIdMapping
*idmap
;
313 GArray
*smmu_idmaps
= g_array_new(false, true, sizeof(AcpiIortIdMapping
));
314 GArray
*its_idmaps
= g_array_new(false, true, sizeof(AcpiIortIdMapping
));
316 AcpiTable table
= { .sig
= "IORT", .rev
= 3, .oem_id
= vms
->oem_id
,
317 .oem_table_id
= vms
->oem_table_id
};
318 /* Table 2 The IORT */
319 acpi_table_begin(&table
, table_data
);
321 if (vms
->iommu
== VIRT_IOMMU_SMMUV3
) {
322 AcpiIortIdMapping next_range
= {0};
324 object_child_foreach_recursive(object_get_root(),
325 iort_host_bridges
, smmu_idmaps
);
327 /* Sort the smmu idmap by input_base */
328 g_array_sort(smmu_idmaps
, iort_idmap_compare
);
331 * Split the whole RIDs by mapping from RC to SMMU,
332 * build the ID mapping from RC to ITS directly.
334 for (i
= 0; i
< smmu_idmaps
->len
; i
++) {
335 idmap
= &g_array_index(smmu_idmaps
, AcpiIortIdMapping
, i
);
337 if (next_range
.input_base
< idmap
->input_base
) {
338 next_range
.id_count
= idmap
->input_base
- next_range
.input_base
;
339 g_array_append_val(its_idmaps
, next_range
);
342 next_range
.input_base
= idmap
->input_base
+ idmap
->id_count
;
345 /* Append the last RC -> ITS ID mapping */
346 if (next_range
.input_base
< 0xFFFF) {
347 next_range
.id_count
= 0xFFFF - next_range
.input_base
;
348 g_array_append_val(its_idmaps
, next_range
);
351 nb_nodes
= 3; /* RC, ITS, SMMUv3 */
352 rc_mapping_count
= smmu_idmaps
->len
+ its_idmaps
->len
;
354 nb_nodes
= 2; /* RC, ITS */
355 rc_mapping_count
= 1;
357 /* Number of IORT Nodes */
358 build_append_int_noprefix(table_data
, nb_nodes
, 4);
360 /* Offset to Array of IORT Nodes */
361 build_append_int_noprefix(table_data
, IORT_NODE_OFFSET
, 4);
362 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
364 /* Table 12 ITS Group Format */
365 build_append_int_noprefix(table_data
, 0 /* ITS Group */, 1); /* Type */
366 node_size
= 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
367 build_append_int_noprefix(table_data
, node_size
, 2); /* Length */
368 build_append_int_noprefix(table_data
, 1, 1); /* Revision */
369 build_append_int_noprefix(table_data
, id
++, 4); /* Identifier */
370 build_append_int_noprefix(table_data
, 0, 4); /* Number of ID mappings */
371 build_append_int_noprefix(table_data
, 0, 4); /* Reference to ID Array */
372 build_append_int_noprefix(table_data
, 1, 4); /* Number of ITSs */
373 /* GIC ITS Identifier Array */
374 build_append_int_noprefix(table_data
, 0 /* MADT translation_id */, 4);
376 if (vms
->iommu
== VIRT_IOMMU_SMMUV3
) {
377 int irq
= vms
->irqmap
[VIRT_SMMU
] + ARM_SPI_BASE
;
379 smmu_offset
= table_data
->len
- table
.table_offset
;
380 /* Table 9 SMMUv3 Format */
381 build_append_int_noprefix(table_data
, 4 /* SMMUv3 */, 1); /* Type */
382 node_size
= SMMU_V3_ENTRY_SIZE
+ ID_MAPPING_ENTRY_SIZE
;
383 build_append_int_noprefix(table_data
, node_size
, 2); /* Length */
384 build_append_int_noprefix(table_data
, 4, 1); /* Revision */
385 build_append_int_noprefix(table_data
, id
++, 4); /* Identifier */
386 build_append_int_noprefix(table_data
, 1, 4); /* Number of ID mappings */
387 /* Reference to ID Array */
388 build_append_int_noprefix(table_data
, SMMU_V3_ENTRY_SIZE
, 4);
390 build_append_int_noprefix(table_data
, vms
->memmap
[VIRT_SMMU
].base
, 8);
392 build_append_int_noprefix(table_data
, 1 /* COHACC Override */, 4);
393 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
394 build_append_int_noprefix(table_data
, 0, 8); /* VATOS address */
396 build_append_int_noprefix(table_data
, 0 /* Generic SMMU-v3 */, 4);
397 build_append_int_noprefix(table_data
, irq
, 4); /* Event */
398 build_append_int_noprefix(table_data
, irq
+ 1, 4); /* PRI */
399 build_append_int_noprefix(table_data
, irq
+ 3, 4); /* GERR */
400 build_append_int_noprefix(table_data
, irq
+ 2, 4); /* Sync */
401 build_append_int_noprefix(table_data
, 0, 4); /* Proximity domain */
402 /* DeviceID mapping index (ignored since interrupts are GSIV based) */
403 build_append_int_noprefix(table_data
, 0, 4);
405 /* output IORT node is the ITS group node (the first node) */
406 build_iort_id_mapping(table_data
, 0, 0xFFFF, IORT_NODE_OFFSET
);
409 /* Table 17 Root Complex Node */
410 build_append_int_noprefix(table_data
, 2 /* Root complex */, 1); /* Type */
411 node_size
= ROOT_COMPLEX_ENTRY_SIZE
+
412 ID_MAPPING_ENTRY_SIZE
* rc_mapping_count
;
413 build_append_int_noprefix(table_data
, node_size
, 2); /* Length */
414 build_append_int_noprefix(table_data
, 3, 1); /* Revision */
415 build_append_int_noprefix(table_data
, id
++, 4); /* Identifier */
416 /* Number of ID mappings */
417 build_append_int_noprefix(table_data
, rc_mapping_count
, 4);
418 /* Reference to ID Array */
419 build_append_int_noprefix(table_data
, ROOT_COMPLEX_ENTRY_SIZE
, 4);
421 /* Table 14 Memory access properties */
422 /* CCA: Cache Coherent Attribute */
423 build_append_int_noprefix(table_data
, 1 /* fully coherent */, 4);
424 build_append_int_noprefix(table_data
, 0, 1); /* AH: Note Allocation Hints */
425 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
426 /* Table 15 Memory Access Flags */
427 build_append_int_noprefix(table_data
, 0x3 /* CCA = CPM = DACS = 1 */, 1);
429 build_append_int_noprefix(table_data
, 0, 4); /* ATS Attribute */
430 /* MCFG pci_segment */
431 build_append_int_noprefix(table_data
, 0, 4); /* PCI Segment number */
433 /* Memory address size limit */
434 build_append_int_noprefix(table_data
, 64, 1);
436 build_append_int_noprefix(table_data
, 0, 3); /* Reserved */
438 /* Output Reference */
439 if (vms
->iommu
== VIRT_IOMMU_SMMUV3
) {
440 AcpiIortIdMapping
*range
;
442 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
443 for (i
= 0; i
< smmu_idmaps
->len
; i
++) {
444 range
= &g_array_index(smmu_idmaps
, AcpiIortIdMapping
, i
);
445 /* output IORT node is the smmuv3 node */
446 build_iort_id_mapping(table_data
, range
->input_base
,
447 range
->id_count
, smmu_offset
);
450 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */
451 for (i
= 0; i
< its_idmaps
->len
; i
++) {
452 range
= &g_array_index(its_idmaps
, AcpiIortIdMapping
, i
);
453 /* output IORT node is the ITS group node (the first node) */
454 build_iort_id_mapping(table_data
, range
->input_base
,
455 range
->id_count
, iort_node_offset
);
458 /* output IORT node is the ITS group node (the first node) */
459 build_iort_id_mapping(table_data
, 0, 0xFFFF, IORT_NODE_OFFSET
);
462 acpi_table_end(linker
, &table
);
463 g_array_free(smmu_idmaps
, true);
464 g_array_free(its_idmaps
, true);
468 * Serial Port Console Redirection Table (SPCR)
472 build_spcr(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
474 AcpiTable table
= { .sig
= "SPCR", .rev
= 2, .oem_id
= vms
->oem_id
,
475 .oem_table_id
= vms
->oem_table_id
};
477 acpi_table_begin(&table
, table_data
);
480 build_append_int_noprefix(table_data
, 3, 1); /* ARM PL011 UART */
481 build_append_int_noprefix(table_data
, 0, 3); /* Reserved */
483 build_append_gas(table_data
, AML_AS_SYSTEM_MEMORY
, 8, 0, 1,
484 vms
->memmap
[VIRT_UART
].base
);
486 build_append_int_noprefix(table_data
,
487 (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
488 build_append_int_noprefix(table_data
, 0, 1); /* IRQ */
489 /* Global System Interrupt */
490 build_append_int_noprefix(table_data
,
491 vms
->irqmap
[VIRT_UART
] + ARM_SPI_BASE
, 4);
492 build_append_int_noprefix(table_data
, 3 /* 9600 */, 1); /* Baud Rate */
493 build_append_int_noprefix(table_data
, 0 /* No Parity */, 1); /* Parity */
495 build_append_int_noprefix(table_data
, 1 /* 1 Stop bit */, 1);
497 build_append_int_noprefix(table_data
,
498 (1 << 1) /* RTS/CTS hardware flow control */, 1);
500 build_append_int_noprefix(table_data
, 0 /* VT100 */, 1);
501 build_append_int_noprefix(table_data
, 0, 1); /* Language */
503 build_append_int_noprefix(table_data
, 0xffff /* not a PCI device*/, 2);
505 build_append_int_noprefix(table_data
, 0xffff /* not a PCI device*/, 2);
506 build_append_int_noprefix(table_data
, 0, 1); /* PCI Bus Number */
507 build_append_int_noprefix(table_data
, 0, 1); /* PCI Device Number */
508 build_append_int_noprefix(table_data
, 0, 1); /* PCI Function Number */
509 build_append_int_noprefix(table_data
, 0, 4); /* PCI Flags */
510 build_append_int_noprefix(table_data
, 0, 1); /* PCI Segment */
511 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
513 acpi_table_end(linker
, &table
);
517 * ACPI spec, Revision 5.1
518 * 5.2.16 System Resource Affinity Table (SRAT)
521 build_srat(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
525 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
526 MachineState
*ms
= MACHINE(vms
);
527 const CPUArchIdList
*cpu_list
= mc
->possible_cpu_arch_ids(ms
);
528 AcpiTable table
= { .sig
= "SRAT", .rev
= 3, .oem_id
= vms
->oem_id
,
529 .oem_table_id
= vms
->oem_table_id
};
531 acpi_table_begin(&table
, table_data
);
532 build_append_int_noprefix(table_data
, 1, 4); /* Reserved */
533 build_append_int_noprefix(table_data
, 0, 8); /* Reserved */
535 for (i
= 0; i
< cpu_list
->len
; ++i
) {
536 uint32_t nodeid
= cpu_list
->cpus
[i
].props
.node_id
;
538 * 5.2.16.4 GICC Affinity Structure
540 build_append_int_noprefix(table_data
, 3, 1); /* Type */
541 build_append_int_noprefix(table_data
, 18, 1); /* Length */
542 build_append_int_noprefix(table_data
, nodeid
, 4); /* Proximity Domain */
543 build_append_int_noprefix(table_data
, i
, 4); /* ACPI Processor UID */
544 /* Flags, Table 5-76 */
545 build_append_int_noprefix(table_data
, 1 /* Enabled */, 4);
546 build_append_int_noprefix(table_data
, 0, 4); /* Clock Domain */
549 mem_base
= vms
->memmap
[VIRT_MEM
].base
;
550 for (i
= 0; i
< ms
->numa_state
->num_nodes
; ++i
) {
551 if (ms
->numa_state
->nodes
[i
].node_mem
> 0) {
552 build_srat_memory(table_data
, mem_base
,
553 ms
->numa_state
->nodes
[i
].node_mem
, i
,
554 MEM_AFFINITY_ENABLED
);
555 mem_base
+= ms
->numa_state
->nodes
[i
].node_mem
;
559 if (ms
->nvdimms_state
->is_enabled
) {
560 nvdimm_build_srat(table_data
);
563 if (ms
->device_memory
) {
564 build_srat_memory(table_data
, ms
->device_memory
->base
,
565 memory_region_size(&ms
->device_memory
->mr
),
566 ms
->numa_state
->num_nodes
- 1,
567 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
570 acpi_table_end(linker
, &table
);
574 * ACPI spec, Revision 5.1
575 * 5.2.24 Generic Timer Description Table (GTDT)
578 build_gtdt(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
580 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
582 * Table 5-117 Flag Definitions
583 * set only "Timer interrupt Mode" and assume "Timer Interrupt
584 * polarity" bit as '0: Interrupt is Active high'
586 uint32_t irqflags
= vmc
->claim_edge_triggered_timers
?
587 1 : /* Interrupt is Edge triggered */
588 0; /* Interrupt is Level triggered */
589 AcpiTable table
= { .sig
= "GTDT", .rev
= 2, .oem_id
= vms
->oem_id
,
590 .oem_table_id
= vms
->oem_table_id
};
592 acpi_table_begin(&table
, table_data
);
594 /* CntControlBase Physical Address */
595 build_append_int_noprefix(table_data
, 0xFFFFFFFFFFFFFFFF, 8);
596 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
598 * FIXME: clarify comment:
599 * The interrupt values are the same with the device tree when adding 16
601 /* Secure EL1 timer GSIV */
602 build_append_int_noprefix(table_data
, ARCH_TIMER_S_EL1_IRQ
+ 16, 4);
603 /* Secure EL1 timer Flags */
604 build_append_int_noprefix(table_data
, irqflags
, 4);
605 /* Non-Secure EL1 timer GSIV */
606 build_append_int_noprefix(table_data
, ARCH_TIMER_NS_EL1_IRQ
+ 16, 4);
607 /* Non-Secure EL1 timer Flags */
608 build_append_int_noprefix(table_data
, irqflags
|
609 1UL << 2, /* Always-on Capability */
611 /* Virtual timer GSIV */
612 build_append_int_noprefix(table_data
, ARCH_TIMER_VIRT_IRQ
+ 16, 4);
613 /* Virtual Timer Flags */
614 build_append_int_noprefix(table_data
, irqflags
, 4);
615 /* Non-Secure EL2 timer GSIV */
616 build_append_int_noprefix(table_data
, ARCH_TIMER_NS_EL2_IRQ
+ 16, 4);
617 /* Non-Secure EL2 timer Flags */
618 build_append_int_noprefix(table_data
, irqflags
, 4);
619 /* CntReadBase Physical address */
620 build_append_int_noprefix(table_data
, 0xFFFFFFFFFFFFFFFF, 8);
621 /* Platform Timer Count */
622 build_append_int_noprefix(table_data
, 0, 4);
623 /* Platform Timer Offset */
624 build_append_int_noprefix(table_data
, 0, 4);
626 acpi_table_end(linker
, &table
);
629 /* Debug Port Table 2 (DBG2) */
631 build_dbg2(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
633 AcpiTable table
= { .sig
= "DBG2", .rev
= 0, .oem_id
= vms
->oem_id
,
634 .oem_table_id
= vms
->oem_table_id
};
635 int dbg2devicelength
;
636 const char name
[] = "COM0";
637 const int namespace_length
= sizeof(name
);
639 acpi_table_begin(&table
, table_data
);
641 dbg2devicelength
= 22 + /* BaseAddressRegister[] offset */
642 12 + /* BaseAddressRegister[] */
643 4 + /* AddressSize[] */
644 namespace_length
/* NamespaceString[] */;
646 /* OffsetDbgDeviceInfo */
647 build_append_int_noprefix(table_data
, 44, 4);
648 /* NumberDbgDeviceInfo */
649 build_append_int_noprefix(table_data
, 1, 4);
651 /* Table 2. Debug Device Information structure format */
652 build_append_int_noprefix(table_data
, 0, 1); /* Revision */
653 build_append_int_noprefix(table_data
, dbg2devicelength
, 2); /* Length */
654 /* NumberofGenericAddressRegisters */
655 build_append_int_noprefix(table_data
, 1, 1);
656 /* NameSpaceStringLength */
657 build_append_int_noprefix(table_data
, namespace_length
, 2);
658 build_append_int_noprefix(table_data
, 38, 2); /* NameSpaceStringOffset */
659 build_append_int_noprefix(table_data
, 0, 2); /* OemDataLength */
660 /* OemDataOffset (0 means no OEM data) */
661 build_append_int_noprefix(table_data
, 0, 2);
664 build_append_int_noprefix(table_data
, 0x8000 /* Serial */, 2);
666 build_append_int_noprefix(table_data
, 0x3 /* ARM PL011 UART */, 2);
667 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
668 /* BaseAddressRegisterOffset */
669 build_append_int_noprefix(table_data
, 22, 2);
670 /* AddressSizeOffset */
671 build_append_int_noprefix(table_data
, 34, 2);
673 /* BaseAddressRegister[] */
674 build_append_gas(table_data
, AML_AS_SYSTEM_MEMORY
, 8, 0, 1,
675 vms
->memmap
[VIRT_UART
].base
);
678 build_append_int_noprefix(table_data
,
679 vms
->memmap
[VIRT_UART
].size
, 4);
681 /* NamespaceString[] */
682 g_array_append_vals(table_data
, name
, namespace_length
);
684 acpi_table_end(linker
, &table
);
688 * ACPI spec, Revision 5.1 Errata A
689 * 5.2.12 Multiple APIC Description Table (MADT)
691 static void build_append_gicr(GArray
*table_data
, uint64_t base
, uint32_t size
)
693 build_append_int_noprefix(table_data
, 0xE, 1); /* Type */
694 build_append_int_noprefix(table_data
, 16, 1); /* Length */
695 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
696 /* Discovery Range Base Addres */
697 build_append_int_noprefix(table_data
, base
, 8);
698 build_append_int_noprefix(table_data
, size
, 4); /* Discovery Range Length */
702 build_madt(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
705 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
706 const MemMapEntry
*memmap
= vms
->memmap
;
707 AcpiTable table
= { .sig
= "APIC", .rev
= 3, .oem_id
= vms
->oem_id
,
708 .oem_table_id
= vms
->oem_table_id
};
710 acpi_table_begin(&table
, table_data
);
711 /* Local Interrupt Controller Address */
712 build_append_int_noprefix(table_data
, 0, 4);
713 build_append_int_noprefix(table_data
, 0, 4); /* Flags */
715 /* 5.2.12.15 GIC Distributor Structure */
716 build_append_int_noprefix(table_data
, 0xC, 1); /* Type */
717 build_append_int_noprefix(table_data
, 24, 1); /* Length */
718 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
719 build_append_int_noprefix(table_data
, 0, 4); /* GIC ID */
720 /* Physical Base Address */
721 build_append_int_noprefix(table_data
, memmap
[VIRT_GIC_DIST
].base
, 8);
722 build_append_int_noprefix(table_data
, 0, 4); /* System Vector Base */
724 build_append_int_noprefix(table_data
, vms
->gic_version
, 1);
725 build_append_int_noprefix(table_data
, 0, 3); /* Reserved */
727 for (i
= 0; i
< MACHINE(vms
)->smp
.cpus
; i
++) {
728 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(i
));
729 uint64_t physical_base_address
= 0, gich
= 0, gicv
= 0;
730 uint32_t vgic_interrupt
= vms
->virt
? PPI(ARCH_GIC_MAINT_IRQ
) : 0;
731 uint32_t pmu_interrupt
= arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ?
732 PPI(VIRTUAL_PMU_IRQ
) : 0;
734 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
735 physical_base_address
= memmap
[VIRT_GIC_CPU
].base
;
736 gicv
= memmap
[VIRT_GIC_VCPU
].base
;
737 gich
= memmap
[VIRT_GIC_HYP
].base
;
740 /* 5.2.12.14 GIC Structure */
741 build_append_int_noprefix(table_data
, 0xB, 1); /* Type */
742 build_append_int_noprefix(table_data
, 76, 1); /* Length */
743 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
744 build_append_int_noprefix(table_data
, i
, 4); /* GIC ID */
745 build_append_int_noprefix(table_data
, i
, 4); /* ACPI Processor UID */
747 build_append_int_noprefix(table_data
, 1, 4); /* Enabled */
748 /* Parking Protocol Version */
749 build_append_int_noprefix(table_data
, 0, 4);
750 /* Performance Interrupt GSIV */
751 build_append_int_noprefix(table_data
, pmu_interrupt
, 4);
752 build_append_int_noprefix(table_data
, 0, 8); /* Parked Address */
753 /* Physical Base Address */
754 build_append_int_noprefix(table_data
, physical_base_address
, 8);
755 build_append_int_noprefix(table_data
, gicv
, 8); /* GICV */
756 build_append_int_noprefix(table_data
, gich
, 8); /* GICH */
757 /* VGIC Maintenance interrupt */
758 build_append_int_noprefix(table_data
, vgic_interrupt
, 4);
759 build_append_int_noprefix(table_data
, 0, 8); /* GICR Base Address*/
761 build_append_int_noprefix(table_data
, armcpu
->mp_affinity
, 8);
764 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
765 build_append_gicr(table_data
, memmap
[VIRT_GIC_REDIST
].base
,
766 memmap
[VIRT_GIC_REDIST
].size
);
767 if (virt_gicv3_redist_region_count(vms
) == 2) {
768 build_append_gicr(table_data
, memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
769 memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
772 if (its_class_name() && !vmc
->no_its
) {
774 * FIXME: Structure is from Revision 6.0 where 'GIC Structure'
775 * has additional fields on top of implemented 5.1 Errata A,
776 * to make it consistent with v6.0 we need to bump everything
780 * ACPI spec, Revision 6.0 Errata A
781 * (original 6.0 definition has invalid Length)
782 * 5.2.12.18 GIC ITS Structure
784 build_append_int_noprefix(table_data
, 0xF, 1); /* Type */
785 build_append_int_noprefix(table_data
, 20, 1); /* Length */
786 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
787 build_append_int_noprefix(table_data
, 0, 4); /* GIC ITS ID */
788 /* Physical Base Address */
789 build_append_int_noprefix(table_data
, memmap
[VIRT_GIC_ITS
].base
, 8);
790 build_append_int_noprefix(table_data
, 0, 4); /* Reserved */
793 const uint16_t spi_base
= vms
->irqmap
[VIRT_GIC_V2M
] + ARM_SPI_BASE
;
795 /* 5.2.12.16 GIC MSI Frame Structure */
796 build_append_int_noprefix(table_data
, 0xD, 1); /* Type */
797 build_append_int_noprefix(table_data
, 24, 1); /* Length */
798 build_append_int_noprefix(table_data
, 0, 2); /* Reserved */
799 build_append_int_noprefix(table_data
, 0, 4); /* GIC MSI Frame ID */
800 /* Physical Base Address */
801 build_append_int_noprefix(table_data
, memmap
[VIRT_GIC_V2M
].base
, 8);
802 build_append_int_noprefix(table_data
, 1, 4); /* Flags */
804 build_append_int_noprefix(table_data
, NUM_GICV2M_SPIS
, 2);
805 build_append_int_noprefix(table_data
, spi_base
, 2); /* SPI Base */
807 acpi_table_end(linker
, &table
);
811 static void build_fadt_rev5(GArray
*table_data
, BIOSLinker
*linker
,
812 VirtMachineState
*vms
, unsigned dsdt_tbl_offset
)
815 AcpiFadtData fadt
= {
818 .flags
= 1 << ACPI_FADT_F_HW_REDUCED_ACPI
,
819 .xdsdt_tbl_offset
= &dsdt_tbl_offset
,
822 switch (vms
->psci_conduit
) {
823 case QEMU_PSCI_CONDUIT_DISABLED
:
824 fadt
.arm_boot_arch
= 0;
826 case QEMU_PSCI_CONDUIT_HVC
:
827 fadt
.arm_boot_arch
= ACPI_FADT_ARM_PSCI_COMPLIANT
|
828 ACPI_FADT_ARM_PSCI_USE_HVC
;
830 case QEMU_PSCI_CONDUIT_SMC
:
831 fadt
.arm_boot_arch
= ACPI_FADT_ARM_PSCI_COMPLIANT
;
834 g_assert_not_reached();
837 build_fadt(table_data
, linker
, &fadt
, vms
->oem_id
, vms
->oem_table_id
);
842 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
, VirtMachineState
*vms
)
844 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
846 MachineState
*ms
= MACHINE(vms
);
847 const MemMapEntry
*memmap
= vms
->memmap
;
848 const int *irqmap
= vms
->irqmap
;
849 AcpiTable table
= { .sig
= "DSDT", .rev
= 2, .oem_id
= vms
->oem_id
,
850 .oem_table_id
= vms
->oem_table_id
};
852 acpi_table_begin(&table
, table_data
);
853 dsdt
= init_aml_allocator();
855 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
856 * While UEFI can use libfdt to disable the RTC device node in the DTB that
857 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
858 * the RTC ACPI device at all when using UEFI.
860 scope
= aml_scope("\\_SB");
861 acpi_dsdt_add_cpus(scope
, vms
);
862 acpi_dsdt_add_uart(scope
, &memmap
[VIRT_UART
],
863 (irqmap
[VIRT_UART
] + ARM_SPI_BASE
));
864 if (vmc
->acpi_expose_flash
) {
865 acpi_dsdt_add_flash(scope
, &memmap
[VIRT_FLASH
]);
867 acpi_dsdt_add_fw_cfg(scope
, &memmap
[VIRT_FW_CFG
]);
868 acpi_dsdt_add_virtio(scope
, &memmap
[VIRT_MMIO
],
869 (irqmap
[VIRT_MMIO
] + ARM_SPI_BASE
), NUM_VIRTIO_TRANSPORTS
);
870 acpi_dsdt_add_pci(scope
, memmap
, irqmap
[VIRT_PCIE
] + ARM_SPI_BASE
, vms
);
872 build_ged_aml(scope
, "\\_SB."GED_DEVICE
,
873 HOTPLUG_HANDLER(vms
->acpi_dev
),
874 irqmap
[VIRT_ACPI_GED
] + ARM_SPI_BASE
, AML_SYSTEM_MEMORY
,
875 memmap
[VIRT_ACPI_GED
].base
);
877 acpi_dsdt_add_gpio(scope
, &memmap
[VIRT_GPIO
],
878 (irqmap
[VIRT_GPIO
] + ARM_SPI_BASE
));
882 uint32_t event
= object_property_get_uint(OBJECT(vms
->acpi_dev
),
883 "ged-event", &error_abort
);
885 if (event
& ACPI_GED_MEM_HOTPLUG_EVT
) {
886 build_memory_hotplug_aml(scope
, ms
->ram_slots
, "\\_SB", NULL
,
888 memmap
[VIRT_PCDIMM_ACPI
].base
);
892 acpi_dsdt_add_power_button(scope
);
894 acpi_dsdt_add_tpm(scope
, vms
);
897 aml_append(dsdt
, scope
);
899 /* copy AML table into ACPI tables blob */
900 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
902 acpi_table_end(linker
, &table
);
903 free_aml_allocator();
907 struct AcpiBuildState
{
908 /* Copy of table in RAM (for patching). */
909 MemoryRegion
*table_mr
;
910 MemoryRegion
*rsdp_mr
;
911 MemoryRegion
*linker_mr
;
912 /* Is table patched? */
916 static void acpi_align_size(GArray
*blob
, unsigned align
)
919 * Align size to multiple of given size. This reduces the chance
920 * we need to change size in the future (breaking cross version migration).
922 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
926 void virt_acpi_build(VirtMachineState
*vms
, AcpiBuildTables
*tables
)
928 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
929 GArray
*table_offsets
;
931 GArray
*tables_blob
= tables
->table_data
;
932 MachineState
*ms
= MACHINE(vms
);
934 table_offsets
= g_array_new(false, true /* clear */,
937 bios_linker_loader_alloc(tables
->linker
,
938 ACPI_BUILD_TABLE_FILE
, tables_blob
,
939 64, false /* high memory */);
941 /* DSDT is pointed to by FADT */
942 dsdt
= tables_blob
->len
;
943 build_dsdt(tables_blob
, tables
->linker
, vms
);
945 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
946 acpi_add_table(table_offsets
, tables_blob
);
947 build_fadt_rev5(tables_blob
, tables
->linker
, vms
, dsdt
);
949 acpi_add_table(table_offsets
, tables_blob
);
950 build_madt(tables_blob
, tables
->linker
, vms
);
952 if (!vmc
->no_cpu_topology
) {
953 acpi_add_table(table_offsets
, tables_blob
);
954 build_pptt(tables_blob
, tables
->linker
, ms
,
955 vms
->oem_id
, vms
->oem_table_id
);
958 acpi_add_table(table_offsets
, tables_blob
);
959 build_gtdt(tables_blob
, tables
->linker
, vms
);
961 acpi_add_table(table_offsets
, tables_blob
);
963 AcpiMcfgInfo mcfg
= {
964 .base
= vms
->memmap
[VIRT_ECAM_ID(vms
->highmem_ecam
)].base
,
965 .size
= vms
->memmap
[VIRT_ECAM_ID(vms
->highmem_ecam
)].size
,
967 build_mcfg(tables_blob
, tables
->linker
, &mcfg
, vms
->oem_id
,
971 acpi_add_table(table_offsets
, tables_blob
);
972 build_spcr(tables_blob
, tables
->linker
, vms
);
974 acpi_add_table(table_offsets
, tables_blob
);
975 build_dbg2(tables_blob
, tables
->linker
, vms
);
978 build_ghes_error_table(tables
->hardware_errors
, tables
->linker
);
979 acpi_add_table(table_offsets
, tables_blob
);
980 acpi_build_hest(tables_blob
, tables
->linker
, vms
->oem_id
,
984 if (ms
->numa_state
->num_nodes
> 0) {
985 acpi_add_table(table_offsets
, tables_blob
);
986 build_srat(tables_blob
, tables
->linker
, vms
);
987 if (ms
->numa_state
->have_numa_distance
) {
988 acpi_add_table(table_offsets
, tables_blob
);
989 build_slit(tables_blob
, tables
->linker
, ms
, vms
->oem_id
,
994 if (ms
->nvdimms_state
->is_enabled
) {
995 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
996 ms
->nvdimms_state
, ms
->ram_slots
, vms
->oem_id
,
1000 if (its_class_name() && !vmc
->no_its
) {
1001 acpi_add_table(table_offsets
, tables_blob
);
1002 build_iort(tables_blob
, tables
->linker
, vms
);
1006 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0
) {
1007 acpi_add_table(table_offsets
, tables_blob
);
1008 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
, vms
->oem_id
,
1013 if (vms
->iommu
== VIRT_IOMMU_VIRTIO
) {
1014 acpi_add_table(table_offsets
, tables_blob
);
1015 build_viot(ms
, tables_blob
, tables
->linker
, vms
->virtio_iommu_bdf
,
1016 vms
->oem_id
, vms
->oem_table_id
);
1019 /* XSDT is pointed to by RSDP */
1020 xsdt
= tables_blob
->len
;
1021 build_xsdt(tables_blob
, tables
->linker
, table_offsets
, vms
->oem_id
,
1024 /* RSDP is in FSEG memory, so allocate it separately */
1026 AcpiRsdpData rsdp_data
= {
1028 .oem_id
= vms
->oem_id
,
1029 .xsdt_tbl_offset
= &xsdt
,
1030 .rsdt_tbl_offset
= NULL
,
1032 build_rsdp(tables
->rsdp
, tables
->linker
, &rsdp_data
);
1036 * The align size is 128, warn if 64k is not enough therefore
1037 * the align size could be resized.
1039 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
1040 warn_report("ACPI table size %u exceeds %d bytes,"
1041 " migration may not work",
1042 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
1043 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1044 " or PCI bridges.");
1046 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
1049 /* Cleanup memory that's no longer used. */
1050 g_array_free(table_offsets
, true);
1053 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
1055 uint32_t size
= acpi_data_len(data
);
1057 /* Make sure RAM size is correct - in case it got changed
1058 * e.g. by migration */
1059 memory_region_ram_resize(mr
, size
, &error_abort
);
1061 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
1062 memory_region_set_dirty(mr
, 0, size
);
1065 static void virt_acpi_build_update(void *build_opaque
)
1067 AcpiBuildState
*build_state
= build_opaque
;
1068 AcpiBuildTables tables
;
1070 /* No state to update or already patched? Nothing to do. */
1071 if (!build_state
|| build_state
->patched
) {
1074 build_state
->patched
= true;
1076 acpi_build_tables_init(&tables
);
1078 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables
);
1080 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
1081 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
1082 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
1084 acpi_build_tables_cleanup(&tables
, true);
1087 static void virt_acpi_build_reset(void *build_opaque
)
1089 AcpiBuildState
*build_state
= build_opaque
;
1090 build_state
->patched
= false;
1093 static const VMStateDescription vmstate_virt_acpi_build
= {
1094 .name
= "virt_acpi_build",
1096 .minimum_version_id
= 1,
1097 .fields
= (VMStateField
[]) {
1098 VMSTATE_BOOL(patched
, AcpiBuildState
),
1099 VMSTATE_END_OF_LIST()
1103 void virt_acpi_setup(VirtMachineState
*vms
)
1105 AcpiBuildTables tables
;
1106 AcpiBuildState
*build_state
;
1107 AcpiGedState
*acpi_ged_state
;
1110 trace_virt_acpi_setup();
1114 if (!virt_is_acpi_enabled(vms
)) {
1115 trace_virt_acpi_setup();
1119 build_state
= g_malloc0(sizeof *build_state
);
1121 acpi_build_tables_init(&tables
);
1122 virt_acpi_build(vms
, &tables
);
1124 /* Now expose it all to Guest */
1125 build_state
->table_mr
= acpi_add_rom_blob(virt_acpi_build_update
,
1126 build_state
, tables
.table_data
,
1127 ACPI_BUILD_TABLE_FILE
);
1128 assert(build_state
->table_mr
!= NULL
);
1130 build_state
->linker_mr
= acpi_add_rom_blob(virt_acpi_build_update
,
1132 tables
.linker
->cmd_blob
,
1133 ACPI_BUILD_LOADER_FILE
);
1135 fw_cfg_add_file(vms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
, tables
.tcpalog
->data
,
1136 acpi_data_len(tables
.tcpalog
));
1139 assert(vms
->acpi_dev
);
1140 acpi_ged_state
= ACPI_GED(vms
->acpi_dev
);
1141 acpi_ghes_add_fw_cfg(&acpi_ged_state
->ghes_state
,
1142 vms
->fw_cfg
, tables
.hardware_errors
);
1145 build_state
->rsdp_mr
= acpi_add_rom_blob(virt_acpi_build_update
,
1146 build_state
, tables
.rsdp
,
1147 ACPI_BUILD_RSDP_FILE
);
1149 qemu_register_reset(virt_acpi_build_reset
, build_state
);
1150 virt_acpi_build_reset(build_state
);
1151 vmstate_register(NULL
, 0, &vmstate_virt_acpi_build
, build_state
);
1153 /* Cleanup tables but don't free the memory: we track it
1156 acpi_build_tables_cleanup(&tables
, false);