macio: move ESCC device within the macio device
[qemu/ar7.git] / hw / ppc / mac_oldworld.c
blob4401ce5af2a3aff052868bf25ca88ca38f478d87
2 /*
3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
5 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2007 Jocelyn Mayer
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "hw/hw.h"
29 #include "hw/ppc/ppc.h"
30 #include "mac.h"
31 #include "hw/input/adb.h"
32 #include "hw/timer/m48t59.h"
33 #include "sysemu/sysemu.h"
34 #include "net/net.h"
35 #include "hw/isa/isa.h"
36 #include "hw/pci/pci.h"
37 #include "hw/boards.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/char/escc.h"
40 #include "hw/ide.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "qemu/error-report.h"
44 #include "sysemu/kvm.h"
45 #include "kvm_ppc.h"
46 #include "sysemu/block-backend.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/cutils.h"
50 #define MAX_IDE_BUS 2
51 #define CFG_ADDR 0xf0000510
52 #define TBFREQ 16600000UL
53 #define CLOCKFREQ 266000000UL
54 #define BUSFREQ 66000000UL
56 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
58 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
59 Error **errp)
61 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
64 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
66 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
69 static void ppc_heathrow_reset(void *opaque)
71 PowerPCCPU *cpu = opaque;
73 cpu_reset(CPU(cpu));
76 static void ppc_heathrow_init(MachineState *machine)
78 ram_addr_t ram_size = machine->ram_size;
79 const char *kernel_filename = machine->kernel_filename;
80 const char *kernel_cmdline = machine->kernel_cmdline;
81 const char *initrd_filename = machine->initrd_filename;
82 const char *boot_device = machine->boot_order;
83 MemoryRegion *sysmem = get_system_memory();
84 PowerPCCPU *cpu = NULL;
85 CPUPPCState *env = NULL;
86 char *filename;
87 qemu_irq *pic, **heathrow_irqs;
88 int linux_boot, i;
89 MemoryRegion *ram = g_new(MemoryRegion, 1);
90 MemoryRegion *bios = g_new(MemoryRegion, 1);
91 MemoryRegion *isa = g_new(MemoryRegion, 1);
92 uint32_t kernel_base, initrd_base, cmdline_base = 0;
93 int32_t kernel_size, initrd_size;
94 PCIBus *pci_bus;
95 PCIDevice *macio;
96 MACIOIDEState *macio_ide;
97 DeviceState *dev;
98 BusState *adb_bus;
99 int bios_size, ndrv_size;
100 uint8_t *ndrv_file;
101 MemoryRegion *pic_mem;
102 uint16_t ppc_boot_device;
103 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
104 void *fw_cfg;
105 uint64_t tbfreq;
107 linux_boot = (kernel_filename != NULL);
109 /* init CPUs */
110 for (i = 0; i < smp_cpus; i++) {
111 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
112 env = &cpu->env;
114 /* Set time-base frequency to 16.6 Mhz */
115 cpu_ppc_tb_init(env, TBFREQ);
116 qemu_register_reset(ppc_heathrow_reset, cpu);
119 /* allocate RAM */
120 if (ram_size > (2047 << 20)) {
121 fprintf(stderr,
122 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
123 ((unsigned int)ram_size / (1 << 20)));
124 exit(1);
127 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
128 ram_size);
129 memory_region_add_subregion(sysmem, 0, ram);
131 /* allocate and load BIOS */
132 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
133 &error_fatal);
135 if (bios_name == NULL)
136 bios_name = PROM_FILENAME;
137 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
138 memory_region_set_readonly(bios, true);
139 memory_region_add_subregion(sysmem, PROM_ADDR, bios);
141 /* Load OpenBIOS (ELF) */
142 if (filename) {
143 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
144 1, PPC_ELF_MACHINE, 0, 0);
145 g_free(filename);
146 } else {
147 bios_size = -1;
149 if (bios_size < 0 || bios_size > BIOS_SIZE) {
150 error_report("could not load PowerPC bios '%s'", bios_name);
151 exit(1);
154 if (linux_boot) {
155 uint64_t lowaddr = 0;
156 int bswap_needed;
158 #ifdef BSWAP_NEEDED
159 bswap_needed = 1;
160 #else
161 bswap_needed = 0;
162 #endif
163 kernel_base = KERNEL_LOAD_ADDR;
164 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
165 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
166 0, 0);
167 if (kernel_size < 0)
168 kernel_size = load_aout(kernel_filename, kernel_base,
169 ram_size - kernel_base, bswap_needed,
170 TARGET_PAGE_SIZE);
171 if (kernel_size < 0)
172 kernel_size = load_image_targphys(kernel_filename,
173 kernel_base,
174 ram_size - kernel_base);
175 if (kernel_size < 0) {
176 error_report("could not load kernel '%s'", kernel_filename);
177 exit(1);
179 /* load initrd */
180 if (initrd_filename) {
181 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
182 initrd_size = load_image_targphys(initrd_filename, initrd_base,
183 ram_size - initrd_base);
184 if (initrd_size < 0) {
185 error_report("could not load initial ram disk '%s'",
186 initrd_filename);
187 exit(1);
189 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
190 } else {
191 initrd_base = 0;
192 initrd_size = 0;
193 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
195 ppc_boot_device = 'm';
196 } else {
197 kernel_base = 0;
198 kernel_size = 0;
199 initrd_base = 0;
200 initrd_size = 0;
201 ppc_boot_device = '\0';
202 for (i = 0; boot_device[i] != '\0'; i++) {
203 /* TOFIX: for now, the second IDE channel is not properly
204 * used by OHW. The Mac floppy disk are not emulated.
205 * For now, OHW cannot boot from the network.
207 #if 0
208 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
209 ppc_boot_device = boot_device[i];
210 break;
212 #else
213 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
214 ppc_boot_device = boot_device[i];
215 break;
217 #endif
219 if (ppc_boot_device == '\0') {
220 error_report("No valid boot device for G3 Beige machine");
221 exit(1);
225 /* Register 2 MB of ISA IO space */
226 memory_region_init_alias(isa, NULL, "isa_mmio",
227 get_system_io(), 0, 0x00200000);
228 memory_region_add_subregion(sysmem, 0xfe000000, isa);
230 /* XXX: we register only 1 output pin for heathrow PIC */
231 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
232 heathrow_irqs[0] =
233 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
234 /* Connect the heathrow PIC outputs to the 6xx bus */
235 for (i = 0; i < smp_cpus; i++) {
236 switch (PPC_INPUT(env)) {
237 case PPC_FLAGS_INPUT_6xx:
238 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
239 heathrow_irqs[i][0] =
240 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
241 break;
242 default:
243 error_report("Bus model not supported on OldWorld Mac machine");
244 exit(1);
248 /* Timebase Frequency */
249 if (kvm_enabled()) {
250 tbfreq = kvmppc_get_tbfreq();
251 } else {
252 tbfreq = TBFREQ;
255 /* init basic PC hardware */
256 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
257 error_report("Only 6xx bus is supported on heathrow machine");
258 exit(1);
260 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
261 pci_bus = pci_grackle_init(0xfec00000, pic,
262 get_system_memory(),
263 get_system_io());
264 pci_vga_init(pci_bus);
266 for (i = 0; i < nb_nics; i++) {
267 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
270 ide_drive_get(hd, ARRAY_SIZE(hd));
272 /* MacIO */
273 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
274 dev = DEVICE(macio);
275 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
276 qdev_connect_gpio_out(dev, 1, pic[0x10]); /* ESCC-B */
277 qdev_connect_gpio_out(dev, 2, pic[0x0F]); /* ESCC-A */
278 qdev_connect_gpio_out(dev, 3, pic[0x0D]); /* IDE-0 */
279 qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE-0 DMA */
280 qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */
281 qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */
282 qdev_prop_set_uint64(dev, "frequency", tbfreq);
283 macio_init(macio, pic_mem);
285 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
286 "ide[0]"));
287 macio_ide_init_drives(macio_ide, hd);
289 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
290 "ide[1]"));
291 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
293 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
294 adb_bus = qdev_get_child_bus(dev, "adb.0");
295 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
296 qdev_init_nofail(dev);
297 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
298 qdev_init_nofail(dev);
300 if (machine_usb(machine)) {
301 pci_create_simple(pci_bus, -1, "pci-ohci");
304 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
305 graphic_depth = 15;
307 /* No PCI init: the BIOS will do it */
309 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
310 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
311 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
312 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
313 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
314 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
315 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
316 if (kernel_cmdline) {
317 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
318 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
319 } else {
320 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
322 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
323 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
324 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
326 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
327 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
328 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
330 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
331 if (kvm_enabled()) {
332 #ifdef CONFIG_KVM
333 uint8_t *hypercall;
335 hypercall = g_malloc(16);
336 kvmppc_get_hypercall(env, hypercall, 16);
337 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
338 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
339 #endif
341 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
342 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
343 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
344 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
346 /* MacOS NDRV VGA driver */
347 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
348 if (filename) {
349 ndrv_size = get_image_size(filename);
350 if (ndrv_size != -1) {
351 ndrv_file = g_malloc(ndrv_size);
352 ndrv_size = load_image(filename, ndrv_file);
354 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
356 g_free(filename);
359 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
362 static int heathrow_kvm_type(const char *arg)
364 /* Always force PR KVM */
365 return 2;
368 static void heathrow_class_init(ObjectClass *oc, void *data)
370 MachineClass *mc = MACHINE_CLASS(oc);
372 mc->desc = "Heathrow based PowerMAC";
373 mc->init = ppc_heathrow_init;
374 mc->block_default_type = IF_IDE;
375 mc->max_cpus = MAX_CPUS;
376 #ifndef TARGET_PPC64
377 mc->is_default = 1;
378 #endif
379 /* TOFIX "cad" when Mac floppy is implemented */
380 mc->default_boot_order = "cd";
381 mc->kvm_type = heathrow_kvm_type;
382 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
385 static const TypeInfo ppc_heathrow_machine_info = {
386 .name = MACHINE_TYPE_NAME("g3beige"),
387 .parent = TYPE_MACHINE,
388 .class_init = heathrow_class_init
391 static void ppc_heathrow_register_types(void)
393 type_register_static(&ppc_heathrow_machine_info);
396 type_init(ppc_heathrow_register_types);