target-s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "gdbstub.h"
  23 #include "qemu-timer.h"
  24 #ifndef CONFIG_USER_ONLY
  25 #include "sysemu.h"
  26 #endif
  27
  28 //#define DEBUG_S390
  29 //#define DEBUG_S390_PTE
  30 //#define DEBUG_S390_STDOUT
  31
  32 #ifdef DEBUG_S390
  33 #ifdef DEBUG_S390_STDOUT
  34 #define DPRINTF(fmt, ...) \
  35     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  36          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  37 #else
  38 #define DPRINTF(fmt, ...) \
  39     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  40 #endif
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #ifdef DEBUG_S390_PTE
  47 #define PTE_DPRINTF DPRINTF
  48 #else
  49 #define PTE_DPRINTF(fmt, ...) \
  50     do { } while (0)
  51 #endif
  52
  53 #ifndef CONFIG_USER_ONLY
  54 void s390x_tod_timer(void *opaque)
  55 {
  56     S390CPU *cpu = opaque;
  57     CPUS390XState *env = &cpu->env;
  58
  59     env->pending_int |= INTERRUPT_TOD;
  60     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  61 }
  62
  63 void s390x_cpu_timer(void *opaque)
  64 {
  65     S390CPU *cpu = opaque;
  66     CPUS390XState *env = &cpu->env;
  67
  68     env->pending_int |= INTERRUPT_CPUTIMER;
  69     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  70 }
  71 #endif
  72
  73 S390CPU *cpu_s390x_init(const char *cpu_model)
  74 {
  75     S390CPU *cpu;
  76     CPUS390XState *env;
  77     static int inited = 0;
  78
  79     cpu = S390_CPU(object_new(TYPE_S390_CPU));
  80     env = &cpu->env;
  81
  82     if (tcg_enabled() && !inited) {
  83         inited = 1;
  84         s390x_translate_init();
  85     }
  86
  87     env->cpu_model_str = cpu_model;
  88     qemu_init_vcpu(env);
  89     return cpu;
  90 }
  91
  92 #if defined(CONFIG_USER_ONLY)
  93
  94 void do_interrupt (CPUS390XState *env)
  95 {
  96     env->exception_index = -1;
  97 }
  98
  99 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
 100                                 int mmu_idx)
 101 {
 102     /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
 103             __FUNCTION__, address, rw, mmu_idx); */
 104     env->exception_index = EXCP_ADDR;
 105     env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
 106     return 1;
 107 }
 108
 109 #else /* !CONFIG_USER_ONLY */
 110
 111 /* Ensure to exit the TB after this call! */
 112 static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
 113 {
 114     env->exception_index = EXCP_PGM;
 115     env->int_pgm_code = code;
 116     env->int_pgm_ilc = ilc;
 117 }
 118
 119 static int trans_bits(CPUS390XState *env, uint64_t mode)
 120 {
 121     int bits = 0;
 122
 123     switch (mode) {
 124     case PSW_ASC_PRIMARY:
 125         bits = 1;
 126         break;
 127     case PSW_ASC_SECONDARY:
 128         bits = 2;
 129         break;
 130     case PSW_ASC_HOME:
 131         bits = 3;
 132         break;
 133     default:
 134         cpu_abort(env, "unknown asc mode\n");
 135         break;
 136     }
 137
 138     return bits;
 139 }
 140
 141 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
 142 {
 143     int ilc = ILC_LATER_INC_2;
 144     int bits = trans_bits(env, mode) | 4;
 145
 146     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
 147
 148     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 149     trigger_pgm_exception(env, PGM_PROTECTION, ilc);
 150 }
 151
 152 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
 153                                uint64_t asc, int rw)
 154 {
 155     int ilc = ILC_LATER;
 156     int bits = trans_bits(env, asc);
 157
 158     if (rw == 2) {
 159         /* code has is undefined ilc */
 160         ilc = 2;
 161     }
 162
 163     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
 164
 165     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 166     trigger_pgm_exception(env, type, ilc);
 167 }
 168
 169 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
 170                               uint64_t asce, int level, target_ulong *raddr,
 171                               int *flags, int rw)
 172 {
 173     uint64_t offs = 0;
 174     uint64_t origin;
 175     uint64_t new_asce;
 176
 177     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);
 178
 179     if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
 180         ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
 181         /* XXX different regions have different faults */
 182         DPRINTF("%s: invalid region\n", __FUNCTION__);
 183         trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
 184         return -1;
 185     }
 186
 187     if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
 188         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 189         return -1;
 190     }
 191
 192     if (asce & _ASCE_REAL_SPACE) {
 193         /* direct mapping */
 194
 195         *raddr = vaddr;
 196         return 0;
 197     }
 198
 199     origin = asce & _ASCE_ORIGIN;
 200
 201     switch (level) {
 202     case _ASCE_TYPE_REGION1 + 4:
 203         offs = (vaddr >> 50) & 0x3ff8;
 204         break;
 205     case _ASCE_TYPE_REGION1:
 206         offs = (vaddr >> 39) & 0x3ff8;
 207         break;
 208     case _ASCE_TYPE_REGION2:
 209         offs = (vaddr >> 28) & 0x3ff8;
 210         break;
 211     case _ASCE_TYPE_REGION3:
 212         offs = (vaddr >> 17) & 0x3ff8;
 213         break;
 214     case _ASCE_TYPE_SEGMENT:
 215         offs = (vaddr >> 9) & 0x07f8;
 216         origin = asce & _SEGMENT_ENTRY_ORIGIN;
 217         break;
 218     }
 219
 220     /* XXX region protection flags */
 221     /* *flags &= ~PAGE_WRITE */
 222
 223     new_asce = ldq_phys(origin + offs);
 224     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 225                 __FUNCTION__, origin, offs, new_asce);
 226
 227     if (level != _ASCE_TYPE_SEGMENT) {
 228         /* yet another region */
 229         return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
 230                                   flags, rw);
 231     }
 232
 233     /* PTE */
 234     if (new_asce & _PAGE_INVALID) {
 235         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
 236         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
 237         return -1;
 238     }
 239
 240     if (new_asce & _PAGE_RO) {
 241         *flags &= ~PAGE_WRITE;
 242     }
 243
 244     *raddr = new_asce & _ASCE_ORIGIN;
 245
 246     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);
 247
 248     return 0;
 249 }
 250
 251 static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
 252                              target_ulong *raddr, int *flags, int rw)
 253 {
 254     uint64_t asce = 0;
 255     int level, new_level;
 256     int r;
 257
 258     switch (asc) {
 259     case PSW_ASC_PRIMARY:
 260         PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
 261         asce = env->cregs[1];
 262         break;
 263     case PSW_ASC_SECONDARY:
 264         PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
 265         asce = env->cregs[7];
 266         break;
 267     case PSW_ASC_HOME:
 268         PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
 269         asce = env->cregs[13];
 270         break;
 271     }
 272
 273     switch (asce & _ASCE_TYPE_MASK) {
 274     case _ASCE_TYPE_REGION1:
 275         break;
 276     case _ASCE_TYPE_REGION2:
 277         if (vaddr & 0xffe0000000000000ULL) {
 278             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 279                         " 0xffe0000000000000ULL\n", __FUNCTION__,
 280                         vaddr);
 281             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 282             return -1;
 283         }
 284         break;
 285     case _ASCE_TYPE_REGION3:
 286         if (vaddr & 0xfffffc0000000000ULL) {
 287             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 288                         " 0xfffffc0000000000ULL\n", __FUNCTION__,
 289                         vaddr);
 290             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 291             return -1;
 292         }
 293         break;
 294     case _ASCE_TYPE_SEGMENT:
 295         if (vaddr & 0xffffffff80000000ULL) {
 296             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 297                         " 0xffffffff80000000ULL\n", __FUNCTION__,
 298                         vaddr);
 299             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 300             return -1;
 301         }
 302         break;
 303     }
 304
 305     /* fake level above current */
 306     level = asce & _ASCE_TYPE_MASK;
 307     new_level = level + 4;
 308     asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
 309
 310     r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
 311
 312     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 313         trigger_prot_fault(env, vaddr, asc);
 314         return -1;
 315     }
 316
 317     return r;
 318 }
 319
 320 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 321                   target_ulong *raddr, int *flags)
 322 {
 323     int r = -1;
 324     uint8_t *sk;
 325
 326     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 327     vaddr &= TARGET_PAGE_MASK;
 328
 329     if (!(env->psw.mask & PSW_MASK_DAT)) {
 330         *raddr = vaddr;
 331         r = 0;
 332         goto out;
 333     }
 334
 335     switch (asc) {
 336     case PSW_ASC_PRIMARY:
 337     case PSW_ASC_HOME:
 338         r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
 339         break;
 340     case PSW_ASC_SECONDARY:
 341         /*
 342          * Instruction: Primary
 343          * Data: Secondary
 344          */
 345         if (rw == 2) {
 346             r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
 347                                   rw);
 348             *flags &= ~(PAGE_READ | PAGE_WRITE);
 349         } else {
 350             r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
 351                                   rw);
 352             *flags &= ~(PAGE_EXEC);
 353         }
 354         break;
 355     case PSW_ASC_ACCREG:
 356     default:
 357         hw_error("guest switched to unknown asc mode\n");
 358         break;
 359     }
 360
 361 out:
 362     /* Convert real address -> absolute address */
 363     if (*raddr < 0x2000) {
 364         *raddr = *raddr + env->psa;
 365     }
 366
 367     if (*raddr <= ram_size) {
 368         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 369         if (*flags & PAGE_READ) {
 370             *sk |= SK_R;
 371         }
 372
 373         if (*flags & PAGE_WRITE) {
 374             *sk |= SK_C;
 375         }
 376     }
 377
 378     return r;
 379 }
 380
 381 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
 382                                 int mmu_idx)
 383 {
 384     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 385     target_ulong vaddr, raddr;
 386     int prot;
 387
 388     DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
 389             __FUNCTION__, _vaddr, rw, mmu_idx);
 390
 391     _vaddr &= TARGET_PAGE_MASK;
 392     vaddr = _vaddr;
 393
 394     /* 31-Bit mode */
 395     if (!(env->psw.mask & PSW_MASK_64)) {
 396         vaddr &= 0x7fffffff;
 397     }
 398
 399     if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
 400         /* Translation ended in exception */
 401         return 1;
 402     }
 403
 404     /* check out of RAM access */
 405     if (raddr > (ram_size + virtio_size)) {
 406         DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
 407                 (uint64_t)aaddr, (uint64_t)ram_size);
 408         trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
 409         return 1;
 410     }
 411
 412     DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
 413             (uint64_t)vaddr, (uint64_t)raddr, prot);
 414
 415     tlb_set_page(env, _vaddr, raddr, prot,
 416                  mmu_idx, TARGET_PAGE_SIZE);
 417
 418     return 0;
 419 }
 420
 421 target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
 422 {
 423     target_ulong raddr;
 424     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 425     int old_exc = env->exception_index;
 426     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 427
 428     /* 31-Bit mode */
 429     if (!(env->psw.mask & PSW_MASK_64)) {
 430         vaddr &= 0x7fffffff;
 431     }
 432
 433     mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
 434     env->exception_index = old_exc;
 435
 436     return raddr;
 437 }
 438
 439 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
 440 {
 441     if (mask & PSW_MASK_WAIT) {
 442         if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
 443             if (s390_del_running_cpu(env) == 0) {
 444 #ifndef CONFIG_USER_ONLY
 445                 qemu_system_shutdown_request();
 446 #endif
 447             }
 448         }
 449         env->halted = 1;
 450         env->exception_index = EXCP_HLT;
 451     }
 452
 453     env->psw.addr = addr;
 454     env->psw.mask = mask;
 455     env->cc_op = (mask >> 13) & 3;
 456 }
 457
 458 static uint64_t get_psw_mask(CPUS390XState *env)
 459 {
 460     uint64_t r = env->psw.mask;
 461
 462     env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
 463
 464     r &= ~(3ULL << 13);
 465     assert(!(env->cc_op & ~3));
 466     r |= env->cc_op << 13;
 467
 468     return r;
 469 }
 470
 471 static void do_svc_interrupt(CPUS390XState *env)
 472 {
 473     uint64_t mask, addr;
 474     LowCore *lowcore;
 475     target_phys_addr_t len = TARGET_PAGE_SIZE;
 476
 477     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 478
 479     lowcore->svc_code = cpu_to_be16(env->int_svc_code);
 480     lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
 481     lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 482     lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
 483     mask = be64_to_cpu(lowcore->svc_new_psw.mask);
 484     addr = be64_to_cpu(lowcore->svc_new_psw.addr);
 485
 486     cpu_physical_memory_unmap(lowcore, len, 1, len);
 487
 488     load_psw(env, mask, addr);
 489 }
 490
 491 static void do_program_interrupt(CPUS390XState *env)
 492 {
 493     uint64_t mask, addr;
 494     LowCore *lowcore;
 495     target_phys_addr_t len = TARGET_PAGE_SIZE;
 496     int ilc = env->int_pgm_ilc;
 497
 498     switch (ilc) {
 499     case ILC_LATER:
 500         ilc = get_ilc(ldub_code(env->psw.addr));
 501         break;
 502     case ILC_LATER_INC:
 503         ilc = get_ilc(ldub_code(env->psw.addr));
 504         env->psw.addr += ilc * 2;
 505         break;
 506     case ILC_LATER_INC_2:
 507         ilc = get_ilc(ldub_code(env->psw.addr)) * 2;
 508         env->psw.addr += ilc;
 509         break;
 510     }
 511
 512     qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);
 513
 514     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 515
 516     lowcore->pgm_ilc = cpu_to_be16(ilc);
 517     lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
 518     lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 519     lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
 520     mask = be64_to_cpu(lowcore->program_new_psw.mask);
 521     addr = be64_to_cpu(lowcore->program_new_psw.addr);
 522
 523     cpu_physical_memory_unmap(lowcore, len, 1, len);
 524
 525     DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
 526             env->int_pgm_code, ilc, env->psw.mask,
 527             env->psw.addr);
 528
 529     load_psw(env, mask, addr);
 530 }
 531
 532 #define VIRTIO_SUBCODE_64 0x0D00
 533
 534 static void do_ext_interrupt(CPUS390XState *env)
 535 {
 536     uint64_t mask, addr;
 537     LowCore *lowcore;
 538     target_phys_addr_t len = TARGET_PAGE_SIZE;
 539     ExtQueue *q;
 540
 541     if (!(env->psw.mask & PSW_MASK_EXT)) {
 542         cpu_abort(env, "Ext int w/o ext mask\n");
 543     }
 544
 545     if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
 546         cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
 547     }
 548
 549     q = &env->ext_queue[env->ext_index];
 550     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 551
 552     lowcore->ext_int_code = cpu_to_be16(q->code);
 553     lowcore->ext_params = cpu_to_be32(q->param);
 554     lowcore->ext_params2 = cpu_to_be64(q->param64);
 555     lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 556     lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
 557     lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
 558     mask = be64_to_cpu(lowcore->external_new_psw.mask);
 559     addr = be64_to_cpu(lowcore->external_new_psw.addr);
 560
 561     cpu_physical_memory_unmap(lowcore, len, 1, len);
 562
 563     env->ext_index--;
 564     if (env->ext_index == -1) {
 565         env->pending_int &= ~INTERRUPT_EXT;
 566     }
 567
 568     DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
 569             env->psw.mask, env->psw.addr);
 570
 571     load_psw(env, mask, addr);
 572 }
 573
 574 void do_interrupt (CPUS390XState *env)
 575 {
 576     qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
 577              env->psw.addr);
 578
 579     s390_add_running_cpu(env);
 580     /* handle external interrupts */
 581     if ((env->psw.mask & PSW_MASK_EXT) &&
 582         env->exception_index == -1) {
 583         if (env->pending_int & INTERRUPT_EXT) {
 584             /* code is already in env */
 585             env->exception_index = EXCP_EXT;
 586         } else if (env->pending_int & INTERRUPT_TOD) {
 587             cpu_inject_ext(env, 0x1004, 0, 0);
 588             env->exception_index = EXCP_EXT;
 589             env->pending_int &= ~INTERRUPT_EXT;
 590             env->pending_int &= ~INTERRUPT_TOD;
 591         } else if (env->pending_int & INTERRUPT_CPUTIMER) {
 592             cpu_inject_ext(env, 0x1005, 0, 0);
 593             env->exception_index = EXCP_EXT;
 594             env->pending_int &= ~INTERRUPT_EXT;
 595             env->pending_int &= ~INTERRUPT_TOD;
 596         }
 597     }
 598
 599     switch (env->exception_index) {
 600     case EXCP_PGM:
 601         do_program_interrupt(env);
 602         break;
 603     case EXCP_SVC:
 604         do_svc_interrupt(env);
 605         break;
 606     case EXCP_EXT:
 607         do_ext_interrupt(env);
 608         break;
 609     }
 610     env->exception_index = -1;
 611
 612     if (!env->pending_int) {
 613         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 614     }
 615 }
 616
 617 #endif /* CONFIG_USER_ONLY */