target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "internals.h"
  24 #include "qemu-common.h"
  25 #include "hw/qdev-properties.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  84 {
  85     /* Purely an assertion check: we've already done reset once,
  86      * so now check that running the reset for the cpreg doesn't
  87      * change its value. This traps bugs where two different cpregs
  88      * both try to reset the same state field but to different values.
  89      */
  90     ARMCPRegInfo *ri = value;
  91     ARMCPU *cpu = opaque;
  92     uint64_t oldvalue, newvalue;
  93
  94     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
  95         return;
  96     }
  97
  98     oldvalue = read_raw_cp_reg(&cpu->env, ri);
  99     cp_reg_reset(key, value, opaque);
 100     newvalue = read_raw_cp_reg(&cpu->env, ri);
 101     assert(oldvalue == newvalue);
 102 }
 103
 104 /* CPUClass::reset() */
 105 static void arm_cpu_reset(CPUState *s)
 106 {
 107     ARMCPU *cpu = ARM_CPU(s);
 108     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 109     CPUARMState *env = &cpu->env;
 110
 111     acc->parent_reset(s);
 112
 113     memset(env, 0, offsetof(CPUARMState, features));
 114     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 115     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 116
 117     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 118     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 119     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 120     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 121
 122     cpu->powered_off = cpu->start_powered_off;
 123     s->halted = cpu->start_powered_off;
 124
 125     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 126         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 127     }
 128
 129     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 130         /* 64 bit CPUs always start in 64 bit mode */
 131         env->aarch64 = 1;
 132 #if defined(CONFIG_USER_ONLY)
 133         env->pstate = PSTATE_MODE_EL0t;
 134         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 135         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 136         /* and to the FP/Neon instructions */
 137         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 138 #else
 139         /* Reset into the highest available EL */
 140         if (arm_feature(env, ARM_FEATURE_EL3)) {
 141             env->pstate = PSTATE_MODE_EL3h;
 142         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 143             env->pstate = PSTATE_MODE_EL2h;
 144         } else {
 145             env->pstate = PSTATE_MODE_EL1h;
 146         }
 147         env->pc = cpu->rvbar;
 148 #endif
 149     } else {
 150 #if defined(CONFIG_USER_ONLY)
 151         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 152         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 153 #endif
 154     }
 155
 156 #if defined(CONFIG_USER_ONLY)
 157     env->uncached_cpsr = ARM_CPU_MODE_USR;
 158     /* For user mode we must enable access to coprocessors */
 159     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 160     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 161         env->cp15.c15_cpar = 3;
 162     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 163         env->cp15.c15_cpar = 1;
 164     }
 165 #else
 166     /* SVC mode with interrupts disabled.  */
 167     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 168     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 169     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 170      * clear at reset. Initial SP and PC are loaded from ROM.
 171      */
 172     if (IS_M(env)) {
 173         uint32_t initial_msp; /* Loaded from 0x0 */
 174         uint32_t initial_pc; /* Loaded from 0x4 */
 175         uint8_t *rom;
 176
 177         env->daif &= ~PSTATE_I;
 178         rom = rom_ptr(0);
 179         if (rom) {
 180             /* Address zero is covered by ROM which hasn't yet been
 181              * copied into physical memory.
 182              */
 183             initial_msp = ldl_p(rom);
 184             initial_pc = ldl_p(rom + 4);
 185         } else {
 186             /* Address zero not covered by a ROM blob, or the ROM blob
 187              * is in non-modifiable memory and this is a second reset after
 188              * it got copied into memory. In the latter case, rom_ptr
 189              * will return a NULL pointer and we should use ldl_phys instead.
 190              */
 191             initial_msp = ldl_phys(s->as, 0);
 192             initial_pc = ldl_phys(s->as, 4);
 193         }
 194
 195         env->regs[13] = initial_msp & 0xFFFFFFFC;
 196         env->regs[15] = initial_pc & ~1;
 197         env->thumb = initial_pc & 1;
 198     }
 199
 200     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 201      * executing as AArch32 then check if highvecs are enabled and
 202      * adjust the PC accordingly.
 203      */
 204     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 205         env->regs[15] = 0xFFFF0000;
 206     }
 207
 208     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 209 #endif
 210     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 211     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 212     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 213     set_float_detect_tininess(float_tininess_before_rounding,
 214                               &env->vfp.fp_status);
 215     set_float_detect_tininess(float_tininess_before_rounding,
 216                               &env->vfp.standard_fp_status);
 217     tlb_flush(s, 1);
 218
 219 #ifndef CONFIG_USER_ONLY
 220     if (kvm_enabled()) {
 221         kvm_arm_reset_vcpu(cpu);
 222     }
 223 #endif
 224
 225     hw_breakpoint_update_all(cpu);
 226     hw_watchpoint_update_all(cpu);
 227 }
 228
 229 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 230 {
 231     CPUClass *cc = CPU_GET_CLASS(cs);
 232     CPUARMState *env = cs->env_ptr;
 233     uint32_t cur_el = arm_current_el(env);
 234     bool secure = arm_is_secure(env);
 235     uint32_t target_el;
 236     uint32_t excp_idx;
 237     bool ret = false;
 238
 239     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 240         excp_idx = EXCP_FIQ;
 241         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 242         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 243             cs->exception_index = excp_idx;
 244             env->exception.target_el = target_el;
 245             cc->do_interrupt(cs);
 246             ret = true;
 247         }
 248     }
 249     if (interrupt_request & CPU_INTERRUPT_HARD) {
 250         excp_idx = EXCP_IRQ;
 251         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 252         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 253             cs->exception_index = excp_idx;
 254             env->exception.target_el = target_el;
 255             cc->do_interrupt(cs);
 256             ret = true;
 257         }
 258     }
 259     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 260         excp_idx = EXCP_VIRQ;
 261         target_el = 1;
 262         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 263             cs->exception_index = excp_idx;
 264             env->exception.target_el = target_el;
 265             cc->do_interrupt(cs);
 266             ret = true;
 267         }
 268     }
 269     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 270         excp_idx = EXCP_VFIQ;
 271         target_el = 1;
 272         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 273             cs->exception_index = excp_idx;
 274             env->exception.target_el = target_el;
 275             cc->do_interrupt(cs);
 276             ret = true;
 277         }
 278     }
 279
 280     return ret;
 281 }
 282
 283 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 284 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 285 {
 286     CPUClass *cc = CPU_GET_CLASS(cs);
 287     ARMCPU *cpu = ARM_CPU(cs);
 288     CPUARMState *env = &cpu->env;
 289     bool ret = false;
 290
 291
 292     if (interrupt_request & CPU_INTERRUPT_FIQ
 293         && !(env->daif & PSTATE_F)) {
 294         cs->exception_index = EXCP_FIQ;
 295         cc->do_interrupt(cs);
 296         ret = true;
 297     }
 298     /* ARMv7-M interrupt return works by loading a magic value
 299      * into the PC.  On real hardware the load causes the
 300      * return to occur.  The qemu implementation performs the
 301      * jump normally, then does the exception return when the
 302      * CPU tries to execute code at the magic address.
 303      * This will cause the magic PC value to be pushed to
 304      * the stack if an interrupt occurred at the wrong time.
 305      * We avoid this by disabling interrupts when
 306      * pc contains a magic address.
 307      */
 308     if (interrupt_request & CPU_INTERRUPT_HARD
 309         && !(env->daif & PSTATE_I)
 310         && (env->regs[15] < 0xfffffff0)) {
 311         cs->exception_index = EXCP_IRQ;
 312         cc->do_interrupt(cs);
 313         ret = true;
 314     }
 315     return ret;
 316 }
 317 #endif
 318
 319 #ifndef CONFIG_USER_ONLY
 320 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 321 {
 322     ARMCPU *cpu = opaque;
 323     CPUARMState *env = &cpu->env;
 324     CPUState *cs = CPU(cpu);
 325     static const int mask[] = {
 326         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 327         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 328         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 329         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 330     };
 331
 332     switch (irq) {
 333     case ARM_CPU_VIRQ:
 334     case ARM_CPU_VFIQ:
 335         assert(arm_feature(env, ARM_FEATURE_EL2));
 336         /* fall through */
 337     case ARM_CPU_IRQ:
 338     case ARM_CPU_FIQ:
 339         if (level) {
 340             cpu_interrupt(cs, mask[irq]);
 341         } else {
 342             cpu_reset_interrupt(cs, mask[irq]);
 343         }
 344         break;
 345     default:
 346         g_assert_not_reached();
 347     }
 348 }
 349
 350 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 351 {
 352 #ifdef CONFIG_KVM
 353     ARMCPU *cpu = opaque;
 354     CPUState *cs = CPU(cpu);
 355     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 356
 357     switch (irq) {
 358     case ARM_CPU_IRQ:
 359         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 360         break;
 361     case ARM_CPU_FIQ:
 362         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 363         break;
 364     default:
 365         g_assert_not_reached();
 366     }
 367     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 368     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 369 #endif
 370 }
 371
 372 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 373 {
 374     ARMCPU *cpu = ARM_CPU(cs);
 375     CPUARMState *env = &cpu->env;
 376
 377     cpu_synchronize_state(cs);
 378     return arm_cpu_data_is_big_endian(env);
 379 }
 380
 381 #endif
 382
 383 static inline void set_feature(CPUARMState *env, int feature)
 384 {
 385     env->features |= 1ULL << feature;
 386 }
 387
 388 static inline void unset_feature(CPUARMState *env, int feature)
 389 {
 390     env->features &= ~(1ULL << feature);
 391 }
 392
 393 static int
 394 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 395 {
 396   return print_insn_arm(pc | 1, info);
 397 }
 398
 399 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 400 {
 401     ARMCPU *ac = ARM_CPU(cpu);
 402     CPUARMState *env = &ac->env;
 403
 404     if (is_a64(env)) {
 405         /* We might not be compiled with the A64 disassembler
 406          * because it needs a C++ compiler. Leave print_insn
 407          * unset in this case to use the caller default behaviour.
 408          */
 409 #if defined(CONFIG_ARM_A64_DIS)
 410         info->print_insn = print_insn_arm_a64;
 411 #endif
 412     } else if (env->thumb) {
 413         info->print_insn = print_insn_thumb1;
 414     } else {
 415         info->print_insn = print_insn_arm;
 416     }
 417     if (bswap_code(arm_sctlr_b(env))) {
 418 #ifdef TARGET_WORDS_BIGENDIAN
 419         info->endian = BFD_ENDIAN_LITTLE;
 420 #else
 421         info->endian = BFD_ENDIAN_BIG;
 422 #endif
 423     }
 424 }
 425
 426 #define ARM_CPUS_PER_CLUSTER 8
 427
 428 static void arm_cpu_initfn(Object *obj)
 429 {
 430     CPUState *cs = CPU(obj);
 431     ARMCPU *cpu = ARM_CPU(obj);
 432     static bool inited;
 433     uint32_t Aff1, Aff0;
 434
 435     cs->env_ptr = &cpu->env;
 436     cpu_exec_init(cs, &error_abort);
 437     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 438                                          g_free, g_free);
 439
 440     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 441      * We don't support setting cluster ID ([16..23]) (known as Aff2
 442      * in later ARM ARM versions), or any of the higher affinity level fields,
 443      * so these bits always RAZ.
 444      */
 445     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 446     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 447     cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 448
 449 #ifndef CONFIG_USER_ONLY
 450     /* Our inbound IRQ and FIQ lines */
 451     if (kvm_enabled()) {
 452         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 453          * the same interface as non-KVM CPUs.
 454          */
 455         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 456     } else {
 457         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 458     }
 459
 460     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 461                                                 arm_gt_ptimer_cb, cpu);
 462     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 463                                                 arm_gt_vtimer_cb, cpu);
 464     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 465                                                 arm_gt_htimer_cb, cpu);
 466     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 467                                                 arm_gt_stimer_cb, cpu);
 468     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 469                        ARRAY_SIZE(cpu->gt_timer_outputs));
 470 #endif
 471
 472     /* DTB consumers generally don't in fact care what the 'compatible'
 473      * string is, so always provide some string and trust that a hypothetical
 474      * picky DTB consumer will also provide a helpful error message.
 475      */
 476     cpu->dtb_compatible = "qemu,unknown";
 477     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 478     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 479
 480     if (tcg_enabled()) {
 481         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 482         if (!inited) {
 483             inited = true;
 484             arm_translate_init();
 485         }
 486     }
 487 }
 488
 489 static Property arm_cpu_reset_cbar_property =
 490             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 491
 492 static Property arm_cpu_reset_hivecs_property =
 493             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 494
 495 static Property arm_cpu_rvbar_property =
 496             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 497
 498 static Property arm_cpu_has_el3_property =
 499             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 500
 501 static Property arm_cpu_has_mpu_property =
 502             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 503
 504 static Property arm_cpu_pmsav7_dregion_property =
 505             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 506
 507 static void arm_cpu_post_init(Object *obj)
 508 {
 509     ARMCPU *cpu = ARM_CPU(obj);
 510
 511     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 512         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 513         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 514                                  &error_abort);
 515     }
 516
 517     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 518         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 519                                  &error_abort);
 520     }
 521
 522     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 523         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 524                                  &error_abort);
 525     }
 526
 527     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 528         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 529          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 530          */
 531         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 532                                  &error_abort);
 533
 534 #ifndef CONFIG_USER_ONLY
 535         object_property_add_link(obj, "secure-memory",
 536                                  TYPE_MEMORY_REGION,
 537                                  (Object **)&cpu->secure_memory,
 538                                  qdev_prop_allow_set_link_before_realize,
 539                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 540                                  &error_abort);
 541 #endif
 542     }
 543
 544     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 545         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 546                                  &error_abort);
 547         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 548             qdev_property_add_static(DEVICE(obj),
 549                                      &arm_cpu_pmsav7_dregion_property,
 550                                      &error_abort);
 551         }
 552     }
 553
 554 }
 555
 556 static void arm_cpu_finalizefn(Object *obj)
 557 {
 558     ARMCPU *cpu = ARM_CPU(obj);
 559     g_hash_table_destroy(cpu->cp_regs);
 560 }
 561
 562 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 563 {
 564     CPUState *cs = CPU(dev);
 565     ARMCPU *cpu = ARM_CPU(dev);
 566     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 567     CPUARMState *env = &cpu->env;
 568
 569     /* Some features automatically imply others: */
 570     if (arm_feature(env, ARM_FEATURE_V8)) {
 571         set_feature(env, ARM_FEATURE_V7);
 572         set_feature(env, ARM_FEATURE_ARM_DIV);
 573         set_feature(env, ARM_FEATURE_LPAE);
 574     }
 575     if (arm_feature(env, ARM_FEATURE_V7)) {
 576         set_feature(env, ARM_FEATURE_VAPA);
 577         set_feature(env, ARM_FEATURE_THUMB2);
 578         set_feature(env, ARM_FEATURE_MPIDR);
 579         if (!arm_feature(env, ARM_FEATURE_M)) {
 580             set_feature(env, ARM_FEATURE_V6K);
 581         } else {
 582             set_feature(env, ARM_FEATURE_V6);
 583         }
 584     }
 585     if (arm_feature(env, ARM_FEATURE_V6K)) {
 586         set_feature(env, ARM_FEATURE_V6);
 587         set_feature(env, ARM_FEATURE_MVFR);
 588     }
 589     if (arm_feature(env, ARM_FEATURE_V6)) {
 590         set_feature(env, ARM_FEATURE_V5);
 591         if (!arm_feature(env, ARM_FEATURE_M)) {
 592             set_feature(env, ARM_FEATURE_AUXCR);
 593         }
 594     }
 595     if (arm_feature(env, ARM_FEATURE_V5)) {
 596         set_feature(env, ARM_FEATURE_V4T);
 597     }
 598     if (arm_feature(env, ARM_FEATURE_M)) {
 599         set_feature(env, ARM_FEATURE_THUMB_DIV);
 600     }
 601     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 602         set_feature(env, ARM_FEATURE_THUMB_DIV);
 603     }
 604     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 605         set_feature(env, ARM_FEATURE_VFP3);
 606         set_feature(env, ARM_FEATURE_VFP_FP16);
 607     }
 608     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 609         set_feature(env, ARM_FEATURE_VFP);
 610     }
 611     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 612         set_feature(env, ARM_FEATURE_V7MP);
 613         set_feature(env, ARM_FEATURE_PXN);
 614     }
 615     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 616         set_feature(env, ARM_FEATURE_CBAR);
 617     }
 618     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 619         !arm_feature(env, ARM_FEATURE_M)) {
 620         set_feature(env, ARM_FEATURE_THUMB_DSP);
 621     }
 622
 623     if (cpu->reset_hivecs) {
 624             cpu->reset_sctlr |= (1 << 13);
 625     }
 626
 627     if (!cpu->has_el3) {
 628         /* If the has_el3 CPU property is disabled then we need to disable the
 629          * feature.
 630          */
 631         unset_feature(env, ARM_FEATURE_EL3);
 632
 633         /* Disable the security extension feature bits in the processor feature
 634          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 635          */
 636         cpu->id_pfr1 &= ~0xf0;
 637         cpu->id_aa64pfr0 &= ~0xf000;
 638     }
 639
 640     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 641         /* Disable the hypervisor feature bits in the processor feature
 642          * registers if we don't have EL2. These are id_pfr1[15:12] and
 643          * id_aa64pfr0_el1[11:8].
 644          */
 645         cpu->id_aa64pfr0 &= ~0xf00;
 646         cpu->id_pfr1 &= ~0xf000;
 647     }
 648
 649     if (!cpu->has_mpu) {
 650         unset_feature(env, ARM_FEATURE_MPU);
 651     }
 652
 653     if (arm_feature(env, ARM_FEATURE_MPU) &&
 654         arm_feature(env, ARM_FEATURE_V7)) {
 655         uint32_t nr = cpu->pmsav7_dregion;
 656
 657         if (nr > 0xff) {
 658             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 659             return;
 660         }
 661
 662         if (nr) {
 663             env->pmsav7.drbar = g_new0(uint32_t, nr);
 664             env->pmsav7.drsr = g_new0(uint32_t, nr);
 665             env->pmsav7.dracr = g_new0(uint32_t, nr);
 666         }
 667     }
 668
 669     register_cp_regs_for_features(cpu);
 670     arm_cpu_register_gdb_regs_for_features(cpu);
 671
 672     init_cpreg_list(cpu);
 673
 674 #ifndef CONFIG_USER_ONLY
 675     if (cpu->has_el3) {
 676         cs->num_ases = 2;
 677     } else {
 678         cs->num_ases = 1;
 679     }
 680
 681     if (cpu->has_el3) {
 682         AddressSpace *as;
 683
 684         if (!cpu->secure_memory) {
 685             cpu->secure_memory = cs->memory;
 686         }
 687         as = address_space_init_shareable(cpu->secure_memory,
 688                                           "cpu-secure-memory");
 689         cpu_address_space_init(cs, as, ARMASIdx_S);
 690     }
 691     cpu_address_space_init(cs,
 692                            address_space_init_shareable(cs->memory,
 693                                                         "cpu-memory"),
 694                            ARMASIdx_NS);
 695 #endif
 696
 697     qemu_init_vcpu(cs);
 698     cpu_reset(cs);
 699
 700     acc->parent_realize(dev, errp);
 701 }
 702
 703 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 704 {
 705     ObjectClass *oc;
 706     char *typename;
 707     char **cpuname;
 708
 709     if (!cpu_model) {
 710         return NULL;
 711     }
 712
 713     cpuname = g_strsplit(cpu_model, ",", 1);
 714     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 715     oc = object_class_by_name(typename);
 716     g_strfreev(cpuname);
 717     g_free(typename);
 718     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 719         object_class_is_abstract(oc)) {
 720         return NULL;
 721     }
 722     return oc;
 723 }
 724
 725 /* CPU models. These are not needed for the AArch64 linux-user build. */
 726 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 727
 728 static void arm926_initfn(Object *obj)
 729 {
 730     ARMCPU *cpu = ARM_CPU(obj);
 731
 732     cpu->dtb_compatible = "arm,arm926";
 733     set_feature(&cpu->env, ARM_FEATURE_V5);
 734     set_feature(&cpu->env, ARM_FEATURE_VFP);
 735     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 736     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 737     cpu->midr = 0x41069265;
 738     cpu->reset_fpsid = 0x41011090;
 739     cpu->ctr = 0x1dd20d2;
 740     cpu->reset_sctlr = 0x00090078;
 741 }
 742
 743 static void arm946_initfn(Object *obj)
 744 {
 745     ARMCPU *cpu = ARM_CPU(obj);
 746
 747     cpu->dtb_compatible = "arm,arm946";
 748     set_feature(&cpu->env, ARM_FEATURE_V5);
 749     set_feature(&cpu->env, ARM_FEATURE_MPU);
 750     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 751     cpu->midr = 0x41059461;
 752     cpu->ctr = 0x0f004006;
 753     cpu->reset_sctlr = 0x00000078;
 754 }
 755
 756 static void arm1026_initfn(Object *obj)
 757 {
 758     ARMCPU *cpu = ARM_CPU(obj);
 759
 760     cpu->dtb_compatible = "arm,arm1026";
 761     set_feature(&cpu->env, ARM_FEATURE_V5);
 762     set_feature(&cpu->env, ARM_FEATURE_VFP);
 763     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 764     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 765     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 766     cpu->midr = 0x4106a262;
 767     cpu->reset_fpsid = 0x410110a0;
 768     cpu->ctr = 0x1dd20d2;
 769     cpu->reset_sctlr = 0x00090078;
 770     cpu->reset_auxcr = 1;
 771     {
 772         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 773         ARMCPRegInfo ifar = {
 774             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 775             .access = PL1_RW,
 776             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 777             .resetvalue = 0
 778         };
 779         define_one_arm_cp_reg(cpu, &ifar);
 780     }
 781 }
 782
 783 static void arm1136_r2_initfn(Object *obj)
 784 {
 785     ARMCPU *cpu = ARM_CPU(obj);
 786     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 787      * older core than plain "arm1136". In particular this does not
 788      * have the v6K features.
 789      * These ID register values are correct for 1136 but may be wrong
 790      * for 1136_r2 (in particular r0p2 does not actually implement most
 791      * of the ID registers).
 792      */
 793
 794     cpu->dtb_compatible = "arm,arm1136";
 795     set_feature(&cpu->env, ARM_FEATURE_V6);
 796     set_feature(&cpu->env, ARM_FEATURE_VFP);
 797     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 798     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 799     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 800     cpu->midr = 0x4107b362;
 801     cpu->reset_fpsid = 0x410120b4;
 802     cpu->mvfr0 = 0x11111111;
 803     cpu->mvfr1 = 0x00000000;
 804     cpu->ctr = 0x1dd20d2;
 805     cpu->reset_sctlr = 0x00050078;
 806     cpu->id_pfr0 = 0x111;
 807     cpu->id_pfr1 = 0x1;
 808     cpu->id_dfr0 = 0x2;
 809     cpu->id_afr0 = 0x3;
 810     cpu->id_mmfr0 = 0x01130003;
 811     cpu->id_mmfr1 = 0x10030302;
 812     cpu->id_mmfr2 = 0x01222110;
 813     cpu->id_isar0 = 0x00140011;
 814     cpu->id_isar1 = 0x12002111;
 815     cpu->id_isar2 = 0x11231111;
 816     cpu->id_isar3 = 0x01102131;
 817     cpu->id_isar4 = 0x141;
 818     cpu->reset_auxcr = 7;
 819 }
 820
 821 static void arm1136_initfn(Object *obj)
 822 {
 823     ARMCPU *cpu = ARM_CPU(obj);
 824
 825     cpu->dtb_compatible = "arm,arm1136";
 826     set_feature(&cpu->env, ARM_FEATURE_V6K);
 827     set_feature(&cpu->env, ARM_FEATURE_V6);
 828     set_feature(&cpu->env, ARM_FEATURE_VFP);
 829     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 830     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 831     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 832     cpu->midr = 0x4117b363;
 833     cpu->reset_fpsid = 0x410120b4;
 834     cpu->mvfr0 = 0x11111111;
 835     cpu->mvfr1 = 0x00000000;
 836     cpu->ctr = 0x1dd20d2;
 837     cpu->reset_sctlr = 0x00050078;
 838     cpu->id_pfr0 = 0x111;
 839     cpu->id_pfr1 = 0x1;
 840     cpu->id_dfr0 = 0x2;
 841     cpu->id_afr0 = 0x3;
 842     cpu->id_mmfr0 = 0x01130003;
 843     cpu->id_mmfr1 = 0x10030302;
 844     cpu->id_mmfr2 = 0x01222110;
 845     cpu->id_isar0 = 0x00140011;
 846     cpu->id_isar1 = 0x12002111;
 847     cpu->id_isar2 = 0x11231111;
 848     cpu->id_isar3 = 0x01102131;
 849     cpu->id_isar4 = 0x141;
 850     cpu->reset_auxcr = 7;
 851 }
 852
 853 static void arm1176_initfn(Object *obj)
 854 {
 855     ARMCPU *cpu = ARM_CPU(obj);
 856
 857     cpu->dtb_compatible = "arm,arm1176";
 858     set_feature(&cpu->env, ARM_FEATURE_V6K);
 859     set_feature(&cpu->env, ARM_FEATURE_VFP);
 860     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 861     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 862     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 863     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 864     set_feature(&cpu->env, ARM_FEATURE_EL3);
 865     cpu->midr = 0x410fb767;
 866     cpu->reset_fpsid = 0x410120b5;
 867     cpu->mvfr0 = 0x11111111;
 868     cpu->mvfr1 = 0x00000000;
 869     cpu->ctr = 0x1dd20d2;
 870     cpu->reset_sctlr = 0x00050078;
 871     cpu->id_pfr0 = 0x111;
 872     cpu->id_pfr1 = 0x11;
 873     cpu->id_dfr0 = 0x33;
 874     cpu->id_afr0 = 0;
 875     cpu->id_mmfr0 = 0x01130003;
 876     cpu->id_mmfr1 = 0x10030302;
 877     cpu->id_mmfr2 = 0x01222100;
 878     cpu->id_isar0 = 0x0140011;
 879     cpu->id_isar1 = 0x12002111;
 880     cpu->id_isar2 = 0x11231121;
 881     cpu->id_isar3 = 0x01102131;
 882     cpu->id_isar4 = 0x01141;
 883     cpu->reset_auxcr = 7;
 884 }
 885
 886 static void arm11mpcore_initfn(Object *obj)
 887 {
 888     ARMCPU *cpu = ARM_CPU(obj);
 889
 890     cpu->dtb_compatible = "arm,arm11mpcore";
 891     set_feature(&cpu->env, ARM_FEATURE_V6K);
 892     set_feature(&cpu->env, ARM_FEATURE_VFP);
 893     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 894     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 895     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 896     cpu->midr = 0x410fb022;
 897     cpu->reset_fpsid = 0x410120b4;
 898     cpu->mvfr0 = 0x11111111;
 899     cpu->mvfr1 = 0x00000000;
 900     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 901     cpu->id_pfr0 = 0x111;
 902     cpu->id_pfr1 = 0x1;
 903     cpu->id_dfr0 = 0;
 904     cpu->id_afr0 = 0x2;
 905     cpu->id_mmfr0 = 0x01100103;
 906     cpu->id_mmfr1 = 0x10020302;
 907     cpu->id_mmfr2 = 0x01222000;
 908     cpu->id_isar0 = 0x00100011;
 909     cpu->id_isar1 = 0x12002111;
 910     cpu->id_isar2 = 0x11221011;
 911     cpu->id_isar3 = 0x01102131;
 912     cpu->id_isar4 = 0x141;
 913     cpu->reset_auxcr = 1;
 914 }
 915
 916 static void cortex_m3_initfn(Object *obj)
 917 {
 918     ARMCPU *cpu = ARM_CPU(obj);
 919     set_feature(&cpu->env, ARM_FEATURE_V7);
 920     set_feature(&cpu->env, ARM_FEATURE_M);
 921     cpu->midr = 0x410fc231;
 922 }
 923
 924 static void cortex_m4_initfn(Object *obj)
 925 {
 926     ARMCPU *cpu = ARM_CPU(obj);
 927
 928     set_feature(&cpu->env, ARM_FEATURE_V7);
 929     set_feature(&cpu->env, ARM_FEATURE_M);
 930     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 931     cpu->midr = 0x410fc240; /* r0p0 */
 932 }
 933 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 934 {
 935     CPUClass *cc = CPU_CLASS(oc);
 936
 937 #ifndef CONFIG_USER_ONLY
 938     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 939 #endif
 940
 941     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 942 }
 943
 944 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 945     /* Dummy the TCM region regs for the moment */
 946     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 947       .access = PL1_RW, .type = ARM_CP_CONST },
 948     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 949       .access = PL1_RW, .type = ARM_CP_CONST },
 950     REGINFO_SENTINEL
 951 };
 952
 953 static void cortex_r5_initfn(Object *obj)
 954 {
 955     ARMCPU *cpu = ARM_CPU(obj);
 956
 957     set_feature(&cpu->env, ARM_FEATURE_V7);
 958     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 959     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 960     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 961     set_feature(&cpu->env, ARM_FEATURE_MPU);
 962     cpu->midr = 0x411fc153; /* r1p3 */
 963     cpu->id_pfr0 = 0x0131;
 964     cpu->id_pfr1 = 0x001;
 965     cpu->id_dfr0 = 0x010400;
 966     cpu->id_afr0 = 0x0;
 967     cpu->id_mmfr0 = 0x0210030;
 968     cpu->id_mmfr1 = 0x00000000;
 969     cpu->id_mmfr2 = 0x01200000;
 970     cpu->id_mmfr3 = 0x0211;
 971     cpu->id_isar0 = 0x2101111;
 972     cpu->id_isar1 = 0x13112111;
 973     cpu->id_isar2 = 0x21232141;
 974     cpu->id_isar3 = 0x01112131;
 975     cpu->id_isar4 = 0x0010142;
 976     cpu->id_isar5 = 0x0;
 977     cpu->mp_is_up = true;
 978     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 979 }
 980
 981 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 982     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 983       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 984     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 985       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 986     REGINFO_SENTINEL
 987 };
 988
 989 static void cortex_a8_initfn(Object *obj)
 990 {
 991     ARMCPU *cpu = ARM_CPU(obj);
 992
 993     cpu->dtb_compatible = "arm,cortex-a8";
 994     set_feature(&cpu->env, ARM_FEATURE_V7);
 995     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 996     set_feature(&cpu->env, ARM_FEATURE_NEON);
 997     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 998     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 999     set_feature(&cpu->env, ARM_FEATURE_EL3);
1000     cpu->midr = 0x410fc080;
1001     cpu->reset_fpsid = 0x410330c0;
1002     cpu->mvfr0 = 0x11110222;
1003     cpu->mvfr1 = 0x00011100;
1004     cpu->ctr = 0x82048004;
1005     cpu->reset_sctlr = 0x00c50078;
1006     cpu->id_pfr0 = 0x1031;
1007     cpu->id_pfr1 = 0x11;
1008     cpu->id_dfr0 = 0x400;
1009     cpu->id_afr0 = 0;
1010     cpu->id_mmfr0 = 0x31100003;
1011     cpu->id_mmfr1 = 0x20000000;
1012     cpu->id_mmfr2 = 0x01202000;
1013     cpu->id_mmfr3 = 0x11;
1014     cpu->id_isar0 = 0x00101111;
1015     cpu->id_isar1 = 0x12112111;
1016     cpu->id_isar2 = 0x21232031;
1017     cpu->id_isar3 = 0x11112131;
1018     cpu->id_isar4 = 0x00111142;
1019     cpu->dbgdidr = 0x15141000;
1020     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1021     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1022     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1023     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1024     cpu->reset_auxcr = 2;
1025     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1026 }
1027
1028 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1029     /* power_control should be set to maximum latency. Again,
1030      * default to 0 and set by private hook
1031      */
1032     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1033       .access = PL1_RW, .resetvalue = 0,
1034       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1035     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1036       .access = PL1_RW, .resetvalue = 0,
1037       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1038     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1039       .access = PL1_RW, .resetvalue = 0,
1040       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1041     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1042       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1043     /* TLB lockdown control */
1044     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1045       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1046     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1047       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1048     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1049       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1050     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1051       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1052     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1053       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1054     REGINFO_SENTINEL
1055 };
1056
1057 static void cortex_a9_initfn(Object *obj)
1058 {
1059     ARMCPU *cpu = ARM_CPU(obj);
1060
1061     cpu->dtb_compatible = "arm,cortex-a9";
1062     set_feature(&cpu->env, ARM_FEATURE_V7);
1063     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1064     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1065     set_feature(&cpu->env, ARM_FEATURE_NEON);
1066     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1067     set_feature(&cpu->env, ARM_FEATURE_EL3);
1068     /* Note that A9 supports the MP extensions even for
1069      * A9UP and single-core A9MP (which are both different
1070      * and valid configurations; we don't model A9UP).
1071      */
1072     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1073     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1074     cpu->midr = 0x410fc090;
1075     cpu->reset_fpsid = 0x41033090;
1076     cpu->mvfr0 = 0x11110222;
1077     cpu->mvfr1 = 0x01111111;
1078     cpu->ctr = 0x80038003;
1079     cpu->reset_sctlr = 0x00c50078;
1080     cpu->id_pfr0 = 0x1031;
1081     cpu->id_pfr1 = 0x11;
1082     cpu->id_dfr0 = 0x000;
1083     cpu->id_afr0 = 0;
1084     cpu->id_mmfr0 = 0x00100103;
1085     cpu->id_mmfr1 = 0x20000000;
1086     cpu->id_mmfr2 = 0x01230000;
1087     cpu->id_mmfr3 = 0x00002111;
1088     cpu->id_isar0 = 0x00101111;
1089     cpu->id_isar1 = 0x13112111;
1090     cpu->id_isar2 = 0x21232041;
1091     cpu->id_isar3 = 0x11112131;
1092     cpu->id_isar4 = 0x00111142;
1093     cpu->dbgdidr = 0x35141000;
1094     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1095     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1096     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1097     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1098 }
1099
1100 #ifndef CONFIG_USER_ONLY
1101 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1102 {
1103     /* Linux wants the number of processors from here.
1104      * Might as well set the interrupt-controller bit too.
1105      */
1106     return ((smp_cpus - 1) << 24) | (1 << 23);
1107 }
1108 #endif
1109
1110 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1111 #ifndef CONFIG_USER_ONLY
1112     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1113       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1114       .writefn = arm_cp_write_ignore, },
1115 #endif
1116     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1117       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1118     REGINFO_SENTINEL
1119 };
1120
1121 static void cortex_a15_initfn(Object *obj)
1122 {
1123     ARMCPU *cpu = ARM_CPU(obj);
1124
1125     cpu->dtb_compatible = "arm,cortex-a15";
1126     set_feature(&cpu->env, ARM_FEATURE_V7);
1127     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1128     set_feature(&cpu->env, ARM_FEATURE_NEON);
1129     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1130     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1131     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1132     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1133     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1134     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1135     set_feature(&cpu->env, ARM_FEATURE_EL3);
1136     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1137     cpu->midr = 0x412fc0f1;
1138     cpu->reset_fpsid = 0x410430f0;
1139     cpu->mvfr0 = 0x10110222;
1140     cpu->mvfr1 = 0x11111111;
1141     cpu->ctr = 0x8444c004;
1142     cpu->reset_sctlr = 0x00c50078;
1143     cpu->id_pfr0 = 0x00001131;
1144     cpu->id_pfr1 = 0x00011011;
1145     cpu->id_dfr0 = 0x02010555;
1146     cpu->pmceid0 = 0x0000000;
1147     cpu->pmceid1 = 0x00000000;
1148     cpu->id_afr0 = 0x00000000;
1149     cpu->id_mmfr0 = 0x10201105;
1150     cpu->id_mmfr1 = 0x20000000;
1151     cpu->id_mmfr2 = 0x01240000;
1152     cpu->id_mmfr3 = 0x02102211;
1153     cpu->id_isar0 = 0x02101110;
1154     cpu->id_isar1 = 0x13112111;
1155     cpu->id_isar2 = 0x21232041;
1156     cpu->id_isar3 = 0x11112131;
1157     cpu->id_isar4 = 0x10011142;
1158     cpu->dbgdidr = 0x3515f021;
1159     cpu->clidr = 0x0a200023;
1160     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1161     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1162     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1163     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1164 }
1165
1166 static void ti925t_initfn(Object *obj)
1167 {
1168     ARMCPU *cpu = ARM_CPU(obj);
1169     set_feature(&cpu->env, ARM_FEATURE_V4T);
1170     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1171     cpu->midr = ARM_CPUID_TI925T;
1172     cpu->ctr = 0x5109149;
1173     cpu->reset_sctlr = 0x00000070;
1174 }
1175
1176 static void sa1100_initfn(Object *obj)
1177 {
1178     ARMCPU *cpu = ARM_CPU(obj);
1179
1180     cpu->dtb_compatible = "intel,sa1100";
1181     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1182     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1183     cpu->midr = 0x4401A11B;
1184     cpu->reset_sctlr = 0x00000070;
1185 }
1186
1187 static void sa1110_initfn(Object *obj)
1188 {
1189     ARMCPU *cpu = ARM_CPU(obj);
1190     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1191     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1192     cpu->midr = 0x6901B119;
1193     cpu->reset_sctlr = 0x00000070;
1194 }
1195
1196 static void pxa250_initfn(Object *obj)
1197 {
1198     ARMCPU *cpu = ARM_CPU(obj);
1199
1200     cpu->dtb_compatible = "marvell,xscale";
1201     set_feature(&cpu->env, ARM_FEATURE_V5);
1202     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1203     cpu->midr = 0x69052100;
1204     cpu->ctr = 0xd172172;
1205     cpu->reset_sctlr = 0x00000078;
1206 }
1207
1208 static void pxa255_initfn(Object *obj)
1209 {
1210     ARMCPU *cpu = ARM_CPU(obj);
1211
1212     cpu->dtb_compatible = "marvell,xscale";
1213     set_feature(&cpu->env, ARM_FEATURE_V5);
1214     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1215     cpu->midr = 0x69052d00;
1216     cpu->ctr = 0xd172172;
1217     cpu->reset_sctlr = 0x00000078;
1218 }
1219
1220 static void pxa260_initfn(Object *obj)
1221 {
1222     ARMCPU *cpu = ARM_CPU(obj);
1223
1224     cpu->dtb_compatible = "marvell,xscale";
1225     set_feature(&cpu->env, ARM_FEATURE_V5);
1226     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1227     cpu->midr = 0x69052903;
1228     cpu->ctr = 0xd172172;
1229     cpu->reset_sctlr = 0x00000078;
1230 }
1231
1232 static void pxa261_initfn(Object *obj)
1233 {
1234     ARMCPU *cpu = ARM_CPU(obj);
1235
1236     cpu->dtb_compatible = "marvell,xscale";
1237     set_feature(&cpu->env, ARM_FEATURE_V5);
1238     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1239     cpu->midr = 0x69052d05;
1240     cpu->ctr = 0xd172172;
1241     cpu->reset_sctlr = 0x00000078;
1242 }
1243
1244 static void pxa262_initfn(Object *obj)
1245 {
1246     ARMCPU *cpu = ARM_CPU(obj);
1247
1248     cpu->dtb_compatible = "marvell,xscale";
1249     set_feature(&cpu->env, ARM_FEATURE_V5);
1250     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1251     cpu->midr = 0x69052d06;
1252     cpu->ctr = 0xd172172;
1253     cpu->reset_sctlr = 0x00000078;
1254 }
1255
1256 static void pxa270a0_initfn(Object *obj)
1257 {
1258     ARMCPU *cpu = ARM_CPU(obj);
1259
1260     cpu->dtb_compatible = "marvell,xscale";
1261     set_feature(&cpu->env, ARM_FEATURE_V5);
1262     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1263     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1264     cpu->midr = 0x69054110;
1265     cpu->ctr = 0xd172172;
1266     cpu->reset_sctlr = 0x00000078;
1267 }
1268
1269 static void pxa270a1_initfn(Object *obj)
1270 {
1271     ARMCPU *cpu = ARM_CPU(obj);
1272
1273     cpu->dtb_compatible = "marvell,xscale";
1274     set_feature(&cpu->env, ARM_FEATURE_V5);
1275     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1276     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1277     cpu->midr = 0x69054111;
1278     cpu->ctr = 0xd172172;
1279     cpu->reset_sctlr = 0x00000078;
1280 }
1281
1282 static void pxa270b0_initfn(Object *obj)
1283 {
1284     ARMCPU *cpu = ARM_CPU(obj);
1285
1286     cpu->dtb_compatible = "marvell,xscale";
1287     set_feature(&cpu->env, ARM_FEATURE_V5);
1288     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1289     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1290     cpu->midr = 0x69054112;
1291     cpu->ctr = 0xd172172;
1292     cpu->reset_sctlr = 0x00000078;
1293 }
1294
1295 static void pxa270b1_initfn(Object *obj)
1296 {
1297     ARMCPU *cpu = ARM_CPU(obj);
1298
1299     cpu->dtb_compatible = "marvell,xscale";
1300     set_feature(&cpu->env, ARM_FEATURE_V5);
1301     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1302     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1303     cpu->midr = 0x69054113;
1304     cpu->ctr = 0xd172172;
1305     cpu->reset_sctlr = 0x00000078;
1306 }
1307
1308 static void pxa270c0_initfn(Object *obj)
1309 {
1310     ARMCPU *cpu = ARM_CPU(obj);
1311
1312     cpu->dtb_compatible = "marvell,xscale";
1313     set_feature(&cpu->env, ARM_FEATURE_V5);
1314     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1315     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1316     cpu->midr = 0x69054114;
1317     cpu->ctr = 0xd172172;
1318     cpu->reset_sctlr = 0x00000078;
1319 }
1320
1321 static void pxa270c5_initfn(Object *obj)
1322 {
1323     ARMCPU *cpu = ARM_CPU(obj);
1324
1325     cpu->dtb_compatible = "marvell,xscale";
1326     set_feature(&cpu->env, ARM_FEATURE_V5);
1327     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1328     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1329     cpu->midr = 0x69054117;
1330     cpu->ctr = 0xd172172;
1331     cpu->reset_sctlr = 0x00000078;
1332 }
1333
1334 #ifdef CONFIG_USER_ONLY
1335 static void arm_any_initfn(Object *obj)
1336 {
1337     ARMCPU *cpu = ARM_CPU(obj);
1338     set_feature(&cpu->env, ARM_FEATURE_V8);
1339     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1340     set_feature(&cpu->env, ARM_FEATURE_NEON);
1341     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1342     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1343     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1344     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1345     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1346     set_feature(&cpu->env, ARM_FEATURE_CRC);
1347     cpu->midr = 0xffffffff;
1348 }
1349 #endif
1350
1351 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1352
1353 typedef struct ARMCPUInfo {
1354     const char *name;
1355     void (*initfn)(Object *obj);
1356     void (*class_init)(ObjectClass *oc, void *data);
1357 } ARMCPUInfo;
1358
1359 static const ARMCPUInfo arm_cpus[] = {
1360 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1361     { .name = "arm926",      .initfn = arm926_initfn },
1362     { .name = "arm946",      .initfn = arm946_initfn },
1363     { .name = "arm1026",     .initfn = arm1026_initfn },
1364     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1365      * older core than plain "arm1136". In particular this does not
1366      * have the v6K features.
1367      */
1368     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1369     { .name = "arm1136",     .initfn = arm1136_initfn },
1370     { .name = "arm1176",     .initfn = arm1176_initfn },
1371     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1372     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1373                              .class_init = arm_v7m_class_init },
1374     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1375                              .class_init = arm_v7m_class_init },
1376     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1377     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1378     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1379     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1380     { .name = "ti925t",      .initfn = ti925t_initfn },
1381     { .name = "sa1100",      .initfn = sa1100_initfn },
1382     { .name = "sa1110",      .initfn = sa1110_initfn },
1383     { .name = "pxa250",      .initfn = pxa250_initfn },
1384     { .name = "pxa255",      .initfn = pxa255_initfn },
1385     { .name = "pxa260",      .initfn = pxa260_initfn },
1386     { .name = "pxa261",      .initfn = pxa261_initfn },
1387     { .name = "pxa262",      .initfn = pxa262_initfn },
1388     /* "pxa270" is an alias for "pxa270-a0" */
1389     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1390     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1391     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1392     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1393     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1394     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1395     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1396 #ifdef CONFIG_USER_ONLY
1397     { .name = "any",         .initfn = arm_any_initfn },
1398 #endif
1399 #endif
1400     { .name = NULL }
1401 };
1402
1403 static Property arm_cpu_properties[] = {
1404     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1405     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1406     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1407     DEFINE_PROP_END_OF_LIST()
1408 };
1409
1410 #ifdef CONFIG_USER_ONLY
1411 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1412                                     int mmu_idx)
1413 {
1414     ARMCPU *cpu = ARM_CPU(cs);
1415     CPUARMState *env = &cpu->env;
1416
1417     env->exception.vaddress = address;
1418     if (rw == 2) {
1419         cs->exception_index = EXCP_PREFETCH_ABORT;
1420     } else {
1421         cs->exception_index = EXCP_DATA_ABORT;
1422     }
1423     return 1;
1424 }
1425 #endif
1426
1427 static gchar *arm_gdb_arch_name(CPUState *cs)
1428 {
1429     ARMCPU *cpu = ARM_CPU(cs);
1430     CPUARMState *env = &cpu->env;
1431
1432     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1433         return g_strdup("iwmmxt");
1434     }
1435     return g_strdup("arm");
1436 }
1437
1438 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1439 {
1440     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1441     CPUClass *cc = CPU_CLASS(acc);
1442     DeviceClass *dc = DEVICE_CLASS(oc);
1443
1444     acc->parent_realize = dc->realize;
1445     dc->realize = arm_cpu_realizefn;
1446     dc->props = arm_cpu_properties;
1447
1448     acc->parent_reset = cc->reset;
1449     cc->reset = arm_cpu_reset;
1450
1451     cc->class_by_name = arm_cpu_class_by_name;
1452     cc->has_work = arm_cpu_has_work;
1453     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1454     cc->dump_state = arm_cpu_dump_state;
1455     cc->set_pc = arm_cpu_set_pc;
1456     cc->gdb_read_register = arm_cpu_gdb_read_register;
1457     cc->gdb_write_register = arm_cpu_gdb_write_register;
1458 #ifdef CONFIG_USER_ONLY
1459     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1460 #else
1461     cc->do_interrupt = arm_cpu_do_interrupt;
1462     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1463     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1464     cc->asidx_from_attrs = arm_asidx_from_attrs;
1465     cc->vmsd = &vmstate_arm_cpu;
1466     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1467     cc->write_elf64_note = arm_cpu_write_elf64_note;
1468     cc->write_elf32_note = arm_cpu_write_elf32_note;
1469 #endif
1470     cc->gdb_num_core_regs = 26;
1471     cc->gdb_core_xml_file = "arm-core.xml";
1472     cc->gdb_arch_name = arm_gdb_arch_name;
1473     cc->gdb_stop_before_watchpoint = true;
1474     cc->debug_excp_handler = arm_debug_excp_handler;
1475     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1476
1477     cc->disas_set_info = arm_disas_set_info;
1478
1479     /*
1480      * Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves
1481      * the object in cpus -> dangling pointer after final
1482      * object_unref().
1483      *
1484      * Once this is fixed, the devices that create ARM CPUs should be
1485      * updated not to set cannot_destroy_with_object_finalize_yet,
1486      * unless they still screw up something else.
1487      */
1488     dc->cannot_destroy_with_object_finalize_yet = true;
1489 }
1490
1491 static void cpu_register(const ARMCPUInfo *info)
1492 {
1493     TypeInfo type_info = {
1494         .parent = TYPE_ARM_CPU,
1495         .instance_size = sizeof(ARMCPU),
1496         .instance_init = info->initfn,
1497         .class_size = sizeof(ARMCPUClass),
1498         .class_init = info->class_init,
1499     };
1500
1501     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1502     type_register(&type_info);
1503     g_free((void *)type_info.name);
1504 }
1505
1506 static const TypeInfo arm_cpu_type_info = {
1507     .name = TYPE_ARM_CPU,
1508     .parent = TYPE_CPU,
1509     .instance_size = sizeof(ARMCPU),
1510     .instance_init = arm_cpu_initfn,
1511     .instance_post_init = arm_cpu_post_init,
1512     .instance_finalize = arm_cpu_finalizefn,
1513     .abstract = true,
1514     .class_size = sizeof(ARMCPUClass),
1515     .class_init = arm_cpu_class_init,
1516 };
1517
1518 static void arm_cpu_register_types(void)
1519 {
1520     const ARMCPUInfo *info = arm_cpus;
1521
1522     type_register_static(&arm_cpu_type_info);
1523
1524     while (info->name) {
1525         cpu_register(info);
1526         info++;
1527     }
1528 }
1529
1530 type_init(arm_cpu_register_types)