4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat-helpers.h"
30 static void superh_cpu_set_pc(CPUState
*cs
, vaddr value
)
32 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
37 static void superh_cpu_synchronize_from_tb(CPUState
*cs
,
38 const TranslationBlock
*tb
)
40 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
43 cpu
->env
.flags
= tb
->flags
& TB_FLAG_ENVFLAGS_MASK
;
46 #ifndef CONFIG_USER_ONLY
47 static bool superh_io_recompile_replay_branch(CPUState
*cs
,
48 const TranslationBlock
*tb
)
50 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
51 CPUSH4State
*env
= &cpu
->env
;
53 if ((env
->flags
& ((DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
))) != 0
54 && env
->pc
!= tb
->pc
) {
56 env
->flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
);
63 static bool superh_cpu_has_work(CPUState
*cs
)
65 return cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
68 static void superh_cpu_reset(DeviceState
*dev
)
70 CPUState
*s
= CPU(dev
);
71 SuperHCPU
*cpu
= SUPERH_CPU(s
);
72 SuperHCPUClass
*scc
= SUPERH_CPU_GET_CLASS(cpu
);
73 CPUSH4State
*env
= &cpu
->env
;
75 scc
->parent_reset(dev
);
77 memset(env
, 0, offsetof(CPUSH4State
, end_reset_fields
));
80 #if defined(CONFIG_USER_ONLY)
81 env
->fpscr
= FPSCR_PR
; /* value for userspace according to the kernel */
82 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
); /* ?! */
84 env
->sr
= (1u << SR_MD
) | (1u << SR_RB
) | (1u << SR_BL
) |
85 (1u << SR_I3
) | (1u << SR_I2
) | (1u << SR_I1
) | (1u << SR_I0
);
86 env
->fpscr
= FPSCR_DN
| FPSCR_RM_ZERO
; /* CPU reset value according to SH4 manual */
87 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
88 set_flush_to_zero(1, &env
->fp_status
);
90 set_default_nan_mode(1, &env
->fp_status
);
93 static void superh_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
95 info
->mach
= bfd_mach_sh4
;
96 info
->print_insn
= print_insn_sh
;
99 static void superh_cpu_list_entry(gpointer data
, gpointer user_data
)
101 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
102 int len
= strlen(typename
) - strlen(SUPERH_CPU_TYPE_SUFFIX
);
104 qemu_printf("%.*s\n", len
, typename
);
107 void sh4_cpu_list(void)
111 list
= object_class_get_list_sorted(TYPE_SUPERH_CPU
, false);
112 g_slist_foreach(list
, superh_cpu_list_entry
, NULL
);
116 static ObjectClass
*superh_cpu_class_by_name(const char *cpu_model
)
119 char *s
, *typename
= NULL
;
121 s
= g_ascii_strdown(cpu_model
, -1);
122 if (strcmp(s
, "any") == 0) {
123 oc
= object_class_by_name(TYPE_SH7750R_CPU
);
127 typename
= g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s
);
128 oc
= object_class_by_name(typename
);
129 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
139 static void sh7750r_cpu_initfn(Object
*obj
)
141 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
142 CPUSH4State
*env
= &cpu
->env
;
144 env
->id
= SH_CPU_SH7750R
;
145 env
->features
= SH_FEATURE_BCR3_AND_BCR4
;
148 static void sh7750r_class_init(ObjectClass
*oc
, void *data
)
150 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
152 scc
->pvr
= 0x00050000;
153 scc
->prr
= 0x00000100;
154 scc
->cvr
= 0x00110000;
157 static void sh7751r_cpu_initfn(Object
*obj
)
159 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
160 CPUSH4State
*env
= &cpu
->env
;
162 env
->id
= SH_CPU_SH7751R
;
163 env
->features
= SH_FEATURE_BCR3_AND_BCR4
;
166 static void sh7751r_class_init(ObjectClass
*oc
, void *data
)
168 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
170 scc
->pvr
= 0x04050005;
171 scc
->prr
= 0x00000113;
172 scc
->cvr
= 0x00110000; /* Neutered caches, should be 0x20480000 */
175 static void sh7785_cpu_initfn(Object
*obj
)
177 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
178 CPUSH4State
*env
= &cpu
->env
;
180 env
->id
= SH_CPU_SH7785
;
181 env
->features
= SH_FEATURE_SH4A
;
184 static void sh7785_class_init(ObjectClass
*oc
, void *data
)
186 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
188 scc
->pvr
= 0x10300700;
189 scc
->prr
= 0x00000200;
190 scc
->cvr
= 0x71440211;
193 static void superh_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
195 CPUState
*cs
= CPU(dev
);
196 SuperHCPUClass
*scc
= SUPERH_CPU_GET_CLASS(dev
);
197 Error
*local_err
= NULL
;
199 cpu_exec_realizefn(cs
, &local_err
);
200 if (local_err
!= NULL
) {
201 error_propagate(errp
, local_err
);
208 scc
->parent_realize(dev
, errp
);
211 static void superh_cpu_initfn(Object
*obj
)
213 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
214 CPUSH4State
*env
= &cpu
->env
;
216 cpu_set_cpustate_pointers(cpu
);
218 env
->movcal_backup_tail
= &(env
->movcal_backup
);
221 #ifndef CONFIG_USER_ONLY
222 static const VMStateDescription vmstate_sh_cpu
= {
227 #include "hw/core/sysemu-cpu-ops.h"
229 static const struct SysemuCPUOps sh4_sysemu_ops
= {
230 .get_phys_page_debug
= superh_cpu_get_phys_page_debug
,
234 #include "hw/core/tcg-cpu-ops.h"
236 static const struct TCGCPUOps superh_tcg_ops
= {
237 .initialize
= sh4_translate_init
,
238 .synchronize_from_tb
= superh_cpu_synchronize_from_tb
,
240 #ifndef CONFIG_USER_ONLY
241 .tlb_fill
= superh_cpu_tlb_fill
,
242 .cpu_exec_interrupt
= superh_cpu_exec_interrupt
,
243 .do_interrupt
= superh_cpu_do_interrupt
,
244 .do_unaligned_access
= superh_cpu_do_unaligned_access
,
245 .io_recompile_replay_branch
= superh_io_recompile_replay_branch
,
246 #endif /* !CONFIG_USER_ONLY */
249 static void superh_cpu_class_init(ObjectClass
*oc
, void *data
)
251 DeviceClass
*dc
= DEVICE_CLASS(oc
);
252 CPUClass
*cc
= CPU_CLASS(oc
);
253 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
255 device_class_set_parent_realize(dc
, superh_cpu_realizefn
,
256 &scc
->parent_realize
);
258 device_class_set_parent_reset(dc
, superh_cpu_reset
, &scc
->parent_reset
);
260 cc
->class_by_name
= superh_cpu_class_by_name
;
261 cc
->has_work
= superh_cpu_has_work
;
262 cc
->dump_state
= superh_cpu_dump_state
;
263 cc
->set_pc
= superh_cpu_set_pc
;
264 cc
->gdb_read_register
= superh_cpu_gdb_read_register
;
265 cc
->gdb_write_register
= superh_cpu_gdb_write_register
;
266 #ifndef CONFIG_USER_ONLY
267 cc
->sysemu_ops
= &sh4_sysemu_ops
;
268 dc
->vmsd
= &vmstate_sh_cpu
;
270 cc
->disas_set_info
= superh_cpu_disas_set_info
;
272 cc
->gdb_num_core_regs
= 59;
273 cc
->tcg_ops
= &superh_tcg_ops
;
276 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
279 .parent = TYPE_SUPERH_CPU, \
280 .class_init = cinit, \
281 .instance_init = initfn, \
283 static const TypeInfo superh_cpu_type_infos
[] = {
285 .name
= TYPE_SUPERH_CPU
,
287 .instance_size
= sizeof(SuperHCPU
),
288 .instance_init
= superh_cpu_initfn
,
290 .class_size
= sizeof(SuperHCPUClass
),
291 .class_init
= superh_cpu_class_init
,
293 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU
, sh7750r_class_init
,
295 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU
, sh7751r_class_init
,
297 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU
, sh7785_class_init
,
302 DEFINE_TYPES(superh_cpu_type_infos
)