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target/ppc: Move SPR_DSISR setting to powerpc_excp
[qemu/ar7.git] / hw / arm / aspeed_soc.c
blob7d53cf2f513327ef244741299567aa058324aff5
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/misc/unimp.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/char/serial.h"
18 #include "qemu/module.h"
19 #include "qemu/error-report.h"
20 #include "hw/i2c/aspeed_i2c.h"
21 #include "net/net.h"
22 #include "sysemu/sysemu.h"
23
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
25
26 static const hwaddr aspeed_soc_ast2400_memmap[] = {
27 [ASPEED_DEV_IOMEM] = 0x1E600000,
28 [ASPEED_DEV_FMC] = 0x1E620000,
29 [ASPEED_DEV_SPI1] = 0x1E630000,
30 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
31 [ASPEED_DEV_VIC] = 0x1E6C0000,
32 [ASPEED_DEV_SDMC] = 0x1E6E0000,
33 [ASPEED_DEV_SCU] = 0x1E6E2000,
34 [ASPEED_DEV_HACE] = 0x1E6E3000,
35 [ASPEED_DEV_XDMA] = 0x1E6E7000,
36 [ASPEED_DEV_VIDEO] = 0x1E700000,
37 [ASPEED_DEV_ADC] = 0x1E6E9000,
38 [ASPEED_DEV_SRAM] = 0x1E720000,
39 [ASPEED_DEV_SDHCI] = 0x1E740000,
40 [ASPEED_DEV_GPIO] = 0x1E780000,
41 [ASPEED_DEV_RTC] = 0x1E781000,
42 [ASPEED_DEV_TIMER1] = 0x1E782000,
43 [ASPEED_DEV_WDT] = 0x1E785000,
44 [ASPEED_DEV_PWM] = 0x1E786000,
45 [ASPEED_DEV_LPC] = 0x1E789000,
46 [ASPEED_DEV_IBT] = 0x1E789140,
47 [ASPEED_DEV_I2C] = 0x1E78A000,
48 [ASPEED_DEV_ETH1] = 0x1E660000,
49 [ASPEED_DEV_ETH2] = 0x1E680000,
50 [ASPEED_DEV_UART1] = 0x1E783000,
51 [ASPEED_DEV_UART5] = 0x1E784000,
52 [ASPEED_DEV_VUART] = 0x1E787000,
53 [ASPEED_DEV_SDRAM] = 0x40000000,
54 };
55
56 static const hwaddr aspeed_soc_ast2500_memmap[] = {
57 [ASPEED_DEV_IOMEM] = 0x1E600000,
58 [ASPEED_DEV_FMC] = 0x1E620000,
59 [ASPEED_DEV_SPI1] = 0x1E630000,
60 [ASPEED_DEV_SPI2] = 0x1E631000,
61 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
62 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
63 [ASPEED_DEV_VIC] = 0x1E6C0000,
64 [ASPEED_DEV_SDMC] = 0x1E6E0000,
65 [ASPEED_DEV_SCU] = 0x1E6E2000,
66 [ASPEED_DEV_HACE] = 0x1E6E3000,
67 [ASPEED_DEV_XDMA] = 0x1E6E7000,
68 [ASPEED_DEV_ADC] = 0x1E6E9000,
69 [ASPEED_DEV_VIDEO] = 0x1E700000,
70 [ASPEED_DEV_SRAM] = 0x1E720000,
71 [ASPEED_DEV_SDHCI] = 0x1E740000,
72 [ASPEED_DEV_GPIO] = 0x1E780000,
73 [ASPEED_DEV_RTC] = 0x1E781000,
74 [ASPEED_DEV_TIMER1] = 0x1E782000,
75 [ASPEED_DEV_WDT] = 0x1E785000,
76 [ASPEED_DEV_PWM] = 0x1E786000,
77 [ASPEED_DEV_LPC] = 0x1E789000,
78 [ASPEED_DEV_IBT] = 0x1E789140,
79 [ASPEED_DEV_I2C] = 0x1E78A000,
80 [ASPEED_DEV_ETH1] = 0x1E660000,
81 [ASPEED_DEV_ETH2] = 0x1E680000,
82 [ASPEED_DEV_UART1] = 0x1E783000,
83 [ASPEED_DEV_UART5] = 0x1E784000,
84 [ASPEED_DEV_VUART] = 0x1E787000,
85 [ASPEED_DEV_SDRAM] = 0x80000000,
86 };
87
88 static const int aspeed_soc_ast2400_irqmap[] = {
89 [ASPEED_DEV_UART1] = 9,
90 [ASPEED_DEV_UART2] = 32,
91 [ASPEED_DEV_UART3] = 33,
92 [ASPEED_DEV_UART4] = 34,
93 [ASPEED_DEV_UART5] = 10,
94 [ASPEED_DEV_VUART] = 8,
95 [ASPEED_DEV_FMC] = 19,
96 [ASPEED_DEV_EHCI1] = 5,
97 [ASPEED_DEV_EHCI2] = 13,
98 [ASPEED_DEV_SDMC] = 0,
99 [ASPEED_DEV_SCU] = 21,
100 [ASPEED_DEV_ADC] = 31,
101 [ASPEED_DEV_GPIO] = 20,
102 [ASPEED_DEV_RTC] = 22,
103 [ASPEED_DEV_TIMER1] = 16,
104 [ASPEED_DEV_TIMER2] = 17,
105 [ASPEED_DEV_TIMER3] = 18,
106 [ASPEED_DEV_TIMER4] = 35,
107 [ASPEED_DEV_TIMER5] = 36,
108 [ASPEED_DEV_TIMER6] = 37,
109 [ASPEED_DEV_TIMER7] = 38,
110 [ASPEED_DEV_TIMER8] = 39,
111 [ASPEED_DEV_WDT] = 27,
112 [ASPEED_DEV_PWM] = 28,
113 [ASPEED_DEV_LPC] = 8,
114 [ASPEED_DEV_I2C] = 12,
115 [ASPEED_DEV_ETH1] = 2,
116 [ASPEED_DEV_ETH2] = 3,
117 [ASPEED_DEV_XDMA] = 6,
118 [ASPEED_DEV_SDHCI] = 26,
119 [ASPEED_DEV_HACE] = 4,
120 };
121
122 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
123
124 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
125 {
126 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
127
128 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
129 }
130
131 static void aspeed_soc_init(Object *obj)
132 {
133 AspeedSoCState *s = ASPEED_SOC(obj);
134 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
135 int i;
136 char socname[8];
137 char typename[64];
138
139 if (sscanf(sc->name, "%7s", socname) != 1) {
140 g_assert_not_reached();
141 }
142
143 for (i = 0; i < sc->num_cpus; i++) {
144 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
145 }
146
147 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
148 object_initialize_child(obj, "scu", &s->scu, typename);
149 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
150 sc->silicon_rev);
151 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
152 "hw-strap1");
153 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
154 "hw-strap2");
155 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
156 "hw-prot-key");
157
158 object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
159
160 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
161
162 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
163 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
164
165 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
166 object_initialize_child(obj, "adc", &s->adc, typename);
167
168 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
169 object_initialize_child(obj, "i2c", &s->i2c, typename);
170
171 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
172 object_initialize_child(obj, "fmc", &s->fmc, typename);
173 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
174
175 for (i = 0; i < sc->spis_num; i++) {
176 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
177 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
178 }
179
180 for (i = 0; i < sc->ehcis_num; i++) {
181 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
182 TYPE_PLATFORM_EHCI);
183 }
184
185 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
186 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
187 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
188 "ram-size");
189 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
190 "max-ram-size");
191
192 for (i = 0; i < sc->wdts_num; i++) {
193 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
194 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
195 }
196
197 for (i = 0; i < sc->macs_num; i++) {
198 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
199 TYPE_FTGMAC100);
200 }
201
202 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
203 object_initialize_child(obj, "xdma", &s->xdma, typename);
204
205 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
206 object_initialize_child(obj, "gpio", &s->gpio, typename);
207
208 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
209
210 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
211
212 /* Init sd card slot class here so that they're under the correct parent */
213 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
214 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
215 TYPE_SYSBUS_SDHCI);
216 }
217
218 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
219
220 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
221 object_initialize_child(obj, "hace", &s->hace, typename);
222 }
223
224 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
225 {
226 int i;
227 AspeedSoCState *s = ASPEED_SOC(dev);
228 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
229 Error *err = NULL;
230
231 /* IO space */
232 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM],
233 ASPEED_SOC_IOMEM_SIZE);
234
235 /* Video engine stub */
236 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO],
237 0x1000);
238
239 /* CPU */
240 for (i = 0; i < sc->num_cpus; i++) {
241 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
242 return;
243 }
244 }
245
246 /* SRAM */
247 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
248 sc->sram_size, &err);
249 if (err) {
250 error_propagate(errp, err);
251 return;
252 }
253 memory_region_add_subregion(get_system_memory(),
254 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
255
256 /* SCU */
257 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
258 return;
259 }
260 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
261
262 /* VIC */
263 if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
264 return;
265 }
266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
267 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
268 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
269 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
270 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
271
272 /* RTC */
273 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
274 return;
275 }
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
277 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
278 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
279
280 /* Timer */
281 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
282 &error_abort);
283 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
284 return;
285 }
286 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
287 sc->memmap[ASPEED_DEV_TIMER1]);
288 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
289 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
290 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
291 }
292
293 /* ADC */
294 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
295 return;
296 }
297 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
299 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
300
301 /* UART - attach an 8250 to the IO space as our UART */
302 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
303 aspeed_soc_get_irq(s, s->uart_default), 38400,
304 serial_hd(0), DEVICE_LITTLE_ENDIAN);
305
306 /* I2C */
307 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
308 &error_abort);
309 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
310 return;
311 }
312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
314 aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
315
316 /* FMC, The number of CS is set at the board level */
317 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
318 &error_abort);
319 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
320 return;
321 }
322 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
323 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
324 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
325 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
326 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
327
328 /* SPI */
329 for (i = 0; i < sc->spis_num; i++) {
330 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort);
331 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
332 return;
333 }
334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
335 sc->memmap[ASPEED_DEV_SPI1 + i]);
336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
337 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
338 }
339
340 /* EHCI */
341 for (i = 0; i < sc->ehcis_num; i++) {
342 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
343 return;
344 }
345 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
346 sc->memmap[ASPEED_DEV_EHCI1 + i]);
347 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
348 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
349 }
350
351 /* SDMC - SDRAM Memory Controller */
352 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
353 return;
354 }
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]);
356
357 /* Watch dog */
358 for (i = 0; i < sc->wdts_num; i++) {
359 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
360
361 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
362 &error_abort);
363 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
364 return;
365 }
366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
367 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
368 }
369
370 /* Net */
371 for (i = 0; i < sc->macs_num; i++) {
372 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
373 &error_abort);
374 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
375 return;
376 }
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
378 sc->memmap[ASPEED_DEV_ETH1 + i]);
379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
380 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
381 }
382
383 /* XDMA */
384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
385 return;
386 }
387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
388 sc->memmap[ASPEED_DEV_XDMA]);
389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
390 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
391
392 /* GPIO */
393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
394 return;
395 }
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
398 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
399
400 /* SDHCI */
401 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
402 return;
403 }
404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
405 sc->memmap[ASPEED_DEV_SDHCI]);
406 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
407 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
408
409 /* LPC */
410 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
411 return;
412 }
413 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
414
415 /* Connect the LPC IRQ to the VIC */
416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
417 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
418
419 /*
420 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
421 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
422 * contrast, on the AST2600, the subdevice IRQs are connected straight to
423 * the GIC).
424 *
425 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
426 * to the VIC is at offset 0.
427 */
428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
429 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
430
431 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
432 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
433
434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
435 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
436
437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
438 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
439
440 /* HACE */
441 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
442 &error_abort);
443 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
444 return;
445 }
446 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]);
447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
448 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
449 }
450 static Property aspeed_soc_properties[] = {
451 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
452 MemoryRegion *),
453 DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default,
454 ASPEED_DEV_UART5),
455 DEFINE_PROP_END_OF_LIST(),
456 };
457
458 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
459 {
460 DeviceClass *dc = DEVICE_CLASS(oc);
461
462 dc->realize = aspeed_soc_realize;
463 /* Reason: Uses serial_hds and nd_table in realize() directly */
464 dc->user_creatable = false;
465 device_class_set_props(dc, aspeed_soc_properties);
466 }
467
468 static const TypeInfo aspeed_soc_type_info = {
469 .name = TYPE_ASPEED_SOC,
470 .parent = TYPE_DEVICE,
471 .instance_size = sizeof(AspeedSoCState),
472 .class_size = sizeof(AspeedSoCClass),
473 .class_init = aspeed_soc_class_init,
474 .abstract = true,
475 };
476
477 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
478 {
479 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
480
481 sc->name = "ast2400-a1";
482 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
483 sc->silicon_rev = AST2400_A1_SILICON_REV;
484 sc->sram_size = 0x8000;
485 sc->spis_num = 1;
486 sc->ehcis_num = 1;
487 sc->wdts_num = 2;
488 sc->macs_num = 2;
489 sc->irqmap = aspeed_soc_ast2400_irqmap;
490 sc->memmap = aspeed_soc_ast2400_memmap;
491 sc->num_cpus = 1;
492 }
493
494 static const TypeInfo aspeed_soc_ast2400_type_info = {
495 .name = "ast2400-a1",
496 .parent = TYPE_ASPEED_SOC,
497 .instance_init = aspeed_soc_init,
498 .instance_size = sizeof(AspeedSoCState),
499 .class_init = aspeed_soc_ast2400_class_init,
500 };
501
502 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
503 {
504 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
505
506 sc->name = "ast2500-a1";
507 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
508 sc->silicon_rev = AST2500_A1_SILICON_REV;
509 sc->sram_size = 0x9000;
510 sc->spis_num = 2;
511 sc->ehcis_num = 2;
512 sc->wdts_num = 3;
513 sc->macs_num = 2;
514 sc->irqmap = aspeed_soc_ast2500_irqmap;
515 sc->memmap = aspeed_soc_ast2500_memmap;
516 sc->num_cpus = 1;
517 }
518
519 static const TypeInfo aspeed_soc_ast2500_type_info = {
520 .name = "ast2500-a1",
521 .parent = TYPE_ASPEED_SOC,
522 .instance_init = aspeed_soc_init,
523 .instance_size = sizeof(AspeedSoCState),
524 .class_init = aspeed_soc_ast2500_class_init,
525 };
526 static void aspeed_soc_register_types(void)
527 {
528 type_register_static(&aspeed_soc_type_info);
529 type_register_static(&aspeed_soc_ast2400_type_info);
530 type_register_static(&aspeed_soc_ast2500_type_info);
531 };
532
533 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU