?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
IDE: Add register hints to tracing
[qemu/ar7.git] / hw / ide / core.c
blobcb250e62be10672cb0da9d87c2766aac8949d44a
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "hw/isa/isa.h"
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/dma.h"
34 #include "hw/block/block.h"
35 #include "sysemu/block-backend.h"
36 #include "qemu/cutils.h"
37
38 #include "hw/ide/internal.h"
39 #include "trace.h"
40
41 /* These values were based on a Seagate ST3500418AS but have been modified
42 to make more sense in QEMU */
43 static const int smart_attributes[][12] = {
44 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
45 /* raw read error rate*/
46 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
47 /* spin up */
48 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
49 /* start stop count */
50 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
51 /* remapped sectors */
52 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
53 /* power on hours */
54 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
55 /* power cycle count */
56 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
57 /* airflow-temperature-celsius */
58 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
59 };
60
61 static void ide_dummy_transfer_stop(IDEState *s);
62
63 static void padstr(char *str, const char *src, int len)
64 {
65 int i, v;
66 for(i = 0; i < len; i++) {
67 if (*src)
68 v = *src++;
69 else
70 v = ' ';
71 str[i^1] = v;
72 }
73 }
74
75 static void put_le16(uint16_t *p, unsigned int v)
76 {
77 *p = cpu_to_le16(v);
78 }
79
80 static void ide_identify_size(IDEState *s)
81 {
82 uint16_t *p = (uint16_t *)s->identify_data;
83 put_le16(p + 60, s->nb_sectors);
84 put_le16(p + 61, s->nb_sectors >> 16);
85 put_le16(p + 100, s->nb_sectors);
86 put_le16(p + 101, s->nb_sectors >> 16);
87 put_le16(p + 102, s->nb_sectors >> 32);
88 put_le16(p + 103, s->nb_sectors >> 48);
89 }
90
91 static void ide_identify(IDEState *s)
92 {
93 uint16_t *p;
94 unsigned int oldsize;
95 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
96
97 p = (uint16_t *)s->identify_data;
98 if (s->identify_set) {
99 goto fill_buffer;
100 }
101 memset(p, 0, sizeof(s->identify_data));
102
103 put_le16(p + 0, 0x0040);
104 put_le16(p + 1, s->cylinders);
105 put_le16(p + 3, s->heads);
106 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
107 put_le16(p + 5, 512); /* XXX: retired, remove ? */
108 put_le16(p + 6, s->sectors);
109 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
110 put_le16(p + 20, 3); /* XXX: retired, remove ? */
111 put_le16(p + 21, 512); /* cache size in sectors */
112 put_le16(p + 22, 4); /* ecc bytes */
113 padstr((char *)(p + 23), s->version, 8); /* firmware version */
114 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
115 #if MAX_MULT_SECTORS > 1
116 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
117 #endif
118 put_le16(p + 48, 1); /* dword I/O */
119 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
120 put_le16(p + 51, 0x200); /* PIO transfer cycle */
121 put_le16(p + 52, 0x200); /* DMA transfer cycle */
122 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
123 put_le16(p + 54, s->cylinders);
124 put_le16(p + 55, s->heads);
125 put_le16(p + 56, s->sectors);
126 oldsize = s->cylinders * s->heads * s->sectors;
127 put_le16(p + 57, oldsize);
128 put_le16(p + 58, oldsize >> 16);
129 if (s->mult_sectors)
130 put_le16(p + 59, 0x100 | s->mult_sectors);
131 /* *(p + 60) := nb_sectors -- see ide_identify_size */
132 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
133 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
134 put_le16(p + 63, 0x07); /* mdma0-2 supported */
135 put_le16(p + 64, 0x03); /* pio3-4 supported */
136 put_le16(p + 65, 120);
137 put_le16(p + 66, 120);
138 put_le16(p + 67, 120);
139 put_le16(p + 68, 120);
140 if (dev && dev->conf.discard_granularity) {
141 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
142 }
143
144 if (s->ncq_queues) {
145 put_le16(p + 75, s->ncq_queues - 1);
146 /* NCQ supported */
147 put_le16(p + 76, (1 << 8));
148 }
149
150 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
151 put_le16(p + 81, 0x16); /* conforms to ata5 */
152 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
153 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
154 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
155 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
156 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
157 if (s->wwn) {
158 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
159 } else {
160 put_le16(p + 84, (1 << 14) | 0);
161 }
162 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
163 if (blk_enable_write_cache(s->blk)) {
164 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
165 } else {
166 put_le16(p + 85, (1 << 14) | 1);
167 }
168 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
169 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
170 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
171 if (s->wwn) {
172 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
173 } else {
174 put_le16(p + 87, (1 << 14) | 0);
175 }
176 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
177 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
178 /* *(p + 100) := nb_sectors -- see ide_identify_size */
179 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
180 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
181 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
182
183 if (dev && dev->conf.physical_block_size)
184 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
185 if (s->wwn) {
186 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
187 put_le16(p + 108, s->wwn >> 48);
188 put_le16(p + 109, s->wwn >> 32);
189 put_le16(p + 110, s->wwn >> 16);
190 put_le16(p + 111, s->wwn);
191 }
192 if (dev && dev->conf.discard_granularity) {
193 put_le16(p + 169, 1); /* TRIM support */
194 }
195
196 ide_identify_size(s);
197 s->identify_set = 1;
198
199 fill_buffer:
200 memcpy(s->io_buffer, p, sizeof(s->identify_data));
201 }
202
203 static void ide_atapi_identify(IDEState *s)
204 {
205 uint16_t *p;
206
207 p = (uint16_t *)s->identify_data;
208 if (s->identify_set) {
209 goto fill_buffer;
210 }
211 memset(p, 0, sizeof(s->identify_data));
212
213 /* Removable CDROM, 50us response, 12 byte packets */
214 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
215 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
216 put_le16(p + 20, 3); /* buffer type */
217 put_le16(p + 21, 512); /* cache size in sectors */
218 put_le16(p + 22, 4); /* ecc bytes */
219 padstr((char *)(p + 23), s->version, 8); /* firmware version */
220 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
221 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
222 #ifdef USE_DMA_CDROM
223 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
224 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
225 put_le16(p + 62, 7); /* single word dma0-2 supported */
226 put_le16(p + 63, 7); /* mdma0-2 supported */
227 #else
228 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
229 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
230 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
231 #endif
232 put_le16(p + 64, 3); /* pio3-4 supported */
233 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
234 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
235 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
236 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
237
238 put_le16(p + 71, 30); /* in ns */
239 put_le16(p + 72, 30); /* in ns */
240
241 if (s->ncq_queues) {
242 put_le16(p + 75, s->ncq_queues - 1);
243 /* NCQ supported */
244 put_le16(p + 76, (1 << 8));
245 }
246
247 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
248 if (s->wwn) {
249 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
250 put_le16(p + 87, (1 << 8)); /* WWN enabled */
251 }
252
253 #ifdef USE_DMA_CDROM
254 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
255 #endif
256
257 if (s->wwn) {
258 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
259 put_le16(p + 108, s->wwn >> 48);
260 put_le16(p + 109, s->wwn >> 32);
261 put_le16(p + 110, s->wwn >> 16);
262 put_le16(p + 111, s->wwn);
263 }
264
265 s->identify_set = 1;
266
267 fill_buffer:
268 memcpy(s->io_buffer, p, sizeof(s->identify_data));
269 }
270
271 static void ide_cfata_identify_size(IDEState *s)
272 {
273 uint16_t *p = (uint16_t *)s->identify_data;
274 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
275 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
276 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
277 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
278 }
279
280 static void ide_cfata_identify(IDEState *s)
281 {
282 uint16_t *p;
283 uint32_t cur_sec;
284
285 p = (uint16_t *)s->identify_data;
286 if (s->identify_set) {
287 goto fill_buffer;
288 }
289 memset(p, 0, sizeof(s->identify_data));
290
291 cur_sec = s->cylinders * s->heads * s->sectors;
292
293 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
294 put_le16(p + 1, s->cylinders); /* Default cylinders */
295 put_le16(p + 3, s->heads); /* Default heads */
296 put_le16(p + 6, s->sectors); /* Default sectors per track */
297 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
298 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
299 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
300 put_le16(p + 22, 0x0004); /* ECC bytes */
301 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
302 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
303 #if MAX_MULT_SECTORS > 1
304 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
305 #else
306 put_le16(p + 47, 0x0000);
307 #endif
308 put_le16(p + 49, 0x0f00); /* Capabilities */
309 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
310 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
311 put_le16(p + 53, 0x0003); /* Translation params valid */
312 put_le16(p + 54, s->cylinders); /* Current cylinders */
313 put_le16(p + 55, s->heads); /* Current heads */
314 put_le16(p + 56, s->sectors); /* Current sectors */
315 put_le16(p + 57, cur_sec); /* Current capacity */
316 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
317 if (s->mult_sectors) /* Multiple sector setting */
318 put_le16(p + 59, 0x100 | s->mult_sectors);
319 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
320 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
321 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
322 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
323 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
324 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
325 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
326 put_le16(p + 82, 0x400c); /* Command Set supported */
327 put_le16(p + 83, 0x7068); /* Command Set supported */
328 put_le16(p + 84, 0x4000); /* Features supported */
329 put_le16(p + 85, 0x000c); /* Command Set enabled */
330 put_le16(p + 86, 0x7044); /* Command Set enabled */
331 put_le16(p + 87, 0x4000); /* Features enabled */
332 put_le16(p + 91, 0x4060); /* Current APM level */
333 put_le16(p + 129, 0x0002); /* Current features option */
334 put_le16(p + 130, 0x0005); /* Reassigned sectors */
335 put_le16(p + 131, 0x0001); /* Initial power mode */
336 put_le16(p + 132, 0x0000); /* User signature */
337 put_le16(p + 160, 0x8100); /* Power requirement */
338 put_le16(p + 161, 0x8001); /* CF command set */
339
340 ide_cfata_identify_size(s);
341 s->identify_set = 1;
342
343 fill_buffer:
344 memcpy(s->io_buffer, p, sizeof(s->identify_data));
345 }
346
347 static void ide_set_signature(IDEState *s)
348 {
349 s->select &= 0xf0; /* clear head */
350 /* put signature */
351 s->nsector = 1;
352 s->sector = 1;
353 if (s->drive_kind == IDE_CD) {
354 s->lcyl = 0x14;
355 s->hcyl = 0xeb;
356 } else if (s->blk) {
357 s->lcyl = 0;
358 s->hcyl = 0;
359 } else {
360 s->lcyl = 0xff;
361 s->hcyl = 0xff;
362 }
363 }
364
365 typedef struct TrimAIOCB {
366 BlockAIOCB common;
367 BlockBackend *blk;
368 QEMUBH *bh;
369 int ret;
370 QEMUIOVector *qiov;
371 BlockAIOCB *aiocb;
372 int i, j;
373 } TrimAIOCB;
374
375 static void trim_aio_cancel(BlockAIOCB *acb)
376 {
377 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
378
379 /* Exit the loop so ide_issue_trim_cb will not continue */
380 iocb->j = iocb->qiov->niov - 1;
381 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
382
383 iocb->ret = -ECANCELED;
384
385 if (iocb->aiocb) {
386 blk_aio_cancel_async(iocb->aiocb);
387 iocb->aiocb = NULL;
388 }
389 }
390
391 static const AIOCBInfo trim_aiocb_info = {
392 .aiocb_size = sizeof(TrimAIOCB),
393 .cancel_async = trim_aio_cancel,
394 };
395
396 static void ide_trim_bh_cb(void *opaque)
397 {
398 TrimAIOCB *iocb = opaque;
399
400 iocb->common.cb(iocb->common.opaque, iocb->ret);
401
402 qemu_bh_delete(iocb->bh);
403 iocb->bh = NULL;
404 qemu_aio_unref(iocb);
405 }
406
407 static void ide_issue_trim_cb(void *opaque, int ret)
408 {
409 TrimAIOCB *iocb = opaque;
410 if (ret >= 0) {
411 while (iocb->j < iocb->qiov->niov) {
412 int j = iocb->j;
413 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
414 int i = iocb->i;
415 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
416
417 /* 6-byte LBA + 2-byte range per entry */
418 uint64_t entry = le64_to_cpu(buffer[i]);
419 uint64_t sector = entry & 0x0000ffffffffffffULL;
420 uint16_t count = entry >> 48;
421
422 if (count == 0) {
423 continue;
424 }
425
426 /* Got an entry! Submit and exit. */
427 iocb->aiocb = blk_aio_pdiscard(iocb->blk,
428 sector << BDRV_SECTOR_BITS,
429 count << BDRV_SECTOR_BITS,
430 ide_issue_trim_cb, opaque);
431 return;
432 }
433
434 iocb->j++;
435 iocb->i = -1;
436 }
437 } else {
438 iocb->ret = ret;
439 }
440
441 iocb->aiocb = NULL;
442 if (iocb->bh) {
443 qemu_bh_schedule(iocb->bh);
444 }
445 }
446
447 BlockAIOCB *ide_issue_trim(
448 int64_t offset, QEMUIOVector *qiov,
449 BlockCompletionFunc *cb, void *cb_opaque, void *opaque)
450 {
451 BlockBackend *blk = opaque;
452 TrimAIOCB *iocb;
453
454 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, cb_opaque);
455 iocb->blk = blk;
456 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
457 iocb->ret = 0;
458 iocb->qiov = qiov;
459 iocb->i = -1;
460 iocb->j = 0;
461 ide_issue_trim_cb(iocb, 0);
462 return &iocb->common;
463 }
464
465 void ide_abort_command(IDEState *s)
466 {
467 ide_transfer_stop(s);
468 s->status = READY_STAT | ERR_STAT;
469 s->error = ABRT_ERR;
470 }
471
472 static void ide_set_retry(IDEState *s)
473 {
474 s->bus->retry_unit = s->unit;
475 s->bus->retry_sector_num = ide_get_sector(s);
476 s->bus->retry_nsector = s->nsector;
477 }
478
479 static void ide_clear_retry(IDEState *s)
480 {
481 s->bus->retry_unit = -1;
482 s->bus->retry_sector_num = 0;
483 s->bus->retry_nsector = 0;
484 }
485
486 /* prepare data transfer and tell what to do after */
487 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
488 EndTransferFunc *end_transfer_func)
489 {
490 s->end_transfer_func = end_transfer_func;
491 s->data_ptr = buf;
492 s->data_end = buf + size;
493 ide_set_retry(s);
494 if (!(s->status & ERR_STAT)) {
495 s->status |= DRQ_STAT;
496 }
497 if (s->bus->dma->ops->start_transfer) {
498 s->bus->dma->ops->start_transfer(s->bus->dma);
499 }
500 }
501
502 static void ide_cmd_done(IDEState *s)
503 {
504 if (s->bus->dma->ops->cmd_done) {
505 s->bus->dma->ops->cmd_done(s->bus->dma);
506 }
507 }
508
509 static void ide_transfer_halt(IDEState *s,
510 void(*end_transfer_func)(IDEState *),
511 bool notify)
512 {
513 s->end_transfer_func = end_transfer_func;
514 s->data_ptr = s->io_buffer;
515 s->data_end = s->io_buffer;
516 s->status &= ~DRQ_STAT;
517 if (notify) {
518 ide_cmd_done(s);
519 }
520 }
521
522 void ide_transfer_stop(IDEState *s)
523 {
524 ide_transfer_halt(s, ide_transfer_stop, true);
525 }
526
527 static void ide_transfer_cancel(IDEState *s)
528 {
529 ide_transfer_halt(s, ide_transfer_cancel, false);
530 }
531
532 int64_t ide_get_sector(IDEState *s)
533 {
534 int64_t sector_num;
535 if (s->select & 0x40) {
536 /* lba */
537 if (!s->lba48) {
538 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
539 (s->lcyl << 8) | s->sector;
540 } else {
541 sector_num = ((int64_t)s->hob_hcyl << 40) |
542 ((int64_t) s->hob_lcyl << 32) |
543 ((int64_t) s->hob_sector << 24) |
544 ((int64_t) s->hcyl << 16) |
545 ((int64_t) s->lcyl << 8) | s->sector;
546 }
547 } else {
548 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
549 (s->select & 0x0f) * s->sectors + (s->sector - 1);
550 }
551 return sector_num;
552 }
553
554 void ide_set_sector(IDEState *s, int64_t sector_num)
555 {
556 unsigned int cyl, r;
557 if (s->select & 0x40) {
558 if (!s->lba48) {
559 s->select = (s->select & 0xf0) | (sector_num >> 24);
560 s->hcyl = (sector_num >> 16);
561 s->lcyl = (sector_num >> 8);
562 s->sector = (sector_num);
563 } else {
564 s->sector = sector_num;
565 s->lcyl = sector_num >> 8;
566 s->hcyl = sector_num >> 16;
567 s->hob_sector = sector_num >> 24;
568 s->hob_lcyl = sector_num >> 32;
569 s->hob_hcyl = sector_num >> 40;
570 }
571 } else {
572 cyl = sector_num / (s->heads * s->sectors);
573 r = sector_num % (s->heads * s->sectors);
574 s->hcyl = cyl >> 8;
575 s->lcyl = cyl;
576 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
577 s->sector = (r % s->sectors) + 1;
578 }
579 }
580
581 static void ide_rw_error(IDEState *s) {
582 ide_abort_command(s);
583 ide_set_irq(s->bus);
584 }
585
586 static bool ide_sect_range_ok(IDEState *s,
587 uint64_t sector, uint64_t nb_sectors)
588 {
589 uint64_t total_sectors;
590
591 blk_get_geometry(s->blk, &total_sectors);
592 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
593 return false;
594 }
595 return true;
596 }
597
598 static void ide_buffered_readv_cb(void *opaque, int ret)
599 {
600 IDEBufferedRequest *req = opaque;
601 if (!req->orphaned) {
602 if (!ret) {
603 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
604 req->original_qiov->size);
605 }
606 req->original_cb(req->original_opaque, ret);
607 }
608 QLIST_REMOVE(req, list);
609 qemu_vfree(req->iov.iov_base);
610 g_free(req);
611 }
612
613 #define MAX_BUFFERED_REQS 16
614
615 BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
616 QEMUIOVector *iov, int nb_sectors,
617 BlockCompletionFunc *cb, void *opaque)
618 {
619 BlockAIOCB *aioreq;
620 IDEBufferedRequest *req;
621 int c = 0;
622
623 QLIST_FOREACH(req, &s->buffered_requests, list) {
624 c++;
625 }
626 if (c > MAX_BUFFERED_REQS) {
627 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
628 }
629
630 req = g_new0(IDEBufferedRequest, 1);
631 req->original_qiov = iov;
632 req->original_cb = cb;
633 req->original_opaque = opaque;
634 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
635 req->iov.iov_len = iov->size;
636 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
637
638 aioreq = blk_aio_preadv(s->blk, sector_num << BDRV_SECTOR_BITS,
639 &req->qiov, 0, ide_buffered_readv_cb, req);
640
641 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
642 return aioreq;
643 }
644
645 /**
646 * Cancel all pending DMA requests.
647 * Any buffered DMA requests are instantly canceled,
648 * but any pending unbuffered DMA requests must be waited on.
649 */
650 void ide_cancel_dma_sync(IDEState *s)
651 {
652 IDEBufferedRequest *req;
653
654 /* First invoke the callbacks of all buffered requests
655 * and flag those requests as orphaned. Ideally there
656 * are no unbuffered (Scatter Gather DMA Requests or
657 * write requests) pending and we can avoid to drain. */
658 QLIST_FOREACH(req, &s->buffered_requests, list) {
659 if (!req->orphaned) {
660 trace_ide_cancel_dma_sync_buffered(req->original_cb, req);
661 req->original_cb(req->original_opaque, -ECANCELED);
662 }
663 req->orphaned = true;
664 }
665
666 /*
667 * We can't cancel Scatter Gather DMA in the middle of the
668 * operation or a partial (not full) DMA transfer would reach
669 * the storage so we wait for completion instead (we beahve
670 * like if the DMA was completed by the time the guest trying
671 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
672 * set).
673 *
674 * In the future we'll be able to safely cancel the I/O if the
675 * whole DMA operation will be submitted to disk with a single
676 * aio operation with preadv/pwritev.
677 */
678 if (s->bus->dma->aiocb) {
679 trace_ide_cancel_dma_sync_remaining();
680 blk_drain(s->blk);
681 assert(s->bus->dma->aiocb == NULL);
682 }
683 }
684
685 static void ide_sector_read(IDEState *s);
686
687 static void ide_sector_read_cb(void *opaque, int ret)
688 {
689 IDEState *s = opaque;
690 int n;
691
692 s->pio_aiocb = NULL;
693 s->status &= ~BUSY_STAT;
694
695 if (ret == -ECANCELED) {
696 return;
697 }
698 if (ret != 0) {
699 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
700 IDE_RETRY_READ)) {
701 return;
702 }
703 }
704
705 block_acct_done(blk_get_stats(s->blk), &s->acct);
706
707 n = s->nsector;
708 if (n > s->req_nb_sectors) {
709 n = s->req_nb_sectors;
710 }
711
712 ide_set_sector(s, ide_get_sector(s) + n);
713 s->nsector -= n;
714 /* Allow the guest to read the io_buffer */
715 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
716 ide_set_irq(s->bus);
717 }
718
719 static void ide_sector_read(IDEState *s)
720 {
721 int64_t sector_num;
722 int n;
723
724 s->status = READY_STAT | SEEK_STAT;
725 s->error = 0; /* not needed by IDE spec, but needed by Windows */
726 sector_num = ide_get_sector(s);
727 n = s->nsector;
728
729 if (n == 0) {
730 ide_transfer_stop(s);
731 return;
732 }
733
734 s->status |= BUSY_STAT;
735
736 if (n > s->req_nb_sectors) {
737 n = s->req_nb_sectors;
738 }
739
740 trace_ide_sector_read(sector_num, n);
741
742 if (!ide_sect_range_ok(s, sector_num, n)) {
743 ide_rw_error(s);
744 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
745 return;
746 }
747
748 s->iov.iov_base = s->io_buffer;
749 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
750 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
751
752 block_acct_start(blk_get_stats(s->blk), &s->acct,
753 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
754 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
755 ide_sector_read_cb, s);
756 }
757
758 void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
759 {
760 if (s->bus->dma->ops->commit_buf) {
761 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
762 }
763 s->io_buffer_offset += tx_bytes;
764 qemu_sglist_destroy(&s->sg);
765 }
766
767 void ide_set_inactive(IDEState *s, bool more)
768 {
769 s->bus->dma->aiocb = NULL;
770 ide_clear_retry(s);
771 if (s->bus->dma->ops->set_inactive) {
772 s->bus->dma->ops->set_inactive(s->bus->dma, more);
773 }
774 ide_cmd_done(s);
775 }
776
777 void ide_dma_error(IDEState *s)
778 {
779 dma_buf_commit(s, 0);
780 ide_abort_command(s);
781 ide_set_inactive(s, false);
782 ide_set_irq(s->bus);
783 }
784
785 int ide_handle_rw_error(IDEState *s, int error, int op)
786 {
787 bool is_read = (op & IDE_RETRY_READ) != 0;
788 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
789
790 if (action == BLOCK_ERROR_ACTION_STOP) {
791 assert(s->bus->retry_unit == s->unit);
792 s->bus->error_status = op;
793 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
794 block_acct_failed(blk_get_stats(s->blk), &s->acct);
795 if (IS_IDE_RETRY_DMA(op)) {
796 ide_dma_error(s);
797 } else if (IS_IDE_RETRY_ATAPI(op)) {
798 ide_atapi_io_error(s, -error);
799 } else {
800 ide_rw_error(s);
801 }
802 }
803 blk_error_action(s->blk, action, is_read, error);
804 return action != BLOCK_ERROR_ACTION_IGNORE;
805 }
806
807 static void ide_dma_cb(void *opaque, int ret)
808 {
809 IDEState *s = opaque;
810 int n;
811 int64_t sector_num;
812 uint64_t offset;
813 bool stay_active = false;
814
815 if (ret == -ECANCELED) {
816 return;
817 }
818 if (ret < 0) {
819 if (ide_handle_rw_error(s, -ret, ide_dma_cmd_to_retry(s->dma_cmd))) {
820 s->bus->dma->aiocb = NULL;
821 dma_buf_commit(s, 0);
822 return;
823 }
824 }
825
826 n = s->io_buffer_size >> 9;
827 if (n > s->nsector) {
828 /* The PRDs were longer than needed for this request. Shorten them so
829 * we don't get a negative remainder. The Active bit must remain set
830 * after the request completes. */
831 n = s->nsector;
832 stay_active = true;
833 }
834
835 sector_num = ide_get_sector(s);
836 if (n > 0) {
837 assert(n * 512 == s->sg.size);
838 dma_buf_commit(s, s->sg.size);
839 sector_num += n;
840 ide_set_sector(s, sector_num);
841 s->nsector -= n;
842 }
843
844 /* end of transfer ? */
845 if (s->nsector == 0) {
846 s->status = READY_STAT | SEEK_STAT;
847 ide_set_irq(s->bus);
848 goto eot;
849 }
850
851 /* launch next transfer */
852 n = s->nsector;
853 s->io_buffer_index = 0;
854 s->io_buffer_size = n * 512;
855 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
856 /* The PRDs were too short. Reset the Active bit, but don't raise an
857 * interrupt. */
858 s->status = READY_STAT | SEEK_STAT;
859 dma_buf_commit(s, 0);
860 goto eot;
861 }
862
863 #ifdef DEBUG_AIO
864 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
865 sector_num, n, s->dma_cmd);
866 #endif
867
868 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
869 !ide_sect_range_ok(s, sector_num, n)) {
870 ide_dma_error(s);
871 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
872 return;
873 }
874
875 offset = sector_num << BDRV_SECTOR_BITS;
876 switch (s->dma_cmd) {
877 case IDE_DMA_READ:
878 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset,
879 BDRV_SECTOR_SIZE, ide_dma_cb, s);
880 break;
881 case IDE_DMA_WRITE:
882 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset,
883 BDRV_SECTOR_SIZE, ide_dma_cb, s);
884 break;
885 case IDE_DMA_TRIM:
886 s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk),
887 &s->sg, offset, BDRV_SECTOR_SIZE,
888 ide_issue_trim, s->blk, ide_dma_cb, s,
889 DMA_DIRECTION_TO_DEVICE);
890 break;
891 default:
892 abort();
893 }
894 return;
895
896 eot:
897 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
898 block_acct_done(blk_get_stats(s->blk), &s->acct);
899 }
900 ide_set_inactive(s, stay_active);
901 }
902
903 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
904 {
905 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
906 s->io_buffer_size = 0;
907 s->dma_cmd = dma_cmd;
908
909 switch (dma_cmd) {
910 case IDE_DMA_READ:
911 block_acct_start(blk_get_stats(s->blk), &s->acct,
912 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
913 break;
914 case IDE_DMA_WRITE:
915 block_acct_start(blk_get_stats(s->blk), &s->acct,
916 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
917 break;
918 default:
919 break;
920 }
921
922 ide_start_dma(s, ide_dma_cb);
923 }
924
925 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
926 {
927 s->io_buffer_index = 0;
928 ide_set_retry(s);
929 if (s->bus->dma->ops->start_dma) {
930 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
931 }
932 }
933
934 static void ide_sector_write(IDEState *s);
935
936 static void ide_sector_write_timer_cb(void *opaque)
937 {
938 IDEState *s = opaque;
939 ide_set_irq(s->bus);
940 }
941
942 static void ide_sector_write_cb(void *opaque, int ret)
943 {
944 IDEState *s = opaque;
945 int n;
946
947 if (ret == -ECANCELED) {
948 return;
949 }
950
951 s->pio_aiocb = NULL;
952 s->status &= ~BUSY_STAT;
953
954 if (ret != 0) {
955 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
956 return;
957 }
958 }
959
960 block_acct_done(blk_get_stats(s->blk), &s->acct);
961
962 n = s->nsector;
963 if (n > s->req_nb_sectors) {
964 n = s->req_nb_sectors;
965 }
966 s->nsector -= n;
967
968 ide_set_sector(s, ide_get_sector(s) + n);
969 if (s->nsector == 0) {
970 /* no more sectors to write */
971 ide_transfer_stop(s);
972 } else {
973 int n1 = s->nsector;
974 if (n1 > s->req_nb_sectors) {
975 n1 = s->req_nb_sectors;
976 }
977 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
978 ide_sector_write);
979 }
980
981 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
982 /* It seems there is a bug in the Windows 2000 installer HDD
983 IDE driver which fills the disk with empty logs when the
984 IDE write IRQ comes too early. This hack tries to correct
985 that at the expense of slower write performances. Use this
986 option _only_ to install Windows 2000. You must disable it
987 for normal use. */
988 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
989 (NANOSECONDS_PER_SECOND / 1000));
990 } else {
991 ide_set_irq(s->bus);
992 }
993 }
994
995 static void ide_sector_write(IDEState *s)
996 {
997 int64_t sector_num;
998 int n;
999
1000 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
1001 sector_num = ide_get_sector(s);
1002
1003 n = s->nsector;
1004 if (n > s->req_nb_sectors) {
1005 n = s->req_nb_sectors;
1006 }
1007
1008 trace_ide_sector_write(sector_num, n);
1009
1010 if (!ide_sect_range_ok(s, sector_num, n)) {
1011 ide_rw_error(s);
1012 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
1013 return;
1014 }
1015
1016 s->iov.iov_base = s->io_buffer;
1017 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
1018 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
1019
1020 block_acct_start(blk_get_stats(s->blk), &s->acct,
1021 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
1022 s->pio_aiocb = blk_aio_pwritev(s->blk, sector_num << BDRV_SECTOR_BITS,
1023 &s->qiov, 0, ide_sector_write_cb, s);
1024 }
1025
1026 static void ide_flush_cb(void *opaque, int ret)
1027 {
1028 IDEState *s = opaque;
1029
1030 s->pio_aiocb = NULL;
1031
1032 if (ret == -ECANCELED) {
1033 return;
1034 }
1035 if (ret < 0) {
1036 /* XXX: What sector number to set here? */
1037 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
1038 return;
1039 }
1040 }
1041
1042 if (s->blk) {
1043 block_acct_done(blk_get_stats(s->blk), &s->acct);
1044 }
1045 s->status = READY_STAT | SEEK_STAT;
1046 ide_cmd_done(s);
1047 ide_set_irq(s->bus);
1048 }
1049
1050 static void ide_flush_cache(IDEState *s)
1051 {
1052 if (s->blk == NULL) {
1053 ide_flush_cb(s, 0);
1054 return;
1055 }
1056
1057 s->status |= BUSY_STAT;
1058 ide_set_retry(s);
1059 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
1060
1061 if (blk_bs(s->blk)) {
1062 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
1063 } else {
1064 /* XXX blk_aio_flush() crashes when blk_bs(blk) is NULL, remove this
1065 * temporary workaround when blk_aio_*() functions handle NULL blk_bs.
1066 */
1067 ide_flush_cb(s, 0);
1068 }
1069 }
1070
1071 static void ide_cfata_metadata_inquiry(IDEState *s)
1072 {
1073 uint16_t *p;
1074 uint32_t spd;
1075
1076 p = (uint16_t *) s->io_buffer;
1077 memset(p, 0, 0x200);
1078 spd = ((s->mdata_size - 1) >> 9) + 1;
1079
1080 put_le16(p + 0, 0x0001); /* Data format revision */
1081 put_le16(p + 1, 0x0000); /* Media property: silicon */
1082 put_le16(p + 2, s->media_changed); /* Media status */
1083 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1084 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1085 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1086 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1087 }
1088
1089 static void ide_cfata_metadata_read(IDEState *s)
1090 {
1091 uint16_t *p;
1092
1093 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1094 s->status = ERR_STAT;
1095 s->error = ABRT_ERR;
1096 return;
1097 }
1098
1099 p = (uint16_t *) s->io_buffer;
1100 memset(p, 0, 0x200);
1101
1102 put_le16(p + 0, s->media_changed); /* Media status */
1103 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1104 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1105 s->nsector << 9), 0x200 - 2));
1106 }
1107
1108 static void ide_cfata_metadata_write(IDEState *s)
1109 {
1110 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1111 s->status = ERR_STAT;
1112 s->error = ABRT_ERR;
1113 return;
1114 }
1115
1116 s->media_changed = 0;
1117
1118 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1119 s->io_buffer + 2,
1120 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1121 s->nsector << 9), 0x200 - 2));
1122 }
1123
1124 /* called when the inserted state of the media has changed */
1125 static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
1126 {
1127 IDEState *s = opaque;
1128 uint64_t nb_sectors;
1129
1130 s->tray_open = !load;
1131 blk_get_geometry(s->blk, &nb_sectors);
1132 s->nb_sectors = nb_sectors;
1133
1134 /*
1135 * First indicate to the guest that a CD has been removed. That's
1136 * done on the next command the guest sends us.
1137 *
1138 * Then we set UNIT_ATTENTION, by which the guest will
1139 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1140 */
1141 s->cdrom_changed = 1;
1142 s->events.new_media = true;
1143 s->events.eject_request = false;
1144 ide_set_irq(s->bus);
1145 }
1146
1147 static void ide_cd_eject_request_cb(void *opaque, bool force)
1148 {
1149 IDEState *s = opaque;
1150
1151 s->events.eject_request = true;
1152 if (force) {
1153 s->tray_locked = false;
1154 }
1155 ide_set_irq(s->bus);
1156 }
1157
1158 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1159 {
1160 s->lba48 = lba48;
1161
1162 /* handle the 'magic' 0 nsector count conversion here. to avoid
1163 * fiddling with the rest of the read logic, we just store the
1164 * full sector count in ->nsector and ignore ->hob_nsector from now
1165 */
1166 if (!s->lba48) {
1167 if (!s->nsector)
1168 s->nsector = 256;
1169 } else {
1170 if (!s->nsector && !s->hob_nsector)
1171 s->nsector = 65536;
1172 else {
1173 int lo = s->nsector;
1174 int hi = s->hob_nsector;
1175
1176 s->nsector = (hi << 8) | lo;
1177 }
1178 }
1179 }
1180
1181 static void ide_clear_hob(IDEBus *bus)
1182 {
1183 /* any write clears HOB high bit of device control register */
1184 bus->ifs[0].select &= ~(1 << 7);
1185 bus->ifs[1].select &= ~(1 << 7);
1186 }
1187
1188 /* IOport [W]rite [R]egisters */
1189 enum ATA_IOPORT_WR {
1190 ATA_IOPORT_WR_DATA = 0,
1191 ATA_IOPORT_WR_FEATURES = 1,
1192 ATA_IOPORT_WR_SECTOR_COUNT = 2,
1193 ATA_IOPORT_WR_SECTOR_NUMBER = 3,
1194 ATA_IOPORT_WR_CYLINDER_LOW = 4,
1195 ATA_IOPORT_WR_CYLINDER_HIGH = 5,
1196 ATA_IOPORT_WR_DEVICE_HEAD = 6,
1197 ATA_IOPORT_WR_COMMAND = 7,
1198 ATA_IOPORT_WR_NUM_REGISTERS,
1199 };
1200
1201 const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
1202 [ATA_IOPORT_WR_DATA] = "Data",
1203 [ATA_IOPORT_WR_FEATURES] = "Features",
1204 [ATA_IOPORT_WR_SECTOR_COUNT] = "Sector Count",
1205 [ATA_IOPORT_WR_SECTOR_NUMBER] = "Sector Number",
1206 [ATA_IOPORT_WR_CYLINDER_LOW] = "Cylinder Low",
1207 [ATA_IOPORT_WR_CYLINDER_HIGH] = "Cylinder High",
1208 [ATA_IOPORT_WR_DEVICE_HEAD] = "Device/Head",
1209 [ATA_IOPORT_WR_COMMAND] = "Command"
1210 };
1211
1212 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1213 {
1214 IDEBus *bus = opaque;
1215 IDEState *s = idebus_active_if(bus);
1216 int reg_num = addr & 7;
1217
1218 trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
1219
1220 /* ignore writes to command block while busy with previous command */
1221 if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {
1222 return;
1223 }
1224
1225 switch (reg_num) {
1226 case 0:
1227 break;
1228 case ATA_IOPORT_WR_FEATURES:
1229 ide_clear_hob(bus);
1230 /* NOTE: data is written to the two drives */
1231 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1232 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1233 bus->ifs[0].feature = val;
1234 bus->ifs[1].feature = val;
1235 break;
1236 case ATA_IOPORT_WR_SECTOR_COUNT:
1237 ide_clear_hob(bus);
1238 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1239 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1240 bus->ifs[0].nsector = val;
1241 bus->ifs[1].nsector = val;
1242 break;
1243 case ATA_IOPORT_WR_SECTOR_NUMBER:
1244 ide_clear_hob(bus);
1245 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1246 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1247 bus->ifs[0].sector = val;
1248 bus->ifs[1].sector = val;
1249 break;
1250 case ATA_IOPORT_WR_CYLINDER_LOW:
1251 ide_clear_hob(bus);
1252 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1253 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1254 bus->ifs[0].lcyl = val;
1255 bus->ifs[1].lcyl = val;
1256 break;
1257 case ATA_IOPORT_WR_CYLINDER_HIGH:
1258 ide_clear_hob(bus);
1259 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1260 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1261 bus->ifs[0].hcyl = val;
1262 bus->ifs[1].hcyl = val;
1263 break;
1264 case ATA_IOPORT_WR_DEVICE_HEAD:
1265 /* FIXME: HOB readback uses bit 7 */
1266 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1267 bus->ifs[1].select = (val | 0x10) | 0xa0;
1268 /* select drive */
1269 bus->unit = (val >> 4) & 1;
1270 break;
1271 default:
1272 case ATA_IOPORT_WR_COMMAND:
1273 /* command */
1274 ide_exec_cmd(bus, val);
1275 break;
1276 }
1277 }
1278
1279 static void ide_reset(IDEState *s)
1280 {
1281 trace_ide_reset(s);
1282
1283 if (s->pio_aiocb) {
1284 blk_aio_cancel(s->pio_aiocb);
1285 s->pio_aiocb = NULL;
1286 }
1287
1288 if (s->drive_kind == IDE_CFATA)
1289 s->mult_sectors = 0;
1290 else
1291 s->mult_sectors = MAX_MULT_SECTORS;
1292 /* ide regs */
1293 s->feature = 0;
1294 s->error = 0;
1295 s->nsector = 0;
1296 s->sector = 0;
1297 s->lcyl = 0;
1298 s->hcyl = 0;
1299
1300 /* lba48 */
1301 s->hob_feature = 0;
1302 s->hob_sector = 0;
1303 s->hob_nsector = 0;
1304 s->hob_lcyl = 0;
1305 s->hob_hcyl = 0;
1306
1307 s->select = 0xa0;
1308 s->status = READY_STAT | SEEK_STAT;
1309
1310 s->lba48 = 0;
1311
1312 /* ATAPI specific */
1313 s->sense_key = 0;
1314 s->asc = 0;
1315 s->cdrom_changed = 0;
1316 s->packet_transfer_size = 0;
1317 s->elementary_transfer_size = 0;
1318 s->io_buffer_index = 0;
1319 s->cd_sector_size = 0;
1320 s->atapi_dma = 0;
1321 s->tray_locked = 0;
1322 s->tray_open = 0;
1323 /* ATA DMA state */
1324 s->io_buffer_size = 0;
1325 s->req_nb_sectors = 0;
1326
1327 ide_set_signature(s);
1328 /* init the transfer handler so that 0xffff is returned on data
1329 accesses */
1330 s->end_transfer_func = ide_dummy_transfer_stop;
1331 ide_dummy_transfer_stop(s);
1332 s->media_changed = 0;
1333 }
1334
1335 static bool cmd_nop(IDEState *s, uint8_t cmd)
1336 {
1337 return true;
1338 }
1339
1340 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1341 {
1342 /* Halt PIO (in the DRQ phase), then DMA */
1343 ide_transfer_cancel(s);
1344 ide_cancel_dma_sync(s);
1345
1346 /* Reset any PIO commands, reset signature, etc */
1347 ide_reset(s);
1348
1349 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1350 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1351 s->status = 0x00;
1352
1353 /* Do not overwrite status register */
1354 return false;
1355 }
1356
1357 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1358 {
1359 switch (s->feature) {
1360 case DSM_TRIM:
1361 if (s->blk) {
1362 ide_sector_start_dma(s, IDE_DMA_TRIM);
1363 return false;
1364 }
1365 break;
1366 }
1367
1368 ide_abort_command(s);
1369 return true;
1370 }
1371
1372 static bool cmd_identify(IDEState *s, uint8_t cmd)
1373 {
1374 if (s->blk && s->drive_kind != IDE_CD) {
1375 if (s->drive_kind != IDE_CFATA) {
1376 ide_identify(s);
1377 } else {
1378 ide_cfata_identify(s);
1379 }
1380 s->status = READY_STAT | SEEK_STAT;
1381 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1382 ide_set_irq(s->bus);
1383 return false;
1384 } else {
1385 if (s->drive_kind == IDE_CD) {
1386 ide_set_signature(s);
1387 }
1388 ide_abort_command(s);
1389 }
1390
1391 return true;
1392 }
1393
1394 static bool cmd_verify(IDEState *s, uint8_t cmd)
1395 {
1396 bool lba48 = (cmd == WIN_VERIFY_EXT);
1397
1398 /* do sector number check ? */
1399 ide_cmd_lba48_transform(s, lba48);
1400
1401 return true;
1402 }
1403
1404 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1405 {
1406 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1407 /* Disable Read and Write Multiple */
1408 s->mult_sectors = 0;
1409 } else if ((s->nsector & 0xff) != 0 &&
1410 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1411 (s->nsector & (s->nsector - 1)) != 0)) {
1412 ide_abort_command(s);
1413 } else {
1414 s->mult_sectors = s->nsector & 0xff;
1415 }
1416
1417 return true;
1418 }
1419
1420 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1421 {
1422 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1423
1424 if (!s->blk || !s->mult_sectors) {
1425 ide_abort_command(s);
1426 return true;
1427 }
1428
1429 ide_cmd_lba48_transform(s, lba48);
1430 s->req_nb_sectors = s->mult_sectors;
1431 ide_sector_read(s);
1432 return false;
1433 }
1434
1435 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1436 {
1437 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1438 int n;
1439
1440 if (!s->blk || !s->mult_sectors) {
1441 ide_abort_command(s);
1442 return true;
1443 }
1444
1445 ide_cmd_lba48_transform(s, lba48);
1446
1447 s->req_nb_sectors = s->mult_sectors;
1448 n = MIN(s->nsector, s->req_nb_sectors);
1449
1450 s->status = SEEK_STAT | READY_STAT;
1451 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1452
1453 s->media_changed = 1;
1454
1455 return false;
1456 }
1457
1458 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1459 {
1460 bool lba48 = (cmd == WIN_READ_EXT);
1461
1462 if (s->drive_kind == IDE_CD) {
1463 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1464 ide_abort_command(s);
1465 return true;
1466 }
1467
1468 if (!s->blk) {
1469 ide_abort_command(s);
1470 return true;
1471 }
1472
1473 ide_cmd_lba48_transform(s, lba48);
1474 s->req_nb_sectors = 1;
1475 ide_sector_read(s);
1476
1477 return false;
1478 }
1479
1480 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1481 {
1482 bool lba48 = (cmd == WIN_WRITE_EXT);
1483
1484 if (!s->blk) {
1485 ide_abort_command(s);
1486 return true;
1487 }
1488
1489 ide_cmd_lba48_transform(s, lba48);
1490
1491 s->req_nb_sectors = 1;
1492 s->status = SEEK_STAT | READY_STAT;
1493 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1494
1495 s->media_changed = 1;
1496
1497 return false;
1498 }
1499
1500 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1501 {
1502 bool lba48 = (cmd == WIN_READDMA_EXT);
1503
1504 if (!s->blk) {
1505 ide_abort_command(s);
1506 return true;
1507 }
1508
1509 ide_cmd_lba48_transform(s, lba48);
1510 ide_sector_start_dma(s, IDE_DMA_READ);
1511
1512 return false;
1513 }
1514
1515 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1516 {
1517 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1518
1519 if (!s->blk) {
1520 ide_abort_command(s);
1521 return true;
1522 }
1523
1524 ide_cmd_lba48_transform(s, lba48);
1525 ide_sector_start_dma(s, IDE_DMA_WRITE);
1526
1527 s->media_changed = 1;
1528
1529 return false;
1530 }
1531
1532 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1533 {
1534 ide_flush_cache(s);
1535 return false;
1536 }
1537
1538 static bool cmd_seek(IDEState *s, uint8_t cmd)
1539 {
1540 /* XXX: Check that seek is within bounds */
1541 return true;
1542 }
1543
1544 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1545 {
1546 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1547
1548 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1549 if (s->nb_sectors == 0) {
1550 ide_abort_command(s);
1551 return true;
1552 }
1553
1554 ide_cmd_lba48_transform(s, lba48);
1555 ide_set_sector(s, s->nb_sectors - 1);
1556
1557 return true;
1558 }
1559
1560 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1561 {
1562 s->nsector = 0xff; /* device active or idle */
1563 return true;
1564 }
1565
1566 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1567 {
1568 uint16_t *identify_data;
1569
1570 if (!s->blk) {
1571 ide_abort_command(s);
1572 return true;
1573 }
1574
1575 /* XXX: valid for CDROM ? */
1576 switch (s->feature) {
1577 case 0x02: /* write cache enable */
1578 blk_set_enable_write_cache(s->blk, true);
1579 identify_data = (uint16_t *)s->identify_data;
1580 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1581 return true;
1582 case 0x82: /* write cache disable */
1583 blk_set_enable_write_cache(s->blk, false);
1584 identify_data = (uint16_t *)s->identify_data;
1585 put_le16(identify_data + 85, (1 << 14) | 1);
1586 ide_flush_cache(s);
1587 return false;
1588 case 0xcc: /* reverting to power-on defaults enable */
1589 case 0x66: /* reverting to power-on defaults disable */
1590 case 0xaa: /* read look-ahead enable */
1591 case 0x55: /* read look-ahead disable */
1592 case 0x05: /* set advanced power management mode */
1593 case 0x85: /* disable advanced power management mode */
1594 case 0x69: /* NOP */
1595 case 0x67: /* NOP */
1596 case 0x96: /* NOP */
1597 case 0x9a: /* NOP */
1598 case 0x42: /* enable Automatic Acoustic Mode */
1599 case 0xc2: /* disable Automatic Acoustic Mode */
1600 return true;
1601 case 0x03: /* set transfer mode */
1602 {
1603 uint8_t val = s->nsector & 0x07;
1604 identify_data = (uint16_t *)s->identify_data;
1605
1606 switch (s->nsector >> 3) {
1607 case 0x00: /* pio default */
1608 case 0x01: /* pio mode */
1609 put_le16(identify_data + 62, 0x07);
1610 put_le16(identify_data + 63, 0x07);
1611 put_le16(identify_data + 88, 0x3f);
1612 break;
1613 case 0x02: /* sigle word dma mode*/
1614 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1615 put_le16(identify_data + 63, 0x07);
1616 put_le16(identify_data + 88, 0x3f);
1617 break;
1618 case 0x04: /* mdma mode */
1619 put_le16(identify_data + 62, 0x07);
1620 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1621 put_le16(identify_data + 88, 0x3f);
1622 break;
1623 case 0x08: /* udma mode */
1624 put_le16(identify_data + 62, 0x07);
1625 put_le16(identify_data + 63, 0x07);
1626 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1627 break;
1628 default:
1629 goto abort_cmd;
1630 }
1631 return true;
1632 }
1633 }
1634
1635 abort_cmd:
1636 ide_abort_command(s);
1637 return true;
1638 }
1639
1640
1641 /*** ATAPI commands ***/
1642
1643 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1644 {
1645 ide_atapi_identify(s);
1646 s->status = READY_STAT | SEEK_STAT;
1647 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1648 ide_set_irq(s->bus);
1649 return false;
1650 }
1651
1652 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1653 {
1654 ide_set_signature(s);
1655
1656 if (s->drive_kind == IDE_CD) {
1657 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1658 * devices to return a clear status register
1659 * with READY_STAT *not* set. */
1660 s->error = 0x01;
1661 } else {
1662 s->status = READY_STAT | SEEK_STAT;
1663 /* The bits of the error register are not as usual for this command!
1664 * They are part of the regular output (this is why ERR_STAT isn't set)
1665 * Device 0 passed, Device 1 passed or not present. */
1666 s->error = 0x01;
1667 ide_set_irq(s->bus);
1668 }
1669
1670 return false;
1671 }
1672
1673 static bool cmd_packet(IDEState *s, uint8_t cmd)
1674 {
1675 /* overlapping commands not supported */
1676 if (s->feature & 0x02) {
1677 ide_abort_command(s);
1678 return true;
1679 }
1680
1681 s->status = READY_STAT | SEEK_STAT;
1682 s->atapi_dma = s->feature & 1;
1683 if (s->atapi_dma) {
1684 s->dma_cmd = IDE_DMA_ATAPI;
1685 }
1686 s->nsector = 1;
1687 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1688 ide_atapi_cmd);
1689 return false;
1690 }
1691
1692
1693 /*** CF-ATA commands ***/
1694
1695 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1696 {
1697 s->error = 0x09; /* miscellaneous error */
1698 s->status = READY_STAT | SEEK_STAT;
1699 ide_set_irq(s->bus);
1700
1701 return false;
1702 }
1703
1704 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1705 {
1706 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1707 * required for Windows 8 to work with AHCI */
1708
1709 if (cmd == CFA_WEAR_LEVEL) {
1710 s->nsector = 0;
1711 }
1712
1713 if (cmd == CFA_ERASE_SECTORS) {
1714 s->media_changed = 1;
1715 }
1716
1717 return true;
1718 }
1719
1720 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1721 {
1722 s->status = READY_STAT | SEEK_STAT;
1723
1724 memset(s->io_buffer, 0, 0x200);
1725 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1726 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1727 s->io_buffer[0x02] = s->select; /* Head */
1728 s->io_buffer[0x03] = s->sector; /* Sector */
1729 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1730 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1731 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1732 s->io_buffer[0x13] = 0x00; /* Erase flag */
1733 s->io_buffer[0x18] = 0x00; /* Hot count */
1734 s->io_buffer[0x19] = 0x00; /* Hot count */
1735 s->io_buffer[0x1a] = 0x01; /* Hot count */
1736
1737 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1738 ide_set_irq(s->bus);
1739
1740 return false;
1741 }
1742
1743 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1744 {
1745 switch (s->feature) {
1746 case 0x02: /* Inquiry Metadata Storage */
1747 ide_cfata_metadata_inquiry(s);
1748 break;
1749 case 0x03: /* Read Metadata Storage */
1750 ide_cfata_metadata_read(s);
1751 break;
1752 case 0x04: /* Write Metadata Storage */
1753 ide_cfata_metadata_write(s);
1754 break;
1755 default:
1756 ide_abort_command(s);
1757 return true;
1758 }
1759
1760 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1761 s->status = 0x00; /* NOTE: READY is _not_ set */
1762 ide_set_irq(s->bus);
1763
1764 return false;
1765 }
1766
1767 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1768 {
1769 switch (s->feature) {
1770 case 0x01: /* sense temperature in device */
1771 s->nsector = 0x50; /* +20 C */
1772 break;
1773 default:
1774 ide_abort_command(s);
1775 return true;
1776 }
1777
1778 return true;
1779 }
1780
1781
1782 /*** SMART commands ***/
1783
1784 static bool cmd_smart(IDEState *s, uint8_t cmd)
1785 {
1786 int n;
1787
1788 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1789 goto abort_cmd;
1790 }
1791
1792 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1793 goto abort_cmd;
1794 }
1795
1796 switch (s->feature) {
1797 case SMART_DISABLE:
1798 s->smart_enabled = 0;
1799 return true;
1800
1801 case SMART_ENABLE:
1802 s->smart_enabled = 1;
1803 return true;
1804
1805 case SMART_ATTR_AUTOSAVE:
1806 switch (s->sector) {
1807 case 0x00:
1808 s->smart_autosave = 0;
1809 break;
1810 case 0xf1:
1811 s->smart_autosave = 1;
1812 break;
1813 default:
1814 goto abort_cmd;
1815 }
1816 return true;
1817
1818 case SMART_STATUS:
1819 if (!s->smart_errors) {
1820 s->hcyl = 0xc2;
1821 s->lcyl = 0x4f;
1822 } else {
1823 s->hcyl = 0x2c;
1824 s->lcyl = 0xf4;
1825 }
1826 return true;
1827
1828 case SMART_READ_THRESH:
1829 memset(s->io_buffer, 0, 0x200);
1830 s->io_buffer[0] = 0x01; /* smart struct version */
1831
1832 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1833 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1834 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1835 }
1836
1837 /* checksum */
1838 for (n = 0; n < 511; n++) {
1839 s->io_buffer[511] += s->io_buffer[n];
1840 }
1841 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1842
1843 s->status = READY_STAT | SEEK_STAT;
1844 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1845 ide_set_irq(s->bus);
1846 return false;
1847
1848 case SMART_READ_DATA:
1849 memset(s->io_buffer, 0, 0x200);
1850 s->io_buffer[0] = 0x01; /* smart struct version */
1851
1852 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1853 int i;
1854 for (i = 0; i < 11; i++) {
1855 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1856 }
1857 }
1858
1859 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1860 if (s->smart_selftest_count == 0) {
1861 s->io_buffer[363] = 0;
1862 } else {
1863 s->io_buffer[363] =
1864 s->smart_selftest_data[3 +
1865 (s->smart_selftest_count - 1) *
1866 24];
1867 }
1868 s->io_buffer[364] = 0x20;
1869 s->io_buffer[365] = 0x01;
1870 /* offline data collection capacity: execute + self-test*/
1871 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1872 s->io_buffer[368] = 0x03; /* smart capability (1) */
1873 s->io_buffer[369] = 0x00; /* smart capability (2) */
1874 s->io_buffer[370] = 0x01; /* error logging supported */
1875 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1876 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1877 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1878
1879 for (n = 0; n < 511; n++) {
1880 s->io_buffer[511] += s->io_buffer[n];
1881 }
1882 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1883
1884 s->status = READY_STAT | SEEK_STAT;
1885 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1886 ide_set_irq(s->bus);
1887 return false;
1888
1889 case SMART_READ_LOG:
1890 switch (s->sector) {
1891 case 0x01: /* summary smart error log */
1892 memset(s->io_buffer, 0, 0x200);
1893 s->io_buffer[0] = 0x01;
1894 s->io_buffer[1] = 0x00; /* no error entries */
1895 s->io_buffer[452] = s->smart_errors & 0xff;
1896 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1897
1898 for (n = 0; n < 511; n++) {
1899 s->io_buffer[511] += s->io_buffer[n];
1900 }
1901 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1902 break;
1903 case 0x06: /* smart self test log */
1904 memset(s->io_buffer, 0, 0x200);
1905 s->io_buffer[0] = 0x01;
1906 if (s->smart_selftest_count == 0) {
1907 s->io_buffer[508] = 0;
1908 } else {
1909 s->io_buffer[508] = s->smart_selftest_count;
1910 for (n = 2; n < 506; n++) {
1911 s->io_buffer[n] = s->smart_selftest_data[n];
1912 }
1913 }
1914
1915 for (n = 0; n < 511; n++) {
1916 s->io_buffer[511] += s->io_buffer[n];
1917 }
1918 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1919 break;
1920 default:
1921 goto abort_cmd;
1922 }
1923 s->status = READY_STAT | SEEK_STAT;
1924 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1925 ide_set_irq(s->bus);
1926 return false;
1927
1928 case SMART_EXECUTE_OFFLINE:
1929 switch (s->sector) {
1930 case 0: /* off-line routine */
1931 case 1: /* short self test */
1932 case 2: /* extended self test */
1933 s->smart_selftest_count++;
1934 if (s->smart_selftest_count > 21) {
1935 s->smart_selftest_count = 1;
1936 }
1937 n = 2 + (s->smart_selftest_count - 1) * 24;
1938 s->smart_selftest_data[n] = s->sector;
1939 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1940 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1941 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1942 break;
1943 default:
1944 goto abort_cmd;
1945 }
1946 return true;
1947 }
1948
1949 abort_cmd:
1950 ide_abort_command(s);
1951 return true;
1952 }
1953
1954 #define HD_OK (1u << IDE_HD)
1955 #define CD_OK (1u << IDE_CD)
1956 #define CFA_OK (1u << IDE_CFATA)
1957 #define HD_CFA_OK (HD_OK | CFA_OK)
1958 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1959
1960 /* Set the Disk Seek Completed status bit during completion */
1961 #define SET_DSC (1u << 8)
1962
1963 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1964 static const struct {
1965 /* Returns true if the completion code should be run */
1966 bool (*handler)(IDEState *s, uint8_t cmd);
1967 int flags;
1968 } ide_cmd_table[0x100] = {
1969 /* NOP not implemented, mandatory for CD */
1970 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1971 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
1972 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1973 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1974 [WIN_READ] = { cmd_read_pio, ALL_OK },
1975 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
1976 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1977 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1978 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1979 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1980 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1981 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1982 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1983 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1984 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1985 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1986 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1987 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1988 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1989 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1990 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1991 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1992 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1993 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1994 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1995 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1996 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1997 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1998 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1999 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
2000 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
2001 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
2002 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
2003 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
2004 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
2005 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
2006 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
2007 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
2008 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
2009 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
2010 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
2011 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
2012 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
2013 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
2014 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
2015 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
2016 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
2017 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
2018 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
2019 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
2020 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
2021 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
2022 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
2023 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
2024 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
2025 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
2026 };
2027
2028 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
2029 {
2030 return cmd < ARRAY_SIZE(ide_cmd_table)
2031 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
2032 }
2033
2034 void ide_exec_cmd(IDEBus *bus, uint32_t val)
2035 {
2036 IDEState *s;
2037 bool complete;
2038
2039 s = idebus_active_if(bus);
2040 trace_ide_exec_cmd(bus, s, val);
2041
2042 /* ignore commands to non existent slave */
2043 if (s != bus->ifs && !s->blk) {
2044 return;
2045 }
2046
2047 /* Only RESET is allowed while BSY and/or DRQ are set,
2048 * and only to ATAPI devices. */
2049 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2050 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2051 return;
2052 }
2053 }
2054
2055 if (!ide_cmd_permitted(s, val)) {
2056 ide_abort_command(s);
2057 ide_set_irq(s->bus);
2058 return;
2059 }
2060
2061 s->status = READY_STAT | BUSY_STAT;
2062 s->error = 0;
2063 s->io_buffer_offset = 0;
2064
2065 complete = ide_cmd_table[val].handler(s, val);
2066 if (complete) {
2067 s->status &= ~BUSY_STAT;
2068 assert(!!s->error == !!(s->status & ERR_STAT));
2069
2070 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2071 s->status |= SEEK_STAT;
2072 }
2073
2074 ide_cmd_done(s);
2075 ide_set_irq(s->bus);
2076 }
2077 }
2078
2079 /* IOport [R]ead [R]egisters */
2080 enum ATA_IOPORT_RR {
2081 ATA_IOPORT_RR_DATA = 0,
2082 ATA_IOPORT_RR_ERROR = 1,
2083 ATA_IOPORT_RR_SECTOR_COUNT = 2,
2084 ATA_IOPORT_RR_SECTOR_NUMBER = 3,
2085 ATA_IOPORT_RR_CYLINDER_LOW = 4,
2086 ATA_IOPORT_RR_CYLINDER_HIGH = 5,
2087 ATA_IOPORT_RR_DEVICE_HEAD = 6,
2088 ATA_IOPORT_RR_STATUS = 7,
2089 ATA_IOPORT_RR_NUM_REGISTERS,
2090 };
2091
2092 const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
2093 [ATA_IOPORT_RR_DATA] = "Data",
2094 [ATA_IOPORT_RR_ERROR] = "Error",
2095 [ATA_IOPORT_RR_SECTOR_COUNT] = "Sector Count",
2096 [ATA_IOPORT_RR_SECTOR_NUMBER] = "Sector Number",
2097 [ATA_IOPORT_RR_CYLINDER_LOW] = "Cylinder Low",
2098 [ATA_IOPORT_RR_CYLINDER_HIGH] = "Cylinder High",
2099 [ATA_IOPORT_RR_DEVICE_HEAD] = "Device/Head",
2100 [ATA_IOPORT_RR_STATUS] = "Status"
2101 };
2102
2103 uint32_t ide_ioport_read(void *opaque, uint32_t addr)
2104 {
2105 IDEBus *bus = opaque;
2106 IDEState *s = idebus_active_if(bus);
2107 uint32_t reg_num;
2108 int ret, hob;
2109
2110 reg_num = addr & 7;
2111 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2112 //hob = s->select & (1 << 7);
2113 hob = 0;
2114 switch (reg_num) {
2115 case ATA_IOPORT_RR_DATA:
2116 ret = 0xff;
2117 break;
2118 case ATA_IOPORT_RR_ERROR:
2119 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2120 (s != bus->ifs && !s->blk)) {
2121 ret = 0;
2122 } else if (!hob) {
2123 ret = s->error;
2124 } else {
2125 ret = s->hob_feature;
2126 }
2127 break;
2128 case ATA_IOPORT_RR_SECTOR_COUNT:
2129 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2130 ret = 0;
2131 } else if (!hob) {
2132 ret = s->nsector & 0xff;
2133 } else {
2134 ret = s->hob_nsector;
2135 }
2136 break;
2137 case ATA_IOPORT_RR_SECTOR_NUMBER:
2138 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2139 ret = 0;
2140 } else if (!hob) {
2141 ret = s->sector;
2142 } else {
2143 ret = s->hob_sector;
2144 }
2145 break;
2146 case ATA_IOPORT_RR_CYLINDER_LOW:
2147 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2148 ret = 0;
2149 } else if (!hob) {
2150 ret = s->lcyl;
2151 } else {
2152 ret = s->hob_lcyl;
2153 }
2154 break;
2155 case ATA_IOPORT_RR_CYLINDER_HIGH:
2156 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2157 ret = 0;
2158 } else if (!hob) {
2159 ret = s->hcyl;
2160 } else {
2161 ret = s->hob_hcyl;
2162 }
2163 break;
2164 case ATA_IOPORT_RR_DEVICE_HEAD:
2165 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2166 ret = 0;
2167 } else {
2168 ret = s->select;
2169 }
2170 break;
2171 default:
2172 case ATA_IOPORT_RR_STATUS:
2173 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2174 (s != bus->ifs && !s->blk)) {
2175 ret = 0;
2176 } else {
2177 ret = s->status;
2178 }
2179 qemu_irq_lower(bus->irq);
2180 break;
2181 }
2182
2183 trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s);
2184 return ret;
2185 }
2186
2187 uint32_t ide_status_read(void *opaque, uint32_t addr)
2188 {
2189 IDEBus *bus = opaque;
2190 IDEState *s = idebus_active_if(bus);
2191 int ret;
2192
2193 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2194 (s != bus->ifs && !s->blk)) {
2195 ret = 0;
2196 } else {
2197 ret = s->status;
2198 }
2199
2200 trace_ide_status_read(addr, ret, bus, s);
2201 return ret;
2202 }
2203
2204 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2205 {
2206 IDEBus *bus = opaque;
2207 IDEState *s;
2208 int i;
2209
2210 trace_ide_cmd_write(addr, val, bus);
2211
2212 /* common for both drives */
2213 if (!(bus->cmd & IDE_CMD_RESET) &&
2214 (val & IDE_CMD_RESET)) {
2215 /* reset low to high */
2216 for(i = 0;i < 2; i++) {
2217 s = &bus->ifs[i];
2218 s->status = BUSY_STAT | SEEK_STAT;
2219 s->error = 0x01;
2220 }
2221 } else if ((bus->cmd & IDE_CMD_RESET) &&
2222 !(val & IDE_CMD_RESET)) {
2223 /* high to low */
2224 for(i = 0;i < 2; i++) {
2225 s = &bus->ifs[i];
2226 if (s->drive_kind == IDE_CD)
2227 s->status = 0x00; /* NOTE: READY is _not_ set */
2228 else
2229 s->status = READY_STAT | SEEK_STAT;
2230 ide_set_signature(s);
2231 }
2232 }
2233
2234 bus->cmd = val;
2235 }
2236
2237 /*
2238 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2239 * transferred from the device to the guest), false if it's a PIO in
2240 */
2241 static bool ide_is_pio_out(IDEState *s)
2242 {
2243 if (s->end_transfer_func == ide_sector_write ||
2244 s->end_transfer_func == ide_atapi_cmd) {
2245 return false;
2246 } else if (s->end_transfer_func == ide_sector_read ||
2247 s->end_transfer_func == ide_transfer_stop ||
2248 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2249 s->end_transfer_func == ide_dummy_transfer_stop) {
2250 return true;
2251 }
2252
2253 abort();
2254 }
2255
2256 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2257 {
2258 IDEBus *bus = opaque;
2259 IDEState *s = idebus_active_if(bus);
2260 uint8_t *p;
2261
2262 /* PIO data access allowed only when DRQ bit is set. The result of a write
2263 * during PIO out is indeterminate, just ignore it. */
2264 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2265 return;
2266 }
2267
2268 p = s->data_ptr;
2269 if (p + 2 > s->data_end) {
2270 return;
2271 }
2272
2273 *(uint16_t *)p = le16_to_cpu(val);
2274 p += 2;
2275 s->data_ptr = p;
2276 if (p >= s->data_end) {
2277 s->status &= ~DRQ_STAT;
2278 s->end_transfer_func(s);
2279 }
2280 }
2281
2282 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2283 {
2284 IDEBus *bus = opaque;
2285 IDEState *s = idebus_active_if(bus);
2286 uint8_t *p;
2287 int ret;
2288
2289 /* PIO data access allowed only when DRQ bit is set. The result of a read
2290 * during PIO in is indeterminate, return 0 and don't move forward. */
2291 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2292 return 0;
2293 }
2294
2295 p = s->data_ptr;
2296 if (p + 2 > s->data_end) {
2297 return 0;
2298 }
2299
2300 ret = cpu_to_le16(*(uint16_t *)p);
2301 p += 2;
2302 s->data_ptr = p;
2303 if (p >= s->data_end) {
2304 s->status &= ~DRQ_STAT;
2305 s->end_transfer_func(s);
2306 }
2307 return ret;
2308 }
2309
2310 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2311 {
2312 IDEBus *bus = opaque;
2313 IDEState *s = idebus_active_if(bus);
2314 uint8_t *p;
2315
2316 /* PIO data access allowed only when DRQ bit is set. The result of a write
2317 * during PIO out is indeterminate, just ignore it. */
2318 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2319 return;
2320 }
2321
2322 p = s->data_ptr;
2323 if (p + 4 > s->data_end) {
2324 return;
2325 }
2326
2327 *(uint32_t *)p = le32_to_cpu(val);
2328 p += 4;
2329 s->data_ptr = p;
2330 if (p >= s->data_end) {
2331 s->status &= ~DRQ_STAT;
2332 s->end_transfer_func(s);
2333 }
2334 }
2335
2336 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2337 {
2338 IDEBus *bus = opaque;
2339 IDEState *s = idebus_active_if(bus);
2340 uint8_t *p;
2341 int ret;
2342
2343 /* PIO data access allowed only when DRQ bit is set. The result of a read
2344 * during PIO in is indeterminate, return 0 and don't move forward. */
2345 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2346 return 0;
2347 }
2348
2349 p = s->data_ptr;
2350 if (p + 4 > s->data_end) {
2351 return 0;
2352 }
2353
2354 ret = cpu_to_le32(*(uint32_t *)p);
2355 p += 4;
2356 s->data_ptr = p;
2357 if (p >= s->data_end) {
2358 s->status &= ~DRQ_STAT;
2359 s->end_transfer_func(s);
2360 }
2361 return ret;
2362 }
2363
2364 static void ide_dummy_transfer_stop(IDEState *s)
2365 {
2366 s->data_ptr = s->io_buffer;
2367 s->data_end = s->io_buffer;
2368 s->io_buffer[0] = 0xff;
2369 s->io_buffer[1] = 0xff;
2370 s->io_buffer[2] = 0xff;
2371 s->io_buffer[3] = 0xff;
2372 }
2373
2374 void ide_bus_reset(IDEBus *bus)
2375 {
2376 bus->unit = 0;
2377 bus->cmd = 0;
2378 ide_reset(&bus->ifs[0]);
2379 ide_reset(&bus->ifs[1]);
2380 ide_clear_hob(bus);
2381
2382 /* pending async DMA */
2383 if (bus->dma->aiocb) {
2384 #ifdef DEBUG_AIO
2385 printf("aio_cancel\n");
2386 #endif
2387 blk_aio_cancel(bus->dma->aiocb);
2388 bus->dma->aiocb = NULL;
2389 }
2390
2391 /* reset dma provider too */
2392 if (bus->dma->ops->reset) {
2393 bus->dma->ops->reset(bus->dma);
2394 }
2395 }
2396
2397 static bool ide_cd_is_tray_open(void *opaque)
2398 {
2399 return ((IDEState *)opaque)->tray_open;
2400 }
2401
2402 static bool ide_cd_is_medium_locked(void *opaque)
2403 {
2404 return ((IDEState *)opaque)->tray_locked;
2405 }
2406
2407 static void ide_resize_cb(void *opaque)
2408 {
2409 IDEState *s = opaque;
2410 uint64_t nb_sectors;
2411
2412 if (!s->identify_set) {
2413 return;
2414 }
2415
2416 blk_get_geometry(s->blk, &nb_sectors);
2417 s->nb_sectors = nb_sectors;
2418
2419 /* Update the identify data buffer. */
2420 if (s->drive_kind == IDE_CFATA) {
2421 ide_cfata_identify_size(s);
2422 } else {
2423 /* IDE_CD uses a different set of callbacks entirely. */
2424 assert(s->drive_kind != IDE_CD);
2425 ide_identify_size(s);
2426 }
2427 }
2428
2429 static const BlockDevOps ide_cd_block_ops = {
2430 .change_media_cb = ide_cd_change_cb,
2431 .eject_request_cb = ide_cd_eject_request_cb,
2432 .is_tray_open = ide_cd_is_tray_open,
2433 .is_medium_locked = ide_cd_is_medium_locked,
2434 };
2435
2436 static const BlockDevOps ide_hd_block_ops = {
2437 .resize_cb = ide_resize_cb,
2438 };
2439
2440 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2441 const char *version, const char *serial, const char *model,
2442 uint64_t wwn,
2443 uint32_t cylinders, uint32_t heads, uint32_t secs,
2444 int chs_trans)
2445 {
2446 uint64_t nb_sectors;
2447
2448 s->blk = blk;
2449 s->drive_kind = kind;
2450
2451 blk_get_geometry(blk, &nb_sectors);
2452 s->cylinders = cylinders;
2453 s->heads = heads;
2454 s->sectors = secs;
2455 s->chs_trans = chs_trans;
2456 s->nb_sectors = nb_sectors;
2457 s->wwn = wwn;
2458 /* The SMART values should be preserved across power cycles
2459 but they aren't. */
2460 s->smart_enabled = 1;
2461 s->smart_autosave = 1;
2462 s->smart_errors = 0;
2463 s->smart_selftest_count = 0;
2464 if (kind == IDE_CD) {
2465 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2466 blk_set_guest_block_size(blk, 2048);
2467 } else {
2468 if (!blk_is_inserted(s->blk)) {
2469 error_report("Device needs media, but drive is empty");
2470 return -1;
2471 }
2472 if (blk_is_read_only(blk)) {
2473 error_report("Can't use a read-only drive");
2474 return -1;
2475 }
2476 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2477 }
2478 if (serial) {
2479 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2480 } else {
2481 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2482 "QM%05d", s->drive_serial);
2483 }
2484 if (model) {
2485 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2486 } else {
2487 switch (kind) {
2488 case IDE_CD:
2489 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2490 break;
2491 case IDE_CFATA:
2492 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2493 break;
2494 default:
2495 strcpy(s->drive_model_str, "QEMU HARDDISK");
2496 break;
2497 }
2498 }
2499
2500 if (version) {
2501 pstrcpy(s->version, sizeof(s->version), version);
2502 } else {
2503 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
2504 }
2505
2506 ide_reset(s);
2507 blk_iostatus_enable(blk);
2508 return 0;
2509 }
2510
2511 static void ide_init1(IDEBus *bus, int unit)
2512 {
2513 static int drive_serial = 1;
2514 IDEState *s = &bus->ifs[unit];
2515
2516 s->bus = bus;
2517 s->unit = unit;
2518 s->drive_serial = drive_serial++;
2519 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2520 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2521 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2522 memset(s->io_buffer, 0, s->io_buffer_total_len);
2523
2524 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2525 memset(s->smart_selftest_data, 0, 512);
2526
2527 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2528 ide_sector_write_timer_cb, s);
2529 }
2530
2531 static int ide_nop_int(IDEDMA *dma, int x)
2532 {
2533 return 0;
2534 }
2535
2536 static void ide_nop(IDEDMA *dma)
2537 {
2538 }
2539
2540 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
2541 {
2542 return 0;
2543 }
2544
2545 static const IDEDMAOps ide_dma_nop_ops = {
2546 .prepare_buf = ide_nop_int32,
2547 .restart_dma = ide_nop,
2548 .rw_buf = ide_nop_int,
2549 };
2550
2551 static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2552 {
2553 s->unit = s->bus->retry_unit;
2554 ide_set_sector(s, s->bus->retry_sector_num);
2555 s->nsector = s->bus->retry_nsector;
2556 s->bus->dma->ops->restart_dma(s->bus->dma);
2557 s->io_buffer_size = 0;
2558 s->dma_cmd = dma_cmd;
2559 ide_start_dma(s, ide_dma_cb);
2560 }
2561
2562 static void ide_restart_bh(void *opaque)
2563 {
2564 IDEBus *bus = opaque;
2565 IDEState *s;
2566 bool is_read;
2567 int error_status;
2568
2569 qemu_bh_delete(bus->bh);
2570 bus->bh = NULL;
2571
2572 error_status = bus->error_status;
2573 if (bus->error_status == 0) {
2574 return;
2575 }
2576
2577 s = idebus_active_if(bus);
2578 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2579
2580 /* The error status must be cleared before resubmitting the request: The
2581 * request may fail again, and this case can only be distinguished if the
2582 * called function can set a new error status. */
2583 bus->error_status = 0;
2584
2585 /* The HBA has generically asked to be kicked on retry */
2586 if (error_status & IDE_RETRY_HBA) {
2587 if (s->bus->dma->ops->restart) {
2588 s->bus->dma->ops->restart(s->bus->dma);
2589 }
2590 } else if (IS_IDE_RETRY_DMA(error_status)) {
2591 if (error_status & IDE_RETRY_TRIM) {
2592 ide_restart_dma(s, IDE_DMA_TRIM);
2593 } else {
2594 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2595 }
2596 } else if (IS_IDE_RETRY_PIO(error_status)) {
2597 if (is_read) {
2598 ide_sector_read(s);
2599 } else {
2600 ide_sector_write(s);
2601 }
2602 } else if (error_status & IDE_RETRY_FLUSH) {
2603 ide_flush_cache(s);
2604 } else if (IS_IDE_RETRY_ATAPI(error_status)) {
2605 assert(s->end_transfer_func == ide_atapi_cmd);
2606 ide_atapi_dma_restart(s);
2607 } else {
2608 abort();
2609 }
2610 }
2611
2612 static void ide_restart_cb(void *opaque, int running, RunState state)
2613 {
2614 IDEBus *bus = opaque;
2615
2616 if (!running)
2617 return;
2618
2619 if (!bus->bh) {
2620 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2621 qemu_bh_schedule(bus->bh);
2622 }
2623 }
2624
2625 void ide_register_restart_cb(IDEBus *bus)
2626 {
2627 if (bus->dma->ops->restart_dma) {
2628 bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2629 }
2630 }
2631
2632 static IDEDMA ide_dma_nop = {
2633 .ops = &ide_dma_nop_ops,
2634 .aiocb = NULL,
2635 };
2636
2637 void ide_init2(IDEBus *bus, qemu_irq irq)
2638 {
2639 int i;
2640
2641 for(i = 0; i < 2; i++) {
2642 ide_init1(bus, i);
2643 ide_reset(&bus->ifs[i]);
2644 }
2645 bus->irq = irq;
2646 bus->dma = &ide_dma_nop;
2647 }
2648
2649 void ide_exit(IDEState *s)
2650 {
2651 timer_del(s->sector_write_timer);
2652 timer_free(s->sector_write_timer);
2653 qemu_vfree(s->smart_selftest_data);
2654 qemu_vfree(s->io_buffer);
2655 }
2656
2657 static const MemoryRegionPortio ide_portio_list[] = {
2658 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2659 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2660 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
2661 PORTIO_END_OF_LIST(),
2662 };
2663
2664 static const MemoryRegionPortio ide_portio2_list[] = {
2665 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2666 PORTIO_END_OF_LIST(),
2667 };
2668
2669 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2670 {
2671 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2672 bridge has been setup properly to always register with ISA. */
2673 isa_register_portio_list(dev, &bus->portio_list,
2674 iobase, ide_portio_list, bus, "ide");
2675
2676 if (iobase2) {
2677 isa_register_portio_list(dev, &bus->portio2_list,
2678 iobase2, ide_portio2_list, bus, "ide");
2679 }
2680 }
2681
2682 static bool is_identify_set(void *opaque, int version_id)
2683 {
2684 IDEState *s = opaque;
2685
2686 return s->identify_set != 0;
2687 }
2688
2689 static EndTransferFunc* transfer_end_table[] = {
2690 ide_sector_read,
2691 ide_sector_write,
2692 ide_transfer_stop,
2693 ide_atapi_cmd_reply_end,
2694 ide_atapi_cmd,
2695 ide_dummy_transfer_stop,
2696 };
2697
2698 static int transfer_end_table_idx(EndTransferFunc *fn)
2699 {
2700 int i;
2701
2702 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2703 if (transfer_end_table[i] == fn)
2704 return i;
2705
2706 return -1;
2707 }
2708
2709 static int ide_drive_post_load(void *opaque, int version_id)
2710 {
2711 IDEState *s = opaque;
2712
2713 if (s->blk && s->identify_set) {
2714 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2715 }
2716 return 0;
2717 }
2718
2719 static int ide_drive_pio_post_load(void *opaque, int version_id)
2720 {
2721 IDEState *s = opaque;
2722
2723 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2724 return -EINVAL;
2725 }
2726 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2727 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2728 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2729 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
2730
2731 return 0;
2732 }
2733
2734 static void ide_drive_pio_pre_save(void *opaque)
2735 {
2736 IDEState *s = opaque;
2737 int idx;
2738
2739 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2740 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2741
2742 idx = transfer_end_table_idx(s->end_transfer_func);
2743 if (idx == -1) {
2744 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2745 __func__);
2746 s->end_transfer_fn_idx = 2;
2747 } else {
2748 s->end_transfer_fn_idx = idx;
2749 }
2750 }
2751
2752 static bool ide_drive_pio_state_needed(void *opaque)
2753 {
2754 IDEState *s = opaque;
2755
2756 return ((s->status & DRQ_STAT) != 0)
2757 || (s->bus->error_status & IDE_RETRY_PIO);
2758 }
2759
2760 static bool ide_tray_state_needed(void *opaque)
2761 {
2762 IDEState *s = opaque;
2763
2764 return s->tray_open || s->tray_locked;
2765 }
2766
2767 static bool ide_atapi_gesn_needed(void *opaque)
2768 {
2769 IDEState *s = opaque;
2770
2771 return s->events.new_media || s->events.eject_request;
2772 }
2773
2774 static bool ide_error_needed(void *opaque)
2775 {
2776 IDEBus *bus = opaque;
2777
2778 return (bus->error_status != 0);
2779 }
2780
2781 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2782 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2783 .name ="ide_drive/atapi/gesn_state",
2784 .version_id = 1,
2785 .minimum_version_id = 1,
2786 .needed = ide_atapi_gesn_needed,
2787 .fields = (VMStateField[]) {
2788 VMSTATE_BOOL(events.new_media, IDEState),
2789 VMSTATE_BOOL(events.eject_request, IDEState),
2790 VMSTATE_END_OF_LIST()
2791 }
2792 };
2793
2794 static const VMStateDescription vmstate_ide_tray_state = {
2795 .name = "ide_drive/tray_state",
2796 .version_id = 1,
2797 .minimum_version_id = 1,
2798 .needed = ide_tray_state_needed,
2799 .fields = (VMStateField[]) {
2800 VMSTATE_BOOL(tray_open, IDEState),
2801 VMSTATE_BOOL(tray_locked, IDEState),
2802 VMSTATE_END_OF_LIST()
2803 }
2804 };
2805
2806 static const VMStateDescription vmstate_ide_drive_pio_state = {
2807 .name = "ide_drive/pio_state",
2808 .version_id = 1,
2809 .minimum_version_id = 1,
2810 .pre_save = ide_drive_pio_pre_save,
2811 .post_load = ide_drive_pio_post_load,
2812 .needed = ide_drive_pio_state_needed,
2813 .fields = (VMStateField[]) {
2814 VMSTATE_INT32(req_nb_sectors, IDEState),
2815 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2816 vmstate_info_uint8, uint8_t),
2817 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2818 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2819 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2820 VMSTATE_INT32(elementary_transfer_size, IDEState),
2821 VMSTATE_INT32(packet_transfer_size, IDEState),
2822 VMSTATE_END_OF_LIST()
2823 }
2824 };
2825
2826 const VMStateDescription vmstate_ide_drive = {
2827 .name = "ide_drive",
2828 .version_id = 3,
2829 .minimum_version_id = 0,
2830 .post_load = ide_drive_post_load,
2831 .fields = (VMStateField[]) {
2832 VMSTATE_INT32(mult_sectors, IDEState),
2833 VMSTATE_INT32(identify_set, IDEState),
2834 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2835 VMSTATE_UINT8(feature, IDEState),
2836 VMSTATE_UINT8(error, IDEState),
2837 VMSTATE_UINT32(nsector, IDEState),
2838 VMSTATE_UINT8(sector, IDEState),
2839 VMSTATE_UINT8(lcyl, IDEState),
2840 VMSTATE_UINT8(hcyl, IDEState),
2841 VMSTATE_UINT8(hob_feature, IDEState),
2842 VMSTATE_UINT8(hob_sector, IDEState),
2843 VMSTATE_UINT8(hob_nsector, IDEState),
2844 VMSTATE_UINT8(hob_lcyl, IDEState),
2845 VMSTATE_UINT8(hob_hcyl, IDEState),
2846 VMSTATE_UINT8(select, IDEState),
2847 VMSTATE_UINT8(status, IDEState),
2848 VMSTATE_UINT8(lba48, IDEState),
2849 VMSTATE_UINT8(sense_key, IDEState),
2850 VMSTATE_UINT8(asc, IDEState),
2851 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2852 VMSTATE_END_OF_LIST()
2853 },
2854 .subsections = (const VMStateDescription*[]) {
2855 &vmstate_ide_drive_pio_state,
2856 &vmstate_ide_tray_state,
2857 &vmstate_ide_atapi_gesn_state,
2858 NULL
2859 }
2860 };
2861
2862 static const VMStateDescription vmstate_ide_error_status = {
2863 .name ="ide_bus/error",
2864 .version_id = 2,
2865 .minimum_version_id = 1,
2866 .needed = ide_error_needed,
2867 .fields = (VMStateField[]) {
2868 VMSTATE_INT32(error_status, IDEBus),
2869 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2870 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2871 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
2872 VMSTATE_END_OF_LIST()
2873 }
2874 };
2875
2876 const VMStateDescription vmstate_ide_bus = {
2877 .name = "ide_bus",
2878 .version_id = 1,
2879 .minimum_version_id = 1,
2880 .fields = (VMStateField[]) {
2881 VMSTATE_UINT8(cmd, IDEBus),
2882 VMSTATE_UINT8(unit, IDEBus),
2883 VMSTATE_END_OF_LIST()
2884 },
2885 .subsections = (const VMStateDescription*[]) {
2886 &vmstate_ide_error_status,
2887 NULL
2888 }
2889 };
2890
2891 void ide_drive_get(DriveInfo **hd, int n)
2892 {
2893 int i;
2894
2895 for (i = 0; i < n; i++) {
2896 hd[i] = drive_get_by_index(IF_IDE, i);
2897 }
2898 }
AR7 emulation for QEMU