hw/arm/ast2400.c

   1 /*
   2  * AST2400 SoC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/ast2400.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22
  23 #define AST2400_UART_5_BASE      0x00184000
  24 #define AST2400_IOMEM_SIZE       0x00200000
  25 #define AST2400_IOMEM_BASE       0x1E600000
  26 #define AST2400_VIC_BASE         0x1E6C0000
  27 #define AST2400_SCU_BASE         0x1E6E2000
  28 #define AST2400_TIMER_BASE       0x1E782000
  29 #define AST2400_I2C_BASE         0x1E78A000
  30
  31 #define AST2400_A0_SILICON_REV   0x02000303
  32
  33 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  34 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  35
  36 /*
  37  * IO handlers: simply catch any reads/writes to IO addresses that aren't
  38  * handled by a device mapping.
  39  */
  40
  41 static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
  42 {
  43     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  44                   __func__, offset, size);
  45     return 0;
  46 }
  47
  48 static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
  49                 unsigned size)
  50 {
  51     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  52                   __func__, offset, value, size);
  53 }
  54
  55 static const MemoryRegionOps ast2400_io_ops = {
  56     .read = ast2400_io_read,
  57     .write = ast2400_io_write,
  58     .endianness = DEVICE_LITTLE_ENDIAN,
  59 };
  60
  61 static void ast2400_init(Object *obj)
  62 {
  63     AST2400State *s = AST2400(obj);
  64
  65     s->cpu = cpu_arm_init("arm926");
  66
  67     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
  68     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
  69     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
  70
  71     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
  72     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
  73     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
  74
  75     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
  76     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
  77     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
  78
  79     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
  80     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
  81     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
  82     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
  83                          AST2400_A0_SILICON_REV);
  84     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
  85                               "hw-strap1", &error_abort);
  86     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
  87                               "hw-strap2", &error_abort);
  88 }
  89
  90 static void ast2400_realize(DeviceState *dev, Error **errp)
  91 {
  92     int i;
  93     AST2400State *s = AST2400(dev);
  94     Error *err = NULL;
  95
  96     /* IO space */
  97     memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
  98             "ast2400.io", AST2400_IOMEM_SIZE);
  99     memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
 100             &s->iomem, -1);
 101
 102     /* VIC */
 103     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 104     if (err) {
 105         error_propagate(errp, err);
 106         return;
 107     }
 108     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
 109     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 110                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 111     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 112                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
 113
 114     /* Timer */
 115     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 116     if (err) {
 117         error_propagate(errp, err);
 118         return;
 119     }
 120     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
 121     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 122         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 123         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 124     }
 125
 126     /* SCU */
 127     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 128     if (err) {
 129         error_propagate(errp, err);
 130         return;
 131     }
 132     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
 133
 134     /* UART - attach an 8250 to the IO space as our UART5 */
 135     if (serial_hds[0]) {
 136         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 137         serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
 138                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 139     }
 140
 141     /* I2C */
 142     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 143     if (err) {
 144         error_propagate(errp, err);
 145         return;
 146     }
 147     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);
 148     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 149                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 150 }
 151
 152 static void ast2400_class_init(ObjectClass *oc, void *data)
 153 {
 154     DeviceClass *dc = DEVICE_CLASS(oc);
 155
 156     dc->realize = ast2400_realize;
 157
 158     /*
 159      * Reason: creates an ARM CPU, thus use after free(), see
 160      * arm_cpu_class_init()
 161      */
 162     dc->cannot_destroy_with_object_finalize_yet = true;
 163 }
 164
 165 static const TypeInfo ast2400_type_info = {
 166     .name = TYPE_AST2400,
 167     .parent = TYPE_SYS_BUS_DEVICE,
 168     .instance_size = sizeof(AST2400State),
 169     .instance_init = ast2400_init,
 170     .class_init = ast2400_class_init,
 171 };
 172
 173 static void ast2400_register_types(void)
 174 {
 175     type_register_static(&ast2400_type_info);
 176 }
 177
 178 type_init(ast2400_register_types)