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hw/arm/musca: Add MPCs
[qemu/ar7.git] / target / ppc / translate_init.inc.c
blobd8849060043baf76e6b30dff266f0200301184f8
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include "kvm_ppc.h"
24 #include "sysemu/arch_init.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
32 #include "qapi/qmp/qnull.h"
33 #include "qapi/visitor.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/ppc/ppc.h"
36 #include "mmu-book3s-v3.h"
37 #include "sysemu/qtest.h"
38 #include "qemu/cutils.h"
39 #include "disas/capstone.h"
40 #include "fpu/softfloat.h"
41 #include "qapi/qapi-commands-target.h"
42
43 //#define PPC_DUMP_CPU
44 //#define PPC_DEBUG_SPR
45 //#define PPC_DUMP_SPR_ACCESSES
46 /* #define USE_APPLE_GDB */
47
48 /* Generic callbacks:
49 * do nothing but store/retrieve spr value
50 */
51 static void spr_load_dump_spr(int sprn)
52 {
53 #ifdef PPC_DUMP_SPR_ACCESSES
54 TCGv_i32 t0 = tcg_const_i32(sprn);
55 gen_helper_load_dump_spr(cpu_env, t0);
56 tcg_temp_free_i32(t0);
57 #endif
58 }
59
60 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
61 {
62 gen_load_spr(cpu_gpr[gprn], sprn);
63 spr_load_dump_spr(sprn);
64 }
65
66 static void spr_store_dump_spr(int sprn)
67 {
68 #ifdef PPC_DUMP_SPR_ACCESSES
69 TCGv_i32 t0 = tcg_const_i32(sprn);
70 gen_helper_store_dump_spr(cpu_env, t0);
71 tcg_temp_free_i32(t0);
72 #endif
73 }
74
75 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
76 {
77 gen_store_spr(sprn, cpu_gpr[gprn]);
78 spr_store_dump_spr(sprn);
79 }
80
81 #if !defined(CONFIG_USER_ONLY)
82 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
83 {
84 #ifdef TARGET_PPC64
85 TCGv t0 = tcg_temp_new();
86 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
87 gen_store_spr(sprn, t0);
88 tcg_temp_free(t0);
89 spr_store_dump_spr(sprn);
90 #else
91 spr_write_generic(ctx, sprn, gprn);
92 #endif
93 }
94
95 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
96 {
97 TCGv t0 = tcg_temp_new();
98 TCGv t1 = tcg_temp_new();
99 gen_load_spr(t0, sprn);
100 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
101 tcg_gen_and_tl(t0, t0, t1);
102 gen_store_spr(sprn, t0);
103 tcg_temp_free(t0);
104 tcg_temp_free(t1);
105 }
106
107 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
108 {
109 }
110
111 #endif
112
113 /* SPR common to all PowerPC */
114 /* XER */
115 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
116 {
117 gen_read_xer(ctx, cpu_gpr[gprn]);
118 }
119
120 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
121 {
122 gen_write_xer(cpu_gpr[gprn]);
123 }
124
125 /* LR */
126 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
127 {
128 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
129 }
130
131 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
132 {
133 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
134 }
135
136 /* CFAR */
137 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
138 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
139 {
140 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
141 }
142
143 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
144 {
145 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
146 }
147 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
148
149 /* CTR */
150 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
151 {
152 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
153 }
154
155 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
156 {
157 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
158 }
159
160 /* User read access to SPR */
161 /* USPRx */
162 /* UMMCRx */
163 /* UPMCx */
164 /* USIA */
165 /* UDECR */
166 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
167 {
168 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
169 }
170
171 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
172 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
173 {
174 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
175 }
176 #endif
177
178 /* SPR common to all non-embedded PowerPC */
179 /* DECR */
180 #if !defined(CONFIG_USER_ONLY)
181 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
182 {
183 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
184 gen_io_start();
185 }
186 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
187 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
188 gen_io_end();
189 gen_stop_exception(ctx);
190 }
191 }
192
193 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
194 {
195 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
196 gen_io_start();
197 }
198 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
199 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
200 gen_io_end();
201 gen_stop_exception(ctx);
202 }
203 }
204 #endif
205
206 /* SPR common to all non-embedded PowerPC, except 601 */
207 /* Time base */
208 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
209 {
210 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
211 gen_io_start();
212 }
213 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
214 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
215 gen_io_end();
216 gen_stop_exception(ctx);
217 }
218 }
219
220 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
221 {
222 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
223 gen_io_start();
224 }
225 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
226 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
227 gen_io_end();
228 gen_stop_exception(ctx);
229 }
230 }
231
232 __attribute__ (( unused ))
233 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
234 {
235 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
236 }
237
238 __attribute__ (( unused ))
239 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
240 {
241 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
242 }
243
244 #if !defined(CONFIG_USER_ONLY)
245 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
246 {
247 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
248 gen_io_start();
249 }
250 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
251 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
252 gen_io_end();
253 gen_stop_exception(ctx);
254 }
255 }
256
257 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
258 {
259 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
260 gen_io_start();
261 }
262 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
263 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
264 gen_io_end();
265 gen_stop_exception(ctx);
266 }
267 }
268
269 __attribute__ (( unused ))
270 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
271 {
272 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
273 }
274
275 __attribute__ (( unused ))
276 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
277 {
278 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
279 }
280
281 #if defined(TARGET_PPC64)
282 __attribute__ (( unused ))
283 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
284 {
285 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
286 }
287
288 /* HDECR */
289 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
290 {
291 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
292 gen_io_start();
293 }
294 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
295 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
296 gen_io_end();
297 gen_stop_exception(ctx);
298 }
299 }
300
301 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
302 {
303 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
304 gen_io_start();
305 }
306 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
307 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
308 gen_io_end();
309 gen_stop_exception(ctx);
310 }
311 }
312
313 #endif
314 #endif
315
316 #if !defined(CONFIG_USER_ONLY)
317 /* IBAT0U...IBAT0U */
318 /* IBAT0L...IBAT7L */
319 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
320 {
321 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
322 }
323
324 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
325 {
326 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
327 }
328
329 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
330 {
331 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
332 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
333 tcg_temp_free_i32(t0);
334 }
335
336 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
337 {
338 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
339 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
340 tcg_temp_free_i32(t0);
341 }
342
343 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
346 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
353 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 /* DBAT0U...DBAT7U */
358 /* DBAT0L...DBAT7L */
359 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
360 {
361 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
362 }
363
364 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
365 {
366 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
367 }
368
369 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
370 {
371 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
372 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
373 tcg_temp_free_i32(t0);
374 }
375
376 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
377 {
378 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
379 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
380 tcg_temp_free_i32(t0);
381 }
382
383 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
384 {
385 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
386 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
387 tcg_temp_free_i32(t0);
388 }
389
390 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
391 {
392 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
393 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
394 tcg_temp_free_i32(t0);
395 }
396
397 /* SDR1 */
398 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
399 {
400 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
401 }
402
403 #if defined(TARGET_PPC64)
404 /* 64 bits PowerPC specific SPRs */
405 /* PIDR */
406 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
407 {
408 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
409 }
410
411 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
412 {
413 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
414 }
415
416 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
417 {
418 TCGv t0 = tcg_temp_new();
419 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
420 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
421 tcg_temp_free(t0);
422 }
423 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
424 {
425 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
426 }
427
428 static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
429 {
430 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
431 }
432 #endif
433 #endif
434
435 /* PowerPC 601 specific registers */
436 /* RTC */
437 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
438 {
439 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
440 }
441
442 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
443 {
444 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
445 }
446
447 #if !defined(CONFIG_USER_ONLY)
448 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
449 {
450 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
451 }
452
453 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
454 {
455 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
456 }
457
458 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
459 {
460 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
461 /* Must stop the translation as endianness may have changed */
462 gen_stop_exception(ctx);
463 }
464 #endif
465
466 /* Unified bats */
467 #if !defined(CONFIG_USER_ONLY)
468 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
469 {
470 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
471 }
472
473 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
474 {
475 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
476 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
477 tcg_temp_free_i32(t0);
478 }
479
480 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
481 {
482 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
483 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
484 tcg_temp_free_i32(t0);
485 }
486 #endif
487
488 /* PowerPC 40x specific registers */
489 #if !defined(CONFIG_USER_ONLY)
490 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
491 {
492 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
493 }
494
495 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
496 {
497 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
498 }
499
500 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
501 {
502 gen_store_spr(sprn, cpu_gpr[gprn]);
503 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
504 /* We must stop translation as we may have rebooted */
505 gen_stop_exception(ctx);
506 }
507
508 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
509 {
510 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
511 }
512
513 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
514 {
515 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
516 }
517
518 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
519 {
520 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
521 }
522 #endif
523
524 /* PowerPC 403 specific registers */
525 /* PBL1 / PBU1 / PBL2 / PBU2 */
526 #if !defined(CONFIG_USER_ONLY)
527 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
528 {
529 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
530 }
531
532 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
533 {
534 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
535 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
536 tcg_temp_free_i32(t0);
537 }
538
539 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
540 {
541 TCGv t0 = tcg_temp_new();
542 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
543 gen_store_spr(SPR_PIR, t0);
544 tcg_temp_free(t0);
545 }
546 #endif
547
548 /* SPE specific registers */
549 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
550 {
551 TCGv_i32 t0 = tcg_temp_new_i32();
552 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
553 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
554 tcg_temp_free_i32(t0);
555 }
556
557 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
558 {
559 TCGv_i32 t0 = tcg_temp_new_i32();
560 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
561 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
562 tcg_temp_free_i32(t0);
563 }
564
565 #if !defined(CONFIG_USER_ONLY)
566 /* Callback used to write the exception vector base */
567 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
568 {
569 TCGv t0 = tcg_temp_new();
570 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
571 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
572 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
573 gen_store_spr(sprn, t0);
574 tcg_temp_free(t0);
575 }
576
577 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
578 {
579 int sprn_offs;
580
581 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
582 sprn_offs = sprn - SPR_BOOKE_IVOR0;
583 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
584 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
585 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
586 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
587 } else {
588 printf("Trying to write an unknown exception vector %d %03x\n",
589 sprn, sprn);
590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
591 return;
592 }
593
594 TCGv t0 = tcg_temp_new();
595 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
596 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
597 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
598 gen_store_spr(sprn, t0);
599 tcg_temp_free(t0);
600 }
601 #endif
602
603 static inline void vscr_init(CPUPPCState *env, uint32_t val)
604 {
605 /* Altivec always uses round-to-nearest */
606 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
607 helper_mtvscr(env, val);
608 }
609
610 #ifdef CONFIG_USER_ONLY
611 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
612 oea_read, oea_write, one_reg_id, initial_value) \
613 _spr_register(env, num, name, uea_read, uea_write, initial_value)
614 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
615 oea_read, oea_write, hea_read, hea_write, \
616 one_reg_id, initial_value) \
617 _spr_register(env, num, name, uea_read, uea_write, initial_value)
618 #else
619 #if !defined(CONFIG_KVM)
620 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
621 oea_read, oea_write, one_reg_id, initial_value) \
622 _spr_register(env, num, name, uea_read, uea_write, \
623 oea_read, oea_write, oea_read, oea_write, initial_value)
624 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
625 oea_read, oea_write, hea_read, hea_write, \
626 one_reg_id, initial_value) \
627 _spr_register(env, num, name, uea_read, uea_write, \
628 oea_read, oea_write, hea_read, hea_write, initial_value)
629 #else
630 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
631 oea_read, oea_write, one_reg_id, initial_value) \
632 _spr_register(env, num, name, uea_read, uea_write, \
633 oea_read, oea_write, oea_read, oea_write, \
634 one_reg_id, initial_value)
635 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
636 oea_read, oea_write, hea_read, hea_write, \
637 one_reg_id, initial_value) \
638 _spr_register(env, num, name, uea_read, uea_write, \
639 oea_read, oea_write, hea_read, hea_write, \
640 one_reg_id, initial_value)
641 #endif
642 #endif
643
644 #define spr_register(env, num, name, uea_read, uea_write, \
645 oea_read, oea_write, initial_value) \
646 spr_register_kvm(env, num, name, uea_read, uea_write, \
647 oea_read, oea_write, 0, initial_value)
648
649 #define spr_register_hv(env, num, name, uea_read, uea_write, \
650 oea_read, oea_write, hea_read, hea_write, \
651 initial_value) \
652 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
653 oea_read, oea_write, hea_read, hea_write, \
654 0, initial_value)
655
656 static inline void _spr_register(CPUPPCState *env, int num,
657 const char *name,
658 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
659 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
660 #if !defined(CONFIG_USER_ONLY)
661
662 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
663 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
664 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
665 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
666 #endif
667 #if defined(CONFIG_KVM)
668 uint64_t one_reg_id,
669 #endif
670 target_ulong initial_value)
671 {
672 ppc_spr_t *spr;
673
674 spr = &env->spr_cb[num];
675 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
676 #if !defined(CONFIG_USER_ONLY)
677 spr->oea_read != NULL || spr->oea_write != NULL ||
678 #endif
679 spr->uea_read != NULL || spr->uea_write != NULL) {
680 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
681 exit(1);
682 }
683 #if defined(PPC_DEBUG_SPR)
684 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
685 name, initial_value);
686 #endif
687 spr->name = name;
688 spr->uea_read = uea_read;
689 spr->uea_write = uea_write;
690 #if !defined(CONFIG_USER_ONLY)
691 spr->oea_read = oea_read;
692 spr->oea_write = oea_write;
693 spr->hea_read = hea_read;
694 spr->hea_write = hea_write;
695 #endif
696 #if defined(CONFIG_KVM)
697 spr->one_reg_id = one_reg_id,
698 #endif
699 env->spr[num] = spr->default_value = initial_value;
700 }
701
702 /* Generic PowerPC SPRs */
703 static void gen_spr_generic(CPUPPCState *env)
704 {
705 /* Integer processing */
706 spr_register(env, SPR_XER, "XER",
707 &spr_read_xer, &spr_write_xer,
708 &spr_read_xer, &spr_write_xer,
709 0x00000000);
710 /* Branch contol */
711 spr_register(env, SPR_LR, "LR",
712 &spr_read_lr, &spr_write_lr,
713 &spr_read_lr, &spr_write_lr,
714 0x00000000);
715 spr_register(env, SPR_CTR, "CTR",
716 &spr_read_ctr, &spr_write_ctr,
717 &spr_read_ctr, &spr_write_ctr,
718 0x00000000);
719 /* Interrupt processing */
720 spr_register(env, SPR_SRR0, "SRR0",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724 spr_register(env, SPR_SRR1, "SRR1",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, &spr_write_generic,
727 0x00000000);
728 /* Processor control */
729 spr_register(env, SPR_SPRG0, "SPRG0",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
733 spr_register(env, SPR_SPRG1, "SPRG1",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 0x00000000);
737 spr_register(env, SPR_SPRG2, "SPRG2",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
740 0x00000000);
741 spr_register(env, SPR_SPRG3, "SPRG3",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745 }
746
747 /* SPR common to all non-embedded PowerPC, including 601 */
748 static void gen_spr_ne_601(CPUPPCState *env)
749 {
750 /* Exception processing */
751 spr_register_kvm(env, SPR_DSISR, "DSISR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 KVM_REG_PPC_DSISR, 0x00000000);
755 spr_register_kvm(env, SPR_DAR, "DAR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 KVM_REG_PPC_DAR, 0x00000000);
759 /* Timer */
760 spr_register(env, SPR_DECR, "DECR",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_decr, &spr_write_decr,
763 0x00000000);
764 }
765
766 /* Storage Description Register 1 */
767 static void gen_spr_sdr1(CPUPPCState *env)
768 {
769 #ifndef CONFIG_USER_ONLY
770 if (env->has_hv_mode) {
771 /* SDR1 is a hypervisor resource on CPUs which have a
772 * hypervisor mode */
773 spr_register_hv(env, SPR_SDR1, "SDR1",
774 SPR_NOACCESS, SPR_NOACCESS,
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_sdr1,
777 0x00000000);
778 } else {
779 spr_register(env, SPR_SDR1, "SDR1",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_sdr1,
782 0x00000000);
783 }
784 #endif
785 }
786
787 /* BATs 0-3 */
788 static void gen_low_BATs(CPUPPCState *env)
789 {
790 #if !defined(CONFIG_USER_ONLY)
791 spr_register(env, SPR_IBAT0U, "IBAT0U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_ibat, &spr_write_ibatu,
794 0x00000000);
795 spr_register(env, SPR_IBAT0L, "IBAT0L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_ibat, &spr_write_ibatl,
798 0x00000000);
799 spr_register(env, SPR_IBAT1U, "IBAT1U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat, &spr_write_ibatu,
802 0x00000000);
803 spr_register(env, SPR_IBAT1L, "IBAT1L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat, &spr_write_ibatl,
806 0x00000000);
807 spr_register(env, SPR_IBAT2U, "IBAT2U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat, &spr_write_ibatu,
810 0x00000000);
811 spr_register(env, SPR_IBAT2L, "IBAT2L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_ibat, &spr_write_ibatl,
814 0x00000000);
815 spr_register(env, SPR_IBAT3U, "IBAT3U",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat, &spr_write_ibatu,
818 0x00000000);
819 spr_register(env, SPR_IBAT3L, "IBAT3L",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_ibat, &spr_write_ibatl,
822 0x00000000);
823 spr_register(env, SPR_DBAT0U, "DBAT0U",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_dbat, &spr_write_dbatu,
826 0x00000000);
827 spr_register(env, SPR_DBAT0L, "DBAT0L",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_dbat, &spr_write_dbatl,
830 0x00000000);
831 spr_register(env, SPR_DBAT1U, "DBAT1U",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat, &spr_write_dbatu,
834 0x00000000);
835 spr_register(env, SPR_DBAT1L, "DBAT1L",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat, &spr_write_dbatl,
838 0x00000000);
839 spr_register(env, SPR_DBAT2U, "DBAT2U",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat, &spr_write_dbatu,
842 0x00000000);
843 spr_register(env, SPR_DBAT2L, "DBAT2L",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_dbat, &spr_write_dbatl,
846 0x00000000);
847 spr_register(env, SPR_DBAT3U, "DBAT3U",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat, &spr_write_dbatu,
850 0x00000000);
851 spr_register(env, SPR_DBAT3L, "DBAT3L",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_dbat, &spr_write_dbatl,
854 0x00000000);
855 env->nb_BATs += 4;
856 #endif
857 }
858
859 /* BATs 4-7 */
860 static void gen_high_BATs(CPUPPCState *env)
861 {
862 #if !defined(CONFIG_USER_ONLY)
863 spr_register(env, SPR_IBAT4U, "IBAT4U",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_ibat_h, &spr_write_ibatu_h,
866 0x00000000);
867 spr_register(env, SPR_IBAT4L, "IBAT4L",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_ibat_h, &spr_write_ibatl_h,
870 0x00000000);
871 spr_register(env, SPR_IBAT5U, "IBAT5U",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_ibat_h, &spr_write_ibatu_h,
874 0x00000000);
875 spr_register(env, SPR_IBAT5L, "IBAT5L",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_ibat_h, &spr_write_ibatl_h,
878 0x00000000);
879 spr_register(env, SPR_IBAT6U, "IBAT6U",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_ibat_h, &spr_write_ibatu_h,
882 0x00000000);
883 spr_register(env, SPR_IBAT6L, "IBAT6L",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_ibat_h, &spr_write_ibatl_h,
886 0x00000000);
887 spr_register(env, SPR_IBAT7U, "IBAT7U",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_ibat_h, &spr_write_ibatu_h,
890 0x00000000);
891 spr_register(env, SPR_IBAT7L, "IBAT7L",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_ibat_h, &spr_write_ibatl_h,
894 0x00000000);
895 spr_register(env, SPR_DBAT4U, "DBAT4U",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_dbat_h, &spr_write_dbatu_h,
898 0x00000000);
899 spr_register(env, SPR_DBAT4L, "DBAT4L",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_dbat_h, &spr_write_dbatl_h,
902 0x00000000);
903 spr_register(env, SPR_DBAT5U, "DBAT5U",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_dbat_h, &spr_write_dbatu_h,
906 0x00000000);
907 spr_register(env, SPR_DBAT5L, "DBAT5L",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_dbat_h, &spr_write_dbatl_h,
910 0x00000000);
911 spr_register(env, SPR_DBAT6U, "DBAT6U",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_dbat_h, &spr_write_dbatu_h,
914 0x00000000);
915 spr_register(env, SPR_DBAT6L, "DBAT6L",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_dbat_h, &spr_write_dbatl_h,
918 0x00000000);
919 spr_register(env, SPR_DBAT7U, "DBAT7U",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_dbat_h, &spr_write_dbatu_h,
922 0x00000000);
923 spr_register(env, SPR_DBAT7L, "DBAT7L",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_dbat_h, &spr_write_dbatl_h,
926 0x00000000);
927 env->nb_BATs += 4;
928 #endif
929 }
930
931 /* Generic PowerPC time base */
932 static void gen_tbl(CPUPPCState *env)
933 {
934 spr_register(env, SPR_VTBL, "TBL",
935 &spr_read_tbl, SPR_NOACCESS,
936 &spr_read_tbl, SPR_NOACCESS,
937 0x00000000);
938 spr_register(env, SPR_TBL, "TBL",
939 &spr_read_tbl, SPR_NOACCESS,
940 &spr_read_tbl, &spr_write_tbl,
941 0x00000000);
942 spr_register(env, SPR_VTBU, "TBU",
943 &spr_read_tbu, SPR_NOACCESS,
944 &spr_read_tbu, SPR_NOACCESS,
945 0x00000000);
946 spr_register(env, SPR_TBU, "TBU",
947 &spr_read_tbu, SPR_NOACCESS,
948 &spr_read_tbu, &spr_write_tbu,
949 0x00000000);
950 }
951
952 /* Softare table search registers */
953 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
954 {
955 #if !defined(CONFIG_USER_ONLY)
956 env->nb_tlb = nb_tlbs;
957 env->nb_ways = nb_ways;
958 env->id_tlbs = 1;
959 env->tlb_type = TLB_6XX;
960 spr_register(env, SPR_DMISS, "DMISS",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, SPR_NOACCESS,
963 0x00000000);
964 spr_register(env, SPR_DCMP, "DCMP",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, SPR_NOACCESS,
967 0x00000000);
968 spr_register(env, SPR_HASH1, "HASH1",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_generic, SPR_NOACCESS,
971 0x00000000);
972 spr_register(env, SPR_HASH2, "HASH2",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_generic, SPR_NOACCESS,
975 0x00000000);
976 spr_register(env, SPR_IMISS, "IMISS",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, SPR_NOACCESS,
979 0x00000000);
980 spr_register(env, SPR_ICMP, "ICMP",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, SPR_NOACCESS,
983 0x00000000);
984 spr_register(env, SPR_RPA, "RPA",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988 #endif
989 }
990
991 /* SPR common to MPC755 and G2 */
992 static void gen_spr_G2_755(CPUPPCState *env)
993 {
994 /* SGPRs */
995 spr_register(env, SPR_SPRG4, "SPRG4",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 spr_register(env, SPR_SPRG5, "SPRG5",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003 spr_register(env, SPR_SPRG6, "SPRG6",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 spr_register(env, SPR_SPRG7, "SPRG7",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 }
1012
1013 /* SPR common to all 7xx PowerPC implementations */
1014 static void gen_spr_7xx(CPUPPCState *env)
1015 {
1016 /* Breakpoints */
1017 /* XXX : not implemented */
1018 spr_register_kvm(env, SPR_DABR, "DABR",
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, &spr_write_generic,
1021 KVM_REG_PPC_DABR, 0x00000000);
1022 /* XXX : not implemented */
1023 spr_register(env, SPR_IABR, "IABR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_generic,
1026 0x00000000);
1027 /* Cache management */
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_ICTC, "ICTC",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* Performance monitors */
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_7XX_PMC1, "PMC1",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_7XX_PMC2, "PMC2",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_7XX_PMC3, "PMC3",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_7XX_PMC4, "PMC4",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 /* XXX : not implemented */
1065 spr_register(env, SPR_7XX_SIAR, "SIAR",
1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, SPR_NOACCESS,
1068 0x00000000);
1069 /* XXX : not implemented */
1070 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1071 &spr_read_ureg, SPR_NOACCESS,
1072 &spr_read_ureg, SPR_NOACCESS,
1073 0x00000000);
1074 /* XXX : not implemented */
1075 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1076 &spr_read_ureg, SPR_NOACCESS,
1077 &spr_read_ureg, SPR_NOACCESS,
1078 0x00000000);
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1081 &spr_read_ureg, SPR_NOACCESS,
1082 &spr_read_ureg, SPR_NOACCESS,
1083 0x00000000);
1084 /* XXX : not implemented */
1085 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1086 &spr_read_ureg, SPR_NOACCESS,
1087 &spr_read_ureg, SPR_NOACCESS,
1088 0x00000000);
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1091 &spr_read_ureg, SPR_NOACCESS,
1092 &spr_read_ureg, SPR_NOACCESS,
1093 0x00000000);
1094 /* XXX : not implemented */
1095 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1096 &spr_read_ureg, SPR_NOACCESS,
1097 &spr_read_ureg, SPR_NOACCESS,
1098 0x00000000);
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_7XX_USIAR, "USIAR",
1101 &spr_read_ureg, SPR_NOACCESS,
1102 &spr_read_ureg, SPR_NOACCESS,
1103 0x00000000);
1104 /* External access control */
1105 /* XXX : not implemented */
1106 spr_register(env, SPR_EAR, "EAR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 }
1111
1112 #ifdef TARGET_PPC64
1113 #ifndef CONFIG_USER_ONLY
1114 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1115 {
1116 TCGv t0 = tcg_temp_new();
1117 TCGv t1 = tcg_temp_new();
1118 TCGv t2 = tcg_temp_new();
1119
1120 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1121 * spr_write_generic for HV mode in the SPR table
1122 */
1123
1124 /* Build insertion mask into t1 based on context */
1125 if (ctx->pr) {
1126 gen_load_spr(t1, SPR_UAMOR);
1127 } else {
1128 gen_load_spr(t1, SPR_AMOR);
1129 }
1130
1131 /* Mask new bits into t2 */
1132 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1133
1134 /* Load AMR and clear new bits in t0 */
1135 gen_load_spr(t0, SPR_AMR);
1136 tcg_gen_andc_tl(t0, t0, t1);
1137
1138 /* Or'in new bits and write it out */
1139 tcg_gen_or_tl(t0, t0, t2);
1140 gen_store_spr(SPR_AMR, t0);
1141 spr_store_dump_spr(SPR_AMR);
1142
1143 tcg_temp_free(t0);
1144 tcg_temp_free(t1);
1145 tcg_temp_free(t2);
1146 }
1147
1148 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1149 {
1150 TCGv t0 = tcg_temp_new();
1151 TCGv t1 = tcg_temp_new();
1152 TCGv t2 = tcg_temp_new();
1153
1154 /* Note, the HV=1 case is handled earlier by simply using
1155 * spr_write_generic for HV mode in the SPR table
1156 */
1157
1158 /* Build insertion mask into t1 based on context */
1159 gen_load_spr(t1, SPR_AMOR);
1160
1161 /* Mask new bits into t2 */
1162 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1163
1164 /* Load AMR and clear new bits in t0 */
1165 gen_load_spr(t0, SPR_UAMOR);
1166 tcg_gen_andc_tl(t0, t0, t1);
1167
1168 /* Or'in new bits and write it out */
1169 tcg_gen_or_tl(t0, t0, t2);
1170 gen_store_spr(SPR_UAMOR, t0);
1171 spr_store_dump_spr(SPR_UAMOR);
1172
1173 tcg_temp_free(t0);
1174 tcg_temp_free(t1);
1175 tcg_temp_free(t2);
1176 }
1177
1178 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1179 {
1180 TCGv t0 = tcg_temp_new();
1181 TCGv t1 = tcg_temp_new();
1182 TCGv t2 = tcg_temp_new();
1183
1184 /* Note, the HV=1 case is handled earlier by simply using
1185 * spr_write_generic for HV mode in the SPR table
1186 */
1187
1188 /* Build insertion mask into t1 based on context */
1189 gen_load_spr(t1, SPR_AMOR);
1190
1191 /* Mask new bits into t2 */
1192 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1193
1194 /* Load AMR and clear new bits in t0 */
1195 gen_load_spr(t0, SPR_IAMR);
1196 tcg_gen_andc_tl(t0, t0, t1);
1197
1198 /* Or'in new bits and write it out */
1199 tcg_gen_or_tl(t0, t0, t2);
1200 gen_store_spr(SPR_IAMR, t0);
1201 spr_store_dump_spr(SPR_IAMR);
1202
1203 tcg_temp_free(t0);
1204 tcg_temp_free(t1);
1205 tcg_temp_free(t2);
1206 }
1207 #endif /* CONFIG_USER_ONLY */
1208
1209 static void gen_spr_amr(CPUPPCState *env)
1210 {
1211 #ifndef CONFIG_USER_ONLY
1212 /* Virtual Page Class Key protection */
1213 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1214 * userspace accessible, 29 is privileged. So we only need to set
1215 * the kvm ONE_REG id on one of them, we use 29 */
1216 spr_register(env, SPR_UAMR, "UAMR",
1217 &spr_read_generic, &spr_write_amr,
1218 &spr_read_generic, &spr_write_amr,
1219 0);
1220 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_amr,
1223 &spr_read_generic, &spr_write_generic,
1224 KVM_REG_PPC_AMR, 0);
1225 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_generic, &spr_write_uamor,
1228 &spr_read_generic, &spr_write_generic,
1229 KVM_REG_PPC_UAMOR, 0);
1230 spr_register_hv(env, SPR_AMOR, "AMOR",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_generic,
1234 0);
1235 #endif /* !CONFIG_USER_ONLY */
1236 }
1237
1238 static void gen_spr_iamr(CPUPPCState *env)
1239 {
1240 #ifndef CONFIG_USER_ONLY
1241 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_iamr,
1244 &spr_read_generic, &spr_write_generic,
1245 KVM_REG_PPC_IAMR, 0);
1246 #endif /* !CONFIG_USER_ONLY */
1247 }
1248 #endif /* TARGET_PPC64 */
1249
1250 #ifndef CONFIG_USER_ONLY
1251 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1252 {
1253 gen_helper_fixup_thrm(cpu_env);
1254 gen_load_spr(cpu_gpr[gprn], sprn);
1255 spr_load_dump_spr(sprn);
1256 }
1257 #endif /* !CONFIG_USER_ONLY */
1258
1259 static void gen_spr_thrm(CPUPPCState *env)
1260 {
1261 /* Thermal management */
1262 /* XXX : not implemented */
1263 spr_register(env, SPR_THRM1, "THRM1",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_thrm, &spr_write_generic,
1266 0x00000000);
1267 /* XXX : not implemented */
1268 spr_register(env, SPR_THRM2, "THRM2",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_thrm, &spr_write_generic,
1271 0x00000000);
1272 /* XXX : not implemented */
1273 spr_register(env, SPR_THRM3, "THRM3",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_thrm, &spr_write_generic,
1276 0x00000000);
1277 }
1278
1279 /* SPR specific to PowerPC 604 implementation */
1280 static void gen_spr_604(CPUPPCState *env)
1281 {
1282 /* Processor identification */
1283 spr_register(env, SPR_PIR, "PIR",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_pir,
1286 0x00000000);
1287 /* Breakpoints */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_IABR, "IABR",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register_kvm(env, SPR_DABR, "DABR",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 KVM_REG_PPC_DABR, 0x00000000);
1298 /* Performance counters */
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_7XX_PMC1, "PMC1",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_7XX_PMC2, "PMC2",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_7XX_SIAR, "SIAR",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, SPR_NOACCESS,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_SDA, "SDA",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, SPR_NOACCESS,
1323 0x00000000);
1324 /* External access control */
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_EAR, "EAR",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 }
1331
1332 /* SPR specific to PowerPC 603 implementation */
1333 static void gen_spr_603(CPUPPCState *env)
1334 {
1335 /* External access control */
1336 /* XXX : not implemented */
1337 spr_register(env, SPR_EAR, "EAR",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_generic, &spr_write_generic,
1340 0x00000000);
1341 /* Breakpoints */
1342 /* XXX : not implemented */
1343 spr_register(env, SPR_IABR, "IABR",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347
1348 }
1349
1350 /* SPR specific to PowerPC G2 implementation */
1351 static void gen_spr_G2(CPUPPCState *env)
1352 {
1353 /* Memory base address */
1354 /* MBAR */
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_MBAR, "MBAR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* Exception processing */
1361 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* Breakpoints */
1370 /* XXX : not implemented */
1371 spr_register(env, SPR_DABR, "DABR",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_DABR2, "DABR2",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_IABR, "IABR",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 /* XXX : not implemented */
1386 spr_register(env, SPR_IABR2, "IABR2",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 /* XXX : not implemented */
1391 spr_register(env, SPR_IBCR, "IBCR",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395 /* XXX : not implemented */
1396 spr_register(env, SPR_DBCR, "DBCR",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400 }
1401
1402 /* SPR specific to PowerPC 602 implementation */
1403 static void gen_spr_602(CPUPPCState *env)
1404 {
1405 /* ESA registers */
1406 /* XXX : not implemented */
1407 spr_register(env, SPR_SER, "SER",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, &spr_write_generic,
1410 0x00000000);
1411 /* XXX : not implemented */
1412 spr_register(env, SPR_SEBR, "SEBR",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_generic,
1415 0x00000000);
1416 /* XXX : not implemented */
1417 spr_register(env, SPR_ESASRR, "ESASRR",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421 /* Floating point status */
1422 /* XXX : not implemented */
1423 spr_register(env, SPR_SP, "SP",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427 /* XXX : not implemented */
1428 spr_register(env, SPR_LT, "LT",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_generic,
1431 0x00000000);
1432 /* Watchdog timer */
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_TCR, "TCR",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* Interrupt base */
1439 spr_register(env, SPR_IBR, "IBR",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 /* XXX : not implemented */
1444 spr_register(env, SPR_IABR, "IABR",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 }
1449
1450 /* SPR specific to PowerPC 601 implementation */
1451 static void gen_spr_601(CPUPPCState *env)
1452 {
1453 /* Multiplication/division register */
1454 /* MQ */
1455 spr_register(env, SPR_MQ, "MQ",
1456 &spr_read_generic, &spr_write_generic,
1457 &spr_read_generic, &spr_write_generic,
1458 0x00000000);
1459 /* RTC registers */
1460 spr_register(env, SPR_601_RTCU, "RTCU",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 SPR_NOACCESS, &spr_write_601_rtcu,
1463 0x00000000);
1464 spr_register(env, SPR_601_VRTCU, "RTCU",
1465 &spr_read_601_rtcu, SPR_NOACCESS,
1466 &spr_read_601_rtcu, SPR_NOACCESS,
1467 0x00000000);
1468 spr_register(env, SPR_601_RTCL, "RTCL",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 SPR_NOACCESS, &spr_write_601_rtcl,
1471 0x00000000);
1472 spr_register(env, SPR_601_VRTCL, "RTCL",
1473 &spr_read_601_rtcl, SPR_NOACCESS,
1474 &spr_read_601_rtcl, SPR_NOACCESS,
1475 0x00000000);
1476 /* Timer */
1477 #if 0 /* ? */
1478 spr_register(env, SPR_601_UDECR, "UDECR",
1479 &spr_read_decr, SPR_NOACCESS,
1480 &spr_read_decr, SPR_NOACCESS,
1481 0x00000000);
1482 #endif
1483 /* External access control */
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_EAR, "EAR",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* Memory management */
1490 #if !defined(CONFIG_USER_ONLY)
1491 spr_register(env, SPR_IBAT0U, "IBAT0U",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_601_ubat, &spr_write_601_ubatu,
1494 0x00000000);
1495 spr_register(env, SPR_IBAT0L, "IBAT0L",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_601_ubat, &spr_write_601_ubatl,
1498 0x00000000);
1499 spr_register(env, SPR_IBAT1U, "IBAT1U",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_601_ubat, &spr_write_601_ubatu,
1502 0x00000000);
1503 spr_register(env, SPR_IBAT1L, "IBAT1L",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_601_ubat, &spr_write_601_ubatl,
1506 0x00000000);
1507 spr_register(env, SPR_IBAT2U, "IBAT2U",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_601_ubat, &spr_write_601_ubatu,
1510 0x00000000);
1511 spr_register(env, SPR_IBAT2L, "IBAT2L",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_601_ubat, &spr_write_601_ubatl,
1514 0x00000000);
1515 spr_register(env, SPR_IBAT3U, "IBAT3U",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_601_ubat, &spr_write_601_ubatu,
1518 0x00000000);
1519 spr_register(env, SPR_IBAT3L, "IBAT3L",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_601_ubat, &spr_write_601_ubatl,
1522 0x00000000);
1523 env->nb_BATs = 4;
1524 #endif
1525 }
1526
1527 static void gen_spr_74xx(CPUPPCState *env)
1528 {
1529 /* Processor identification */
1530 spr_register(env, SPR_PIR, "PIR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_pir,
1533 0x00000000);
1534 /* XXX : not implemented */
1535 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* XXX : not implemented */
1540 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1541 &spr_read_ureg, SPR_NOACCESS,
1542 &spr_read_ureg, SPR_NOACCESS,
1543 0x00000000);
1544 /* XXX: not implemented */
1545 spr_register(env, SPR_BAMR, "BAMR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 /* XXX : not implemented */
1550 spr_register(env, SPR_MSSCR0, "MSSCR0",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* Hardware implementation registers */
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_HID0, "HID0",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 /* XXX : not implemented */
1561 spr_register(env, SPR_HID1, "HID1",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 /* Altivec */
1566 spr_register(env, SPR_VRSAVE, "VRSAVE",
1567 &spr_read_generic, &spr_write_generic,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 /* XXX : not implemented */
1571 spr_register(env, SPR_L2CR, "L2CR",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, spr_access_nop,
1574 0x00000000);
1575 /* Not strictly an SPR */
1576 vscr_init(env, 0x00010000);
1577 }
1578
1579 static void gen_l3_ctrl(CPUPPCState *env)
1580 {
1581 /* L3CR */
1582 /* XXX : not implemented */
1583 spr_register(env, SPR_L3CR, "L3CR",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 /* L3ITCR0 */
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 /* L3PM */
1594 /* XXX : not implemented */
1595 spr_register(env, SPR_L3PM, "L3PM",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 }
1600
1601 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1602 {
1603 #if !defined(CONFIG_USER_ONLY)
1604 env->nb_tlb = nb_tlbs;
1605 env->nb_ways = nb_ways;
1606 env->id_tlbs = 1;
1607 env->tlb_type = TLB_6XX;
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_PTEHI, "PTEHI",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_PTELO, "PTELO",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_TLBMISS, "TLBMISS",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 #endif
1624 }
1625
1626 #if !defined(CONFIG_USER_ONLY)
1627 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1628 {
1629 TCGv t0 = tcg_temp_new();
1630
1631 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1632 gen_store_spr(sprn, t0);
1633 tcg_temp_free(t0);
1634 }
1635
1636 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1637 {
1638 TCGv t0 = tcg_temp_new();
1639
1640 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1641 gen_store_spr(sprn, t0);
1642 tcg_temp_free(t0);
1643 }
1644
1645 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1646 {
1647 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1648 }
1649
1650 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1651 {
1652 TCGv_i32 t0 = tcg_const_i32(sprn);
1653 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1654 tcg_temp_free_i32(t0);
1655 }
1656 static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1657 {
1658 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1659 }
1660 static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1661 {
1662 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1663 }
1664
1665 #endif
1666
1667 static void gen_spr_usprg3(CPUPPCState *env)
1668 {
1669 spr_register(env, SPR_USPRG3, "USPRG3",
1670 &spr_read_ureg, SPR_NOACCESS,
1671 &spr_read_ureg, SPR_NOACCESS,
1672 0x00000000);
1673 }
1674
1675 static void gen_spr_usprgh(CPUPPCState *env)
1676 {
1677 spr_register(env, SPR_USPRG4, "USPRG4",
1678 &spr_read_ureg, SPR_NOACCESS,
1679 &spr_read_ureg, SPR_NOACCESS,
1680 0x00000000);
1681 spr_register(env, SPR_USPRG5, "USPRG5",
1682 &spr_read_ureg, SPR_NOACCESS,
1683 &spr_read_ureg, SPR_NOACCESS,
1684 0x00000000);
1685 spr_register(env, SPR_USPRG6, "USPRG6",
1686 &spr_read_ureg, SPR_NOACCESS,
1687 &spr_read_ureg, SPR_NOACCESS,
1688 0x00000000);
1689 spr_register(env, SPR_USPRG7, "USPRG7",
1690 &spr_read_ureg, SPR_NOACCESS,
1691 &spr_read_ureg, SPR_NOACCESS,
1692 0x00000000);
1693 }
1694
1695 /* PowerPC BookE SPR */
1696 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1697 {
1698 const char *ivor_names[64] = {
1699 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1700 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1701 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1702 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1703 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1704 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1705 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1706 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1707 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1708 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1709 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1710 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1711 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1712 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1713 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1714 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1715 };
1716 #define SPR_BOOKE_IVORxx (-1)
1717 int ivor_sprn[64] = {
1718 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1719 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1720 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1721 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1722 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1723 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1724 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1725 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1726 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1727 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1728 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1729 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1730 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1731 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1732 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1733 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1734 };
1735 int i;
1736
1737 /* Interrupt processing */
1738 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, &spr_write_generic,
1745 0x00000000);
1746 /* Debug */
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_40x_dbcr0,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790 /* XXX : not implemented */
1791 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_generic, &spr_write_clear,
1794 0x00000000);
1795 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 spr_register(env, SPR_BOOKE_ESR, "ESR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_excp_prefix,
1806 0x00000000);
1807 /* Exception vectors */
1808 for (i = 0; i < 64; i++) {
1809 if (ivor_mask & (1ULL << i)) {
1810 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1811 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1812 exit(1);
1813 }
1814 spr_register(env, ivor_sprn[i], ivor_names[i],
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_excp_vector,
1817 0x00000000);
1818 }
1819 }
1820 spr_register(env, SPR_BOOKE_PID, "PID",
1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_booke_pid,
1823 0x00000000);
1824 spr_register(env, SPR_BOOKE_TCR, "TCR",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_booke_tcr,
1827 0x00000000);
1828 spr_register(env, SPR_BOOKE_TSR, "TSR",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_booke_tsr,
1831 0x00000000);
1832 /* Timer */
1833 spr_register(env, SPR_DECR, "DECR",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_decr, &spr_write_decr,
1836 0x00000000);
1837 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 SPR_NOACCESS, &spr_write_generic,
1840 0x00000000);
1841 /* SPRGs */
1842 spr_register(env, SPR_USPRG0, "USPRG0",
1843 &spr_read_generic, &spr_write_generic,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 spr_register(env, SPR_SPRG4, "SPRG4",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850 spr_register(env, SPR_SPRG5, "SPRG5",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_generic, &spr_write_generic,
1853 0x00000000);
1854 spr_register(env, SPR_SPRG6, "SPRG6",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_generic,
1857 0x00000000);
1858 spr_register(env, SPR_SPRG7, "SPRG7",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 }
1871
1872 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1873 uint32_t maxsize, uint32_t flags,
1874 uint32_t nentries)
1875 {
1876 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1877 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1878 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1879 flags | nentries;
1880 }
1881
1882 /* BookE 2.06 storage control registers */
1883 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1884 uint32_t *tlbncfg, uint32_t mmucfg)
1885 {
1886 #if !defined(CONFIG_USER_ONLY)
1887 const char *mas_names[8] = {
1888 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1889 };
1890 int mas_sprn[8] = {
1891 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1892 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1893 };
1894 int i;
1895
1896 /* TLB assist registers */
1897 /* XXX : not implemented */
1898 for (i = 0; i < 8; i++) {
1899 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1900 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1901 uea_write = &spr_write_generic;
1902 }
1903 if (mas_mask & (1 << i)) {
1904 spr_register(env, mas_sprn[i], mas_names[i],
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, uea_write,
1907 0x00000000);
1908 }
1909 }
1910 if (env->nb_pids > 1) {
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_BOOKE_PID1, "PID1",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_booke_pid,
1915 0x00000000);
1916 }
1917 if (env->nb_pids > 2) {
1918 /* XXX : not implemented */
1919 spr_register(env, SPR_BOOKE_PID2, "PID2",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_booke_pid,
1922 0x00000000);
1923 }
1924
1925 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_eplc,
1928 0x00000000);
1929 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_epsc,
1932 0x00000000);
1933
1934 /* XXX : not implemented */
1935 spr_register(env, SPR_MMUCFG, "MMUCFG",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, SPR_NOACCESS,
1938 mmucfg);
1939 switch (env->nb_ways) {
1940 case 4:
1941 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 &spr_read_generic, SPR_NOACCESS,
1944 tlbncfg[3]);
1945 /* Fallthru */
1946 case 3:
1947 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, SPR_NOACCESS,
1950 tlbncfg[2]);
1951 /* Fallthru */
1952 case 2:
1953 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, SPR_NOACCESS,
1956 tlbncfg[1]);
1957 /* Fallthru */
1958 case 1:
1959 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, SPR_NOACCESS,
1962 tlbncfg[0]);
1963 /* Fallthru */
1964 case 0:
1965 default:
1966 break;
1967 }
1968 #endif
1969
1970 gen_spr_usprgh(env);
1971 }
1972
1973 /* SPR specific to PowerPC 440 implementation */
1974 static void gen_spr_440(CPUPPCState *env)
1975 {
1976 /* Cache control */
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_440_DNV0, "DNV0",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_440_DNV1, "DNV1",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_440_DNV2, "DNV2",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_440_DNV3, "DNV3",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_generic,
1996 0x00000000);
1997 /* XXX : not implemented */
1998 spr_register(env, SPR_440_DTV0, "DTV0",
1999 SPR_NOACCESS, SPR_NOACCESS,
2000 &spr_read_generic, &spr_write_generic,
2001 0x00000000);
2002 /* XXX : not implemented */
2003 spr_register(env, SPR_440_DTV1, "DTV1",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_generic,
2006 0x00000000);
2007 /* XXX : not implemented */
2008 spr_register(env, SPR_440_DTV2, "DTV2",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012 /* XXX : not implemented */
2013 spr_register(env, SPR_440_DTV3, "DTV3",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 /* XXX : not implemented */
2018 spr_register(env, SPR_440_DVLIM, "DVLIM",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 /* XXX : not implemented */
2023 spr_register(env, SPR_440_INV0, "INV0",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_generic,
2026 0x00000000);
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_440_INV1, "INV1",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_generic,
2031 0x00000000);
2032 /* XXX : not implemented */
2033 spr_register(env, SPR_440_INV2, "INV2",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 /* XXX : not implemented */
2038 spr_register(env, SPR_440_INV3, "INV3",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 &spr_read_generic, &spr_write_generic,
2041 0x00000000);
2042 /* XXX : not implemented */
2043 spr_register(env, SPR_440_ITV0, "ITV0",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, &spr_write_generic,
2046 0x00000000);
2047 /* XXX : not implemented */
2048 spr_register(env, SPR_440_ITV1, "ITV1",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_generic,
2051 0x00000000);
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_440_ITV2, "ITV2",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 /* XXX : not implemented */
2058 spr_register(env, SPR_440_ITV3, "ITV3",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_440_IVLIM, "IVLIM",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_generic,
2066 0x00000000);
2067 /* Cache debug */
2068 /* XXX : not implemented */
2069 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, SPR_NOACCESS,
2072 0x00000000);
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, SPR_NOACCESS,
2077 0x00000000);
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, SPR_NOACCESS,
2082 0x00000000);
2083 /* XXX : not implemented */
2084 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, SPR_NOACCESS,
2087 0x00000000);
2088 /* XXX : not implemented */
2089 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, SPR_NOACCESS,
2092 0x00000000);
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_440_DBDR, "DBDR",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 /* Processor control */
2099 spr_register(env, SPR_4xx_CCR0, "CCR0",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, SPR_NOACCESS,
2106 0x00000000);
2107 /* Storage control */
2108 spr_register(env, SPR_440_MMUCR, "MMUCR",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
2112 }
2113
2114 /* SPR shared between PowerPC 40x implementations */
2115 static void gen_spr_40x(CPUPPCState *env)
2116 {
2117 /* Cache */
2118 /* not emulated, as QEMU do not emulate caches */
2119 spr_register(env, SPR_40x_DCCR, "DCCR",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 /* not emulated, as QEMU do not emulate caches */
2124 spr_register(env, SPR_40x_ICCR, "ICCR",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
2128 /* not emulated, as QEMU do not emulate caches */
2129 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, SPR_NOACCESS,
2132 0x00000000);
2133 /* Exception */
2134 spr_register(env, SPR_40x_DEAR, "DEAR",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 spr_register(env, SPR_40x_ESR, "ESR",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 spr_register(env, SPR_40x_EVPR, "EVPR",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, &spr_write_excp_prefix,
2145 0x00000000);
2146 spr_register(env, SPR_40x_SRR2, "SRR2",
2147 &spr_read_generic, &spr_write_generic,
2148 &spr_read_generic, &spr_write_generic,
2149 0x00000000);
2150 spr_register(env, SPR_40x_SRR3, "SRR3",
2151 &spr_read_generic, &spr_write_generic,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
2154 /* Timers */
2155 spr_register(env, SPR_40x_PIT, "PIT",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_40x_pit, &spr_write_40x_pit,
2158 0x00000000);
2159 spr_register(env, SPR_40x_TCR, "TCR",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_booke_tcr,
2162 0x00000000);
2163 spr_register(env, SPR_40x_TSR, "TSR",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_booke_tsr,
2166 0x00000000);
2167 }
2168
2169 /* SPR specific to PowerPC 405 implementation */
2170 static void gen_spr_405(CPUPPCState *env)
2171 {
2172 /* MMU */
2173 spr_register(env, SPR_40x_PID, "PID",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 spr_register(env, SPR_4xx_CCR0, "CCR0",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00700000);
2181 /* Debug interface */
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_40x_dbcr0,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_405_DBCR1, "DBCR1",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_40x_DBSR, "DBSR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_clear,
2196 /* Last reset was system reset */
2197 0x00000300);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_40x_DAC1, "DAC1",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 spr_register(env, SPR_40x_DAC2, "DAC2",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_405_DVC1, "DVC1",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_405_DVC2, "DVC2",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_40x_IAC1, "IAC1",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 spr_register(env, SPR_40x_IAC2, "IAC2",
2223 SPR_NOACCESS, SPR_NOACCESS,
2224 &spr_read_generic, &spr_write_generic,
2225 0x00000000);
2226 /* XXX : not implemented */
2227 spr_register(env, SPR_405_IAC3, "IAC3",
2228 SPR_NOACCESS, SPR_NOACCESS,
2229 &spr_read_generic, &spr_write_generic,
2230 0x00000000);
2231 /* XXX : not implemented */
2232 spr_register(env, SPR_405_IAC4, "IAC4",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 &spr_read_generic, &spr_write_generic,
2235 0x00000000);
2236 /* Storage control */
2237 /* XXX: TODO: not implemented */
2238 spr_register(env, SPR_405_SLER, "SLER",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_40x_sler,
2241 0x00000000);
2242 spr_register(env, SPR_40x_ZPR, "ZPR",
2243 SPR_NOACCESS, SPR_NOACCESS,
2244 &spr_read_generic, &spr_write_generic,
2245 0x00000000);
2246 /* XXX : not implemented */
2247 spr_register(env, SPR_405_SU0R, "SU0R",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 &spr_read_generic, &spr_write_generic,
2250 0x00000000);
2251 /* SPRG */
2252 spr_register(env, SPR_USPRG0, "USPRG0",
2253 &spr_read_ureg, SPR_NOACCESS,
2254 &spr_read_ureg, SPR_NOACCESS,
2255 0x00000000);
2256 spr_register(env, SPR_SPRG4, "SPRG4",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 spr_register(env, SPR_SPRG5, "SPRG5",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 spr_register(env, SPR_SPRG6, "SPRG6",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 spr_register(env, SPR_SPRG7, "SPRG7",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 gen_spr_usprgh(env);
2273 }
2274
2275 /* SPR shared between PowerPC 401 & 403 implementations */
2276 static void gen_spr_401_403(CPUPPCState *env)
2277 {
2278 /* Time base */
2279 spr_register(env, SPR_403_VTBL, "TBL",
2280 &spr_read_tbl, SPR_NOACCESS,
2281 &spr_read_tbl, SPR_NOACCESS,
2282 0x00000000);
2283 spr_register(env, SPR_403_TBL, "TBL",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 SPR_NOACCESS, &spr_write_tbl,
2286 0x00000000);
2287 spr_register(env, SPR_403_VTBU, "TBU",
2288 &spr_read_tbu, SPR_NOACCESS,
2289 &spr_read_tbu, SPR_NOACCESS,
2290 0x00000000);
2291 spr_register(env, SPR_403_TBU, "TBU",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 SPR_NOACCESS, &spr_write_tbu,
2294 0x00000000);
2295 /* Debug */
2296 /* not emulated, as QEMU do not emulate caches */
2297 spr_register(env, SPR_403_CDBCR, "CDBCR",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 }
2302
2303 /* SPR specific to PowerPC 401 implementation */
2304 static void gen_spr_401(CPUPPCState *env)
2305 {
2306 /* Debug interface */
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_40x_DBCR0, "DBCR",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_40x_dbcr0,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_40x_DBSR, "DBSR",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_clear,
2316 /* Last reset was system reset */
2317 0x00000300);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_40x_DAC1, "DAC",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_40x_IAC1, "IAC",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* Storage control */
2329 /* XXX: TODO: not implemented */
2330 spr_register(env, SPR_405_SLER, "SLER",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_40x_sler,
2333 0x00000000);
2334 /* not emulated, as QEMU never does speculative access */
2335 spr_register(env, SPR_40x_SGR, "SGR",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0xFFFFFFFF);
2339 /* not emulated, as QEMU do not emulate caches */
2340 spr_register(env, SPR_40x_DCWR, "DCWR",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 }
2345
2346 static void gen_spr_401x2(CPUPPCState *env)
2347 {
2348 gen_spr_401(env);
2349 spr_register(env, SPR_40x_PID, "PID",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 spr_register(env, SPR_40x_ZPR, "ZPR",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 }
2358
2359 /* SPR specific to PowerPC 403 implementation */
2360 static void gen_spr_403(CPUPPCState *env)
2361 {
2362 /* Debug interface */
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_40x_dbcr0,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_40x_DBSR, "DBSR",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_clear,
2372 /* Last reset was system reset */
2373 0x00000300);
2374 /* XXX : not implemented */
2375 spr_register(env, SPR_40x_DAC1, "DAC1",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_40x_DAC2, "DAC2",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_40x_IAC1, "IAC1",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_40x_IAC2, "IAC2",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2393 0x00000000);
2394 }
2395
2396 static void gen_spr_403_real(CPUPPCState *env)
2397 {
2398 spr_register(env, SPR_403_PBL1, "PBL1",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_403_pbr, &spr_write_403_pbr,
2401 0x00000000);
2402 spr_register(env, SPR_403_PBU1, "PBU1",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_403_pbr, &spr_write_403_pbr,
2405 0x00000000);
2406 spr_register(env, SPR_403_PBL2, "PBL2",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_403_pbr, &spr_write_403_pbr,
2409 0x00000000);
2410 spr_register(env, SPR_403_PBU2, "PBU2",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_403_pbr, &spr_write_403_pbr,
2413 0x00000000);
2414 }
2415
2416 static void gen_spr_403_mmu(CPUPPCState *env)
2417 {
2418 /* MMU */
2419 spr_register(env, SPR_40x_PID, "PID",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 spr_register(env, SPR_40x_ZPR, "ZPR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 }
2428
2429 /* SPR specific to PowerPC compression coprocessor extension */
2430 static void gen_spr_compress(CPUPPCState *env)
2431 {
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_401_SKR, "SKR",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 }
2438
2439 static void gen_spr_5xx_8xx(CPUPPCState *env)
2440 {
2441 /* Exception processing */
2442 spr_register_kvm(env, SPR_DSISR, "DSISR",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 KVM_REG_PPC_DSISR, 0x00000000);
2446 spr_register_kvm(env, SPR_DAR, "DAR",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 KVM_REG_PPC_DAR, 0x00000000);
2450 /* Timer */
2451 spr_register(env, SPR_DECR, "DECR",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_decr, &spr_write_decr,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_EIE, "EIE",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_EID, "EID",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_NRI, "NRI",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_CMPA, "CMPA",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_CMPB, "CMPB",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_CMPC, "CMPC",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_CMPD, "CMPD",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_ECR, "ECR",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_DER, "DER",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_MPC_CMPE, "CMPE",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_CMPF, "CMPF",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_CMPG, "CMPG",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_CMPH, "CMPH",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_BAR, "BAR",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_DPDR, "DPDR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_IMMR, "IMMR",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 }
2556
2557 static void gen_spr_5xx(CPUPPCState *env)
2558 {
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 /* XXX : not implemented */
2580 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2581 SPR_NOACCESS, SPR_NOACCESS,
2582 &spr_read_generic, &spr_write_generic,
2583 0x00000000);
2584 /* XXX : not implemented */
2585 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 /* XXX : not implemented */
2590 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2591 SPR_NOACCESS, SPR_NOACCESS,
2592 &spr_read_generic, &spr_write_generic,
2593 0x00000000);
2594 /* XXX : not implemented */
2595 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2596 SPR_NOACCESS, SPR_NOACCESS,
2597 &spr_read_generic, &spr_write_generic,
2598 0x00000000);
2599 /* XXX : not implemented */
2600 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2601 SPR_NOACCESS, SPR_NOACCESS,
2602 &spr_read_generic, &spr_write_generic,
2603 0x00000000);
2604 /* XXX : not implemented */
2605 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2606 SPR_NOACCESS, SPR_NOACCESS,
2607 &spr_read_generic, &spr_write_generic,
2608 0x00000000);
2609 /* XXX : not implemented */
2610 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2611 SPR_NOACCESS, SPR_NOACCESS,
2612 &spr_read_generic, &spr_write_generic,
2613 0x00000000);
2614 /* XXX : not implemented */
2615 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2616 SPR_NOACCESS, SPR_NOACCESS,
2617 &spr_read_generic, &spr_write_generic,
2618 0x00000000);
2619 /* XXX : not implemented */
2620 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2621 SPR_NOACCESS, SPR_NOACCESS,
2622 &spr_read_generic, &spr_write_generic,
2623 0x00000000);
2624 /* XXX : not implemented */
2625 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2626 SPR_NOACCESS, SPR_NOACCESS,
2627 &spr_read_generic, &spr_write_generic,
2628 0x00000000);
2629 /* XXX : not implemented */
2630 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2631 SPR_NOACCESS, SPR_NOACCESS,
2632 &spr_read_generic, &spr_write_generic,
2633 0x00000000);
2634 /* XXX : not implemented */
2635 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2636 SPR_NOACCESS, SPR_NOACCESS,
2637 &spr_read_generic, &spr_write_generic,
2638 0x00000000);
2639 /* XXX : not implemented */
2640 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2641 SPR_NOACCESS, SPR_NOACCESS,
2642 &spr_read_generic, &spr_write_generic,
2643 0x00000000);
2644 /* XXX : not implemented */
2645 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2646 SPR_NOACCESS, SPR_NOACCESS,
2647 &spr_read_generic, &spr_write_generic,
2648 0x00000000);
2649 /* XXX : not implemented */
2650 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2651 SPR_NOACCESS, SPR_NOACCESS,
2652 &spr_read_generic, &spr_write_generic,
2653 0x00000000);
2654 /* XXX : not implemented */
2655 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2658 0x00000000);
2659 /* XXX : not implemented */
2660 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2663 0x00000000);
2664 }
2665
2666 static void gen_spr_8xx(CPUPPCState *env)
2667 {
2668 /* XXX : not implemented */
2669 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 /* XXX : not implemented */
2674 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2675 SPR_NOACCESS, SPR_NOACCESS,
2676 &spr_read_generic, &spr_write_generic,
2677 0x00000000);
2678 /* XXX : not implemented */
2679 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2680 SPR_NOACCESS, SPR_NOACCESS,
2681 &spr_read_generic, &spr_write_generic,
2682 0x00000000);
2683 /* XXX : not implemented */
2684 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2685 SPR_NOACCESS, SPR_NOACCESS,
2686 &spr_read_generic, &spr_write_generic,
2687 0x00000000);
2688 /* XXX : not implemented */
2689 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2690 SPR_NOACCESS, SPR_NOACCESS,
2691 &spr_read_generic, &spr_write_generic,
2692 0x00000000);
2693 /* XXX : not implemented */
2694 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2695 SPR_NOACCESS, SPR_NOACCESS,
2696 &spr_read_generic, &spr_write_generic,
2697 0x00000000);
2698 /* XXX : not implemented */
2699 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2700 SPR_NOACCESS, SPR_NOACCESS,
2701 &spr_read_generic, &spr_write_generic,
2702 0x00000000);
2703 /* XXX : not implemented */
2704 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2705 SPR_NOACCESS, SPR_NOACCESS,
2706 &spr_read_generic, &spr_write_generic,
2707 0x00000000);
2708 /* XXX : not implemented */
2709 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2710 SPR_NOACCESS, SPR_NOACCESS,
2711 &spr_read_generic, &spr_write_generic,
2712 0x00000000);
2713 /* XXX : not implemented */
2714 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2715 SPR_NOACCESS, SPR_NOACCESS,
2716 &spr_read_generic, &spr_write_generic,
2717 0x00000000);
2718 /* XXX : not implemented */
2719 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2720 SPR_NOACCESS, SPR_NOACCESS,
2721 &spr_read_generic, &spr_write_generic,
2722 0x00000000);
2723 /* XXX : not implemented */
2724 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2725 SPR_NOACCESS, SPR_NOACCESS,
2726 &spr_read_generic, &spr_write_generic,
2727 0x00000000);
2728 /* XXX : not implemented */
2729 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2730 SPR_NOACCESS, SPR_NOACCESS,
2731 &spr_read_generic, &spr_write_generic,
2732 0x00000000);
2733 /* XXX : not implemented */
2734 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2735 SPR_NOACCESS, SPR_NOACCESS,
2736 &spr_read_generic, &spr_write_generic,
2737 0x00000000);
2738 /* XXX : not implemented */
2739 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2740 SPR_NOACCESS, SPR_NOACCESS,
2741 &spr_read_generic, &spr_write_generic,
2742 0x00000000);
2743 /* XXX : not implemented */
2744 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2745 SPR_NOACCESS, SPR_NOACCESS,
2746 &spr_read_generic, &spr_write_generic,
2747 0x00000000);
2748 /* XXX : not implemented */
2749 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2750 SPR_NOACCESS, SPR_NOACCESS,
2751 &spr_read_generic, &spr_write_generic,
2752 0x00000000);
2753 /* XXX : not implemented */
2754 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2755 SPR_NOACCESS, SPR_NOACCESS,
2756 &spr_read_generic, &spr_write_generic,
2757 0x00000000);
2758 /* XXX : not implemented */
2759 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2760 SPR_NOACCESS, SPR_NOACCESS,
2761 &spr_read_generic, &spr_write_generic,
2762 0x00000000);
2763 /* XXX : not implemented */
2764 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2765 SPR_NOACCESS, SPR_NOACCESS,
2766 &spr_read_generic, &spr_write_generic,
2767 0x00000000);
2768 /* XXX : not implemented */
2769 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2770 SPR_NOACCESS, SPR_NOACCESS,
2771 &spr_read_generic, &spr_write_generic,
2772 0x00000000);
2773 /* XXX : not implemented */
2774 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2775 SPR_NOACCESS, SPR_NOACCESS,
2776 &spr_read_generic, &spr_write_generic,
2777 0x00000000);
2778 /* XXX : not implemented */
2779 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2780 SPR_NOACCESS, SPR_NOACCESS,
2781 &spr_read_generic, &spr_write_generic,
2782 0x00000000);
2783 /* XXX : not implemented */
2784 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2785 SPR_NOACCESS, SPR_NOACCESS,
2786 &spr_read_generic, &spr_write_generic,
2787 0x00000000);
2788 /* XXX : not implemented */
2789 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2790 SPR_NOACCESS, SPR_NOACCESS,
2791 &spr_read_generic, &spr_write_generic,
2792 0x00000000);
2793 }
2794
2795 // XXX: TODO
2796 /*
2797 * AMR => SPR 29 (Power 2.04)
2798 * CTRL => SPR 136 (Power 2.04)
2799 * CTRL => SPR 152 (Power 2.04)
2800 * SCOMC => SPR 276 (64 bits ?)
2801 * SCOMD => SPR 277 (64 bits ?)
2802 * TBU40 => SPR 286 (Power 2.04 hypv)
2803 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2804 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2805 * HDSISR => SPR 306 (Power 2.04 hypv)
2806 * HDAR => SPR 307 (Power 2.04 hypv)
2807 * PURR => SPR 309 (Power 2.04 hypv)
2808 * HDEC => SPR 310 (Power 2.04 hypv)
2809 * HIOR => SPR 311 (hypv)
2810 * RMOR => SPR 312 (970)
2811 * HRMOR => SPR 313 (Power 2.04 hypv)
2812 * HSRR0 => SPR 314 (Power 2.04 hypv)
2813 * HSRR1 => SPR 315 (Power 2.04 hypv)
2814 * LPIDR => SPR 317 (970)
2815 * EPR => SPR 702 (Power 2.04 emb)
2816 * perf => 768-783 (Power 2.04)
2817 * perf => 784-799 (Power 2.04)
2818 * PPR => SPR 896 (Power 2.04)
2819 * DABRX => 1015 (Power 2.04 hypv)
2820 * FPECR => SPR 1022 (?)
2821 * ... and more (thermal management, performance counters, ...)
2822 */
2823
2824 /*****************************************************************************/
2825 /* Exception vectors models */
2826 static void init_excp_4xx_real(CPUPPCState *env)
2827 {
2828 #if !defined(CONFIG_USER_ONLY)
2829 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2831 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2832 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2833 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2834 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2835 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2836 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2837 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2838 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2839 env->ivor_mask = 0x0000FFF0UL;
2840 env->ivpr_mask = 0xFFFF0000UL;
2841 /* Hardware reset vector */
2842 env->hreset_vector = 0xFFFFFFFCUL;
2843 #endif
2844 }
2845
2846 static void init_excp_4xx_softmmu(CPUPPCState *env)
2847 {
2848 #if !defined(CONFIG_USER_ONLY)
2849 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2850 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2851 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2852 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2853 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2854 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2855 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2856 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2857 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2858 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2859 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2860 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2861 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2862 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2863 env->ivor_mask = 0x0000FFF0UL;
2864 env->ivpr_mask = 0xFFFF0000UL;
2865 /* Hardware reset vector */
2866 env->hreset_vector = 0xFFFFFFFCUL;
2867 #endif
2868 }
2869
2870 static void init_excp_MPC5xx(CPUPPCState *env)
2871 {
2872 #if !defined(CONFIG_USER_ONLY)
2873 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2874 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2875 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2876 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2877 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2878 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2879 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2880 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2881 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2882 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2883 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2884 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2885 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2886 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2887 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2888 env->ivor_mask = 0x0000FFF0UL;
2889 env->ivpr_mask = 0xFFFF0000UL;
2890 /* Hardware reset vector */
2891 env->hreset_vector = 0x00000100UL;
2892 #endif
2893 }
2894
2895 static void init_excp_MPC8xx(CPUPPCState *env)
2896 {
2897 #if !defined(CONFIG_USER_ONLY)
2898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2899 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2900 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2901 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2902 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2903 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2904 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2905 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2906 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2908 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2909 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2910 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2911 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2912 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2913 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2914 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2915 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2916 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2917 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2918 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2919 env->ivor_mask = 0x0000FFF0UL;
2920 env->ivpr_mask = 0xFFFF0000UL;
2921 /* Hardware reset vector */
2922 env->hreset_vector = 0x00000100UL;
2923 #endif
2924 }
2925
2926 static void init_excp_G2(CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2939 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2940 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2941 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2942 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2943 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2944 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2945 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2946 /* Hardware reset vector */
2947 env->hreset_vector = 0x00000100UL;
2948 #endif
2949 }
2950
2951 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2952 {
2953 #if !defined(CONFIG_USER_ONLY)
2954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2955 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2956 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2957 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2958 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2959 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2960 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2961 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2962 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2963 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2964 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2965 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2966 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2967 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2968 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2969 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2970 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2971 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2972 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2973 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2974 env->ivor_mask = 0x0000FFF7UL;
2975 env->ivpr_mask = ivpr_mask;
2976 /* Hardware reset vector */
2977 env->hreset_vector = 0xFFFFFFFCUL;
2978 #endif
2979 }
2980
2981 static void init_excp_BookE(CPUPPCState *env)
2982 {
2983 #if !defined(CONFIG_USER_ONLY)
2984 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2985 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2986 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2987 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2988 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2989 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2990 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2991 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2992 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2993 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2994 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2995 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2996 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2997 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2998 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2999 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
3000 env->ivor_mask = 0x0000FFF0UL;
3001 env->ivpr_mask = 0xFFFF0000UL;
3002 /* Hardware reset vector */
3003 env->hreset_vector = 0xFFFFFFFCUL;
3004 #endif
3005 }
3006
3007 static void init_excp_601(CPUPPCState *env)
3008 {
3009 #if !defined(CONFIG_USER_ONLY)
3010 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3011 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3012 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3013 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3014 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3015 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3016 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3017 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3018 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3019 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
3020 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3021 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
3022 /* Hardware reset vector */
3023 env->hreset_vector = 0x00000100UL;
3024 #endif
3025 }
3026
3027 static void init_excp_602(CPUPPCState *env)
3028 {
3029 #if !defined(CONFIG_USER_ONLY)
3030 /* XXX: exception prefix has a special behavior on 602 */
3031 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3032 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3033 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3034 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3035 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3036 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3037 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3038 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3039 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3040 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3041 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3042 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3043 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3044 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3045 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3046 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3047 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3048 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3049 /* Hardware reset vector */
3050 env->hreset_vector = 0x00000100UL;
3051 #endif
3052 }
3053
3054 static void init_excp_603(CPUPPCState *env)
3055 {
3056 #if !defined(CONFIG_USER_ONLY)
3057 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3058 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3059 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3060 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3061 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3062 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3063 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3064 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3065 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3066 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3067 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3068 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3069 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3070 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3071 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3072 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3073 /* Hardware reset vector */
3074 env->hreset_vector = 0x00000100UL;
3075 #endif
3076 }
3077
3078 static void init_excp_604(CPUPPCState *env)
3079 {
3080 #if !defined(CONFIG_USER_ONLY)
3081 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3082 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3083 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3084 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3085 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3086 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3087 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3088 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3089 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3090 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3091 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3092 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3093 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3094 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3095 /* Hardware reset vector */
3096 env->hreset_vector = 0x00000100UL;
3097 #endif
3098 }
3099
3100 static void init_excp_7x0(CPUPPCState *env)
3101 {
3102 #if !defined(CONFIG_USER_ONLY)
3103 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3104 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3105 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3106 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3107 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3108 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3109 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3110 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3111 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3112 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3113 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3114 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3115 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3116 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3117 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3118 /* Hardware reset vector */
3119 env->hreset_vector = 0x00000100UL;
3120 #endif
3121 }
3122
3123 static void init_excp_750cl(CPUPPCState *env)
3124 {
3125 #if !defined(CONFIG_USER_ONLY)
3126 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3127 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3128 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3129 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3130 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3131 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3132 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3133 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3134 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3135 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3136 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3137 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3138 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3139 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3140 /* Hardware reset vector */
3141 env->hreset_vector = 0x00000100UL;
3142 #endif
3143 }
3144
3145 static void init_excp_750cx(CPUPPCState *env)
3146 {
3147 #if !defined(CONFIG_USER_ONLY)
3148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3151 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3152 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3153 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3154 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3155 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3156 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3158 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3159 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3160 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3161 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3162 /* Hardware reset vector */
3163 env->hreset_vector = 0x00000100UL;
3164 #endif
3165 }
3166
3167 /* XXX: Check if this is correct */
3168 static void init_excp_7x5(CPUPPCState *env)
3169 {
3170 #if !defined(CONFIG_USER_ONLY)
3171 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3172 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3173 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3174 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3175 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3176 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3177 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3178 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3179 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3180 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3181 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3182 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3183 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3184 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3185 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3186 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3187 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3188 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3189 /* Hardware reset vector */
3190 env->hreset_vector = 0x00000100UL;
3191 #endif
3192 }
3193
3194 static void init_excp_7400(CPUPPCState *env)
3195 {
3196 #if !defined(CONFIG_USER_ONLY)
3197 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3198 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3199 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3200 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3201 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3202 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3203 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3204 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3205 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3206 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3207 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3208 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3209 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3210 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3211 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3212 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3213 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3214 /* Hardware reset vector */
3215 env->hreset_vector = 0x00000100UL;
3216 #endif
3217 }
3218
3219 static void init_excp_7450(CPUPPCState *env)
3220 {
3221 #if !defined(CONFIG_USER_ONLY)
3222 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3223 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3224 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3225 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3226 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3227 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3228 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3229 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3230 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3231 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3232 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3233 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3234 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3235 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3236 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3237 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3238 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3239 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3240 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3241 /* Hardware reset vector */
3242 env->hreset_vector = 0x00000100UL;
3243 #endif
3244 }
3245
3246 #if defined(TARGET_PPC64)
3247 static void init_excp_970(CPUPPCState *env)
3248 {
3249 #if !defined(CONFIG_USER_ONLY)
3250 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3251 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3252 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3253 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3254 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3255 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3256 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3257 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3258 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3259 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3260 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3261 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3262 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3263 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3264 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3265 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3266 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3267 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3268 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3269 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3270 /* Hardware reset vector */
3271 env->hreset_vector = 0x0000000000000100ULL;
3272 #endif
3273 }
3274
3275 static void init_excp_POWER7(CPUPPCState *env)
3276 {
3277 #if !defined(CONFIG_USER_ONLY)
3278 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3279 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3280 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3281 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3282 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3283 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3284 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3285 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3286 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3287 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3288 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3289 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3290 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3291 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3292 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
3293 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
3294 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
3295 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3296 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3297 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3298 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3299 /* Hardware reset vector */
3300 env->hreset_vector = 0x0000000000000100ULL;
3301 #endif
3302 }
3303
3304 static void init_excp_POWER8(CPUPPCState *env)
3305 {
3306 init_excp_POWER7(env);
3307
3308 #if !defined(CONFIG_USER_ONLY)
3309 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
3310 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3311 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
3312 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3313 #endif
3314 }
3315
3316 #endif
3317
3318 /*****************************************************************************/
3319 /* Power management enable checks */
3320 static int check_pow_none(CPUPPCState *env)
3321 {
3322 return 0;
3323 }
3324
3325 static int check_pow_nocheck(CPUPPCState *env)
3326 {
3327 return 1;
3328 }
3329
3330 static int check_pow_hid0(CPUPPCState *env)
3331 {
3332 if (env->spr[SPR_HID0] & 0x00E00000)
3333 return 1;
3334
3335 return 0;
3336 }
3337
3338 static int check_pow_hid0_74xx(CPUPPCState *env)
3339 {
3340 if (env->spr[SPR_HID0] & 0x00600000)
3341 return 1;
3342
3343 return 0;
3344 }
3345
3346 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3347 {
3348 return true;
3349 }
3350
3351 #ifdef TARGET_PPC64
3352 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3353 {
3354 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3355 }
3356 #endif
3357
3358 /*****************************************************************************/
3359 /* PowerPC implementations definitions */
3360
3361 #define POWERPC_FAMILY(_name) \
3362 static void \
3363 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3364 \
3365 static const TypeInfo \
3366 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3367 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3368 .parent = TYPE_POWERPC_CPU, \
3369 .abstract = true, \
3370 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3371 }; \
3372 \
3373 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3374 { \
3375 type_register_static( \
3376 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3377 } \
3378 \
3379 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3380 \
3381 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3382
3383 static void init_proc_401(CPUPPCState *env)
3384 {
3385 gen_spr_40x(env);
3386 gen_spr_401_403(env);
3387 gen_spr_401(env);
3388 init_excp_4xx_real(env);
3389 env->dcache_line_size = 32;
3390 env->icache_line_size = 32;
3391 /* Allocate hardware IRQ controller */
3392 ppc40x_irq_init(ppc_env_get_cpu(env));
3393
3394 SET_FIT_PERIOD(12, 16, 20, 24);
3395 SET_WDT_PERIOD(16, 20, 24, 28);
3396 }
3397
3398 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3399 {
3400 DeviceClass *dc = DEVICE_CLASS(oc);
3401 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3402
3403 dc->desc = "PowerPC 401";
3404 pcc->init_proc = init_proc_401;
3405 pcc->check_pow = check_pow_nocheck;
3406 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3407 PPC_WRTEE | PPC_DCR |
3408 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3409 PPC_CACHE_DCBZ |
3410 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3411 PPC_4xx_COMMON | PPC_40x_EXCP;
3412 pcc->msr_mask = (1ull << MSR_KEY) |
3413 (1ull << MSR_POW) |
3414 (1ull << MSR_CE) |
3415 (1ull << MSR_ILE) |
3416 (1ull << MSR_EE) |
3417 (1ull << MSR_PR) |
3418 (1ull << MSR_ME) |
3419 (1ull << MSR_DE) |
3420 (1ull << MSR_LE);
3421 pcc->mmu_model = POWERPC_MMU_REAL;
3422 pcc->excp_model = POWERPC_EXCP_40x;
3423 pcc->bus_model = PPC_FLAGS_INPUT_401;
3424 pcc->bfd_mach = bfd_mach_ppc_403;
3425 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3426 POWERPC_FLAG_BUS_CLK;
3427 }
3428
3429 static void init_proc_401x2(CPUPPCState *env)
3430 {
3431 gen_spr_40x(env);
3432 gen_spr_401_403(env);
3433 gen_spr_401x2(env);
3434 gen_spr_compress(env);
3435 /* Memory management */
3436 #if !defined(CONFIG_USER_ONLY)
3437 env->nb_tlb = 64;
3438 env->nb_ways = 1;
3439 env->id_tlbs = 0;
3440 env->tlb_type = TLB_EMB;
3441 #endif
3442 init_excp_4xx_softmmu(env);
3443 env->dcache_line_size = 32;
3444 env->icache_line_size = 32;
3445 /* Allocate hardware IRQ controller */
3446 ppc40x_irq_init(ppc_env_get_cpu(env));
3447
3448 SET_FIT_PERIOD(12, 16, 20, 24);
3449 SET_WDT_PERIOD(16, 20, 24, 28);
3450 }
3451
3452 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3453 {
3454 DeviceClass *dc = DEVICE_CLASS(oc);
3455 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3456
3457 dc->desc = "PowerPC 401x2";
3458 pcc->init_proc = init_proc_401x2;
3459 pcc->check_pow = check_pow_nocheck;
3460 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3461 PPC_DCR | PPC_WRTEE |
3462 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3463 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3464 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3465 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3466 PPC_4xx_COMMON | PPC_40x_EXCP;
3467 pcc->msr_mask = (1ull << 20) |
3468 (1ull << MSR_KEY) |
3469 (1ull << MSR_POW) |
3470 (1ull << MSR_CE) |
3471 (1ull << MSR_ILE) |
3472 (1ull << MSR_EE) |
3473 (1ull << MSR_PR) |
3474 (1ull << MSR_ME) |
3475 (1ull << MSR_DE) |
3476 (1ull << MSR_IR) |
3477 (1ull << MSR_DR) |
3478 (1ull << MSR_LE);
3479 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3480 pcc->excp_model = POWERPC_EXCP_40x;
3481 pcc->bus_model = PPC_FLAGS_INPUT_401;
3482 pcc->bfd_mach = bfd_mach_ppc_403;
3483 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3484 POWERPC_FLAG_BUS_CLK;
3485 }
3486
3487 static void init_proc_401x3(CPUPPCState *env)
3488 {
3489 gen_spr_40x(env);
3490 gen_spr_401_403(env);
3491 gen_spr_401(env);
3492 gen_spr_401x2(env);
3493 gen_spr_compress(env);
3494 init_excp_4xx_softmmu(env);
3495 env->dcache_line_size = 32;
3496 env->icache_line_size = 32;
3497 /* Allocate hardware IRQ controller */
3498 ppc40x_irq_init(ppc_env_get_cpu(env));
3499
3500 SET_FIT_PERIOD(12, 16, 20, 24);
3501 SET_WDT_PERIOD(16, 20, 24, 28);
3502 }
3503
3504 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3505 {
3506 DeviceClass *dc = DEVICE_CLASS(oc);
3507 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3508
3509 dc->desc = "PowerPC 401x3";
3510 pcc->init_proc = init_proc_401x3;
3511 pcc->check_pow = check_pow_nocheck;
3512 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3513 PPC_DCR | PPC_WRTEE |
3514 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3515 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3516 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3517 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3518 PPC_4xx_COMMON | PPC_40x_EXCP;
3519 pcc->msr_mask = (1ull << 20) |
3520 (1ull << MSR_KEY) |
3521 (1ull << MSR_POW) |
3522 (1ull << MSR_CE) |
3523 (1ull << MSR_ILE) |
3524 (1ull << MSR_EE) |
3525 (1ull << MSR_PR) |
3526 (1ull << MSR_ME) |
3527 (1ull << MSR_DWE) |
3528 (1ull << MSR_DE) |
3529 (1ull << MSR_IR) |
3530 (1ull << MSR_DR) |
3531 (1ull << MSR_LE);
3532 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3533 pcc->excp_model = POWERPC_EXCP_40x;
3534 pcc->bus_model = PPC_FLAGS_INPUT_401;
3535 pcc->bfd_mach = bfd_mach_ppc_403;
3536 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3537 POWERPC_FLAG_BUS_CLK;
3538 }
3539
3540 static void init_proc_IOP480(CPUPPCState *env)
3541 {
3542 gen_spr_40x(env);
3543 gen_spr_401_403(env);
3544 gen_spr_401x2(env);
3545 gen_spr_compress(env);
3546 /* Memory management */
3547 #if !defined(CONFIG_USER_ONLY)
3548 env->nb_tlb = 64;
3549 env->nb_ways = 1;
3550 env->id_tlbs = 0;
3551 env->tlb_type = TLB_EMB;
3552 #endif
3553 init_excp_4xx_softmmu(env);
3554 env->dcache_line_size = 32;
3555 env->icache_line_size = 32;
3556 /* Allocate hardware IRQ controller */
3557 ppc40x_irq_init(ppc_env_get_cpu(env));
3558
3559 SET_FIT_PERIOD(8, 12, 16, 20);
3560 SET_WDT_PERIOD(16, 20, 24, 28);
3561 }
3562
3563 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3564 {
3565 DeviceClass *dc = DEVICE_CLASS(oc);
3566 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3567
3568 dc->desc = "IOP480";
3569 pcc->init_proc = init_proc_IOP480;
3570 pcc->check_pow = check_pow_nocheck;
3571 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3572 PPC_DCR | PPC_WRTEE |
3573 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3574 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3575 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3576 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3577 PPC_4xx_COMMON | PPC_40x_EXCP;
3578 pcc->msr_mask = (1ull << 20) |
3579 (1ull << MSR_KEY) |
3580 (1ull << MSR_POW) |
3581 (1ull << MSR_CE) |
3582 (1ull << MSR_ILE) |
3583 (1ull << MSR_EE) |
3584 (1ull << MSR_PR) |
3585 (1ull << MSR_ME) |
3586 (1ull << MSR_DE) |
3587 (1ull << MSR_IR) |
3588 (1ull << MSR_DR) |
3589 (1ull << MSR_LE);
3590 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3591 pcc->excp_model = POWERPC_EXCP_40x;
3592 pcc->bus_model = PPC_FLAGS_INPUT_401;
3593 pcc->bfd_mach = bfd_mach_ppc_403;
3594 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3595 POWERPC_FLAG_BUS_CLK;
3596 }
3597
3598 static void init_proc_403(CPUPPCState *env)
3599 {
3600 gen_spr_40x(env);
3601 gen_spr_401_403(env);
3602 gen_spr_403(env);
3603 gen_spr_403_real(env);
3604 init_excp_4xx_real(env);
3605 env->dcache_line_size = 32;
3606 env->icache_line_size = 32;
3607 /* Allocate hardware IRQ controller */
3608 ppc40x_irq_init(ppc_env_get_cpu(env));
3609
3610 SET_FIT_PERIOD(8, 12, 16, 20);
3611 SET_WDT_PERIOD(16, 20, 24, 28);
3612 }
3613
3614 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3615 {
3616 DeviceClass *dc = DEVICE_CLASS(oc);
3617 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3618
3619 dc->desc = "PowerPC 403";
3620 pcc->init_proc = init_proc_403;
3621 pcc->check_pow = check_pow_nocheck;
3622 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3623 PPC_DCR | PPC_WRTEE |
3624 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3625 PPC_CACHE_DCBZ |
3626 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3627 PPC_4xx_COMMON | PPC_40x_EXCP;
3628 pcc->msr_mask = (1ull << MSR_POW) |
3629 (1ull << MSR_CE) |
3630 (1ull << MSR_ILE) |
3631 (1ull << MSR_EE) |
3632 (1ull << MSR_PR) |
3633 (1ull << MSR_ME) |
3634 (1ull << MSR_PE) |
3635 (1ull << MSR_PX) |
3636 (1ull << MSR_LE);
3637 pcc->mmu_model = POWERPC_MMU_REAL;
3638 pcc->excp_model = POWERPC_EXCP_40x;
3639 pcc->bus_model = PPC_FLAGS_INPUT_401;
3640 pcc->bfd_mach = bfd_mach_ppc_403;
3641 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3642 POWERPC_FLAG_BUS_CLK;
3643 }
3644
3645 static void init_proc_403GCX(CPUPPCState *env)
3646 {
3647 gen_spr_40x(env);
3648 gen_spr_401_403(env);
3649 gen_spr_403(env);
3650 gen_spr_403_real(env);
3651 gen_spr_403_mmu(env);
3652 /* Bus access control */
3653 /* not emulated, as QEMU never does speculative access */
3654 spr_register(env, SPR_40x_SGR, "SGR",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0xFFFFFFFF);
3658 /* not emulated, as QEMU do not emulate caches */
3659 spr_register(env, SPR_40x_DCWR, "DCWR",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* Memory management */
3664 #if !defined(CONFIG_USER_ONLY)
3665 env->nb_tlb = 64;
3666 env->nb_ways = 1;
3667 env->id_tlbs = 0;
3668 env->tlb_type = TLB_EMB;
3669 #endif
3670 init_excp_4xx_softmmu(env);
3671 env->dcache_line_size = 32;
3672 env->icache_line_size = 32;
3673 /* Allocate hardware IRQ controller */
3674 ppc40x_irq_init(ppc_env_get_cpu(env));
3675
3676 SET_FIT_PERIOD(8, 12, 16, 20);
3677 SET_WDT_PERIOD(16, 20, 24, 28);
3678 }
3679
3680 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3681 {
3682 DeviceClass *dc = DEVICE_CLASS(oc);
3683 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3684
3685 dc->desc = "PowerPC 403 GCX";
3686 pcc->init_proc = init_proc_403GCX;
3687 pcc->check_pow = check_pow_nocheck;
3688 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3689 PPC_DCR | PPC_WRTEE |
3690 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3691 PPC_CACHE_DCBZ |
3692 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3693 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3694 PPC_4xx_COMMON | PPC_40x_EXCP;
3695 pcc->msr_mask = (1ull << MSR_POW) |
3696 (1ull << MSR_CE) |
3697 (1ull << MSR_ILE) |
3698 (1ull << MSR_EE) |
3699 (1ull << MSR_PR) |
3700 (1ull << MSR_ME) |
3701 (1ull << MSR_PE) |
3702 (1ull << MSR_PX) |
3703 (1ull << MSR_LE);
3704 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3705 pcc->excp_model = POWERPC_EXCP_40x;
3706 pcc->bus_model = PPC_FLAGS_INPUT_401;
3707 pcc->bfd_mach = bfd_mach_ppc_403;
3708 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3709 POWERPC_FLAG_BUS_CLK;
3710 }
3711
3712 static void init_proc_405(CPUPPCState *env)
3713 {
3714 /* Time base */
3715 gen_tbl(env);
3716 gen_spr_40x(env);
3717 gen_spr_405(env);
3718 /* Bus access control */
3719 /* not emulated, as QEMU never does speculative access */
3720 spr_register(env, SPR_40x_SGR, "SGR",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_generic,
3723 0xFFFFFFFF);
3724 /* not emulated, as QEMU do not emulate caches */
3725 spr_register(env, SPR_40x_DCWR, "DCWR",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 /* Memory management */
3730 #if !defined(CONFIG_USER_ONLY)
3731 env->nb_tlb = 64;
3732 env->nb_ways = 1;
3733 env->id_tlbs = 0;
3734 env->tlb_type = TLB_EMB;
3735 #endif
3736 init_excp_4xx_softmmu(env);
3737 env->dcache_line_size = 32;
3738 env->icache_line_size = 32;
3739 /* Allocate hardware IRQ controller */
3740 ppc40x_irq_init(ppc_env_get_cpu(env));
3741
3742 SET_FIT_PERIOD(8, 12, 16, 20);
3743 SET_WDT_PERIOD(16, 20, 24, 28);
3744 }
3745
3746 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3747 {
3748 DeviceClass *dc = DEVICE_CLASS(oc);
3749 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3750
3751 dc->desc = "PowerPC 405";
3752 pcc->init_proc = init_proc_405;
3753 pcc->check_pow = check_pow_nocheck;
3754 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3755 PPC_DCR | PPC_WRTEE |
3756 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3757 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3758 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3759 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3760 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3761 pcc->msr_mask = (1ull << MSR_POW) |
3762 (1ull << MSR_CE) |
3763 (1ull << MSR_EE) |
3764 (1ull << MSR_PR) |
3765 (1ull << MSR_FP) |
3766 (1ull << MSR_DWE) |
3767 (1ull << MSR_DE) |
3768 (1ull << MSR_IR) |
3769 (1ull << MSR_DR);
3770 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3771 pcc->excp_model = POWERPC_EXCP_40x;
3772 pcc->bus_model = PPC_FLAGS_INPUT_405;
3773 pcc->bfd_mach = bfd_mach_ppc_403;
3774 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3775 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3776 }
3777
3778 static void init_proc_440EP(CPUPPCState *env)
3779 {
3780 /* Time base */
3781 gen_tbl(env);
3782 gen_spr_BookE(env, 0x000000000000FFFFULL);
3783 gen_spr_440(env);
3784 gen_spr_usprgh(env);
3785 /* Processor identification */
3786 spr_register(env, SPR_BOOKE_PIR, "PIR",
3787 SPR_NOACCESS, SPR_NOACCESS,
3788 &spr_read_generic, &spr_write_pir,
3789 0x00000000);
3790 /* XXX : not implemented */
3791 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 /* XXX : not implemented */
3796 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
3800 /* XXX : not implemented */
3801 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3802 SPR_NOACCESS, SPR_NOACCESS,
3803 &spr_read_generic, &spr_write_generic,
3804 0x00000000);
3805 /* XXX : not implemented */
3806 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810 /* XXX : not implemented */
3811 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3812 SPR_NOACCESS, SPR_NOACCESS,
3813 &spr_read_generic, &spr_write_generic,
3814 0x00000000);
3815 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3816 SPR_NOACCESS, SPR_NOACCESS,
3817 &spr_read_generic, &spr_write_generic,
3818 0x00000000);
3819 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3820 SPR_NOACCESS, SPR_NOACCESS,
3821 &spr_read_generic, &spr_write_generic,
3822 0x00000000);
3823 /* XXX : not implemented */
3824 spr_register(env, SPR_440_CCR1, "CCR1",
3825 SPR_NOACCESS, SPR_NOACCESS,
3826 &spr_read_generic, &spr_write_generic,
3827 0x00000000);
3828 /* Memory management */
3829 #if !defined(CONFIG_USER_ONLY)
3830 env->nb_tlb = 64;
3831 env->nb_ways = 1;
3832 env->id_tlbs = 0;
3833 env->tlb_type = TLB_EMB;
3834 #endif
3835 init_excp_BookE(env);
3836 env->dcache_line_size = 32;
3837 env->icache_line_size = 32;
3838 ppc40x_irq_init(ppc_env_get_cpu(env));
3839
3840 SET_FIT_PERIOD(12, 16, 20, 24);
3841 SET_WDT_PERIOD(20, 24, 28, 32);
3842 }
3843
3844 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3845 {
3846 DeviceClass *dc = DEVICE_CLASS(oc);
3847 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3848
3849 dc->desc = "PowerPC 440 EP";
3850 pcc->init_proc = init_proc_440EP;
3851 pcc->check_pow = check_pow_nocheck;
3852 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3853 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3854 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3855 PPC_FLOAT_STFIWX |
3856 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3857 PPC_CACHE | PPC_CACHE_ICBI |
3858 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3859 PPC_MEM_TLBSYNC | PPC_MFTB |
3860 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3861 PPC_440_SPEC;
3862 pcc->msr_mask = (1ull << MSR_POW) |
3863 (1ull << MSR_CE) |
3864 (1ull << MSR_EE) |
3865 (1ull << MSR_PR) |
3866 (1ull << MSR_FP) |
3867 (1ull << MSR_ME) |
3868 (1ull << MSR_FE0) |
3869 (1ull << MSR_DWE) |
3870 (1ull << MSR_DE) |
3871 (1ull << MSR_FE1) |
3872 (1ull << MSR_IR) |
3873 (1ull << MSR_DR);
3874 pcc->mmu_model = POWERPC_MMU_BOOKE;
3875 pcc->excp_model = POWERPC_EXCP_BOOKE;
3876 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3877 pcc->bfd_mach = bfd_mach_ppc_403;
3878 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3879 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3880 }
3881
3882 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3883 {
3884 DeviceClass *dc = DEVICE_CLASS(oc);
3885 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3886
3887 dc->desc = "PowerPC 460 EX";
3888 pcc->init_proc = init_proc_440EP;
3889 pcc->check_pow = check_pow_nocheck;
3890 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3891 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3892 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3893 PPC_FLOAT_STFIWX |
3894 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3895 PPC_CACHE | PPC_CACHE_ICBI |
3896 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3897 PPC_MEM_TLBSYNC | PPC_MFTB |
3898 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3899 PPC_440_SPEC;
3900 pcc->msr_mask = (1ull << MSR_POW) |
3901 (1ull << MSR_CE) |
3902 (1ull << MSR_EE) |
3903 (1ull << MSR_PR) |
3904 (1ull << MSR_FP) |
3905 (1ull << MSR_ME) |
3906 (1ull << MSR_FE0) |
3907 (1ull << MSR_DWE) |
3908 (1ull << MSR_DE) |
3909 (1ull << MSR_FE1) |
3910 (1ull << MSR_IR) |
3911 (1ull << MSR_DR);
3912 pcc->mmu_model = POWERPC_MMU_BOOKE;
3913 pcc->excp_model = POWERPC_EXCP_BOOKE;
3914 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3915 pcc->bfd_mach = bfd_mach_ppc_403;
3916 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3917 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3918 }
3919
3920 static void init_proc_440GP(CPUPPCState *env)
3921 {
3922 /* Time base */
3923 gen_tbl(env);
3924 gen_spr_BookE(env, 0x000000000000FFFFULL);
3925 gen_spr_440(env);
3926 gen_spr_usprgh(env);
3927 /* Processor identification */
3928 spr_register(env, SPR_BOOKE_PIR, "PIR",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_pir,
3931 0x00000000);
3932 /* XXX : not implemented */
3933 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 /* XXX : not implemented */
3938 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3939 SPR_NOACCESS, SPR_NOACCESS,
3940 &spr_read_generic, &spr_write_generic,
3941 0x00000000);
3942 /* XXX : not implemented */
3943 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3944 SPR_NOACCESS, SPR_NOACCESS,
3945 &spr_read_generic, &spr_write_generic,
3946 0x00000000);
3947 /* XXX : not implemented */
3948 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3949 SPR_NOACCESS, SPR_NOACCESS,
3950 &spr_read_generic, &spr_write_generic,
3951 0x00000000);
3952 /* Memory management */
3953 #if !defined(CONFIG_USER_ONLY)
3954 env->nb_tlb = 64;
3955 env->nb_ways = 1;
3956 env->id_tlbs = 0;
3957 env->tlb_type = TLB_EMB;
3958 #endif
3959 init_excp_BookE(env);
3960 env->dcache_line_size = 32;
3961 env->icache_line_size = 32;
3962 /* XXX: TODO: allocate internal IRQ controller */
3963
3964 SET_FIT_PERIOD(12, 16, 20, 24);
3965 SET_WDT_PERIOD(20, 24, 28, 32);
3966 }
3967
3968 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3969 {
3970 DeviceClass *dc = DEVICE_CLASS(oc);
3971 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3972
3973 dc->desc = "PowerPC 440 GP";
3974 pcc->init_proc = init_proc_440GP;
3975 pcc->check_pow = check_pow_nocheck;
3976 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3977 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3978 PPC_CACHE | PPC_CACHE_ICBI |
3979 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3980 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3981 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3982 PPC_440_SPEC;
3983 pcc->msr_mask = (1ull << MSR_POW) |
3984 (1ull << MSR_CE) |
3985 (1ull << MSR_EE) |
3986 (1ull << MSR_PR) |
3987 (1ull << MSR_FP) |
3988 (1ull << MSR_ME) |
3989 (1ull << MSR_FE0) |
3990 (1ull << MSR_DWE) |
3991 (1ull << MSR_DE) |
3992 (1ull << MSR_FE1) |
3993 (1ull << MSR_IR) |
3994 (1ull << MSR_DR);
3995 pcc->mmu_model = POWERPC_MMU_BOOKE;
3996 pcc->excp_model = POWERPC_EXCP_BOOKE;
3997 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3998 pcc->bfd_mach = bfd_mach_ppc_403;
3999 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4000 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4001 }
4002
4003 static void init_proc_440x4(CPUPPCState *env)
4004 {
4005 /* Time base */
4006 gen_tbl(env);
4007 gen_spr_BookE(env, 0x000000000000FFFFULL);
4008 gen_spr_440(env);
4009 gen_spr_usprgh(env);
4010 /* Processor identification */
4011 spr_register(env, SPR_BOOKE_PIR, "PIR",
4012 SPR_NOACCESS, SPR_NOACCESS,
4013 &spr_read_generic, &spr_write_pir,
4014 0x00000000);
4015 /* XXX : not implemented */
4016 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4017 SPR_NOACCESS, SPR_NOACCESS,
4018 &spr_read_generic, &spr_write_generic,
4019 0x00000000);
4020 /* XXX : not implemented */
4021 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4022 SPR_NOACCESS, SPR_NOACCESS,
4023 &spr_read_generic, &spr_write_generic,
4024 0x00000000);
4025 /* XXX : not implemented */
4026 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4027 SPR_NOACCESS, SPR_NOACCESS,
4028 &spr_read_generic, &spr_write_generic,
4029 0x00000000);
4030 /* XXX : not implemented */
4031 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4032 SPR_NOACCESS, SPR_NOACCESS,
4033 &spr_read_generic, &spr_write_generic,
4034 0x00000000);
4035 /* Memory management */
4036 #if !defined(CONFIG_USER_ONLY)
4037 env->nb_tlb = 64;
4038 env->nb_ways = 1;
4039 env->id_tlbs = 0;
4040 env->tlb_type = TLB_EMB;
4041 #endif
4042 init_excp_BookE(env);
4043 env->dcache_line_size = 32;
4044 env->icache_line_size = 32;
4045 /* XXX: TODO: allocate internal IRQ controller */
4046
4047 SET_FIT_PERIOD(12, 16, 20, 24);
4048 SET_WDT_PERIOD(20, 24, 28, 32);
4049 }
4050
4051 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4052 {
4053 DeviceClass *dc = DEVICE_CLASS(oc);
4054 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4055
4056 dc->desc = "PowerPC 440x4";
4057 pcc->init_proc = init_proc_440x4;
4058 pcc->check_pow = check_pow_nocheck;
4059 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4060 PPC_DCR | PPC_WRTEE |
4061 PPC_CACHE | PPC_CACHE_ICBI |
4062 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4063 PPC_MEM_TLBSYNC | PPC_MFTB |
4064 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4065 PPC_440_SPEC;
4066 pcc->msr_mask = (1ull << MSR_POW) |
4067 (1ull << MSR_CE) |
4068 (1ull << MSR_EE) |
4069 (1ull << MSR_PR) |
4070 (1ull << MSR_FP) |
4071 (1ull << MSR_ME) |
4072 (1ull << MSR_FE0) |
4073 (1ull << MSR_DWE) |
4074 (1ull << MSR_DE) |
4075 (1ull << MSR_FE1) |
4076 (1ull << MSR_IR) |
4077 (1ull << MSR_DR);
4078 pcc->mmu_model = POWERPC_MMU_BOOKE;
4079 pcc->excp_model = POWERPC_EXCP_BOOKE;
4080 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4081 pcc->bfd_mach = bfd_mach_ppc_403;
4082 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4083 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4084 }
4085
4086 static void init_proc_440x5(CPUPPCState *env)
4087 {
4088 /* Time base */
4089 gen_tbl(env);
4090 gen_spr_BookE(env, 0x000000000000FFFFULL);
4091 gen_spr_440(env);
4092 gen_spr_usprgh(env);
4093 /* Processor identification */
4094 spr_register(env, SPR_BOOKE_PIR, "PIR",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_pir,
4097 0x00000000);
4098 /* XXX : not implemented */
4099 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, &spr_write_generic,
4102 0x00000000);
4103 /* XXX : not implemented */
4104 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108 /* XXX : not implemented */
4109 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4110 SPR_NOACCESS, SPR_NOACCESS,
4111 &spr_read_generic, &spr_write_generic,
4112 0x00000000);
4113 /* XXX : not implemented */
4114 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_generic,
4117 0x00000000);
4118 /* XXX : not implemented */
4119 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4120 SPR_NOACCESS, SPR_NOACCESS,
4121 &spr_read_generic, &spr_write_generic,
4122 0x00000000);
4123 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4124 SPR_NOACCESS, SPR_NOACCESS,
4125 &spr_read_generic, &spr_write_generic,
4126 0x00000000);
4127 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4128 SPR_NOACCESS, SPR_NOACCESS,
4129 &spr_read_generic, &spr_write_generic,
4130 0x00000000);
4131 /* XXX : not implemented */
4132 spr_register(env, SPR_440_CCR1, "CCR1",
4133 SPR_NOACCESS, SPR_NOACCESS,
4134 &spr_read_generic, &spr_write_generic,
4135 0x00000000);
4136 /* Memory management */
4137 #if !defined(CONFIG_USER_ONLY)
4138 env->nb_tlb = 64;
4139 env->nb_ways = 1;
4140 env->id_tlbs = 0;
4141 env->tlb_type = TLB_EMB;
4142 #endif
4143 init_excp_BookE(env);
4144 env->dcache_line_size = 32;
4145 env->icache_line_size = 32;
4146 ppc40x_irq_init(ppc_env_get_cpu(env));
4147
4148 SET_FIT_PERIOD(12, 16, 20, 24);
4149 SET_WDT_PERIOD(20, 24, 28, 32);
4150 }
4151
4152 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4153 {
4154 DeviceClass *dc = DEVICE_CLASS(oc);
4155 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4156
4157 dc->desc = "PowerPC 440x5";
4158 pcc->init_proc = init_proc_440x5;
4159 pcc->check_pow = check_pow_nocheck;
4160 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4161 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4162 PPC_CACHE | PPC_CACHE_ICBI |
4163 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4164 PPC_MEM_TLBSYNC | PPC_MFTB |
4165 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4166 PPC_440_SPEC;
4167 pcc->msr_mask = (1ull << MSR_POW) |
4168 (1ull << MSR_CE) |
4169 (1ull << MSR_EE) |
4170 (1ull << MSR_PR) |
4171 (1ull << MSR_FP) |
4172 (1ull << MSR_ME) |
4173 (1ull << MSR_FE0) |
4174 (1ull << MSR_DWE) |
4175 (1ull << MSR_DE) |
4176 (1ull << MSR_FE1) |
4177 (1ull << MSR_IR) |
4178 (1ull << MSR_DR);
4179 pcc->mmu_model = POWERPC_MMU_BOOKE;
4180 pcc->excp_model = POWERPC_EXCP_BOOKE;
4181 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4182 pcc->bfd_mach = bfd_mach_ppc_403;
4183 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4184 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4185 }
4186
4187 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4188 {
4189 DeviceClass *dc = DEVICE_CLASS(oc);
4190 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4191
4192 dc->desc = "PowerPC 440x5 with double precision FPU";
4193 pcc->init_proc = init_proc_440x5;
4194 pcc->check_pow = check_pow_nocheck;
4195 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4196 PPC_FLOAT | PPC_FLOAT_FSQRT |
4197 PPC_FLOAT_STFIWX |
4198 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4199 PPC_CACHE | PPC_CACHE_ICBI |
4200 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4201 PPC_MEM_TLBSYNC | PPC_MFTB |
4202 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4203 PPC_440_SPEC;
4204 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4205 pcc->msr_mask = (1ull << MSR_POW) |
4206 (1ull << MSR_CE) |
4207 (1ull << MSR_EE) |
4208 (1ull << MSR_PR) |
4209 (1ull << MSR_FP) |
4210 (1ull << MSR_ME) |
4211 (1ull << MSR_FE0) |
4212 (1ull << MSR_DWE) |
4213 (1ull << MSR_DE) |
4214 (1ull << MSR_FE1) |
4215 (1ull << MSR_IR) |
4216 (1ull << MSR_DR);
4217 pcc->mmu_model = POWERPC_MMU_BOOKE;
4218 pcc->excp_model = POWERPC_EXCP_BOOKE;
4219 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4220 pcc->bfd_mach = bfd_mach_ppc_403;
4221 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4222 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4223 }
4224
4225 static void init_proc_MPC5xx(CPUPPCState *env)
4226 {
4227 /* Time base */
4228 gen_tbl(env);
4229 gen_spr_5xx_8xx(env);
4230 gen_spr_5xx(env);
4231 init_excp_MPC5xx(env);
4232 env->dcache_line_size = 32;
4233 env->icache_line_size = 32;
4234 /* XXX: TODO: allocate internal IRQ controller */
4235 }
4236
4237 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4238 {
4239 DeviceClass *dc = DEVICE_CLASS(oc);
4240 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4241
4242 dc->desc = "Freescale 5xx cores (aka RCPU)";
4243 pcc->init_proc = init_proc_MPC5xx;
4244 pcc->check_pow = check_pow_none;
4245 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4246 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4247 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4248 PPC_MFTB;
4249 pcc->msr_mask = (1ull << MSR_ILE) |
4250 (1ull << MSR_EE) |
4251 (1ull << MSR_PR) |
4252 (1ull << MSR_FP) |
4253 (1ull << MSR_ME) |
4254 (1ull << MSR_FE0) |
4255 (1ull << MSR_SE) |
4256 (1ull << MSR_DE) |
4257 (1ull << MSR_FE1) |
4258 (1ull << MSR_EP) |
4259 (1ull << MSR_RI) |
4260 (1ull << MSR_LE);
4261 pcc->mmu_model = POWERPC_MMU_REAL;
4262 pcc->excp_model = POWERPC_EXCP_603;
4263 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4264 pcc->bfd_mach = bfd_mach_ppc_505;
4265 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4266 POWERPC_FLAG_BUS_CLK;
4267 }
4268
4269 static void init_proc_MPC8xx(CPUPPCState *env)
4270 {
4271 /* Time base */
4272 gen_tbl(env);
4273 gen_spr_5xx_8xx(env);
4274 gen_spr_8xx(env);
4275 init_excp_MPC8xx(env);
4276 env->dcache_line_size = 32;
4277 env->icache_line_size = 32;
4278 /* XXX: TODO: allocate internal IRQ controller */
4279 }
4280
4281 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4282 {
4283 DeviceClass *dc = DEVICE_CLASS(oc);
4284 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4285
4286 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4287 pcc->init_proc = init_proc_MPC8xx;
4288 pcc->check_pow = check_pow_none;
4289 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4290 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4291 PPC_CACHE_ICBI | PPC_MFTB;
4292 pcc->msr_mask = (1ull << MSR_ILE) |
4293 (1ull << MSR_EE) |
4294 (1ull << MSR_PR) |
4295 (1ull << MSR_FP) |
4296 (1ull << MSR_ME) |
4297 (1ull << MSR_SE) |
4298 (1ull << MSR_DE) |
4299 (1ull << MSR_EP) |
4300 (1ull << MSR_IR) |
4301 (1ull << MSR_DR) |
4302 (1ull << MSR_RI) |
4303 (1ull << MSR_LE);
4304 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4305 pcc->excp_model = POWERPC_EXCP_603;
4306 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4307 pcc->bfd_mach = bfd_mach_ppc_860;
4308 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4309 POWERPC_FLAG_BUS_CLK;
4310 }
4311
4312 /* Freescale 82xx cores (aka PowerQUICC-II) */
4313
4314 static void init_proc_G2(CPUPPCState *env)
4315 {
4316 gen_spr_ne_601(env);
4317 gen_spr_sdr1(env);
4318 gen_spr_G2_755(env);
4319 gen_spr_G2(env);
4320 /* Time base */
4321 gen_tbl(env);
4322 /* External access control */
4323 /* XXX : not implemented */
4324 spr_register(env, SPR_EAR, "EAR",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 /* Hardware implementation register */
4329 /* XXX : not implemented */
4330 spr_register(env, SPR_HID0, "HID0",
4331 SPR_NOACCESS, SPR_NOACCESS,
4332 &spr_read_generic, &spr_write_generic,
4333 0x00000000);
4334 /* XXX : not implemented */
4335 spr_register(env, SPR_HID1, "HID1",
4336 SPR_NOACCESS, SPR_NOACCESS,
4337 &spr_read_generic, &spr_write_generic,
4338 0x00000000);
4339 /* XXX : not implemented */
4340 spr_register(env, SPR_HID2, "HID2",
4341 SPR_NOACCESS, SPR_NOACCESS,
4342 &spr_read_generic, &spr_write_generic,
4343 0x00000000);
4344 /* Memory management */
4345 gen_low_BATs(env);
4346 gen_high_BATs(env);
4347 gen_6xx_7xx_soft_tlb(env, 64, 2);
4348 init_excp_G2(env);
4349 env->dcache_line_size = 32;
4350 env->icache_line_size = 32;
4351 /* Allocate hardware IRQ controller */
4352 ppc6xx_irq_init(ppc_env_get_cpu(env));
4353 }
4354
4355 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4356 {
4357 DeviceClass *dc = DEVICE_CLASS(oc);
4358 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4359
4360 dc->desc = "PowerPC G2";
4361 pcc->init_proc = init_proc_G2;
4362 pcc->check_pow = check_pow_hid0;
4363 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4364 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4365 PPC_FLOAT_STFIWX |
4366 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4367 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4368 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4369 PPC_SEGMENT | PPC_EXTERN;
4370 pcc->msr_mask = (1ull << MSR_POW) |
4371 (1ull << MSR_TGPR) |
4372 (1ull << MSR_EE) |
4373 (1ull << MSR_PR) |
4374 (1ull << MSR_FP) |
4375 (1ull << MSR_ME) |
4376 (1ull << MSR_FE0) |
4377 (1ull << MSR_SE) |
4378 (1ull << MSR_DE) |
4379 (1ull << MSR_FE1) |
4380 (1ull << MSR_AL) |
4381 (1ull << MSR_EP) |
4382 (1ull << MSR_IR) |
4383 (1ull << MSR_DR) |
4384 (1ull << MSR_RI);
4385 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4386 pcc->excp_model = POWERPC_EXCP_G2;
4387 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4388 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4389 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4390 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4391 }
4392
4393 static void init_proc_G2LE(CPUPPCState *env)
4394 {
4395 gen_spr_ne_601(env);
4396 gen_spr_sdr1(env);
4397 gen_spr_G2_755(env);
4398 gen_spr_G2(env);
4399 /* Time base */
4400 gen_tbl(env);
4401 /* External access control */
4402 /* XXX : not implemented */
4403 spr_register(env, SPR_EAR, "EAR",
4404 SPR_NOACCESS, SPR_NOACCESS,
4405 &spr_read_generic, &spr_write_generic,
4406 0x00000000);
4407 /* Hardware implementation register */
4408 /* XXX : not implemented */
4409 spr_register(env, SPR_HID0, "HID0",
4410 SPR_NOACCESS, SPR_NOACCESS,
4411 &spr_read_generic, &spr_write_generic,
4412 0x00000000);
4413 /* XXX : not implemented */
4414 spr_register(env, SPR_HID1, "HID1",
4415 SPR_NOACCESS, SPR_NOACCESS,
4416 &spr_read_generic, &spr_write_generic,
4417 0x00000000);
4418 /* XXX : not implemented */
4419 spr_register(env, SPR_HID2, "HID2",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423
4424 /* Memory management */
4425 gen_low_BATs(env);
4426 gen_high_BATs(env);
4427 gen_6xx_7xx_soft_tlb(env, 64, 2);
4428 init_excp_G2(env);
4429 env->dcache_line_size = 32;
4430 env->icache_line_size = 32;
4431 /* Allocate hardware IRQ controller */
4432 ppc6xx_irq_init(ppc_env_get_cpu(env));
4433 }
4434
4435 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4436 {
4437 DeviceClass *dc = DEVICE_CLASS(oc);
4438 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4439
4440 dc->desc = "PowerPC G2LE";
4441 pcc->init_proc = init_proc_G2LE;
4442 pcc->check_pow = check_pow_hid0;
4443 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4444 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4445 PPC_FLOAT_STFIWX |
4446 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4447 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4448 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4449 PPC_SEGMENT | PPC_EXTERN;
4450 pcc->msr_mask = (1ull << MSR_POW) |
4451 (1ull << MSR_TGPR) |
4452 (1ull << MSR_ILE) |
4453 (1ull << MSR_EE) |
4454 (1ull << MSR_PR) |
4455 (1ull << MSR_FP) |
4456 (1ull << MSR_ME) |
4457 (1ull << MSR_FE0) |
4458 (1ull << MSR_SE) |
4459 (1ull << MSR_DE) |
4460 (1ull << MSR_FE1) |
4461 (1ull << MSR_AL) |
4462 (1ull << MSR_EP) |
4463 (1ull << MSR_IR) |
4464 (1ull << MSR_DR) |
4465 (1ull << MSR_RI) |
4466 (1ull << MSR_LE);
4467 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4468 pcc->excp_model = POWERPC_EXCP_G2;
4469 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4470 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4471 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4472 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4473 }
4474
4475 static void init_proc_e200(CPUPPCState *env)
4476 {
4477 /* Time base */
4478 gen_tbl(env);
4479 gen_spr_BookE(env, 0x000000070000FFFFULL);
4480 /* XXX : not implemented */
4481 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4482 &spr_read_spefscr, &spr_write_spefscr,
4483 &spr_read_spefscr, &spr_write_spefscr,
4484 0x00000000);
4485 /* Memory management */
4486 gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4487 /* XXX : not implemented */
4488 spr_register(env, SPR_HID0, "HID0",
4489 SPR_NOACCESS, SPR_NOACCESS,
4490 &spr_read_generic, &spr_write_generic,
4491 0x00000000);
4492 /* XXX : not implemented */
4493 spr_register(env, SPR_HID1, "HID1",
4494 SPR_NOACCESS, SPR_NOACCESS,
4495 &spr_read_generic, &spr_write_generic,
4496 0x00000000);
4497 /* XXX : not implemented */
4498 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4499 SPR_NOACCESS, SPR_NOACCESS,
4500 &spr_read_generic, &spr_write_generic,
4501 0x00000000);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 /* XXX : not implemented */
4508 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4509 SPR_NOACCESS, SPR_NOACCESS,
4510 &spr_read_generic, &spr_write_generic,
4511 0x00000000);
4512 /* XXX : not implemented */
4513 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4514 SPR_NOACCESS, SPR_NOACCESS,
4515 &spr_read_generic, &spr_write_generic,
4516 0x00000000);
4517 /* XXX : not implemented */
4518 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4519 SPR_NOACCESS, SPR_NOACCESS,
4520 &spr_read_generic, &spr_write_generic,
4521 0x00000000);
4522 /* XXX : not implemented */
4523 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4524 &spr_read_generic, SPR_NOACCESS,
4525 &spr_read_generic, SPR_NOACCESS,
4526 0x00000000);
4527 /* XXX : not implemented */
4528 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4529 SPR_NOACCESS, SPR_NOACCESS,
4530 &spr_read_generic, &spr_write_generic,
4531 0x00000000);
4532 /* XXX : not implemented */
4533 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 /* XXX : not implemented */
4538 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4539 SPR_NOACCESS, SPR_NOACCESS,
4540 &spr_read_generic, &spr_write_generic,
4541 0x00000000);
4542 /* XXX : not implemented */
4543 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4544 SPR_NOACCESS, SPR_NOACCESS,
4545 &spr_read_generic, &spr_write_generic,
4546 0x00000000);
4547 /* XXX : not implemented */
4548 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4549 SPR_NOACCESS, SPR_NOACCESS,
4550 &spr_read_generic, &spr_write_generic,
4551 0x00000000);
4552 /* XXX : not implemented */
4553 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4554 SPR_NOACCESS, SPR_NOACCESS,
4555 &spr_read_generic, &spr_write_generic,
4556 0x00000000);
4557 /* XXX : not implemented */
4558 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4559 SPR_NOACCESS, SPR_NOACCESS,
4560 &spr_read_generic, &spr_write_generic,
4561 0x00000000); /* TOFIX */
4562 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4563 SPR_NOACCESS, SPR_NOACCESS,
4564 &spr_read_generic, &spr_write_generic,
4565 0x00000000);
4566 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4567 SPR_NOACCESS, SPR_NOACCESS,
4568 &spr_read_generic, &spr_write_generic,
4569 0x00000000);
4570 #if !defined(CONFIG_USER_ONLY)
4571 env->nb_tlb = 64;
4572 env->nb_ways = 1;
4573 env->id_tlbs = 0;
4574 env->tlb_type = TLB_EMB;
4575 #endif
4576 init_excp_e200(env, 0xFFFF0000UL);
4577 env->dcache_line_size = 32;
4578 env->icache_line_size = 32;
4579 /* XXX: TODO: allocate internal IRQ controller */
4580 }
4581
4582 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4583 {
4584 DeviceClass *dc = DEVICE_CLASS(oc);
4585 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4586
4587 dc->desc = "e200 core";
4588 pcc->init_proc = init_proc_e200;
4589 pcc->check_pow = check_pow_hid0;
4590 /* XXX: unimplemented instructions:
4591 * dcblc
4592 * dcbtlst
4593 * dcbtstls
4594 * icblc
4595 * icbtls
4596 * tlbivax
4597 * all SPE multiply-accumulate instructions
4598 */
4599 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4600 PPC_SPE | PPC_SPE_SINGLE |
4601 PPC_WRTEE | PPC_RFDI |
4602 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4603 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4604 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4605 PPC_BOOKE;
4606 pcc->msr_mask = (1ull << MSR_UCLE) |
4607 (1ull << MSR_SPE) |
4608 (1ull << MSR_POW) |
4609 (1ull << MSR_CE) |
4610 (1ull << MSR_EE) |
4611 (1ull << MSR_PR) |
4612 (1ull << MSR_FP) |
4613 (1ull << MSR_ME) |
4614 (1ull << MSR_FE0) |
4615 (1ull << MSR_DWE) |
4616 (1ull << MSR_DE) |
4617 (1ull << MSR_FE1) |
4618 (1ull << MSR_IR) |
4619 (1ull << MSR_DR);
4620 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4621 pcc->excp_model = POWERPC_EXCP_BOOKE;
4622 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4623 pcc->bfd_mach = bfd_mach_ppc_860;
4624 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4625 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4626 POWERPC_FLAG_BUS_CLK;
4627 }
4628
4629 static void init_proc_e300(CPUPPCState *env)
4630 {
4631 gen_spr_ne_601(env);
4632 gen_spr_sdr1(env);
4633 gen_spr_603(env);
4634 /* Time base */
4635 gen_tbl(env);
4636 /* hardware implementation registers */
4637 /* XXX : not implemented */
4638 spr_register(env, SPR_HID0, "HID0",
4639 SPR_NOACCESS, SPR_NOACCESS,
4640 &spr_read_generic, &spr_write_generic,
4641 0x00000000);
4642 /* XXX : not implemented */
4643 spr_register(env, SPR_HID1, "HID1",
4644 SPR_NOACCESS, SPR_NOACCESS,
4645 &spr_read_generic, &spr_write_generic,
4646 0x00000000);
4647 /* XXX : not implemented */
4648 spr_register(env, SPR_HID2, "HID2",
4649 SPR_NOACCESS, SPR_NOACCESS,
4650 &spr_read_generic, &spr_write_generic,
4651 0x00000000);
4652 /* Breakpoints */
4653 /* XXX : not implemented */
4654 spr_register(env, SPR_DABR, "DABR",
4655 SPR_NOACCESS, SPR_NOACCESS,
4656 &spr_read_generic, &spr_write_generic,
4657 0x00000000);
4658 /* XXX : not implemented */
4659 spr_register(env, SPR_DABR2, "DABR2",
4660 SPR_NOACCESS, SPR_NOACCESS,
4661 &spr_read_generic, &spr_write_generic,
4662 0x00000000);
4663 /* XXX : not implemented */
4664 spr_register(env, SPR_IABR2, "IABR2",
4665 SPR_NOACCESS, SPR_NOACCESS,
4666 &spr_read_generic, &spr_write_generic,
4667 0x00000000);
4668 /* XXX : not implemented */
4669 spr_register(env, SPR_IBCR, "IBCR",
4670 SPR_NOACCESS, SPR_NOACCESS,
4671 &spr_read_generic, &spr_write_generic,
4672 0x00000000);
4673 /* XXX : not implemented */
4674 spr_register(env, SPR_DBCR, "DBCR",
4675 SPR_NOACCESS, SPR_NOACCESS,
4676 &spr_read_generic, &spr_write_generic,
4677 0x00000000);
4678 /* Memory management */
4679 gen_low_BATs(env);
4680 gen_high_BATs(env);
4681 gen_6xx_7xx_soft_tlb(env, 64, 2);
4682 init_excp_603(env);
4683 env->dcache_line_size = 32;
4684 env->icache_line_size = 32;
4685 /* Allocate hardware IRQ controller */
4686 ppc6xx_irq_init(ppc_env_get_cpu(env));
4687 }
4688
4689 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4690 {
4691 DeviceClass *dc = DEVICE_CLASS(oc);
4692 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4693
4694 dc->desc = "e300 core";
4695 pcc->init_proc = init_proc_e300;
4696 pcc->check_pow = check_pow_hid0;
4697 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4698 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4699 PPC_FLOAT_STFIWX |
4700 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4701 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4702 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4703 PPC_SEGMENT | PPC_EXTERN;
4704 pcc->msr_mask = (1ull << MSR_POW) |
4705 (1ull << MSR_TGPR) |
4706 (1ull << MSR_ILE) |
4707 (1ull << MSR_EE) |
4708 (1ull << MSR_PR) |
4709 (1ull << MSR_FP) |
4710 (1ull << MSR_ME) |
4711 (1ull << MSR_FE0) |
4712 (1ull << MSR_SE) |
4713 (1ull << MSR_DE) |
4714 (1ull << MSR_FE1) |
4715 (1ull << MSR_AL) |
4716 (1ull << MSR_EP) |
4717 (1ull << MSR_IR) |
4718 (1ull << MSR_DR) |
4719 (1ull << MSR_RI) |
4720 (1ull << MSR_LE);
4721 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4722 pcc->excp_model = POWERPC_EXCP_603;
4723 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4724 pcc->bfd_mach = bfd_mach_ppc_603;
4725 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4726 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4727 }
4728
4729 #if !defined(CONFIG_USER_ONLY)
4730 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4731 {
4732 TCGv val = tcg_temp_new();
4733 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4734 gen_store_spr(SPR_BOOKE_MAS3, val);
4735 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4736 gen_store_spr(SPR_BOOKE_MAS7, val);
4737 tcg_temp_free(val);
4738 }
4739
4740 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4741 {
4742 TCGv mas7 = tcg_temp_new();
4743 TCGv mas3 = tcg_temp_new();
4744 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4745 tcg_gen_shli_tl(mas7, mas7, 32);
4746 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4747 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4748 tcg_temp_free(mas3);
4749 tcg_temp_free(mas7);
4750 }
4751
4752 #endif
4753
4754 enum fsl_e500_version {
4755 fsl_e500v1,
4756 fsl_e500v2,
4757 fsl_e500mc,
4758 fsl_e5500,
4759 fsl_e6500,
4760 };
4761
4762 static void init_proc_e500(CPUPPCState *env, int version)
4763 {
4764 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4765 uint32_t tlbncfg[2];
4766 uint64_t ivor_mask;
4767 uint64_t ivpr_mask = 0xFFFF0000ULL;
4768 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4769 | 0x0020; /* 32 kb */
4770 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4771 | 0x0020; /* 32 kb */
4772 uint32_t mmucfg = 0;
4773 #if !defined(CONFIG_USER_ONLY)
4774 int i;
4775 #endif
4776
4777 /* Time base */
4778 gen_tbl(env);
4779 /*
4780 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4781 * complain when accessing them.
4782 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4783 */
4784 switch (version) {
4785 case fsl_e500v1:
4786 case fsl_e500v2:
4787 default:
4788 ivor_mask = 0x0000000F0000FFFFULL;
4789 break;
4790 case fsl_e500mc:
4791 case fsl_e5500:
4792 ivor_mask = 0x000003FE0000FFFFULL;
4793 break;
4794 case fsl_e6500:
4795 ivor_mask = 0x000003FF0000FFFFULL;
4796 break;
4797 }
4798 gen_spr_BookE(env, ivor_mask);
4799 gen_spr_usprg3(env);
4800 /* Processor identification */
4801 spr_register(env, SPR_BOOKE_PIR, "PIR",
4802 SPR_NOACCESS, SPR_NOACCESS,
4803 &spr_read_generic, &spr_write_pir,
4804 0x00000000);
4805 /* XXX : not implemented */
4806 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4807 &spr_read_spefscr, &spr_write_spefscr,
4808 &spr_read_spefscr, &spr_write_spefscr,
4809 0x00000000);
4810 #if !defined(CONFIG_USER_ONLY)
4811 /* Memory management */
4812 env->nb_pids = 3;
4813 env->nb_ways = 2;
4814 env->id_tlbs = 0;
4815 switch (version) {
4816 case fsl_e500v1:
4817 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4818 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4819 break;
4820 case fsl_e500v2:
4821 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4822 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4823 break;
4824 case fsl_e500mc:
4825 case fsl_e5500:
4826 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4827 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4828 break;
4829 case fsl_e6500:
4830 mmucfg = 0x6510B45;
4831 env->nb_pids = 1;
4832 tlbncfg[0] = 0x08052400;
4833 tlbncfg[1] = 0x40028040;
4834 break;
4835 default:
4836 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4837 }
4838 #endif
4839 /* Cache sizes */
4840 switch (version) {
4841 case fsl_e500v1:
4842 case fsl_e500v2:
4843 env->dcache_line_size = 32;
4844 env->icache_line_size = 32;
4845 break;
4846 case fsl_e500mc:
4847 case fsl_e5500:
4848 env->dcache_line_size = 64;
4849 env->icache_line_size = 64;
4850 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4851 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4852 break;
4853 case fsl_e6500:
4854 env->dcache_line_size = 32;
4855 env->icache_line_size = 32;
4856 l1cfg0 |= 0x0F83820;
4857 l1cfg1 |= 0x0B83820;
4858 break;
4859 default:
4860 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4861 }
4862 gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
4863 /* XXX : not implemented */
4864 spr_register(env, SPR_HID0, "HID0",
4865 SPR_NOACCESS, SPR_NOACCESS,
4866 &spr_read_generic, &spr_write_generic,
4867 0x00000000);
4868 /* XXX : not implemented */
4869 spr_register(env, SPR_HID1, "HID1",
4870 SPR_NOACCESS, SPR_NOACCESS,
4871 &spr_read_generic, &spr_write_generic,
4872 0x00000000);
4873 /* XXX : not implemented */
4874 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4875 SPR_NOACCESS, SPR_NOACCESS,
4876 &spr_read_generic, &spr_write_generic,
4877 0x00000000);
4878 /* XXX : not implemented */
4879 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4880 SPR_NOACCESS, SPR_NOACCESS,
4881 &spr_read_generic, &spr_write_generic,
4882 0x00000000);
4883 /* XXX : not implemented */
4884 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4885 SPR_NOACCESS, SPR_NOACCESS,
4886 &spr_read_generic, &spr_write_generic,
4887 0x00000000);
4888 /* XXX : not implemented */
4889 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4890 SPR_NOACCESS, SPR_NOACCESS,
4891 &spr_read_generic, &spr_write_generic,
4892 0x00000000);
4893 /* XXX : not implemented */
4894 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4895 SPR_NOACCESS, SPR_NOACCESS,
4896 &spr_read_generic, &spr_write_generic,
4897 0x00000000);
4898 /* XXX : not implemented */
4899 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4900 SPR_NOACCESS, SPR_NOACCESS,
4901 &spr_read_generic, &spr_write_generic,
4902 0x00000000);
4903 /* XXX : not implemented */
4904 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4905 &spr_read_generic, SPR_NOACCESS,
4906 &spr_read_generic, SPR_NOACCESS,
4907 l1cfg0);
4908 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4909 &spr_read_generic, SPR_NOACCESS,
4910 &spr_read_generic, SPR_NOACCESS,
4911 l1cfg1);
4912 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_e500_l1csr0,
4915 0x00000000);
4916 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_e500_l1csr1,
4919 0x00000000);
4920 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4921 SPR_NOACCESS, SPR_NOACCESS,
4922 &spr_read_generic, &spr_write_generic,
4923 0x00000000);
4924 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4925 SPR_NOACCESS, SPR_NOACCESS,
4926 &spr_read_generic, &spr_write_generic,
4927 0x00000000);
4928 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4929 SPR_NOACCESS, SPR_NOACCESS,
4930 &spr_read_generic, &spr_write_booke206_mmucsr0,
4931 0x00000000);
4932 spr_register(env, SPR_BOOKE_EPR, "EPR",
4933 SPR_NOACCESS, SPR_NOACCESS,
4934 &spr_read_generic, SPR_NOACCESS,
4935 0x00000000);
4936 /* XXX better abstract into Emb.xxx features */
4937 if ((version == fsl_e5500) || (version == fsl_e6500)) {
4938 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4939 SPR_NOACCESS, SPR_NOACCESS,
4940 &spr_read_generic, &spr_write_generic,
4941 0x00000000);
4942 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4943 SPR_NOACCESS, SPR_NOACCESS,
4944 &spr_read_mas73, &spr_write_mas73,
4945 0x00000000);
4946 ivpr_mask = (target_ulong)~0xFFFFULL;
4947 }
4948
4949 if (version == fsl_e6500) {
4950 /* Thread identification */
4951 spr_register(env, SPR_TIR, "TIR",
4952 SPR_NOACCESS, SPR_NOACCESS,
4953 &spr_read_generic, SPR_NOACCESS,
4954 0x00000000);
4955 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
4956 SPR_NOACCESS, SPR_NOACCESS,
4957 &spr_read_generic, SPR_NOACCESS,
4958 0x00000004);
4959 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
4960 SPR_NOACCESS, SPR_NOACCESS,
4961 &spr_read_generic, SPR_NOACCESS,
4962 0x7FFFFFFC);
4963 }
4964
4965 #if !defined(CONFIG_USER_ONLY)
4966 env->nb_tlb = 0;
4967 env->tlb_type = TLB_MAS;
4968 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4969 env->nb_tlb += booke206_tlb_size(env, i);
4970 }
4971 #endif
4972
4973 init_excp_e200(env, ivpr_mask);
4974 /* Allocate hardware IRQ controller */
4975 ppce500_irq_init(ppc_env_get_cpu(env));
4976 }
4977
4978 static void init_proc_e500v1(CPUPPCState *env)
4979 {
4980 init_proc_e500(env, fsl_e500v1);
4981 }
4982
4983 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4984 {
4985 DeviceClass *dc = DEVICE_CLASS(oc);
4986 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4987
4988 dc->desc = "e500v1 core";
4989 pcc->init_proc = init_proc_e500v1;
4990 pcc->check_pow = check_pow_hid0;
4991 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4992 PPC_SPE | PPC_SPE_SINGLE |
4993 PPC_WRTEE | PPC_RFDI |
4994 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4995 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4996 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4997 pcc->insns_flags2 = PPC2_BOOKE206;
4998 pcc->msr_mask = (1ull << MSR_UCLE) |
4999 (1ull << MSR_SPE) |
5000 (1ull << MSR_POW) |
5001 (1ull << MSR_CE) |
5002 (1ull << MSR_EE) |
5003 (1ull << MSR_PR) |
5004 (1ull << MSR_FP) |
5005 (1ull << MSR_ME) |
5006 (1ull << MSR_FE0) |
5007 (1ull << MSR_DWE) |
5008 (1ull << MSR_DE) |
5009 (1ull << MSR_FE1) |
5010 (1ull << MSR_IR) |
5011 (1ull << MSR_DR);
5012 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5013 pcc->excp_model = POWERPC_EXCP_BOOKE;
5014 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5015 pcc->bfd_mach = bfd_mach_ppc_860;
5016 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5017 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5018 POWERPC_FLAG_BUS_CLK;
5019 }
5020
5021 static void init_proc_e500v2(CPUPPCState *env)
5022 {
5023 init_proc_e500(env, fsl_e500v2);
5024 }
5025
5026 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5027 {
5028 DeviceClass *dc = DEVICE_CLASS(oc);
5029 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5030
5031 dc->desc = "e500v2 core";
5032 pcc->init_proc = init_proc_e500v2;
5033 pcc->check_pow = check_pow_hid0;
5034 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5035 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5036 PPC_WRTEE | PPC_RFDI |
5037 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5038 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5039 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5040 pcc->insns_flags2 = PPC2_BOOKE206;
5041 pcc->msr_mask = (1ull << MSR_UCLE) |
5042 (1ull << MSR_SPE) |
5043 (1ull << MSR_POW) |
5044 (1ull << MSR_CE) |
5045 (1ull << MSR_EE) |
5046 (1ull << MSR_PR) |
5047 (1ull << MSR_FP) |
5048 (1ull << MSR_ME) |
5049 (1ull << MSR_FE0) |
5050 (1ull << MSR_DWE) |
5051 (1ull << MSR_DE) |
5052 (1ull << MSR_FE1) |
5053 (1ull << MSR_IR) |
5054 (1ull << MSR_DR);
5055 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5056 pcc->excp_model = POWERPC_EXCP_BOOKE;
5057 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5058 pcc->bfd_mach = bfd_mach_ppc_860;
5059 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5060 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5061 POWERPC_FLAG_BUS_CLK;
5062 }
5063
5064 static void init_proc_e500mc(CPUPPCState *env)
5065 {
5066 init_proc_e500(env, fsl_e500mc);
5067 }
5068
5069 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5070 {
5071 DeviceClass *dc = DEVICE_CLASS(oc);
5072 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5073
5074 dc->desc = "e500mc core";
5075 pcc->init_proc = init_proc_e500mc;
5076 pcc->check_pow = check_pow_none;
5077 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5078 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5079 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5080 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5081 PPC_FLOAT | PPC_FLOAT_FRES |
5082 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5083 PPC_FLOAT_STFIWX | PPC_WAIT |
5084 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5085 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5086 pcc->msr_mask = (1ull << MSR_GS) |
5087 (1ull << MSR_UCLE) |
5088 (1ull << MSR_CE) |
5089 (1ull << MSR_EE) |
5090 (1ull << MSR_PR) |
5091 (1ull << MSR_FP) |
5092 (1ull << MSR_ME) |
5093 (1ull << MSR_FE0) |
5094 (1ull << MSR_DE) |
5095 (1ull << MSR_FE1) |
5096 (1ull << MSR_IR) |
5097 (1ull << MSR_DR) |
5098 (1ull << MSR_PX) |
5099 (1ull << MSR_RI);
5100 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5101 pcc->excp_model = POWERPC_EXCP_BOOKE;
5102 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5103 /* FIXME: figure out the correct flag for e500mc */
5104 pcc->bfd_mach = bfd_mach_ppc_e500;
5105 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5106 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5107 }
5108
5109 #ifdef TARGET_PPC64
5110 static void init_proc_e5500(CPUPPCState *env)
5111 {
5112 init_proc_e500(env, fsl_e5500);
5113 }
5114
5115 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5116 {
5117 DeviceClass *dc = DEVICE_CLASS(oc);
5118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5119
5120 dc->desc = "e5500 core";
5121 pcc->init_proc = init_proc_e5500;
5122 pcc->check_pow = check_pow_none;
5123 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5124 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5125 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5126 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5127 PPC_FLOAT | PPC_FLOAT_FRES |
5128 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5129 PPC_FLOAT_STFIWX | PPC_WAIT |
5130 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5131 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5132 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5133 PPC2_FP_CVT_S64;
5134 pcc->msr_mask = (1ull << MSR_CM) |
5135 (1ull << MSR_GS) |
5136 (1ull << MSR_UCLE) |
5137 (1ull << MSR_CE) |
5138 (1ull << MSR_EE) |
5139 (1ull << MSR_PR) |
5140 (1ull << MSR_FP) |
5141 (1ull << MSR_ME) |
5142 (1ull << MSR_FE0) |
5143 (1ull << MSR_DE) |
5144 (1ull << MSR_FE1) |
5145 (1ull << MSR_IR) |
5146 (1ull << MSR_DR) |
5147 (1ull << MSR_PX) |
5148 (1ull << MSR_RI);
5149 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5150 pcc->excp_model = POWERPC_EXCP_BOOKE;
5151 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5152 /* FIXME: figure out the correct flag for e5500 */
5153 pcc->bfd_mach = bfd_mach_ppc_e500;
5154 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5155 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5156 }
5157
5158 static void init_proc_e6500(CPUPPCState *env)
5159 {
5160 init_proc_e500(env, fsl_e6500);
5161 }
5162
5163 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
5164 {
5165 DeviceClass *dc = DEVICE_CLASS(oc);
5166 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5167
5168 dc->desc = "e6500 core";
5169 pcc->init_proc = init_proc_e6500;
5170 pcc->check_pow = check_pow_none;
5171 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5172 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5173 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5174 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5175 PPC_FLOAT | PPC_FLOAT_FRES |
5176 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5177 PPC_FLOAT_STFIWX | PPC_WAIT |
5178 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5179 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
5180 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5181 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
5182 pcc->msr_mask = (1ull << MSR_CM) |
5183 (1ull << MSR_GS) |
5184 (1ull << MSR_UCLE) |
5185 (1ull << MSR_CE) |
5186 (1ull << MSR_EE) |
5187 (1ull << MSR_PR) |
5188 (1ull << MSR_FP) |
5189 (1ull << MSR_ME) |
5190 (1ull << MSR_FE0) |
5191 (1ull << MSR_DE) |
5192 (1ull << MSR_FE1) |
5193 (1ull << MSR_IS) |
5194 (1ull << MSR_DS) |
5195 (1ull << MSR_PX) |
5196 (1ull << MSR_RI) |
5197 (1ull << MSR_VR);
5198 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5199 pcc->excp_model = POWERPC_EXCP_BOOKE;
5200 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5201 pcc->bfd_mach = bfd_mach_ppc_e500;
5202 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5203 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
5204 }
5205
5206 #endif
5207
5208 /* Non-embedded PowerPC */
5209
5210 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5211
5212 static void init_proc_601(CPUPPCState *env)
5213 {
5214 gen_spr_ne_601(env);
5215 gen_spr_sdr1(env);
5216 gen_spr_601(env);
5217 /* Hardware implementation registers */
5218 /* XXX : not implemented */
5219 spr_register(env, SPR_HID0, "HID0",
5220 SPR_NOACCESS, SPR_NOACCESS,
5221 &spr_read_generic, &spr_write_hid0_601,
5222 0x80010080);
5223 /* XXX : not implemented */
5224 spr_register(env, SPR_HID1, "HID1",
5225 SPR_NOACCESS, SPR_NOACCESS,
5226 &spr_read_generic, &spr_write_generic,
5227 0x00000000);
5228 /* XXX : not implemented */
5229 spr_register(env, SPR_601_HID2, "HID2",
5230 SPR_NOACCESS, SPR_NOACCESS,
5231 &spr_read_generic, &spr_write_generic,
5232 0x00000000);
5233 /* XXX : not implemented */
5234 spr_register(env, SPR_601_HID5, "HID5",
5235 SPR_NOACCESS, SPR_NOACCESS,
5236 &spr_read_generic, &spr_write_generic,
5237 0x00000000);
5238 /* Memory management */
5239 init_excp_601(env);
5240 /* XXX: beware that dcache line size is 64
5241 * but dcbz uses 32 bytes "sectors"
5242 * XXX: this breaks clcs instruction !
5243 */
5244 env->dcache_line_size = 32;
5245 env->icache_line_size = 64;
5246 /* Allocate hardware IRQ controller */
5247 ppc6xx_irq_init(ppc_env_get_cpu(env));
5248 }
5249
5250 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5251 {
5252 DeviceClass *dc = DEVICE_CLASS(oc);
5253 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5254
5255 dc->desc = "PowerPC 601";
5256 pcc->init_proc = init_proc_601;
5257 pcc->check_pow = check_pow_none;
5258 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5259 PPC_FLOAT |
5260 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5261 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5262 PPC_SEGMENT | PPC_EXTERN;
5263 pcc->msr_mask = (1ull << MSR_EE) |
5264 (1ull << MSR_PR) |
5265 (1ull << MSR_FP) |
5266 (1ull << MSR_ME) |
5267 (1ull << MSR_FE0) |
5268 (1ull << MSR_SE) |
5269 (1ull << MSR_FE1) |
5270 (1ull << MSR_EP) |
5271 (1ull << MSR_IR) |
5272 (1ull << MSR_DR);
5273 pcc->mmu_model = POWERPC_MMU_601;
5274 #if defined(CONFIG_SOFTMMU)
5275 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5276 #endif
5277 pcc->excp_model = POWERPC_EXCP_601;
5278 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5279 pcc->bfd_mach = bfd_mach_ppc_601;
5280 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5281 }
5282
5283 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5284
5285 static void init_proc_601v(CPUPPCState *env)
5286 {
5287 init_proc_601(env);
5288 /* XXX : not implemented */
5289 spr_register(env, SPR_601_HID15, "HID15",
5290 SPR_NOACCESS, SPR_NOACCESS,
5291 &spr_read_generic, &spr_write_generic,
5292 0x00000000);
5293 }
5294
5295 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5296 {
5297 DeviceClass *dc = DEVICE_CLASS(oc);
5298 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5299
5300 dc->desc = "PowerPC 601v";
5301 pcc->init_proc = init_proc_601v;
5302 pcc->check_pow = check_pow_none;
5303 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5304 PPC_FLOAT |
5305 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5306 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5307 PPC_SEGMENT | PPC_EXTERN;
5308 pcc->msr_mask = (1ull << MSR_EE) |
5309 (1ull << MSR_PR) |
5310 (1ull << MSR_FP) |
5311 (1ull << MSR_ME) |
5312 (1ull << MSR_FE0) |
5313 (1ull << MSR_SE) |
5314 (1ull << MSR_FE1) |
5315 (1ull << MSR_EP) |
5316 (1ull << MSR_IR) |
5317 (1ull << MSR_DR);
5318 pcc->mmu_model = POWERPC_MMU_601;
5319 #if defined(CONFIG_SOFTMMU)
5320 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5321 #endif
5322 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5323 pcc->bfd_mach = bfd_mach_ppc_601;
5324 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5325 }
5326
5327 static void init_proc_602(CPUPPCState *env)
5328 {
5329 gen_spr_ne_601(env);
5330 gen_spr_sdr1(env);
5331 gen_spr_602(env);
5332 /* Time base */
5333 gen_tbl(env);
5334 /* hardware implementation registers */
5335 /* XXX : not implemented */
5336 spr_register(env, SPR_HID0, "HID0",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 /* XXX : not implemented */
5341 spr_register(env, SPR_HID1, "HID1",
5342 SPR_NOACCESS, SPR_NOACCESS,
5343 &spr_read_generic, &spr_write_generic,
5344 0x00000000);
5345 /* Memory management */
5346 gen_low_BATs(env);
5347 gen_6xx_7xx_soft_tlb(env, 64, 2);
5348 init_excp_602(env);
5349 env->dcache_line_size = 32;
5350 env->icache_line_size = 32;
5351 /* Allocate hardware IRQ controller */
5352 ppc6xx_irq_init(ppc_env_get_cpu(env));
5353 }
5354
5355 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5356 {
5357 DeviceClass *dc = DEVICE_CLASS(oc);
5358 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5359
5360 dc->desc = "PowerPC 602";
5361 pcc->init_proc = init_proc_602;
5362 pcc->check_pow = check_pow_hid0;
5363 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5364 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5365 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5366 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5367 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5368 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5369 PPC_SEGMENT | PPC_602_SPEC;
5370 pcc->msr_mask = (1ull << MSR_VSX) |
5371 (1ull << MSR_SA) |
5372 (1ull << MSR_POW) |
5373 (1ull << MSR_TGPR) |
5374 (1ull << MSR_ILE) |
5375 (1ull << MSR_EE) |
5376 (1ull << MSR_PR) |
5377 (1ull << MSR_FP) |
5378 (1ull << MSR_ME) |
5379 (1ull << MSR_FE0) |
5380 (1ull << MSR_SE) |
5381 (1ull << MSR_DE) |
5382 (1ull << MSR_FE1) |
5383 (1ull << MSR_EP) |
5384 (1ull << MSR_IR) |
5385 (1ull << MSR_DR) |
5386 (1ull << MSR_RI) |
5387 (1ull << MSR_LE);
5388 /* XXX: 602 MMU is quite specific. Should add a special case */
5389 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5390 pcc->excp_model = POWERPC_EXCP_602;
5391 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5392 pcc->bfd_mach = bfd_mach_ppc_602;
5393 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5394 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5395 }
5396
5397 static void init_proc_603(CPUPPCState *env)
5398 {
5399 gen_spr_ne_601(env);
5400 gen_spr_sdr1(env);
5401 gen_spr_603(env);
5402 /* Time base */
5403 gen_tbl(env);
5404 /* hardware implementation registers */
5405 /* XXX : not implemented */
5406 spr_register(env, SPR_HID0, "HID0",
5407 SPR_NOACCESS, SPR_NOACCESS,
5408 &spr_read_generic, &spr_write_generic,
5409 0x00000000);
5410 /* XXX : not implemented */
5411 spr_register(env, SPR_HID1, "HID1",
5412 SPR_NOACCESS, SPR_NOACCESS,
5413 &spr_read_generic, &spr_write_generic,
5414 0x00000000);
5415 /* Memory management */
5416 gen_low_BATs(env);
5417 gen_6xx_7xx_soft_tlb(env, 64, 2);
5418 init_excp_603(env);
5419 env->dcache_line_size = 32;
5420 env->icache_line_size = 32;
5421 /* Allocate hardware IRQ controller */
5422 ppc6xx_irq_init(ppc_env_get_cpu(env));
5423 }
5424
5425 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5426 {
5427 DeviceClass *dc = DEVICE_CLASS(oc);
5428 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5429
5430 dc->desc = "PowerPC 603";
5431 pcc->init_proc = init_proc_603;
5432 pcc->check_pow = check_pow_hid0;
5433 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5434 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5435 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5436 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5437 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5438 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5439 PPC_SEGMENT | PPC_EXTERN;
5440 pcc->msr_mask = (1ull << MSR_POW) |
5441 (1ull << MSR_TGPR) |
5442 (1ull << MSR_ILE) |
5443 (1ull << MSR_EE) |
5444 (1ull << MSR_PR) |
5445 (1ull << MSR_FP) |
5446 (1ull << MSR_ME) |
5447 (1ull << MSR_FE0) |
5448 (1ull << MSR_SE) |
5449 (1ull << MSR_DE) |
5450 (1ull << MSR_FE1) |
5451 (1ull << MSR_EP) |
5452 (1ull << MSR_IR) |
5453 (1ull << MSR_DR) |
5454 (1ull << MSR_RI) |
5455 (1ull << MSR_LE);
5456 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5457 pcc->excp_model = POWERPC_EXCP_603;
5458 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5459 pcc->bfd_mach = bfd_mach_ppc_603;
5460 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5461 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5462 }
5463
5464 static void init_proc_603E(CPUPPCState *env)
5465 {
5466 gen_spr_ne_601(env);
5467 gen_spr_sdr1(env);
5468 gen_spr_603(env);
5469 /* Time base */
5470 gen_tbl(env);
5471 /* hardware implementation registers */
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_HID0, "HID0",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* XXX : not implemented */
5478 spr_register(env, SPR_HID1, "HID1",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* Memory management */
5483 gen_low_BATs(env);
5484 gen_6xx_7xx_soft_tlb(env, 64, 2);
5485 init_excp_603(env);
5486 env->dcache_line_size = 32;
5487 env->icache_line_size = 32;
5488 /* Allocate hardware IRQ controller */
5489 ppc6xx_irq_init(ppc_env_get_cpu(env));
5490 }
5491
5492 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5493 {
5494 DeviceClass *dc = DEVICE_CLASS(oc);
5495 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5496
5497 dc->desc = "PowerPC 603e";
5498 pcc->init_proc = init_proc_603E;
5499 pcc->check_pow = check_pow_hid0;
5500 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5501 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5502 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5503 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5504 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5505 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5506 PPC_SEGMENT | PPC_EXTERN;
5507 pcc->msr_mask = (1ull << MSR_POW) |
5508 (1ull << MSR_TGPR) |
5509 (1ull << MSR_ILE) |
5510 (1ull << MSR_EE) |
5511 (1ull << MSR_PR) |
5512 (1ull << MSR_FP) |
5513 (1ull << MSR_ME) |
5514 (1ull << MSR_FE0) |
5515 (1ull << MSR_SE) |
5516 (1ull << MSR_DE) |
5517 (1ull << MSR_FE1) |
5518 (1ull << MSR_EP) |
5519 (1ull << MSR_IR) |
5520 (1ull << MSR_DR) |
5521 (1ull << MSR_RI) |
5522 (1ull << MSR_LE);
5523 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5524 pcc->excp_model = POWERPC_EXCP_603E;
5525 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5526 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5527 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5528 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5529 }
5530
5531 static void init_proc_604(CPUPPCState *env)
5532 {
5533 gen_spr_ne_601(env);
5534 gen_spr_sdr1(env);
5535 gen_spr_604(env);
5536 /* Time base */
5537 gen_tbl(env);
5538 /* Hardware implementation registers */
5539 /* XXX : not implemented */
5540 spr_register(env, SPR_HID0, "HID0",
5541 SPR_NOACCESS, SPR_NOACCESS,
5542 &spr_read_generic, &spr_write_generic,
5543 0x00000000);
5544 /* Memory management */
5545 gen_low_BATs(env);
5546 init_excp_604(env);
5547 env->dcache_line_size = 32;
5548 env->icache_line_size = 32;
5549 /* Allocate hardware IRQ controller */
5550 ppc6xx_irq_init(ppc_env_get_cpu(env));
5551 }
5552
5553 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5554 {
5555 DeviceClass *dc = DEVICE_CLASS(oc);
5556 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5557
5558 dc->desc = "PowerPC 604";
5559 pcc->init_proc = init_proc_604;
5560 pcc->check_pow = check_pow_nocheck;
5561 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5562 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5563 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5564 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5565 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5566 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5567 PPC_SEGMENT | PPC_EXTERN;
5568 pcc->msr_mask = (1ull << MSR_POW) |
5569 (1ull << MSR_ILE) |
5570 (1ull << MSR_EE) |
5571 (1ull << MSR_PR) |
5572 (1ull << MSR_FP) |
5573 (1ull << MSR_ME) |
5574 (1ull << MSR_FE0) |
5575 (1ull << MSR_SE) |
5576 (1ull << MSR_DE) |
5577 (1ull << MSR_FE1) |
5578 (1ull << MSR_EP) |
5579 (1ull << MSR_IR) |
5580 (1ull << MSR_DR) |
5581 (1ull << MSR_PMM) |
5582 (1ull << MSR_RI) |
5583 (1ull << MSR_LE);
5584 pcc->mmu_model = POWERPC_MMU_32B;
5585 #if defined(CONFIG_SOFTMMU)
5586 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5587 #endif
5588 pcc->excp_model = POWERPC_EXCP_604;
5589 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5590 pcc->bfd_mach = bfd_mach_ppc_604;
5591 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5592 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5593 }
5594
5595 static void init_proc_604E(CPUPPCState *env)
5596 {
5597 gen_spr_ne_601(env);
5598 gen_spr_sdr1(env);
5599 gen_spr_604(env);
5600 /* XXX : not implemented */
5601 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5602 SPR_NOACCESS, SPR_NOACCESS,
5603 &spr_read_generic, &spr_write_generic,
5604 0x00000000);
5605 /* XXX : not implemented */
5606 spr_register(env, SPR_7XX_PMC3, "PMC3",
5607 SPR_NOACCESS, SPR_NOACCESS,
5608 &spr_read_generic, &spr_write_generic,
5609 0x00000000);
5610 /* XXX : not implemented */
5611 spr_register(env, SPR_7XX_PMC4, "PMC4",
5612 SPR_NOACCESS, SPR_NOACCESS,
5613 &spr_read_generic, &spr_write_generic,
5614 0x00000000);
5615 /* Time base */
5616 gen_tbl(env);
5617 /* Hardware implementation registers */
5618 /* XXX : not implemented */
5619 spr_register(env, SPR_HID0, "HID0",
5620 SPR_NOACCESS, SPR_NOACCESS,
5621 &spr_read_generic, &spr_write_generic,
5622 0x00000000);
5623 /* XXX : not implemented */
5624 spr_register(env, SPR_HID1, "HID1",
5625 SPR_NOACCESS, SPR_NOACCESS,
5626 &spr_read_generic, &spr_write_generic,
5627 0x00000000);
5628 /* Memory management */
5629 gen_low_BATs(env);
5630 init_excp_604(env);
5631 env->dcache_line_size = 32;
5632 env->icache_line_size = 32;
5633 /* Allocate hardware IRQ controller */
5634 ppc6xx_irq_init(ppc_env_get_cpu(env));
5635 }
5636
5637 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5638 {
5639 DeviceClass *dc = DEVICE_CLASS(oc);
5640 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5641
5642 dc->desc = "PowerPC 604E";
5643 pcc->init_proc = init_proc_604E;
5644 pcc->check_pow = check_pow_nocheck;
5645 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5646 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5647 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5648 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5649 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5650 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5651 PPC_SEGMENT | PPC_EXTERN;
5652 pcc->msr_mask = (1ull << MSR_POW) |
5653 (1ull << MSR_ILE) |
5654 (1ull << MSR_EE) |
5655 (1ull << MSR_PR) |
5656 (1ull << MSR_FP) |
5657 (1ull << MSR_ME) |
5658 (1ull << MSR_FE0) |
5659 (1ull << MSR_SE) |
5660 (1ull << MSR_DE) |
5661 (1ull << MSR_FE1) |
5662 (1ull << MSR_EP) |
5663 (1ull << MSR_IR) |
5664 (1ull << MSR_DR) |
5665 (1ull << MSR_PMM) |
5666 (1ull << MSR_RI) |
5667 (1ull << MSR_LE);
5668 pcc->mmu_model = POWERPC_MMU_32B;
5669 #if defined(CONFIG_SOFTMMU)
5670 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5671 #endif
5672 pcc->excp_model = POWERPC_EXCP_604;
5673 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5674 pcc->bfd_mach = bfd_mach_ppc_604;
5675 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5676 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5677 }
5678
5679 static void init_proc_740(CPUPPCState *env)
5680 {
5681 gen_spr_ne_601(env);
5682 gen_spr_sdr1(env);
5683 gen_spr_7xx(env);
5684 /* Time base */
5685 gen_tbl(env);
5686 /* Thermal management */
5687 gen_spr_thrm(env);
5688 /* Hardware implementation registers */
5689 /* XXX : not implemented */
5690 spr_register(env, SPR_HID0, "HID0",
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 &spr_read_generic, &spr_write_generic,
5693 0x00000000);
5694 /* XXX : not implemented */
5695 spr_register(env, SPR_HID1, "HID1",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_read_generic, &spr_write_generic,
5698 0x00000000);
5699 /* Memory management */
5700 gen_low_BATs(env);
5701 init_excp_7x0(env);
5702 env->dcache_line_size = 32;
5703 env->icache_line_size = 32;
5704 /* Allocate hardware IRQ controller */
5705 ppc6xx_irq_init(ppc_env_get_cpu(env));
5706 }
5707
5708 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5709 {
5710 DeviceClass *dc = DEVICE_CLASS(oc);
5711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5712
5713 dc->desc = "PowerPC 740";
5714 pcc->init_proc = init_proc_740;
5715 pcc->check_pow = check_pow_hid0;
5716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5718 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5719 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5720 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5721 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5722 PPC_SEGMENT | PPC_EXTERN;
5723 pcc->msr_mask = (1ull << MSR_POW) |
5724 (1ull << MSR_ILE) |
5725 (1ull << MSR_EE) |
5726 (1ull << MSR_PR) |
5727 (1ull << MSR_FP) |
5728 (1ull << MSR_ME) |
5729 (1ull << MSR_FE0) |
5730 (1ull << MSR_SE) |
5731 (1ull << MSR_DE) |
5732 (1ull << MSR_FE1) |
5733 (1ull << MSR_EP) |
5734 (1ull << MSR_IR) |
5735 (1ull << MSR_DR) |
5736 (1ull << MSR_PMM) |
5737 (1ull << MSR_RI) |
5738 (1ull << MSR_LE);
5739 pcc->mmu_model = POWERPC_MMU_32B;
5740 #if defined(CONFIG_SOFTMMU)
5741 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5742 #endif
5743 pcc->excp_model = POWERPC_EXCP_7x0;
5744 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5745 pcc->bfd_mach = bfd_mach_ppc_750;
5746 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5747 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5748 }
5749
5750 static void init_proc_750(CPUPPCState *env)
5751 {
5752 gen_spr_ne_601(env);
5753 gen_spr_sdr1(env);
5754 gen_spr_7xx(env);
5755 /* XXX : not implemented */
5756 spr_register(env, SPR_L2CR, "L2CR",
5757 SPR_NOACCESS, SPR_NOACCESS,
5758 &spr_read_generic, spr_access_nop,
5759 0x00000000);
5760 /* Time base */
5761 gen_tbl(env);
5762 /* Thermal management */
5763 gen_spr_thrm(env);
5764 /* Hardware implementation registers */
5765 /* XXX : not implemented */
5766 spr_register(env, SPR_HID0, "HID0",
5767 SPR_NOACCESS, SPR_NOACCESS,
5768 &spr_read_generic, &spr_write_generic,
5769 0x00000000);
5770 /* XXX : not implemented */
5771 spr_register(env, SPR_HID1, "HID1",
5772 SPR_NOACCESS, SPR_NOACCESS,
5773 &spr_read_generic, &spr_write_generic,
5774 0x00000000);
5775 /* Memory management */
5776 gen_low_BATs(env);
5777 /* XXX: high BATs are also present but are known to be bugged on
5778 * die version 1.x
5779 */
5780 init_excp_7x0(env);
5781 env->dcache_line_size = 32;
5782 env->icache_line_size = 32;
5783 /* Allocate hardware IRQ controller */
5784 ppc6xx_irq_init(ppc_env_get_cpu(env));
5785 }
5786
5787 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5788 {
5789 DeviceClass *dc = DEVICE_CLASS(oc);
5790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5791
5792 dc->desc = "PowerPC 750";
5793 pcc->init_proc = init_proc_750;
5794 pcc->check_pow = check_pow_hid0;
5795 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5796 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5797 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5798 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5799 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5800 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5801 PPC_SEGMENT | PPC_EXTERN;
5802 pcc->msr_mask = (1ull << MSR_POW) |
5803 (1ull << MSR_ILE) |
5804 (1ull << MSR_EE) |
5805 (1ull << MSR_PR) |
5806 (1ull << MSR_FP) |
5807 (1ull << MSR_ME) |
5808 (1ull << MSR_FE0) |
5809 (1ull << MSR_SE) |
5810 (1ull << MSR_DE) |
5811 (1ull << MSR_FE1) |
5812 (1ull << MSR_EP) |
5813 (1ull << MSR_IR) |
5814 (1ull << MSR_DR) |
5815 (1ull << MSR_PMM) |
5816 (1ull << MSR_RI) |
5817 (1ull << MSR_LE);
5818 pcc->mmu_model = POWERPC_MMU_32B;
5819 #if defined(CONFIG_SOFTMMU)
5820 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5821 #endif
5822 pcc->excp_model = POWERPC_EXCP_7x0;
5823 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5824 pcc->bfd_mach = bfd_mach_ppc_750;
5825 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5826 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5827 }
5828
5829 static void init_proc_750cl(CPUPPCState *env)
5830 {
5831 gen_spr_ne_601(env);
5832 gen_spr_sdr1(env);
5833 gen_spr_7xx(env);
5834 /* XXX : not implemented */
5835 spr_register(env, SPR_L2CR, "L2CR",
5836 SPR_NOACCESS, SPR_NOACCESS,
5837 &spr_read_generic, spr_access_nop,
5838 0x00000000);
5839 /* Time base */
5840 gen_tbl(env);
5841 /* Thermal management */
5842 /* Those registers are fake on 750CL */
5843 spr_register(env, SPR_THRM1, "THRM1",
5844 SPR_NOACCESS, SPR_NOACCESS,
5845 &spr_read_generic, &spr_write_generic,
5846 0x00000000);
5847 spr_register(env, SPR_THRM2, "THRM2",
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_generic,
5850 0x00000000);
5851 spr_register(env, SPR_THRM3, "THRM3",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 &spr_read_generic, &spr_write_generic,
5854 0x00000000);
5855 /* XXX: not implemented */
5856 spr_register(env, SPR_750_TDCL, "TDCL",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 spr_register(env, SPR_750_TDCH, "TDCH",
5861 SPR_NOACCESS, SPR_NOACCESS,
5862 &spr_read_generic, &spr_write_generic,
5863 0x00000000);
5864 /* DMA */
5865 /* XXX : not implemented */
5866 spr_register(env, SPR_750_WPAR, "WPAR",
5867 SPR_NOACCESS, SPR_NOACCESS,
5868 &spr_read_generic, &spr_write_generic,
5869 0x00000000);
5870 spr_register(env, SPR_750_DMAL, "DMAL",
5871 SPR_NOACCESS, SPR_NOACCESS,
5872 &spr_read_generic, &spr_write_generic,
5873 0x00000000);
5874 spr_register(env, SPR_750_DMAU, "DMAU",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 /* Hardware implementation registers */
5879 /* XXX : not implemented */
5880 spr_register(env, SPR_HID0, "HID0",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, &spr_write_generic,
5883 0x00000000);
5884 /* XXX : not implemented */
5885 spr_register(env, SPR_HID1, "HID1",
5886 SPR_NOACCESS, SPR_NOACCESS,
5887 &spr_read_generic, &spr_write_generic,
5888 0x00000000);
5889 /* XXX : not implemented */
5890 spr_register(env, SPR_750CL_HID2, "HID2",
5891 SPR_NOACCESS, SPR_NOACCESS,
5892 &spr_read_generic, &spr_write_generic,
5893 0x00000000);
5894 /* XXX : not implemented */
5895 spr_register(env, SPR_750CL_HID4, "HID4",
5896 SPR_NOACCESS, SPR_NOACCESS,
5897 &spr_read_generic, &spr_write_generic,
5898 0x00000000);
5899 /* Quantization registers */
5900 /* XXX : not implemented */
5901 spr_register(env, SPR_750_GQR0, "GQR0",
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 &spr_read_generic, &spr_write_generic,
5904 0x00000000);
5905 /* XXX : not implemented */
5906 spr_register(env, SPR_750_GQR1, "GQR1",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 0x00000000);
5910 /* XXX : not implemented */
5911 spr_register(env, SPR_750_GQR2, "GQR2",
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_generic,
5914 0x00000000);
5915 /* XXX : not implemented */
5916 spr_register(env, SPR_750_GQR3, "GQR3",
5917 SPR_NOACCESS, SPR_NOACCESS,
5918 &spr_read_generic, &spr_write_generic,
5919 0x00000000);
5920 /* XXX : not implemented */
5921 spr_register(env, SPR_750_GQR4, "GQR4",
5922 SPR_NOACCESS, SPR_NOACCESS,
5923 &spr_read_generic, &spr_write_generic,
5924 0x00000000);
5925 /* XXX : not implemented */
5926 spr_register(env, SPR_750_GQR5, "GQR5",
5927 SPR_NOACCESS, SPR_NOACCESS,
5928 &spr_read_generic, &spr_write_generic,
5929 0x00000000);
5930 /* XXX : not implemented */
5931 spr_register(env, SPR_750_GQR6, "GQR6",
5932 SPR_NOACCESS, SPR_NOACCESS,
5933 &spr_read_generic, &spr_write_generic,
5934 0x00000000);
5935 /* XXX : not implemented */
5936 spr_register(env, SPR_750_GQR7, "GQR7",
5937 SPR_NOACCESS, SPR_NOACCESS,
5938 &spr_read_generic, &spr_write_generic,
5939 0x00000000);
5940 /* Memory management */
5941 gen_low_BATs(env);
5942 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5943 gen_high_BATs(env);
5944 init_excp_750cl(env);
5945 env->dcache_line_size = 32;
5946 env->icache_line_size = 32;
5947 /* Allocate hardware IRQ controller */
5948 ppc6xx_irq_init(ppc_env_get_cpu(env));
5949 }
5950
5951 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5952 {
5953 DeviceClass *dc = DEVICE_CLASS(oc);
5954 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5955
5956 dc->desc = "PowerPC 750 CL";
5957 pcc->init_proc = init_proc_750cl;
5958 pcc->check_pow = check_pow_hid0;
5959 /* XXX: not implemented:
5960 * cache lock instructions:
5961 * dcbz_l
5962 * floating point paired instructions
5963 * psq_lux
5964 * psq_lx
5965 * psq_stux
5966 * psq_stx
5967 * ps_abs
5968 * ps_add
5969 * ps_cmpo0
5970 * ps_cmpo1
5971 * ps_cmpu0
5972 * ps_cmpu1
5973 * ps_div
5974 * ps_madd
5975 * ps_madds0
5976 * ps_madds1
5977 * ps_merge00
5978 * ps_merge01
5979 * ps_merge10
5980 * ps_merge11
5981 * ps_mr
5982 * ps_msub
5983 * ps_mul
5984 * ps_muls0
5985 * ps_muls1
5986 * ps_nabs
5987 * ps_neg
5988 * ps_nmadd
5989 * ps_nmsub
5990 * ps_res
5991 * ps_rsqrte
5992 * ps_sel
5993 * ps_sub
5994 * ps_sum0
5995 * ps_sum1
5996 */
5997 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5998 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5999 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6000 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6001 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6002 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6003 PPC_SEGMENT | PPC_EXTERN;
6004 pcc->msr_mask = (1ull << MSR_POW) |
6005 (1ull << MSR_ILE) |
6006 (1ull << MSR_EE) |
6007 (1ull << MSR_PR) |
6008 (1ull << MSR_FP) |
6009 (1ull << MSR_ME) |
6010 (1ull << MSR_FE0) |
6011 (1ull << MSR_SE) |
6012 (1ull << MSR_DE) |
6013 (1ull << MSR_FE1) |
6014 (1ull << MSR_EP) |
6015 (1ull << MSR_IR) |
6016 (1ull << MSR_DR) |
6017 (1ull << MSR_PMM) |
6018 (1ull << MSR_RI) |
6019 (1ull << MSR_LE);
6020 pcc->mmu_model = POWERPC_MMU_32B;
6021 #if defined(CONFIG_SOFTMMU)
6022 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6023 #endif
6024 pcc->excp_model = POWERPC_EXCP_7x0;
6025 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6026 pcc->bfd_mach = bfd_mach_ppc_750;
6027 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6028 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6029 }
6030
6031 static void init_proc_750cx(CPUPPCState *env)
6032 {
6033 gen_spr_ne_601(env);
6034 gen_spr_sdr1(env);
6035 gen_spr_7xx(env);
6036 /* XXX : not implemented */
6037 spr_register(env, SPR_L2CR, "L2CR",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_generic, spr_access_nop,
6040 0x00000000);
6041 /* Time base */
6042 gen_tbl(env);
6043 /* Thermal management */
6044 gen_spr_thrm(env);
6045 /* This register is not implemented but is present for compatibility */
6046 spr_register(env, SPR_SDA, "SDA",
6047 SPR_NOACCESS, SPR_NOACCESS,
6048 &spr_read_generic, &spr_write_generic,
6049 0x00000000);
6050 /* Hardware implementation registers */
6051 /* XXX : not implemented */
6052 spr_register(env, SPR_HID0, "HID0",
6053 SPR_NOACCESS, SPR_NOACCESS,
6054 &spr_read_generic, &spr_write_generic,
6055 0x00000000);
6056 /* XXX : not implemented */
6057 spr_register(env, SPR_HID1, "HID1",
6058 SPR_NOACCESS, SPR_NOACCESS,
6059 &spr_read_generic, &spr_write_generic,
6060 0x00000000);
6061 /* Memory management */
6062 gen_low_BATs(env);
6063 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6064 gen_high_BATs(env);
6065 init_excp_750cx(env);
6066 env->dcache_line_size = 32;
6067 env->icache_line_size = 32;
6068 /* Allocate hardware IRQ controller */
6069 ppc6xx_irq_init(ppc_env_get_cpu(env));
6070 }
6071
6072 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6073 {
6074 DeviceClass *dc = DEVICE_CLASS(oc);
6075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6076
6077 dc->desc = "PowerPC 750CX";
6078 pcc->init_proc = init_proc_750cx;
6079 pcc->check_pow = check_pow_hid0;
6080 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6081 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6082 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6083 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6084 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6085 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6086 PPC_SEGMENT | PPC_EXTERN;
6087 pcc->msr_mask = (1ull << MSR_POW) |
6088 (1ull << MSR_ILE) |
6089 (1ull << MSR_EE) |
6090 (1ull << MSR_PR) |
6091 (1ull << MSR_FP) |
6092 (1ull << MSR_ME) |
6093 (1ull << MSR_FE0) |
6094 (1ull << MSR_SE) |
6095 (1ull << MSR_DE) |
6096 (1ull << MSR_FE1) |
6097 (1ull << MSR_EP) |
6098 (1ull << MSR_IR) |
6099 (1ull << MSR_DR) |
6100 (1ull << MSR_PMM) |
6101 (1ull << MSR_RI) |
6102 (1ull << MSR_LE);
6103 pcc->mmu_model = POWERPC_MMU_32B;
6104 #if defined(CONFIG_SOFTMMU)
6105 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6106 #endif
6107 pcc->excp_model = POWERPC_EXCP_7x0;
6108 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6109 pcc->bfd_mach = bfd_mach_ppc_750;
6110 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6111 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6112 }
6113
6114 static void init_proc_750fx(CPUPPCState *env)
6115 {
6116 gen_spr_ne_601(env);
6117 gen_spr_sdr1(env);
6118 gen_spr_7xx(env);
6119 /* XXX : not implemented */
6120 spr_register(env, SPR_L2CR, "L2CR",
6121 SPR_NOACCESS, SPR_NOACCESS,
6122 &spr_read_generic, spr_access_nop,
6123 0x00000000);
6124 /* Time base */
6125 gen_tbl(env);
6126 /* Thermal management */
6127 gen_spr_thrm(env);
6128 /* XXX : not implemented */
6129 spr_register(env, SPR_750_THRM4, "THRM4",
6130 SPR_NOACCESS, SPR_NOACCESS,
6131 &spr_read_generic, &spr_write_generic,
6132 0x00000000);
6133 /* Hardware implementation registers */
6134 /* XXX : not implemented */
6135 spr_register(env, SPR_HID0, "HID0",
6136 SPR_NOACCESS, SPR_NOACCESS,
6137 &spr_read_generic, &spr_write_generic,
6138 0x00000000);
6139 /* XXX : not implemented */
6140 spr_register(env, SPR_HID1, "HID1",
6141 SPR_NOACCESS, SPR_NOACCESS,
6142 &spr_read_generic, &spr_write_generic,
6143 0x00000000);
6144 /* XXX : not implemented */
6145 spr_register(env, SPR_750FX_HID2, "HID2",
6146 SPR_NOACCESS, SPR_NOACCESS,
6147 &spr_read_generic, &spr_write_generic,
6148 0x00000000);
6149 /* Memory management */
6150 gen_low_BATs(env);
6151 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6152 gen_high_BATs(env);
6153 init_excp_7x0(env);
6154 env->dcache_line_size = 32;
6155 env->icache_line_size = 32;
6156 /* Allocate hardware IRQ controller */
6157 ppc6xx_irq_init(ppc_env_get_cpu(env));
6158 }
6159
6160 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6161 {
6162 DeviceClass *dc = DEVICE_CLASS(oc);
6163 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6164
6165 dc->desc = "PowerPC 750FX";
6166 pcc->init_proc = init_proc_750fx;
6167 pcc->check_pow = check_pow_hid0;
6168 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6169 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6170 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6171 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6172 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6173 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6174 PPC_SEGMENT | PPC_EXTERN;
6175 pcc->msr_mask = (1ull << MSR_POW) |
6176 (1ull << MSR_ILE) |
6177 (1ull << MSR_EE) |
6178 (1ull << MSR_PR) |
6179 (1ull << MSR_FP) |
6180 (1ull << MSR_ME) |
6181 (1ull << MSR_FE0) |
6182 (1ull << MSR_SE) |
6183 (1ull << MSR_DE) |
6184 (1ull << MSR_FE1) |
6185 (1ull << MSR_EP) |
6186 (1ull << MSR_IR) |
6187 (1ull << MSR_DR) |
6188 (1ull << MSR_PMM) |
6189 (1ull << MSR_RI) |
6190 (1ull << MSR_LE);
6191 pcc->mmu_model = POWERPC_MMU_32B;
6192 #if defined(CONFIG_SOFTMMU)
6193 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6194 #endif
6195 pcc->excp_model = POWERPC_EXCP_7x0;
6196 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6197 pcc->bfd_mach = bfd_mach_ppc_750;
6198 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6199 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6200 }
6201
6202 static void init_proc_750gx(CPUPPCState *env)
6203 {
6204 gen_spr_ne_601(env);
6205 gen_spr_sdr1(env);
6206 gen_spr_7xx(env);
6207 /* XXX : not implemented (XXX: different from 750fx) */
6208 spr_register(env, SPR_L2CR, "L2CR",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 &spr_read_generic, spr_access_nop,
6211 0x00000000);
6212 /* Time base */
6213 gen_tbl(env);
6214 /* Thermal management */
6215 gen_spr_thrm(env);
6216 /* XXX : not implemented */
6217 spr_register(env, SPR_750_THRM4, "THRM4",
6218 SPR_NOACCESS, SPR_NOACCESS,
6219 &spr_read_generic, &spr_write_generic,
6220 0x00000000);
6221 /* Hardware implementation registers */
6222 /* XXX : not implemented (XXX: different from 750fx) */
6223 spr_register(env, SPR_HID0, "HID0",
6224 SPR_NOACCESS, SPR_NOACCESS,
6225 &spr_read_generic, &spr_write_generic,
6226 0x00000000);
6227 /* XXX : not implemented */
6228 spr_register(env, SPR_HID1, "HID1",
6229 SPR_NOACCESS, SPR_NOACCESS,
6230 &spr_read_generic, &spr_write_generic,
6231 0x00000000);
6232 /* XXX : not implemented (XXX: different from 750fx) */
6233 spr_register(env, SPR_750FX_HID2, "HID2",
6234 SPR_NOACCESS, SPR_NOACCESS,
6235 &spr_read_generic, &spr_write_generic,
6236 0x00000000);
6237 /* Memory management */
6238 gen_low_BATs(env);
6239 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6240 gen_high_BATs(env);
6241 init_excp_7x0(env);
6242 env->dcache_line_size = 32;
6243 env->icache_line_size = 32;
6244 /* Allocate hardware IRQ controller */
6245 ppc6xx_irq_init(ppc_env_get_cpu(env));
6246 }
6247
6248 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6249 {
6250 DeviceClass *dc = DEVICE_CLASS(oc);
6251 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6252
6253 dc->desc = "PowerPC 750GX";
6254 pcc->init_proc = init_proc_750gx;
6255 pcc->check_pow = check_pow_hid0;
6256 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6257 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6258 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6259 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6260 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6261 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6262 PPC_SEGMENT | PPC_EXTERN;
6263 pcc->msr_mask = (1ull << MSR_POW) |
6264 (1ull << MSR_ILE) |
6265 (1ull << MSR_EE) |
6266 (1ull << MSR_PR) |
6267 (1ull << MSR_FP) |
6268 (1ull << MSR_ME) |
6269 (1ull << MSR_FE0) |
6270 (1ull << MSR_SE) |
6271 (1ull << MSR_DE) |
6272 (1ull << MSR_FE1) |
6273 (1ull << MSR_EP) |
6274 (1ull << MSR_IR) |
6275 (1ull << MSR_DR) |
6276 (1ull << MSR_PMM) |
6277 (1ull << MSR_RI) |
6278 (1ull << MSR_LE);
6279 pcc->mmu_model = POWERPC_MMU_32B;
6280 #if defined(CONFIG_SOFTMMU)
6281 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6282 #endif
6283 pcc->excp_model = POWERPC_EXCP_7x0;
6284 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6285 pcc->bfd_mach = bfd_mach_ppc_750;
6286 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6287 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6288 }
6289
6290 static void init_proc_745(CPUPPCState *env)
6291 {
6292 gen_spr_ne_601(env);
6293 gen_spr_sdr1(env);
6294 gen_spr_7xx(env);
6295 gen_spr_G2_755(env);
6296 /* Time base */
6297 gen_tbl(env);
6298 /* Thermal management */
6299 gen_spr_thrm(env);
6300 /* Hardware implementation registers */
6301 /* XXX : not implemented */
6302 spr_register(env, SPR_HID0, "HID0",
6303 SPR_NOACCESS, SPR_NOACCESS,
6304 &spr_read_generic, &spr_write_generic,
6305 0x00000000);
6306 /* XXX : not implemented */
6307 spr_register(env, SPR_HID1, "HID1",
6308 SPR_NOACCESS, SPR_NOACCESS,
6309 &spr_read_generic, &spr_write_generic,
6310 0x00000000);
6311 /* XXX : not implemented */
6312 spr_register(env, SPR_HID2, "HID2",
6313 SPR_NOACCESS, SPR_NOACCESS,
6314 &spr_read_generic, &spr_write_generic,
6315 0x00000000);
6316 /* Memory management */
6317 gen_low_BATs(env);
6318 gen_high_BATs(env);
6319 gen_6xx_7xx_soft_tlb(env, 64, 2);
6320 init_excp_7x5(env);
6321 env->dcache_line_size = 32;
6322 env->icache_line_size = 32;
6323 /* Allocate hardware IRQ controller */
6324 ppc6xx_irq_init(ppc_env_get_cpu(env));
6325 }
6326
6327 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6328 {
6329 DeviceClass *dc = DEVICE_CLASS(oc);
6330 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6331
6332 dc->desc = "PowerPC 745";
6333 pcc->init_proc = init_proc_745;
6334 pcc->check_pow = check_pow_hid0;
6335 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6336 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6337 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6338 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6339 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6340 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6341 PPC_SEGMENT | PPC_EXTERN;
6342 pcc->msr_mask = (1ull << MSR_POW) |
6343 (1ull << MSR_ILE) |
6344 (1ull << MSR_EE) |
6345 (1ull << MSR_PR) |
6346 (1ull << MSR_FP) |
6347 (1ull << MSR_ME) |
6348 (1ull << MSR_FE0) |
6349 (1ull << MSR_SE) |
6350 (1ull << MSR_DE) |
6351 (1ull << MSR_FE1) |
6352 (1ull << MSR_EP) |
6353 (1ull << MSR_IR) |
6354 (1ull << MSR_DR) |
6355 (1ull << MSR_PMM) |
6356 (1ull << MSR_RI) |
6357 (1ull << MSR_LE);
6358 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6359 pcc->excp_model = POWERPC_EXCP_7x5;
6360 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6361 pcc->bfd_mach = bfd_mach_ppc_750;
6362 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6363 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6364 }
6365
6366 static void init_proc_755(CPUPPCState *env)
6367 {
6368 gen_spr_ne_601(env);
6369 gen_spr_sdr1(env);
6370 gen_spr_7xx(env);
6371 gen_spr_G2_755(env);
6372 /* Time base */
6373 gen_tbl(env);
6374 /* L2 cache control */
6375 /* XXX : not implemented */
6376 spr_register(env, SPR_L2CR, "L2CR",
6377 SPR_NOACCESS, SPR_NOACCESS,
6378 &spr_read_generic, spr_access_nop,
6379 0x00000000);
6380 /* XXX : not implemented */
6381 spr_register(env, SPR_L2PMCR, "L2PMCR",
6382 SPR_NOACCESS, SPR_NOACCESS,
6383 &spr_read_generic, &spr_write_generic,
6384 0x00000000);
6385 /* Thermal management */
6386 gen_spr_thrm(env);
6387 /* Hardware implementation registers */
6388 /* XXX : not implemented */
6389 spr_register(env, SPR_HID0, "HID0",
6390 SPR_NOACCESS, SPR_NOACCESS,
6391 &spr_read_generic, &spr_write_generic,
6392 0x00000000);
6393 /* XXX : not implemented */
6394 spr_register(env, SPR_HID1, "HID1",
6395 SPR_NOACCESS, SPR_NOACCESS,
6396 &spr_read_generic, &spr_write_generic,
6397 0x00000000);
6398 /* XXX : not implemented */
6399 spr_register(env, SPR_HID2, "HID2",
6400 SPR_NOACCESS, SPR_NOACCESS,
6401 &spr_read_generic, &spr_write_generic,
6402 0x00000000);
6403 /* Memory management */
6404 gen_low_BATs(env);
6405 gen_high_BATs(env);
6406 gen_6xx_7xx_soft_tlb(env, 64, 2);
6407 init_excp_7x5(env);
6408 env->dcache_line_size = 32;
6409 env->icache_line_size = 32;
6410 /* Allocate hardware IRQ controller */
6411 ppc6xx_irq_init(ppc_env_get_cpu(env));
6412 }
6413
6414 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6415 {
6416 DeviceClass *dc = DEVICE_CLASS(oc);
6417 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6418
6419 dc->desc = "PowerPC 755";
6420 pcc->init_proc = init_proc_755;
6421 pcc->check_pow = check_pow_hid0;
6422 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6423 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6424 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6425 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6426 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6427 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6428 PPC_SEGMENT | PPC_EXTERN;
6429 pcc->msr_mask = (1ull << MSR_POW) |
6430 (1ull << MSR_ILE) |
6431 (1ull << MSR_EE) |
6432 (1ull << MSR_PR) |
6433 (1ull << MSR_FP) |
6434 (1ull << MSR_ME) |
6435 (1ull << MSR_FE0) |
6436 (1ull << MSR_SE) |
6437 (1ull << MSR_DE) |
6438 (1ull << MSR_FE1) |
6439 (1ull << MSR_EP) |
6440 (1ull << MSR_IR) |
6441 (1ull << MSR_DR) |
6442 (1ull << MSR_PMM) |
6443 (1ull << MSR_RI) |
6444 (1ull << MSR_LE);
6445 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6446 pcc->excp_model = POWERPC_EXCP_7x5;
6447 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6448 pcc->bfd_mach = bfd_mach_ppc_750;
6449 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6450 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6451 }
6452
6453 static void init_proc_7400(CPUPPCState *env)
6454 {
6455 gen_spr_ne_601(env);
6456 gen_spr_sdr1(env);
6457 gen_spr_7xx(env);
6458 /* Time base */
6459 gen_tbl(env);
6460 /* 74xx specific SPR */
6461 gen_spr_74xx(env);
6462 /* XXX : not implemented */
6463 spr_register(env, SPR_UBAMR, "UBAMR",
6464 &spr_read_ureg, SPR_NOACCESS,
6465 &spr_read_ureg, SPR_NOACCESS,
6466 0x00000000);
6467 /* XXX: this seems not implemented on all revisions. */
6468 /* XXX : not implemented */
6469 spr_register(env, SPR_MSSCR1, "MSSCR1",
6470 SPR_NOACCESS, SPR_NOACCESS,
6471 &spr_read_generic, &spr_write_generic,
6472 0x00000000);
6473 /* Thermal management */
6474 gen_spr_thrm(env);
6475 /* Memory management */
6476 gen_low_BATs(env);
6477 init_excp_7400(env);
6478 env->dcache_line_size = 32;
6479 env->icache_line_size = 32;
6480 /* Allocate hardware IRQ controller */
6481 ppc6xx_irq_init(ppc_env_get_cpu(env));
6482 }
6483
6484 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6485 {
6486 DeviceClass *dc = DEVICE_CLASS(oc);
6487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6488
6489 dc->desc = "PowerPC 7400 (aka G4)";
6490 pcc->init_proc = init_proc_7400;
6491 pcc->check_pow = check_pow_hid0;
6492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6493 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6495 PPC_FLOAT_STFIWX |
6496 PPC_CACHE | PPC_CACHE_ICBI |
6497 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6498 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6499 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6500 PPC_MEM_TLBIA |
6501 PPC_SEGMENT | PPC_EXTERN |
6502 PPC_ALTIVEC;
6503 pcc->msr_mask = (1ull << MSR_VR) |
6504 (1ull << MSR_POW) |
6505 (1ull << MSR_ILE) |
6506 (1ull << MSR_EE) |
6507 (1ull << MSR_PR) |
6508 (1ull << MSR_FP) |
6509 (1ull << MSR_ME) |
6510 (1ull << MSR_FE0) |
6511 (1ull << MSR_SE) |
6512 (1ull << MSR_DE) |
6513 (1ull << MSR_FE1) |
6514 (1ull << MSR_EP) |
6515 (1ull << MSR_IR) |
6516 (1ull << MSR_DR) |
6517 (1ull << MSR_PMM) |
6518 (1ull << MSR_RI) |
6519 (1ull << MSR_LE);
6520 pcc->mmu_model = POWERPC_MMU_32B;
6521 #if defined(CONFIG_SOFTMMU)
6522 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6523 #endif
6524 pcc->excp_model = POWERPC_EXCP_74xx;
6525 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6526 pcc->bfd_mach = bfd_mach_ppc_7400;
6527 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6528 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6529 POWERPC_FLAG_BUS_CLK;
6530 }
6531
6532 static void init_proc_7410(CPUPPCState *env)
6533 {
6534 gen_spr_ne_601(env);
6535 gen_spr_sdr1(env);
6536 gen_spr_7xx(env);
6537 /* Time base */
6538 gen_tbl(env);
6539 /* 74xx specific SPR */
6540 gen_spr_74xx(env);
6541 /* XXX : not implemented */
6542 spr_register(env, SPR_UBAMR, "UBAMR",
6543 &spr_read_ureg, SPR_NOACCESS,
6544 &spr_read_ureg, SPR_NOACCESS,
6545 0x00000000);
6546 /* Thermal management */
6547 gen_spr_thrm(env);
6548 /* L2PMCR */
6549 /* XXX : not implemented */
6550 spr_register(env, SPR_L2PMCR, "L2PMCR",
6551 SPR_NOACCESS, SPR_NOACCESS,
6552 &spr_read_generic, &spr_write_generic,
6553 0x00000000);
6554 /* LDSTDB */
6555 /* XXX : not implemented */
6556 spr_register(env, SPR_LDSTDB, "LDSTDB",
6557 SPR_NOACCESS, SPR_NOACCESS,
6558 &spr_read_generic, &spr_write_generic,
6559 0x00000000);
6560 /* Memory management */
6561 gen_low_BATs(env);
6562 init_excp_7400(env);
6563 env->dcache_line_size = 32;
6564 env->icache_line_size = 32;
6565 /* Allocate hardware IRQ controller */
6566 ppc6xx_irq_init(ppc_env_get_cpu(env));
6567 }
6568
6569 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6570 {
6571 DeviceClass *dc = DEVICE_CLASS(oc);
6572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6573
6574 dc->desc = "PowerPC 7410 (aka G4)";
6575 pcc->init_proc = init_proc_7410;
6576 pcc->check_pow = check_pow_hid0;
6577 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6579 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6580 PPC_FLOAT_STFIWX |
6581 PPC_CACHE | PPC_CACHE_ICBI |
6582 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6583 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6585 PPC_MEM_TLBIA |
6586 PPC_SEGMENT | PPC_EXTERN |
6587 PPC_ALTIVEC;
6588 pcc->msr_mask = (1ull << MSR_VR) |
6589 (1ull << MSR_POW) |
6590 (1ull << MSR_ILE) |
6591 (1ull << MSR_EE) |
6592 (1ull << MSR_PR) |
6593 (1ull << MSR_FP) |
6594 (1ull << MSR_ME) |
6595 (1ull << MSR_FE0) |
6596 (1ull << MSR_SE) |
6597 (1ull << MSR_DE) |
6598 (1ull << MSR_FE1) |
6599 (1ull << MSR_EP) |
6600 (1ull << MSR_IR) |
6601 (1ull << MSR_DR) |
6602 (1ull << MSR_PMM) |
6603 (1ull << MSR_RI) |
6604 (1ull << MSR_LE);
6605 pcc->mmu_model = POWERPC_MMU_32B;
6606 #if defined(CONFIG_SOFTMMU)
6607 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6608 #endif
6609 pcc->excp_model = POWERPC_EXCP_74xx;
6610 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6611 pcc->bfd_mach = bfd_mach_ppc_7400;
6612 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6613 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6614 POWERPC_FLAG_BUS_CLK;
6615 }
6616
6617 static void init_proc_7440(CPUPPCState *env)
6618 {
6619 gen_spr_ne_601(env);
6620 gen_spr_sdr1(env);
6621 gen_spr_7xx(env);
6622 /* Time base */
6623 gen_tbl(env);
6624 /* 74xx specific SPR */
6625 gen_spr_74xx(env);
6626 /* XXX : not implemented */
6627 spr_register(env, SPR_UBAMR, "UBAMR",
6628 &spr_read_ureg, SPR_NOACCESS,
6629 &spr_read_ureg, SPR_NOACCESS,
6630 0x00000000);
6631 /* LDSTCR */
6632 /* XXX : not implemented */
6633 spr_register(env, SPR_LDSTCR, "LDSTCR",
6634 SPR_NOACCESS, SPR_NOACCESS,
6635 &spr_read_generic, &spr_write_generic,
6636 0x00000000);
6637 /* ICTRL */
6638 /* XXX : not implemented */
6639 spr_register(env, SPR_ICTRL, "ICTRL",
6640 SPR_NOACCESS, SPR_NOACCESS,
6641 &spr_read_generic, &spr_write_generic,
6642 0x00000000);
6643 /* MSSSR0 */
6644 /* XXX : not implemented */
6645 spr_register(env, SPR_MSSSR0, "MSSSR0",
6646 SPR_NOACCESS, SPR_NOACCESS,
6647 &spr_read_generic, &spr_write_generic,
6648 0x00000000);
6649 /* PMC */
6650 /* XXX : not implemented */
6651 spr_register(env, SPR_7XX_PMC5, "PMC5",
6652 SPR_NOACCESS, SPR_NOACCESS,
6653 &spr_read_generic, &spr_write_generic,
6654 0x00000000);
6655 /* XXX : not implemented */
6656 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6657 &spr_read_ureg, SPR_NOACCESS,
6658 &spr_read_ureg, SPR_NOACCESS,
6659 0x00000000);
6660 /* XXX : not implemented */
6661 spr_register(env, SPR_7XX_PMC6, "PMC6",
6662 SPR_NOACCESS, SPR_NOACCESS,
6663 &spr_read_generic, &spr_write_generic,
6664 0x00000000);
6665 /* XXX : not implemented */
6666 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6667 &spr_read_ureg, SPR_NOACCESS,
6668 &spr_read_ureg, SPR_NOACCESS,
6669 0x00000000);
6670 /* Memory management */
6671 gen_low_BATs(env);
6672 gen_74xx_soft_tlb(env, 128, 2);
6673 init_excp_7450(env);
6674 env->dcache_line_size = 32;
6675 env->icache_line_size = 32;
6676 /* Allocate hardware IRQ controller */
6677 ppc6xx_irq_init(ppc_env_get_cpu(env));
6678 }
6679
6680 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6681 {
6682 DeviceClass *dc = DEVICE_CLASS(oc);
6683 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6684
6685 dc->desc = "PowerPC 7440 (aka G4)";
6686 pcc->init_proc = init_proc_7440;
6687 pcc->check_pow = check_pow_hid0_74xx;
6688 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6689 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6690 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6691 PPC_FLOAT_STFIWX |
6692 PPC_CACHE | PPC_CACHE_ICBI |
6693 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6694 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6695 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6696 PPC_MEM_TLBIA | PPC_74xx_TLB |
6697 PPC_SEGMENT | PPC_EXTERN |
6698 PPC_ALTIVEC;
6699 pcc->msr_mask = (1ull << MSR_VR) |
6700 (1ull << MSR_POW) |
6701 (1ull << MSR_ILE) |
6702 (1ull << MSR_EE) |
6703 (1ull << MSR_PR) |
6704 (1ull << MSR_FP) |
6705 (1ull << MSR_ME) |
6706 (1ull << MSR_FE0) |
6707 (1ull << MSR_SE) |
6708 (1ull << MSR_DE) |
6709 (1ull << MSR_FE1) |
6710 (1ull << MSR_EP) |
6711 (1ull << MSR_IR) |
6712 (1ull << MSR_DR) |
6713 (1ull << MSR_PMM) |
6714 (1ull << MSR_RI) |
6715 (1ull << MSR_LE);
6716 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6717 pcc->excp_model = POWERPC_EXCP_74xx;
6718 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6719 pcc->bfd_mach = bfd_mach_ppc_7400;
6720 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6721 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6722 POWERPC_FLAG_BUS_CLK;
6723 }
6724
6725 static void init_proc_7450(CPUPPCState *env)
6726 {
6727 gen_spr_ne_601(env);
6728 gen_spr_sdr1(env);
6729 gen_spr_7xx(env);
6730 /* Time base */
6731 gen_tbl(env);
6732 /* 74xx specific SPR */
6733 gen_spr_74xx(env);
6734 /* Level 3 cache control */
6735 gen_l3_ctrl(env);
6736 /* L3ITCR1 */
6737 /* XXX : not implemented */
6738 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6739 SPR_NOACCESS, SPR_NOACCESS,
6740 &spr_read_generic, &spr_write_generic,
6741 0x00000000);
6742 /* L3ITCR2 */
6743 /* XXX : not implemented */
6744 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6745 SPR_NOACCESS, SPR_NOACCESS,
6746 &spr_read_generic, &spr_write_generic,
6747 0x00000000);
6748 /* L3ITCR3 */
6749 /* XXX : not implemented */
6750 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6751 SPR_NOACCESS, SPR_NOACCESS,
6752 &spr_read_generic, &spr_write_generic,
6753 0x00000000);
6754 /* L3OHCR */
6755 /* XXX : not implemented */
6756 spr_register(env, SPR_L3OHCR, "L3OHCR",
6757 SPR_NOACCESS, SPR_NOACCESS,
6758 &spr_read_generic, &spr_write_generic,
6759 0x00000000);
6760 /* XXX : not implemented */
6761 spr_register(env, SPR_UBAMR, "UBAMR",
6762 &spr_read_ureg, SPR_NOACCESS,
6763 &spr_read_ureg, SPR_NOACCESS,
6764 0x00000000);
6765 /* LDSTCR */
6766 /* XXX : not implemented */
6767 spr_register(env, SPR_LDSTCR, "LDSTCR",
6768 SPR_NOACCESS, SPR_NOACCESS,
6769 &spr_read_generic, &spr_write_generic,
6770 0x00000000);
6771 /* ICTRL */
6772 /* XXX : not implemented */
6773 spr_register(env, SPR_ICTRL, "ICTRL",
6774 SPR_NOACCESS, SPR_NOACCESS,
6775 &spr_read_generic, &spr_write_generic,
6776 0x00000000);
6777 /* MSSSR0 */
6778 /* XXX : not implemented */
6779 spr_register(env, SPR_MSSSR0, "MSSSR0",
6780 SPR_NOACCESS, SPR_NOACCESS,
6781 &spr_read_generic, &spr_write_generic,
6782 0x00000000);
6783 /* PMC */
6784 /* XXX : not implemented */
6785 spr_register(env, SPR_7XX_PMC5, "PMC5",
6786 SPR_NOACCESS, SPR_NOACCESS,
6787 &spr_read_generic, &spr_write_generic,
6788 0x00000000);
6789 /* XXX : not implemented */
6790 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6791 &spr_read_ureg, SPR_NOACCESS,
6792 &spr_read_ureg, SPR_NOACCESS,
6793 0x00000000);
6794 /* XXX : not implemented */
6795 spr_register(env, SPR_7XX_PMC6, "PMC6",
6796 SPR_NOACCESS, SPR_NOACCESS,
6797 &spr_read_generic, &spr_write_generic,
6798 0x00000000);
6799 /* XXX : not implemented */
6800 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6801 &spr_read_ureg, SPR_NOACCESS,
6802 &spr_read_ureg, SPR_NOACCESS,
6803 0x00000000);
6804 /* Memory management */
6805 gen_low_BATs(env);
6806 gen_74xx_soft_tlb(env, 128, 2);
6807 init_excp_7450(env);
6808 env->dcache_line_size = 32;
6809 env->icache_line_size = 32;
6810 /* Allocate hardware IRQ controller */
6811 ppc6xx_irq_init(ppc_env_get_cpu(env));
6812 }
6813
6814 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6815 {
6816 DeviceClass *dc = DEVICE_CLASS(oc);
6817 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6818
6819 dc->desc = "PowerPC 7450 (aka G4)";
6820 pcc->init_proc = init_proc_7450;
6821 pcc->check_pow = check_pow_hid0_74xx;
6822 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6823 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6824 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6825 PPC_FLOAT_STFIWX |
6826 PPC_CACHE | PPC_CACHE_ICBI |
6827 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6828 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6829 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6830 PPC_MEM_TLBIA | PPC_74xx_TLB |
6831 PPC_SEGMENT | PPC_EXTERN |
6832 PPC_ALTIVEC;
6833 pcc->msr_mask = (1ull << MSR_VR) |
6834 (1ull << MSR_POW) |
6835 (1ull << MSR_ILE) |
6836 (1ull << MSR_EE) |
6837 (1ull << MSR_PR) |
6838 (1ull << MSR_FP) |
6839 (1ull << MSR_ME) |
6840 (1ull << MSR_FE0) |
6841 (1ull << MSR_SE) |
6842 (1ull << MSR_DE) |
6843 (1ull << MSR_FE1) |
6844 (1ull << MSR_EP) |
6845 (1ull << MSR_IR) |
6846 (1ull << MSR_DR) |
6847 (1ull << MSR_PMM) |
6848 (1ull << MSR_RI) |
6849 (1ull << MSR_LE);
6850 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6851 pcc->excp_model = POWERPC_EXCP_74xx;
6852 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6853 pcc->bfd_mach = bfd_mach_ppc_7400;
6854 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6855 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6856 POWERPC_FLAG_BUS_CLK;
6857 }
6858
6859 static void init_proc_7445(CPUPPCState *env)
6860 {
6861 gen_spr_ne_601(env);
6862 gen_spr_sdr1(env);
6863 gen_spr_7xx(env);
6864 /* Time base */
6865 gen_tbl(env);
6866 /* 74xx specific SPR */
6867 gen_spr_74xx(env);
6868 /* LDSTCR */
6869 /* XXX : not implemented */
6870 spr_register(env, SPR_LDSTCR, "LDSTCR",
6871 SPR_NOACCESS, SPR_NOACCESS,
6872 &spr_read_generic, &spr_write_generic,
6873 0x00000000);
6874 /* ICTRL */
6875 /* XXX : not implemented */
6876 spr_register(env, SPR_ICTRL, "ICTRL",
6877 SPR_NOACCESS, SPR_NOACCESS,
6878 &spr_read_generic, &spr_write_generic,
6879 0x00000000);
6880 /* MSSSR0 */
6881 /* XXX : not implemented */
6882 spr_register(env, SPR_MSSSR0, "MSSSR0",
6883 SPR_NOACCESS, SPR_NOACCESS,
6884 &spr_read_generic, &spr_write_generic,
6885 0x00000000);
6886 /* PMC */
6887 /* XXX : not implemented */
6888 spr_register(env, SPR_7XX_PMC5, "PMC5",
6889 SPR_NOACCESS, SPR_NOACCESS,
6890 &spr_read_generic, &spr_write_generic,
6891 0x00000000);
6892 /* XXX : not implemented */
6893 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6894 &spr_read_ureg, SPR_NOACCESS,
6895 &spr_read_ureg, SPR_NOACCESS,
6896 0x00000000);
6897 /* XXX : not implemented */
6898 spr_register(env, SPR_7XX_PMC6, "PMC6",
6899 SPR_NOACCESS, SPR_NOACCESS,
6900 &spr_read_generic, &spr_write_generic,
6901 0x00000000);
6902 /* XXX : not implemented */
6903 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6904 &spr_read_ureg, SPR_NOACCESS,
6905 &spr_read_ureg, SPR_NOACCESS,
6906 0x00000000);
6907 /* SPRGs */
6908 spr_register(env, SPR_SPRG4, "SPRG4",
6909 SPR_NOACCESS, SPR_NOACCESS,
6910 &spr_read_generic, &spr_write_generic,
6911 0x00000000);
6912 spr_register(env, SPR_USPRG4, "USPRG4",
6913 &spr_read_ureg, SPR_NOACCESS,
6914 &spr_read_ureg, SPR_NOACCESS,
6915 0x00000000);
6916 spr_register(env, SPR_SPRG5, "SPRG5",
6917 SPR_NOACCESS, SPR_NOACCESS,
6918 &spr_read_generic, &spr_write_generic,
6919 0x00000000);
6920 spr_register(env, SPR_USPRG5, "USPRG5",
6921 &spr_read_ureg, SPR_NOACCESS,
6922 &spr_read_ureg, SPR_NOACCESS,
6923 0x00000000);
6924 spr_register(env, SPR_SPRG6, "SPRG6",
6925 SPR_NOACCESS, SPR_NOACCESS,
6926 &spr_read_generic, &spr_write_generic,
6927 0x00000000);
6928 spr_register(env, SPR_USPRG6, "USPRG6",
6929 &spr_read_ureg, SPR_NOACCESS,
6930 &spr_read_ureg, SPR_NOACCESS,
6931 0x00000000);
6932 spr_register(env, SPR_SPRG7, "SPRG7",
6933 SPR_NOACCESS, SPR_NOACCESS,
6934 &spr_read_generic, &spr_write_generic,
6935 0x00000000);
6936 spr_register(env, SPR_USPRG7, "USPRG7",
6937 &spr_read_ureg, SPR_NOACCESS,
6938 &spr_read_ureg, SPR_NOACCESS,
6939 0x00000000);
6940 /* Memory management */
6941 gen_low_BATs(env);
6942 gen_high_BATs(env);
6943 gen_74xx_soft_tlb(env, 128, 2);
6944 init_excp_7450(env);
6945 env->dcache_line_size = 32;
6946 env->icache_line_size = 32;
6947 /* Allocate hardware IRQ controller */
6948 ppc6xx_irq_init(ppc_env_get_cpu(env));
6949 }
6950
6951 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6952 {
6953 DeviceClass *dc = DEVICE_CLASS(oc);
6954 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6955
6956 dc->desc = "PowerPC 7445 (aka G4)";
6957 pcc->init_proc = init_proc_7445;
6958 pcc->check_pow = check_pow_hid0_74xx;
6959 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6961 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6962 PPC_FLOAT_STFIWX |
6963 PPC_CACHE | PPC_CACHE_ICBI |
6964 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6965 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6966 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6967 PPC_MEM_TLBIA | PPC_74xx_TLB |
6968 PPC_SEGMENT | PPC_EXTERN |
6969 PPC_ALTIVEC;
6970 pcc->msr_mask = (1ull << MSR_VR) |
6971 (1ull << MSR_POW) |
6972 (1ull << MSR_ILE) |
6973 (1ull << MSR_EE) |
6974 (1ull << MSR_PR) |
6975 (1ull << MSR_FP) |
6976 (1ull << MSR_ME) |
6977 (1ull << MSR_FE0) |
6978 (1ull << MSR_SE) |
6979 (1ull << MSR_DE) |
6980 (1ull << MSR_FE1) |
6981 (1ull << MSR_EP) |
6982 (1ull << MSR_IR) |
6983 (1ull << MSR_DR) |
6984 (1ull << MSR_PMM) |
6985 (1ull << MSR_RI) |
6986 (1ull << MSR_LE);
6987 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6988 pcc->excp_model = POWERPC_EXCP_74xx;
6989 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6990 pcc->bfd_mach = bfd_mach_ppc_7400;
6991 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6992 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6993 POWERPC_FLAG_BUS_CLK;
6994 }
6995
6996 static void init_proc_7455(CPUPPCState *env)
6997 {
6998 gen_spr_ne_601(env);
6999 gen_spr_sdr1(env);
7000 gen_spr_7xx(env);
7001 /* Time base */
7002 gen_tbl(env);
7003 /* 74xx specific SPR */
7004 gen_spr_74xx(env);
7005 /* Level 3 cache control */
7006 gen_l3_ctrl(env);
7007 /* LDSTCR */
7008 /* XXX : not implemented */
7009 spr_register(env, SPR_LDSTCR, "LDSTCR",
7010 SPR_NOACCESS, SPR_NOACCESS,
7011 &spr_read_generic, &spr_write_generic,
7012 0x00000000);
7013 /* ICTRL */
7014 /* XXX : not implemented */
7015 spr_register(env, SPR_ICTRL, "ICTRL",
7016 SPR_NOACCESS, SPR_NOACCESS,
7017 &spr_read_generic, &spr_write_generic,
7018 0x00000000);
7019 /* MSSSR0 */
7020 /* XXX : not implemented */
7021 spr_register(env, SPR_MSSSR0, "MSSSR0",
7022 SPR_NOACCESS, SPR_NOACCESS,
7023 &spr_read_generic, &spr_write_generic,
7024 0x00000000);
7025 /* PMC */
7026 /* XXX : not implemented */
7027 spr_register(env, SPR_7XX_PMC5, "PMC5",
7028 SPR_NOACCESS, SPR_NOACCESS,
7029 &spr_read_generic, &spr_write_generic,
7030 0x00000000);
7031 /* XXX : not implemented */
7032 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7033 &spr_read_ureg, SPR_NOACCESS,
7034 &spr_read_ureg, SPR_NOACCESS,
7035 0x00000000);
7036 /* XXX : not implemented */
7037 spr_register(env, SPR_7XX_PMC6, "PMC6",
7038 SPR_NOACCESS, SPR_NOACCESS,
7039 &spr_read_generic, &spr_write_generic,
7040 0x00000000);
7041 /* XXX : not implemented */
7042 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7043 &spr_read_ureg, SPR_NOACCESS,
7044 &spr_read_ureg, SPR_NOACCESS,
7045 0x00000000);
7046 /* SPRGs */
7047 spr_register(env, SPR_SPRG4, "SPRG4",
7048 SPR_NOACCESS, SPR_NOACCESS,
7049 &spr_read_generic, &spr_write_generic,
7050 0x00000000);
7051 spr_register(env, SPR_USPRG4, "USPRG4",
7052 &spr_read_ureg, SPR_NOACCESS,
7053 &spr_read_ureg, SPR_NOACCESS,
7054 0x00000000);
7055 spr_register(env, SPR_SPRG5, "SPRG5",
7056 SPR_NOACCESS, SPR_NOACCESS,
7057 &spr_read_generic, &spr_write_generic,
7058 0x00000000);
7059 spr_register(env, SPR_USPRG5, "USPRG5",
7060 &spr_read_ureg, SPR_NOACCESS,
7061 &spr_read_ureg, SPR_NOACCESS,
7062 0x00000000);
7063 spr_register(env, SPR_SPRG6, "SPRG6",
7064 SPR_NOACCESS, SPR_NOACCESS,
7065 &spr_read_generic, &spr_write_generic,
7066 0x00000000);
7067 spr_register(env, SPR_USPRG6, "USPRG6",
7068 &spr_read_ureg, SPR_NOACCESS,
7069 &spr_read_ureg, SPR_NOACCESS,
7070 0x00000000);
7071 spr_register(env, SPR_SPRG7, "SPRG7",
7072 SPR_NOACCESS, SPR_NOACCESS,
7073 &spr_read_generic, &spr_write_generic,
7074 0x00000000);
7075 spr_register(env, SPR_USPRG7, "USPRG7",
7076 &spr_read_ureg, SPR_NOACCESS,
7077 &spr_read_ureg, SPR_NOACCESS,
7078 0x00000000);
7079 /* Memory management */
7080 gen_low_BATs(env);
7081 gen_high_BATs(env);
7082 gen_74xx_soft_tlb(env, 128, 2);
7083 init_excp_7450(env);
7084 env->dcache_line_size = 32;
7085 env->icache_line_size = 32;
7086 /* Allocate hardware IRQ controller */
7087 ppc6xx_irq_init(ppc_env_get_cpu(env));
7088 }
7089
7090 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7091 {
7092 DeviceClass *dc = DEVICE_CLASS(oc);
7093 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7094
7095 dc->desc = "PowerPC 7455 (aka G4)";
7096 pcc->init_proc = init_proc_7455;
7097 pcc->check_pow = check_pow_hid0_74xx;
7098 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7099 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7100 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7101 PPC_FLOAT_STFIWX |
7102 PPC_CACHE | PPC_CACHE_ICBI |
7103 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7104 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7105 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7106 PPC_MEM_TLBIA | PPC_74xx_TLB |
7107 PPC_SEGMENT | PPC_EXTERN |
7108 PPC_ALTIVEC;
7109 pcc->msr_mask = (1ull << MSR_VR) |
7110 (1ull << MSR_POW) |
7111 (1ull << MSR_ILE) |
7112 (1ull << MSR_EE) |
7113 (1ull << MSR_PR) |
7114 (1ull << MSR_FP) |
7115 (1ull << MSR_ME) |
7116 (1ull << MSR_FE0) |
7117 (1ull << MSR_SE) |
7118 (1ull << MSR_DE) |
7119 (1ull << MSR_FE1) |
7120 (1ull << MSR_EP) |
7121 (1ull << MSR_IR) |
7122 (1ull << MSR_DR) |
7123 (1ull << MSR_PMM) |
7124 (1ull << MSR_RI) |
7125 (1ull << MSR_LE);
7126 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7127 pcc->excp_model = POWERPC_EXCP_74xx;
7128 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7129 pcc->bfd_mach = bfd_mach_ppc_7400;
7130 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7131 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7132 POWERPC_FLAG_BUS_CLK;
7133 }
7134
7135 static void init_proc_7457(CPUPPCState *env)
7136 {
7137 gen_spr_ne_601(env);
7138 gen_spr_sdr1(env);
7139 gen_spr_7xx(env);
7140 /* Time base */
7141 gen_tbl(env);
7142 /* 74xx specific SPR */
7143 gen_spr_74xx(env);
7144 /* Level 3 cache control */
7145 gen_l3_ctrl(env);
7146 /* L3ITCR1 */
7147 /* XXX : not implemented */
7148 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7149 SPR_NOACCESS, SPR_NOACCESS,
7150 &spr_read_generic, &spr_write_generic,
7151 0x00000000);
7152 /* L3ITCR2 */
7153 /* XXX : not implemented */
7154 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7155 SPR_NOACCESS, SPR_NOACCESS,
7156 &spr_read_generic, &spr_write_generic,
7157 0x00000000);
7158 /* L3ITCR3 */
7159 /* XXX : not implemented */
7160 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7161 SPR_NOACCESS, SPR_NOACCESS,
7162 &spr_read_generic, &spr_write_generic,
7163 0x00000000);
7164 /* L3OHCR */
7165 /* XXX : not implemented */
7166 spr_register(env, SPR_L3OHCR, "L3OHCR",
7167 SPR_NOACCESS, SPR_NOACCESS,
7168 &spr_read_generic, &spr_write_generic,
7169 0x00000000);
7170 /* LDSTCR */
7171 /* XXX : not implemented */
7172 spr_register(env, SPR_LDSTCR, "LDSTCR",
7173 SPR_NOACCESS, SPR_NOACCESS,
7174 &spr_read_generic, &spr_write_generic,
7175 0x00000000);
7176 /* ICTRL */
7177 /* XXX : not implemented */
7178 spr_register(env, SPR_ICTRL, "ICTRL",
7179 SPR_NOACCESS, SPR_NOACCESS,
7180 &spr_read_generic, &spr_write_generic,
7181 0x00000000);
7182 /* MSSSR0 */
7183 /* XXX : not implemented */
7184 spr_register(env, SPR_MSSSR0, "MSSSR0",
7185 SPR_NOACCESS, SPR_NOACCESS,
7186 &spr_read_generic, &spr_write_generic,
7187 0x00000000);
7188 /* PMC */
7189 /* XXX : not implemented */
7190 spr_register(env, SPR_7XX_PMC5, "PMC5",
7191 SPR_NOACCESS, SPR_NOACCESS,
7192 &spr_read_generic, &spr_write_generic,
7193 0x00000000);
7194 /* XXX : not implemented */
7195 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7196 &spr_read_ureg, SPR_NOACCESS,
7197 &spr_read_ureg, SPR_NOACCESS,
7198 0x00000000);
7199 /* XXX : not implemented */
7200 spr_register(env, SPR_7XX_PMC6, "PMC6",
7201 SPR_NOACCESS, SPR_NOACCESS,
7202 &spr_read_generic, &spr_write_generic,
7203 0x00000000);
7204 /* XXX : not implemented */
7205 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7206 &spr_read_ureg, SPR_NOACCESS,
7207 &spr_read_ureg, SPR_NOACCESS,
7208 0x00000000);
7209 /* SPRGs */
7210 spr_register(env, SPR_SPRG4, "SPRG4",
7211 SPR_NOACCESS, SPR_NOACCESS,
7212 &spr_read_generic, &spr_write_generic,
7213 0x00000000);
7214 spr_register(env, SPR_USPRG4, "USPRG4",
7215 &spr_read_ureg, SPR_NOACCESS,
7216 &spr_read_ureg, SPR_NOACCESS,
7217 0x00000000);
7218 spr_register(env, SPR_SPRG5, "SPRG5",
7219 SPR_NOACCESS, SPR_NOACCESS,
7220 &spr_read_generic, &spr_write_generic,
7221 0x00000000);
7222 spr_register(env, SPR_USPRG5, "USPRG5",
7223 &spr_read_ureg, SPR_NOACCESS,
7224 &spr_read_ureg, SPR_NOACCESS,
7225 0x00000000);
7226 spr_register(env, SPR_SPRG6, "SPRG6",
7227 SPR_NOACCESS, SPR_NOACCESS,
7228 &spr_read_generic, &spr_write_generic,
7229 0x00000000);
7230 spr_register(env, SPR_USPRG6, "USPRG6",
7231 &spr_read_ureg, SPR_NOACCESS,
7232 &spr_read_ureg, SPR_NOACCESS,
7233 0x00000000);
7234 spr_register(env, SPR_SPRG7, "SPRG7",
7235 SPR_NOACCESS, SPR_NOACCESS,
7236 &spr_read_generic, &spr_write_generic,
7237 0x00000000);
7238 spr_register(env, SPR_USPRG7, "USPRG7",
7239 &spr_read_ureg, SPR_NOACCESS,
7240 &spr_read_ureg, SPR_NOACCESS,
7241 0x00000000);
7242 /* Memory management */
7243 gen_low_BATs(env);
7244 gen_high_BATs(env);
7245 gen_74xx_soft_tlb(env, 128, 2);
7246 init_excp_7450(env);
7247 env->dcache_line_size = 32;
7248 env->icache_line_size = 32;
7249 /* Allocate hardware IRQ controller */
7250 ppc6xx_irq_init(ppc_env_get_cpu(env));
7251 }
7252
7253 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7254 {
7255 DeviceClass *dc = DEVICE_CLASS(oc);
7256 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7257
7258 dc->desc = "PowerPC 7457 (aka G4)";
7259 pcc->init_proc = init_proc_7457;
7260 pcc->check_pow = check_pow_hid0_74xx;
7261 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7262 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7263 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7264 PPC_FLOAT_STFIWX |
7265 PPC_CACHE | PPC_CACHE_ICBI |
7266 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7267 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7268 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7269 PPC_MEM_TLBIA | PPC_74xx_TLB |
7270 PPC_SEGMENT | PPC_EXTERN |
7271 PPC_ALTIVEC;
7272 pcc->msr_mask = (1ull << MSR_VR) |
7273 (1ull << MSR_POW) |
7274 (1ull << MSR_ILE) |
7275 (1ull << MSR_EE) |
7276 (1ull << MSR_PR) |
7277 (1ull << MSR_FP) |
7278 (1ull << MSR_ME) |
7279 (1ull << MSR_FE0) |
7280 (1ull << MSR_SE) |
7281 (1ull << MSR_DE) |
7282 (1ull << MSR_FE1) |
7283 (1ull << MSR_EP) |
7284 (1ull << MSR_IR) |
7285 (1ull << MSR_DR) |
7286 (1ull << MSR_PMM) |
7287 (1ull << MSR_RI) |
7288 (1ull << MSR_LE);
7289 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7290 pcc->excp_model = POWERPC_EXCP_74xx;
7291 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7292 pcc->bfd_mach = bfd_mach_ppc_7400;
7293 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7294 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7295 POWERPC_FLAG_BUS_CLK;
7296 }
7297
7298 static void init_proc_e600(CPUPPCState *env)
7299 {
7300 gen_spr_ne_601(env);
7301 gen_spr_sdr1(env);
7302 gen_spr_7xx(env);
7303 /* Time base */
7304 gen_tbl(env);
7305 /* 74xx specific SPR */
7306 gen_spr_74xx(env);
7307 /* XXX : not implemented */
7308 spr_register(env, SPR_UBAMR, "UBAMR",
7309 &spr_read_ureg, SPR_NOACCESS,
7310 &spr_read_ureg, SPR_NOACCESS,
7311 0x00000000);
7312 /* XXX : not implemented */
7313 spr_register(env, SPR_LDSTCR, "LDSTCR",
7314 SPR_NOACCESS, SPR_NOACCESS,
7315 &spr_read_generic, &spr_write_generic,
7316 0x00000000);
7317 /* XXX : not implemented */
7318 spr_register(env, SPR_ICTRL, "ICTRL",
7319 SPR_NOACCESS, SPR_NOACCESS,
7320 &spr_read_generic, &spr_write_generic,
7321 0x00000000);
7322 /* XXX : not implemented */
7323 spr_register(env, SPR_MSSSR0, "MSSSR0",
7324 SPR_NOACCESS, SPR_NOACCESS,
7325 &spr_read_generic, &spr_write_generic,
7326 0x00000000);
7327 /* XXX : not implemented */
7328 spr_register(env, SPR_7XX_PMC5, "PMC5",
7329 SPR_NOACCESS, SPR_NOACCESS,
7330 &spr_read_generic, &spr_write_generic,
7331 0x00000000);
7332 /* XXX : not implemented */
7333 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7334 &spr_read_ureg, SPR_NOACCESS,
7335 &spr_read_ureg, SPR_NOACCESS,
7336 0x00000000);
7337 /* XXX : not implemented */
7338 spr_register(env, SPR_7XX_PMC6, "PMC6",
7339 SPR_NOACCESS, SPR_NOACCESS,
7340 &spr_read_generic, &spr_write_generic,
7341 0x00000000);
7342 /* XXX : not implemented */
7343 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7344 &spr_read_ureg, SPR_NOACCESS,
7345 &spr_read_ureg, SPR_NOACCESS,
7346 0x00000000);
7347 /* SPRGs */
7348 spr_register(env, SPR_SPRG4, "SPRG4",
7349 SPR_NOACCESS, SPR_NOACCESS,
7350 &spr_read_generic, &spr_write_generic,
7351 0x00000000);
7352 spr_register(env, SPR_USPRG4, "USPRG4",
7353 &spr_read_ureg, SPR_NOACCESS,
7354 &spr_read_ureg, SPR_NOACCESS,
7355 0x00000000);
7356 spr_register(env, SPR_SPRG5, "SPRG5",
7357 SPR_NOACCESS, SPR_NOACCESS,
7358 &spr_read_generic, &spr_write_generic,
7359 0x00000000);
7360 spr_register(env, SPR_USPRG5, "USPRG5",
7361 &spr_read_ureg, SPR_NOACCESS,
7362 &spr_read_ureg, SPR_NOACCESS,
7363 0x00000000);
7364 spr_register(env, SPR_SPRG6, "SPRG6",
7365 SPR_NOACCESS, SPR_NOACCESS,
7366 &spr_read_generic, &spr_write_generic,
7367 0x00000000);
7368 spr_register(env, SPR_USPRG6, "USPRG6",
7369 &spr_read_ureg, SPR_NOACCESS,
7370 &spr_read_ureg, SPR_NOACCESS,
7371 0x00000000);
7372 spr_register(env, SPR_SPRG7, "SPRG7",
7373 SPR_NOACCESS, SPR_NOACCESS,
7374 &spr_read_generic, &spr_write_generic,
7375 0x00000000);
7376 spr_register(env, SPR_USPRG7, "USPRG7",
7377 &spr_read_ureg, SPR_NOACCESS,
7378 &spr_read_ureg, SPR_NOACCESS,
7379 0x00000000);
7380 /* Memory management */
7381 gen_low_BATs(env);
7382 gen_high_BATs(env);
7383 gen_74xx_soft_tlb(env, 128, 2);
7384 init_excp_7450(env);
7385 env->dcache_line_size = 32;
7386 env->icache_line_size = 32;
7387 /* Allocate hardware IRQ controller */
7388 ppc6xx_irq_init(ppc_env_get_cpu(env));
7389 }
7390
7391 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7392 {
7393 DeviceClass *dc = DEVICE_CLASS(oc);
7394 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7395
7396 dc->desc = "PowerPC e600";
7397 pcc->init_proc = init_proc_e600;
7398 pcc->check_pow = check_pow_hid0_74xx;
7399 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7400 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7401 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7402 PPC_FLOAT_STFIWX |
7403 PPC_CACHE | PPC_CACHE_ICBI |
7404 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7405 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7406 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7407 PPC_MEM_TLBIA | PPC_74xx_TLB |
7408 PPC_SEGMENT | PPC_EXTERN |
7409 PPC_ALTIVEC;
7410 pcc->insns_flags2 = PPC_NONE;
7411 pcc->msr_mask = (1ull << MSR_VR) |
7412 (1ull << MSR_POW) |
7413 (1ull << MSR_ILE) |
7414 (1ull << MSR_EE) |
7415 (1ull << MSR_PR) |
7416 (1ull << MSR_FP) |
7417 (1ull << MSR_ME) |
7418 (1ull << MSR_FE0) |
7419 (1ull << MSR_SE) |
7420 (1ull << MSR_DE) |
7421 (1ull << MSR_FE1) |
7422 (1ull << MSR_EP) |
7423 (1ull << MSR_IR) |
7424 (1ull << MSR_DR) |
7425 (1ull << MSR_PMM) |
7426 (1ull << MSR_RI) |
7427 (1ull << MSR_LE);
7428 pcc->mmu_model = POWERPC_MMU_32B;
7429 #if defined(CONFIG_SOFTMMU)
7430 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7431 #endif
7432 pcc->excp_model = POWERPC_EXCP_74xx;
7433 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7434 pcc->bfd_mach = bfd_mach_ppc_7400;
7435 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7436 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7437 POWERPC_FLAG_BUS_CLK;
7438 }
7439
7440 #if defined(TARGET_PPC64)
7441 #if defined(CONFIG_USER_ONLY)
7442 #define POWERPC970_HID5_INIT 0x00000080
7443 #else
7444 #define POWERPC970_HID5_INIT 0x00000000
7445 #endif
7446
7447 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7448 int bit, int sprn, int cause)
7449 {
7450 TCGv_i32 t1 = tcg_const_i32(bit);
7451 TCGv_i32 t2 = tcg_const_i32(sprn);
7452 TCGv_i32 t3 = tcg_const_i32(cause);
7453
7454 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7455
7456 tcg_temp_free_i32(t3);
7457 tcg_temp_free_i32(t2);
7458 tcg_temp_free_i32(t1);
7459 }
7460
7461 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7462 int bit, int sprn, int cause)
7463 {
7464 TCGv_i32 t1 = tcg_const_i32(bit);
7465 TCGv_i32 t2 = tcg_const_i32(sprn);
7466 TCGv_i32 t3 = tcg_const_i32(cause);
7467
7468 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7469
7470 tcg_temp_free_i32(t3);
7471 tcg_temp_free_i32(t2);
7472 tcg_temp_free_i32(t1);
7473 }
7474
7475 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7476 {
7477 TCGv spr_up = tcg_temp_new();
7478 TCGv spr = tcg_temp_new();
7479
7480 gen_load_spr(spr, sprn - 1);
7481 tcg_gen_shri_tl(spr_up, spr, 32);
7482 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7483
7484 tcg_temp_free(spr);
7485 tcg_temp_free(spr_up);
7486 }
7487
7488 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7489 {
7490 TCGv spr = tcg_temp_new();
7491
7492 gen_load_spr(spr, sprn - 1);
7493 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7494 gen_store_spr(sprn - 1, spr);
7495
7496 tcg_temp_free(spr);
7497 }
7498
7499 static int check_pow_970(CPUPPCState *env)
7500 {
7501 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7502 return 1;
7503 }
7504
7505 return 0;
7506 }
7507
7508 static void gen_spr_970_hid(CPUPPCState *env)
7509 {
7510 /* Hardware implementation registers */
7511 /* XXX : not implemented */
7512 spr_register(env, SPR_HID0, "HID0",
7513 SPR_NOACCESS, SPR_NOACCESS,
7514 &spr_read_generic, &spr_write_clear,
7515 0x60000000);
7516 spr_register(env, SPR_HID1, "HID1",
7517 SPR_NOACCESS, SPR_NOACCESS,
7518 &spr_read_generic, &spr_write_generic,
7519 0x00000000);
7520 spr_register(env, SPR_970_HID5, "HID5",
7521 SPR_NOACCESS, SPR_NOACCESS,
7522 &spr_read_generic, &spr_write_generic,
7523 POWERPC970_HID5_INIT);
7524 }
7525
7526 static void gen_spr_970_hior(CPUPPCState *env)
7527 {
7528 spr_register(env, SPR_HIOR, "SPR_HIOR",
7529 SPR_NOACCESS, SPR_NOACCESS,
7530 &spr_read_hior, &spr_write_hior,
7531 0x00000000);
7532 }
7533
7534 static void gen_spr_book3s_ctrl(CPUPPCState *env)
7535 {
7536 spr_register(env, SPR_CTRL, "SPR_CTRL",
7537 SPR_NOACCESS, SPR_NOACCESS,
7538 SPR_NOACCESS, &spr_write_generic,
7539 0x00000000);
7540 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7541 &spr_read_ureg, SPR_NOACCESS,
7542 &spr_read_ureg, SPR_NOACCESS,
7543 0x00000000);
7544 }
7545
7546 static void gen_spr_book3s_altivec(CPUPPCState *env)
7547 {
7548 if (!(env->insns_flags & PPC_ALTIVEC)) {
7549 return;
7550 }
7551
7552 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7553 &spr_read_generic, &spr_write_generic,
7554 &spr_read_generic, &spr_write_generic,
7555 KVM_REG_PPC_VRSAVE, 0x00000000);
7556
7557 /* Can't find information on what this should be on reset. This
7558 * value is the one used by 74xx processors. */
7559 vscr_init(env, 0x00010000);
7560 }
7561
7562 static void gen_spr_book3s_dbg(CPUPPCState *env)
7563 {
7564 /*
7565 * TODO: different specs define different scopes for these,
7566 * will have to address this:
7567 * 970: super/write and super/read
7568 * powerisa 2.03..2.04: hypv/write and super/read.
7569 * powerisa 2.05 and newer: hypv/write and hypv/read.
7570 */
7571 spr_register_kvm(env, SPR_DABR, "DABR",
7572 SPR_NOACCESS, SPR_NOACCESS,
7573 &spr_read_generic, &spr_write_generic,
7574 KVM_REG_PPC_DABR, 0x00000000);
7575 spr_register_kvm(env, SPR_DABRX, "DABRX",
7576 SPR_NOACCESS, SPR_NOACCESS,
7577 &spr_read_generic, &spr_write_generic,
7578 KVM_REG_PPC_DABRX, 0x00000000);
7579 }
7580
7581 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7582 {
7583 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7584 SPR_NOACCESS, SPR_NOACCESS,
7585 SPR_NOACCESS, SPR_NOACCESS,
7586 &spr_read_generic, &spr_write_generic,
7587 KVM_REG_PPC_DAWR, 0x00000000);
7588 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7589 SPR_NOACCESS, SPR_NOACCESS,
7590 SPR_NOACCESS, SPR_NOACCESS,
7591 &spr_read_generic, &spr_write_generic,
7592 KVM_REG_PPC_DAWRX, 0x00000000);
7593 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7594 SPR_NOACCESS, SPR_NOACCESS,
7595 SPR_NOACCESS, SPR_NOACCESS,
7596 &spr_read_generic, &spr_write_generic,
7597 KVM_REG_PPC_CIABR, 0x00000000);
7598 }
7599
7600 static void gen_spr_970_dbg(CPUPPCState *env)
7601 {
7602 /* Breakpoints */
7603 spr_register(env, SPR_IABR, "IABR",
7604 SPR_NOACCESS, SPR_NOACCESS,
7605 &spr_read_generic, &spr_write_generic,
7606 0x00000000);
7607 }
7608
7609 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7610 {
7611 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7612 SPR_NOACCESS, SPR_NOACCESS,
7613 &spr_read_generic, &spr_write_generic,
7614 KVM_REG_PPC_MMCR0, 0x00000000);
7615 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7616 SPR_NOACCESS, SPR_NOACCESS,
7617 &spr_read_generic, &spr_write_generic,
7618 KVM_REG_PPC_MMCR1, 0x00000000);
7619 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7620 SPR_NOACCESS, SPR_NOACCESS,
7621 &spr_read_generic, &spr_write_generic,
7622 KVM_REG_PPC_MMCRA, 0x00000000);
7623 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7624 SPR_NOACCESS, SPR_NOACCESS,
7625 &spr_read_generic, &spr_write_generic,
7626 KVM_REG_PPC_PMC1, 0x00000000);
7627 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7628 SPR_NOACCESS, SPR_NOACCESS,
7629 &spr_read_generic, &spr_write_generic,
7630 KVM_REG_PPC_PMC2, 0x00000000);
7631 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7632 SPR_NOACCESS, SPR_NOACCESS,
7633 &spr_read_generic, &spr_write_generic,
7634 KVM_REG_PPC_PMC3, 0x00000000);
7635 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7636 SPR_NOACCESS, SPR_NOACCESS,
7637 &spr_read_generic, &spr_write_generic,
7638 KVM_REG_PPC_PMC4, 0x00000000);
7639 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7640 SPR_NOACCESS, SPR_NOACCESS,
7641 &spr_read_generic, &spr_write_generic,
7642 KVM_REG_PPC_PMC5, 0x00000000);
7643 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7644 SPR_NOACCESS, SPR_NOACCESS,
7645 &spr_read_generic, &spr_write_generic,
7646 KVM_REG_PPC_PMC6, 0x00000000);
7647 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7648 SPR_NOACCESS, SPR_NOACCESS,
7649 &spr_read_generic, &spr_write_generic,
7650 KVM_REG_PPC_SIAR, 0x00000000);
7651 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7652 SPR_NOACCESS, SPR_NOACCESS,
7653 &spr_read_generic, &spr_write_generic,
7654 KVM_REG_PPC_SDAR, 0x00000000);
7655 }
7656
7657 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7658 {
7659 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7660 &spr_read_ureg, SPR_NOACCESS,
7661 &spr_read_ureg, &spr_write_ureg,
7662 0x00000000);
7663 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7664 &spr_read_ureg, SPR_NOACCESS,
7665 &spr_read_ureg, &spr_write_ureg,
7666 0x00000000);
7667 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7668 &spr_read_ureg, SPR_NOACCESS,
7669 &spr_read_ureg, &spr_write_ureg,
7670 0x00000000);
7671 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7672 &spr_read_ureg, SPR_NOACCESS,
7673 &spr_read_ureg, &spr_write_ureg,
7674 0x00000000);
7675 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7676 &spr_read_ureg, SPR_NOACCESS,
7677 &spr_read_ureg, &spr_write_ureg,
7678 0x00000000);
7679 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7680 &spr_read_ureg, SPR_NOACCESS,
7681 &spr_read_ureg, &spr_write_ureg,
7682 0x00000000);
7683 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7684 &spr_read_ureg, SPR_NOACCESS,
7685 &spr_read_ureg, &spr_write_ureg,
7686 0x00000000);
7687 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7688 &spr_read_ureg, SPR_NOACCESS,
7689 &spr_read_ureg, &spr_write_ureg,
7690 0x00000000);
7691 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7692 &spr_read_ureg, SPR_NOACCESS,
7693 &spr_read_ureg, &spr_write_ureg,
7694 0x00000000);
7695 spr_register(env, SPR_POWER_USIAR, "USIAR",
7696 &spr_read_ureg, SPR_NOACCESS,
7697 &spr_read_ureg, &spr_write_ureg,
7698 0x00000000);
7699 spr_register(env, SPR_POWER_USDAR, "USDAR",
7700 &spr_read_ureg, SPR_NOACCESS,
7701 &spr_read_ureg, &spr_write_ureg,
7702 0x00000000);
7703 }
7704
7705 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7706 {
7707 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7708 SPR_NOACCESS, SPR_NOACCESS,
7709 &spr_read_generic, &spr_write_generic,
7710 KVM_REG_PPC_PMC7, 0x00000000);
7711 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7712 SPR_NOACCESS, SPR_NOACCESS,
7713 &spr_read_generic, &spr_write_generic,
7714 KVM_REG_PPC_PMC8, 0x00000000);
7715 }
7716
7717 static void gen_spr_970_pmu_user(CPUPPCState *env)
7718 {
7719 spr_register(env, SPR_970_UPMC7, "UPMC7",
7720 &spr_read_ureg, SPR_NOACCESS,
7721 &spr_read_ureg, &spr_write_ureg,
7722 0x00000000);
7723 spr_register(env, SPR_970_UPMC8, "UPMC8",
7724 &spr_read_ureg, SPR_NOACCESS,
7725 &spr_read_ureg, &spr_write_ureg,
7726 0x00000000);
7727 }
7728
7729 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7730 {
7731 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7732 SPR_NOACCESS, SPR_NOACCESS,
7733 &spr_read_generic, &spr_write_generic,
7734 KVM_REG_PPC_MMCR2, 0x00000000);
7735 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7736 SPR_NOACCESS, SPR_NOACCESS,
7737 &spr_read_generic, &spr_write_generic,
7738 KVM_REG_PPC_MMCRS, 0x00000000);
7739 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7740 SPR_NOACCESS, SPR_NOACCESS,
7741 &spr_read_generic, &spr_write_generic,
7742 KVM_REG_PPC_SIER, 0x00000000);
7743 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7744 SPR_NOACCESS, SPR_NOACCESS,
7745 &spr_read_generic, &spr_write_generic,
7746 KVM_REG_PPC_SPMC1, 0x00000000);
7747 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7748 SPR_NOACCESS, SPR_NOACCESS,
7749 &spr_read_generic, &spr_write_generic,
7750 KVM_REG_PPC_SPMC2, 0x00000000);
7751 spr_register_kvm(env, SPR_TACR, "TACR",
7752 SPR_NOACCESS, SPR_NOACCESS,
7753 &spr_read_generic, &spr_write_generic,
7754 KVM_REG_PPC_TACR, 0x00000000);
7755 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7756 SPR_NOACCESS, SPR_NOACCESS,
7757 &spr_read_generic, &spr_write_generic,
7758 KVM_REG_PPC_TCSCR, 0x00000000);
7759 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7760 SPR_NOACCESS, SPR_NOACCESS,
7761 &spr_read_generic, &spr_write_generic,
7762 KVM_REG_PPC_CSIGR, 0x00000000);
7763 }
7764
7765 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7766 {
7767 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7768 &spr_read_ureg, SPR_NOACCESS,
7769 &spr_read_ureg, &spr_write_ureg,
7770 0x00000000);
7771 spr_register(env, SPR_POWER_USIER, "USIER",
7772 &spr_read_generic, SPR_NOACCESS,
7773 &spr_read_generic, &spr_write_generic,
7774 0x00000000);
7775 }
7776
7777 static void gen_spr_power5p_ear(CPUPPCState *env)
7778 {
7779 /* External access control */
7780 spr_register(env, SPR_EAR, "EAR",
7781 SPR_NOACCESS, SPR_NOACCESS,
7782 &spr_read_generic, &spr_write_generic,
7783 0x00000000);
7784 }
7785
7786 #if !defined(CONFIG_USER_ONLY)
7787 static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7788 {
7789 TCGv hmer = tcg_temp_new();
7790
7791 gen_load_spr(hmer, sprn);
7792 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7793 gen_store_spr(sprn, hmer);
7794 spr_store_dump_spr(sprn);
7795 tcg_temp_free(hmer);
7796 }
7797
7798 static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7799 {
7800 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7801 }
7802
7803 static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
7804 {
7805 #if defined(TARGET_PPC64)
7806 spr_write_generic(ctx, sprn, gprn);
7807 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7808 #endif
7809 }
7810
7811 #endif /* !defined(CONFIG_USER_ONLY) */
7812
7813 static void gen_spr_970_lpar(CPUPPCState *env)
7814 {
7815 #if !defined(CONFIG_USER_ONLY)
7816 /* Logical partitionning */
7817 /* PPC970: HID4 is effectively the LPCR */
7818 spr_register(env, SPR_970_HID4, "HID4",
7819 SPR_NOACCESS, SPR_NOACCESS,
7820 &spr_read_generic, &spr_write_970_hid4,
7821 0x00000000);
7822 #endif
7823 }
7824
7825 static void gen_spr_power5p_lpar(CPUPPCState *env)
7826 {
7827 #if !defined(CONFIG_USER_ONLY)
7828 /* Logical partitionning */
7829 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7830 SPR_NOACCESS, SPR_NOACCESS,
7831 SPR_NOACCESS, SPR_NOACCESS,
7832 &spr_read_generic, &spr_write_lpcr,
7833 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7834 spr_register_hv(env, SPR_HDEC, "HDEC",
7835 SPR_NOACCESS, SPR_NOACCESS,
7836 SPR_NOACCESS, SPR_NOACCESS,
7837 &spr_read_hdecr, &spr_write_hdecr, 0);
7838 #endif
7839 }
7840
7841 static void gen_spr_book3s_ids(CPUPPCState *env)
7842 {
7843 /* FIXME: Will need to deal with thread vs core only SPRs */
7844
7845 /* Processor identification */
7846 spr_register_hv(env, SPR_PIR, "PIR",
7847 SPR_NOACCESS, SPR_NOACCESS,
7848 &spr_read_generic, SPR_NOACCESS,
7849 &spr_read_generic, NULL,
7850 0x00000000);
7851 spr_register_hv(env, SPR_HID0, "HID0",
7852 SPR_NOACCESS, SPR_NOACCESS,
7853 SPR_NOACCESS, SPR_NOACCESS,
7854 &spr_read_generic, &spr_write_generic,
7855 0x00000000);
7856 spr_register_hv(env, SPR_TSCR, "TSCR",
7857 SPR_NOACCESS, SPR_NOACCESS,
7858 SPR_NOACCESS, SPR_NOACCESS,
7859 &spr_read_generic, &spr_write_generic,
7860 0x00000000);
7861 spr_register_hv(env, SPR_HMER, "HMER",
7862 SPR_NOACCESS, SPR_NOACCESS,
7863 SPR_NOACCESS, SPR_NOACCESS,
7864 &spr_read_generic, &spr_write_hmer,
7865 0x00000000);
7866 spr_register_hv(env, SPR_HMEER, "HMEER",
7867 SPR_NOACCESS, SPR_NOACCESS,
7868 SPR_NOACCESS, SPR_NOACCESS,
7869 &spr_read_generic, &spr_write_generic,
7870 0x00000000);
7871 spr_register_hv(env, SPR_TFMR, "TFMR",
7872 SPR_NOACCESS, SPR_NOACCESS,
7873 SPR_NOACCESS, SPR_NOACCESS,
7874 &spr_read_generic, &spr_write_generic,
7875 0x00000000);
7876 spr_register_hv(env, SPR_LPIDR, "LPIDR",
7877 SPR_NOACCESS, SPR_NOACCESS,
7878 SPR_NOACCESS, SPR_NOACCESS,
7879 &spr_read_generic, &spr_write_generic,
7880 0x00000000);
7881 spr_register_hv(env, SPR_HFSCR, "HFSCR",
7882 SPR_NOACCESS, SPR_NOACCESS,
7883 SPR_NOACCESS, SPR_NOACCESS,
7884 &spr_read_generic, &spr_write_generic,
7885 0x00000000);
7886 spr_register_hv(env, SPR_MMCRC, "MMCRC",
7887 SPR_NOACCESS, SPR_NOACCESS,
7888 SPR_NOACCESS, SPR_NOACCESS,
7889 &spr_read_generic, &spr_write_generic,
7890 0x00000000);
7891 spr_register_hv(env, SPR_MMCRH, "MMCRH",
7892 SPR_NOACCESS, SPR_NOACCESS,
7893 SPR_NOACCESS, SPR_NOACCESS,
7894 &spr_read_generic, &spr_write_generic,
7895 0x00000000);
7896 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7897 SPR_NOACCESS, SPR_NOACCESS,
7898 SPR_NOACCESS, SPR_NOACCESS,
7899 &spr_read_generic, &spr_write_generic,
7900 0x00000000);
7901 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7902 SPR_NOACCESS, SPR_NOACCESS,
7903 SPR_NOACCESS, SPR_NOACCESS,
7904 &spr_read_generic, &spr_write_generic,
7905 0x00000000);
7906 spr_register_hv(env, SPR_HSRR0, "HSRR0",
7907 SPR_NOACCESS, SPR_NOACCESS,
7908 SPR_NOACCESS, SPR_NOACCESS,
7909 &spr_read_generic, &spr_write_generic,
7910 0x00000000);
7911 spr_register_hv(env, SPR_HSRR1, "HSRR1",
7912 SPR_NOACCESS, SPR_NOACCESS,
7913 SPR_NOACCESS, SPR_NOACCESS,
7914 &spr_read_generic, &spr_write_generic,
7915 0x00000000);
7916 spr_register_hv(env, SPR_HDAR, "HDAR",
7917 SPR_NOACCESS, SPR_NOACCESS,
7918 SPR_NOACCESS, SPR_NOACCESS,
7919 &spr_read_generic, &spr_write_generic,
7920 0x00000000);
7921 spr_register_hv(env, SPR_HDSISR, "HDSISR",
7922 SPR_NOACCESS, SPR_NOACCESS,
7923 SPR_NOACCESS, SPR_NOACCESS,
7924 &spr_read_generic, &spr_write_generic,
7925 0x00000000);
7926 spr_register_hv(env, SPR_RMOR, "RMOR",
7927 SPR_NOACCESS, SPR_NOACCESS,
7928 SPR_NOACCESS, SPR_NOACCESS,
7929 &spr_read_generic, &spr_write_generic,
7930 0x00000000);
7931 spr_register_hv(env, SPR_HRMOR, "HRMOR",
7932 SPR_NOACCESS, SPR_NOACCESS,
7933 SPR_NOACCESS, SPR_NOACCESS,
7934 &spr_read_generic, &spr_write_generic,
7935 0x00000000);
7936 }
7937
7938 static void gen_spr_power8_ids(CPUPPCState *env)
7939 {
7940 /* Thread identification */
7941 spr_register(env, SPR_TIR, "TIR",
7942 SPR_NOACCESS, SPR_NOACCESS,
7943 &spr_read_generic, SPR_NOACCESS,
7944 0x00000000);
7945 }
7946
7947 static void gen_spr_book3s_purr(CPUPPCState *env)
7948 {
7949 #if !defined(CONFIG_USER_ONLY)
7950 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7951 spr_register_kvm(env, SPR_PURR, "PURR",
7952 &spr_read_purr, SPR_NOACCESS,
7953 &spr_read_purr, SPR_NOACCESS,
7954 KVM_REG_PPC_PURR, 0x00000000);
7955 spr_register_kvm(env, SPR_SPURR, "SPURR",
7956 &spr_read_purr, SPR_NOACCESS,
7957 &spr_read_purr, SPR_NOACCESS,
7958 KVM_REG_PPC_SPURR, 0x00000000);
7959 #endif
7960 }
7961
7962 static void gen_spr_power6_dbg(CPUPPCState *env)
7963 {
7964 #if !defined(CONFIG_USER_ONLY)
7965 spr_register(env, SPR_CFAR, "SPR_CFAR",
7966 SPR_NOACCESS, SPR_NOACCESS,
7967 &spr_read_cfar, &spr_write_cfar,
7968 0x00000000);
7969 #endif
7970 }
7971
7972 static void gen_spr_power5p_common(CPUPPCState *env)
7973 {
7974 spr_register_kvm(env, SPR_PPR, "PPR",
7975 &spr_read_generic, &spr_write_generic,
7976 &spr_read_generic, &spr_write_generic,
7977 KVM_REG_PPC_PPR, 0x00000000);
7978 }
7979
7980 static void gen_spr_power6_common(CPUPPCState *env)
7981 {
7982 #if !defined(CONFIG_USER_ONLY)
7983 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7984 SPR_NOACCESS, SPR_NOACCESS,
7985 &spr_read_generic, &spr_write_generic,
7986 KVM_REG_PPC_DSCR, 0x00000000);
7987 #endif
7988 /*
7989 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7990 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
7991 */
7992 spr_register_hv(env, SPR_PCR, "PCR",
7993 SPR_NOACCESS, SPR_NOACCESS,
7994 SPR_NOACCESS, SPR_NOACCESS,
7995 &spr_read_generic, &spr_write_pcr,
7996 0x00000000);
7997 }
7998
7999 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
8000 {
8001 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8002 spr_read_generic(ctx, gprn, sprn);
8003 }
8004
8005 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
8006 {
8007 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8008 spr_write_generic(ctx, sprn, gprn);
8009 }
8010
8011 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
8012 {
8013 spr_register_kvm(env, SPR_TAR, "TAR",
8014 &spr_read_tar, &spr_write_tar,
8015 &spr_read_generic, &spr_write_generic,
8016 KVM_REG_PPC_TAR, 0x00000000);
8017 }
8018
8019 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
8020 {
8021 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8022 spr_read_generic(ctx, gprn, sprn);
8023 }
8024
8025 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
8026 {
8027 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8028 spr_write_generic(ctx, sprn, gprn);
8029 }
8030
8031 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
8032 {
8033 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8034 spr_read_prev_upper32(ctx, gprn, sprn);
8035 }
8036
8037 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
8038 {
8039 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8040 spr_write_prev_upper32(ctx, sprn, gprn);
8041 }
8042
8043 static void gen_spr_power8_tm(CPUPPCState *env)
8044 {
8045 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8046 &spr_read_tm, &spr_write_tm,
8047 &spr_read_tm, &spr_write_tm,
8048 KVM_REG_PPC_TFHAR, 0x00000000);
8049 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8050 &spr_read_tm, &spr_write_tm,
8051 &spr_read_tm, &spr_write_tm,
8052 KVM_REG_PPC_TFIAR, 0x00000000);
8053 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8054 &spr_read_tm, &spr_write_tm,
8055 &spr_read_tm, &spr_write_tm,
8056 KVM_REG_PPC_TEXASR, 0x00000000);
8057 spr_register(env, SPR_TEXASRU, "TEXASRU",
8058 &spr_read_tm_upper32, &spr_write_tm_upper32,
8059 &spr_read_tm_upper32, &spr_write_tm_upper32,
8060 0x00000000);
8061 }
8062
8063 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
8064 {
8065 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8066 spr_read_generic(ctx, gprn, sprn);
8067 }
8068
8069 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
8070 {
8071 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8072 spr_write_generic(ctx, sprn, gprn);
8073 }
8074
8075 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
8076 {
8077 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8078 spr_read_prev_upper32(ctx, gprn, sprn);
8079 }
8080
8081 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
8082 {
8083 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8084 spr_write_prev_upper32(ctx, sprn, gprn);
8085 }
8086
8087 static void gen_spr_power8_ebb(CPUPPCState *env)
8088 {
8089 spr_register(env, SPR_BESCRS, "BESCRS",
8090 &spr_read_ebb, &spr_write_ebb,
8091 &spr_read_generic, &spr_write_generic,
8092 0x00000000);
8093 spr_register(env, SPR_BESCRSU, "BESCRSU",
8094 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8095 &spr_read_prev_upper32, &spr_write_prev_upper32,
8096 0x00000000);
8097 spr_register(env, SPR_BESCRR, "BESCRR",
8098 &spr_read_ebb, &spr_write_ebb,
8099 &spr_read_generic, &spr_write_generic,
8100 0x00000000);
8101 spr_register(env, SPR_BESCRRU, "BESCRRU",
8102 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8103 &spr_read_prev_upper32, &spr_write_prev_upper32,
8104 0x00000000);
8105 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8106 &spr_read_ebb, &spr_write_ebb,
8107 &spr_read_generic, &spr_write_generic,
8108 KVM_REG_PPC_EBBHR, 0x00000000);
8109 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8110 &spr_read_ebb, &spr_write_ebb,
8111 &spr_read_generic, &spr_write_generic,
8112 KVM_REG_PPC_EBBRR, 0x00000000);
8113 spr_register_kvm(env, SPR_BESCR, "BESCR",
8114 &spr_read_ebb, &spr_write_ebb,
8115 &spr_read_generic, &spr_write_generic,
8116 KVM_REG_PPC_BESCR, 0x00000000);
8117 }
8118
8119 /* Virtual Time Base */
8120 static void gen_spr_vtb(CPUPPCState *env)
8121 {
8122 spr_register_kvm(env, SPR_VTB, "VTB",
8123 SPR_NOACCESS, SPR_NOACCESS,
8124 &spr_read_tbl, SPR_NOACCESS,
8125 KVM_REG_PPC_VTB, 0x00000000);
8126 }
8127
8128 static void gen_spr_power8_fscr(CPUPPCState *env)
8129 {
8130 #if defined(CONFIG_USER_ONLY)
8131 target_ulong initval = 1ULL << FSCR_TAR;
8132 #else
8133 target_ulong initval = 0;
8134 #endif
8135 spr_register_kvm(env, SPR_FSCR, "FSCR",
8136 SPR_NOACCESS, SPR_NOACCESS,
8137 &spr_read_generic, &spr_write_generic,
8138 KVM_REG_PPC_FSCR, initval);
8139 }
8140
8141 static void gen_spr_power8_pspb(CPUPPCState *env)
8142 {
8143 spr_register_kvm(env, SPR_PSPB, "PSPB",
8144 SPR_NOACCESS, SPR_NOACCESS,
8145 &spr_read_generic, &spr_write_generic32,
8146 KVM_REG_PPC_PSPB, 0);
8147 }
8148
8149 static void gen_spr_power8_ic(CPUPPCState *env)
8150 {
8151 #if !defined(CONFIG_USER_ONLY)
8152 spr_register_hv(env, SPR_IC, "IC",
8153 SPR_NOACCESS, SPR_NOACCESS,
8154 &spr_read_generic, SPR_NOACCESS,
8155 &spr_read_generic, &spr_write_generic,
8156 0);
8157 #endif
8158 }
8159
8160 static void gen_spr_power8_book4(CPUPPCState *env)
8161 {
8162 /* Add a number of P8 book4 registers */
8163 #if !defined(CONFIG_USER_ONLY)
8164 spr_register_kvm(env, SPR_ACOP, "ACOP",
8165 SPR_NOACCESS, SPR_NOACCESS,
8166 &spr_read_generic, &spr_write_generic,
8167 KVM_REG_PPC_ACOP, 0);
8168 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8169 SPR_NOACCESS, SPR_NOACCESS,
8170 &spr_read_generic, &spr_write_pidr,
8171 KVM_REG_PPC_PID, 0);
8172 spr_register_kvm(env, SPR_WORT, "WORT",
8173 SPR_NOACCESS, SPR_NOACCESS,
8174 &spr_read_generic, &spr_write_generic,
8175 KVM_REG_PPC_WORT, 0);
8176 #endif
8177 }
8178
8179 static void gen_spr_power7_book4(CPUPPCState *env)
8180 {
8181 /* Add a number of P7 book4 registers */
8182 #if !defined(CONFIG_USER_ONLY)
8183 spr_register_kvm(env, SPR_ACOP, "ACOP",
8184 SPR_NOACCESS, SPR_NOACCESS,
8185 &spr_read_generic, &spr_write_generic,
8186 KVM_REG_PPC_ACOP, 0);
8187 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8188 SPR_NOACCESS, SPR_NOACCESS,
8189 &spr_read_generic, &spr_write_generic,
8190 KVM_REG_PPC_PID, 0);
8191 #endif
8192 }
8193
8194 static void gen_spr_power8_rpr(CPUPPCState *env)
8195 {
8196 #if !defined(CONFIG_USER_ONLY)
8197 spr_register_hv(env, SPR_RPR, "RPR",
8198 SPR_NOACCESS, SPR_NOACCESS,
8199 SPR_NOACCESS, SPR_NOACCESS,
8200 &spr_read_generic, &spr_write_generic,
8201 0x00000103070F1F3F);
8202 #endif
8203 }
8204
8205 static void gen_spr_power9_mmu(CPUPPCState *env)
8206 {
8207 #if !defined(CONFIG_USER_ONLY)
8208 /* Partition Table Control */
8209 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
8210 SPR_NOACCESS, SPR_NOACCESS,
8211 SPR_NOACCESS, SPR_NOACCESS,
8212 &spr_read_generic, &spr_write_ptcr,
8213 KVM_REG_PPC_PTCR, 0x00000000);
8214 #endif
8215 }
8216
8217 static void init_proc_book3s_common(CPUPPCState *env)
8218 {
8219 gen_spr_ne_601(env);
8220 gen_tbl(env);
8221 gen_spr_usprg3(env);
8222 gen_spr_book3s_altivec(env);
8223 gen_spr_book3s_pmu_sup(env);
8224 gen_spr_book3s_pmu_user(env);
8225 gen_spr_book3s_ctrl(env);
8226 }
8227
8228 static void init_proc_970(CPUPPCState *env)
8229 {
8230 /* Common Registers */
8231 init_proc_book3s_common(env);
8232 gen_spr_sdr1(env);
8233 gen_spr_book3s_dbg(env);
8234
8235 /* 970 Specific Registers */
8236 gen_spr_970_hid(env);
8237 gen_spr_970_hior(env);
8238 gen_low_BATs(env);
8239 gen_spr_970_pmu_sup(env);
8240 gen_spr_970_pmu_user(env);
8241 gen_spr_970_lpar(env);
8242 gen_spr_970_dbg(env);
8243
8244 /* env variables */
8245 env->dcache_line_size = 128;
8246 env->icache_line_size = 128;
8247
8248 /* Allocate hardware IRQ controller */
8249 init_excp_970(env);
8250 ppc970_irq_init(ppc_env_get_cpu(env));
8251 }
8252
8253 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8254 {
8255 DeviceClass *dc = DEVICE_CLASS(oc);
8256 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8257
8258 dc->desc = "PowerPC 970";
8259 pcc->init_proc = init_proc_970;
8260 pcc->check_pow = check_pow_970;
8261 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8262 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8263 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8264 PPC_FLOAT_STFIWX |
8265 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8266 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8268 PPC_64B | PPC_ALTIVEC |
8269 PPC_SEGMENT_64B | PPC_SLBI;
8270 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8271 pcc->msr_mask = (1ull << MSR_SF) |
8272 (1ull << MSR_VR) |
8273 (1ull << MSR_POW) |
8274 (1ull << MSR_EE) |
8275 (1ull << MSR_PR) |
8276 (1ull << MSR_FP) |
8277 (1ull << MSR_ME) |
8278 (1ull << MSR_FE0) |
8279 (1ull << MSR_SE) |
8280 (1ull << MSR_DE) |
8281 (1ull << MSR_FE1) |
8282 (1ull << MSR_IR) |
8283 (1ull << MSR_DR) |
8284 (1ull << MSR_PMM) |
8285 (1ull << MSR_RI);
8286 pcc->mmu_model = POWERPC_MMU_64B;
8287 #if defined(CONFIG_SOFTMMU)
8288 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8289 pcc->hash64_opts = &ppc_hash64_opts_basic;
8290 #endif
8291 pcc->excp_model = POWERPC_EXCP_970;
8292 pcc->bus_model = PPC_FLAGS_INPUT_970;
8293 pcc->bfd_mach = bfd_mach_ppc64;
8294 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8295 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8296 POWERPC_FLAG_BUS_CLK;
8297 pcc->l1_dcache_size = 0x8000;
8298 pcc->l1_icache_size = 0x10000;
8299 }
8300
8301 static void init_proc_power5plus(CPUPPCState *env)
8302 {
8303 /* Common Registers */
8304 init_proc_book3s_common(env);
8305 gen_spr_sdr1(env);
8306 gen_spr_book3s_dbg(env);
8307
8308 /* POWER5+ Specific Registers */
8309 gen_spr_970_hid(env);
8310 gen_spr_970_hior(env);
8311 gen_low_BATs(env);
8312 gen_spr_970_pmu_sup(env);
8313 gen_spr_970_pmu_user(env);
8314 gen_spr_power5p_common(env);
8315 gen_spr_power5p_lpar(env);
8316 gen_spr_power5p_ear(env);
8317
8318 /* env variables */
8319 env->dcache_line_size = 128;
8320 env->icache_line_size = 128;
8321
8322 /* Allocate hardware IRQ controller */
8323 init_excp_970(env);
8324 ppc970_irq_init(ppc_env_get_cpu(env));
8325 }
8326
8327 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8328 {
8329 DeviceClass *dc = DEVICE_CLASS(oc);
8330 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8331
8332 dc->fw_name = "PowerPC,POWER5";
8333 dc->desc = "POWER5+";
8334 pcc->init_proc = init_proc_power5plus;
8335 pcc->check_pow = check_pow_970;
8336 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8337 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8338 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8339 PPC_FLOAT_STFIWX |
8340 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8341 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8342 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8343 PPC_64B |
8344 PPC_SEGMENT_64B | PPC_SLBI;
8345 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8346 pcc->msr_mask = (1ull << MSR_SF) |
8347 (1ull << MSR_VR) |
8348 (1ull << MSR_POW) |
8349 (1ull << MSR_EE) |
8350 (1ull << MSR_PR) |
8351 (1ull << MSR_FP) |
8352 (1ull << MSR_ME) |
8353 (1ull << MSR_FE0) |
8354 (1ull << MSR_SE) |
8355 (1ull << MSR_DE) |
8356 (1ull << MSR_FE1) |
8357 (1ull << MSR_IR) |
8358 (1ull << MSR_DR) |
8359 (1ull << MSR_PMM) |
8360 (1ull << MSR_RI);
8361 pcc->mmu_model = POWERPC_MMU_2_03;
8362 #if defined(CONFIG_SOFTMMU)
8363 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8364 pcc->hash64_opts = &ppc_hash64_opts_basic;
8365 #endif
8366 pcc->excp_model = POWERPC_EXCP_970;
8367 pcc->bus_model = PPC_FLAGS_INPUT_970;
8368 pcc->bfd_mach = bfd_mach_ppc64;
8369 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8370 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8371 POWERPC_FLAG_BUS_CLK;
8372 pcc->l1_dcache_size = 0x8000;
8373 pcc->l1_icache_size = 0x10000;
8374 }
8375
8376 /*
8377 * The CPU used to have a "compat" property which set the
8378 * compatibility mode PVR. However, this was conceptually broken - it
8379 * only makes sense on the pseries machine type (otherwise the guest
8380 * owns the PCR and can control the compatibility mode itself). It's
8381 * been replaced with the 'max-cpu-compat' property on the pseries
8382 * machine type. For backwards compatibility, pseries specially
8383 * parses the -cpu parameter and converts old compat= parameters into
8384 * the appropriate machine parameters. This stub implementation of
8385 * the parameter catches any uses on explicitly created CPUs.
8386 */
8387 static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
8388 void *opaque, Error **errp)
8389 {
8390 QNull *null = NULL;
8391
8392 if (!qtest_enabled()) {
8393 warn_report("CPU 'compat' property is deprecated and has no effect; "
8394 "use max-cpu-compat machine property instead");
8395 }
8396 visit_type_null(v, name, &null, NULL);
8397 qobject_unref(null);
8398 }
8399
8400 static const PropertyInfo ppc_compat_deprecated_propinfo = {
8401 .name = "str",
8402 .description = "compatibility mode (deprecated)",
8403 .get = getset_compat_deprecated,
8404 .set = getset_compat_deprecated,
8405 };
8406 static Property powerpc_servercpu_properties[] = {
8407 {
8408 .name = "compat",
8409 .info = &ppc_compat_deprecated_propinfo,
8410 },
8411 DEFINE_PROP_END_OF_LIST(),
8412 };
8413
8414 static void init_proc_POWER7(CPUPPCState *env)
8415 {
8416 /* Common Registers */
8417 init_proc_book3s_common(env);
8418 gen_spr_sdr1(env);
8419 gen_spr_book3s_dbg(env);
8420
8421 /* POWER7 Specific Registers */
8422 gen_spr_book3s_ids(env);
8423 gen_spr_amr(env);
8424 gen_spr_book3s_purr(env);
8425 gen_spr_power5p_common(env);
8426 gen_spr_power5p_lpar(env);
8427 gen_spr_power5p_ear(env);
8428 gen_spr_power6_common(env);
8429 gen_spr_power6_dbg(env);
8430 gen_spr_power7_book4(env);
8431
8432 /* env variables */
8433 env->dcache_line_size = 128;
8434 env->icache_line_size = 128;
8435
8436 /* Allocate hardware IRQ controller */
8437 init_excp_POWER7(env);
8438 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8439 }
8440
8441 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8442 {
8443 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8444 return true;
8445 }
8446 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8447 return true;
8448 }
8449 return false;
8450 }
8451
8452 static bool cpu_has_work_POWER7(CPUState *cs)
8453 {
8454 PowerPCCPU *cpu = POWERPC_CPU(cs);
8455 CPUPPCState *env = &cpu->env;
8456
8457 if (cs->halted) {
8458 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8459 return false;
8460 }
8461 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8462 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8463 return true;
8464 }
8465 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8466 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8467 return true;
8468 }
8469 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8470 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8471 return true;
8472 }
8473 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8474 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8475 return true;
8476 }
8477 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8478 return true;
8479 }
8480 return false;
8481 } else {
8482 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8483 }
8484 }
8485
8486 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8487 {
8488 DeviceClass *dc = DEVICE_CLASS(oc);
8489 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8490 CPUClass *cc = CPU_CLASS(oc);
8491
8492 dc->fw_name = "PowerPC,POWER7";
8493 dc->desc = "POWER7";
8494 dc->props = powerpc_servercpu_properties;
8495 pcc->pvr_match = ppc_pvr_match_power7;
8496 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8497 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8498 pcc->init_proc = init_proc_POWER7;
8499 pcc->check_pow = check_pow_nocheck;
8500 cc->has_work = cpu_has_work_POWER7;
8501 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8502 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8503 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8504 PPC_FLOAT_FRSQRTES |
8505 PPC_FLOAT_STFIWX |
8506 PPC_FLOAT_EXT |
8507 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8508 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8509 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8510 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8511 PPC_SEGMENT_64B | PPC_SLBI |
8512 PPC_POPCNTB | PPC_POPCNTWD |
8513 PPC_CILDST;
8514 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8515 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8516 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8517 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8518 PPC2_PM_ISA206;
8519 pcc->msr_mask = (1ull << MSR_SF) |
8520 (1ull << MSR_VR) |
8521 (1ull << MSR_VSX) |
8522 (1ull << MSR_EE) |
8523 (1ull << MSR_PR) |
8524 (1ull << MSR_FP) |
8525 (1ull << MSR_ME) |
8526 (1ull << MSR_FE0) |
8527 (1ull << MSR_SE) |
8528 (1ull << MSR_DE) |
8529 (1ull << MSR_FE1) |
8530 (1ull << MSR_IR) |
8531 (1ull << MSR_DR) |
8532 (1ull << MSR_PMM) |
8533 (1ull << MSR_RI) |
8534 (1ull << MSR_LE);
8535 pcc->mmu_model = POWERPC_MMU_2_06;
8536 #if defined(CONFIG_SOFTMMU)
8537 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8538 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8539 #endif
8540 pcc->excp_model = POWERPC_EXCP_POWER7;
8541 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8542 pcc->bfd_mach = bfd_mach_ppc64;
8543 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8544 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8545 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8546 POWERPC_FLAG_VSX;
8547 pcc->l1_dcache_size = 0x8000;
8548 pcc->l1_icache_size = 0x8000;
8549 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8550 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
8551 }
8552
8553 static void init_proc_POWER8(CPUPPCState *env)
8554 {
8555 /* Common Registers */
8556 init_proc_book3s_common(env);
8557 gen_spr_sdr1(env);
8558 gen_spr_book3s_207_dbg(env);
8559
8560 /* POWER8 Specific Registers */
8561 gen_spr_book3s_ids(env);
8562 gen_spr_amr(env);
8563 gen_spr_iamr(env);
8564 gen_spr_book3s_purr(env);
8565 gen_spr_power5p_common(env);
8566 gen_spr_power5p_lpar(env);
8567 gen_spr_power5p_ear(env);
8568 gen_spr_power6_common(env);
8569 gen_spr_power6_dbg(env);
8570 gen_spr_power8_tce_address_control(env);
8571 gen_spr_power8_ids(env);
8572 gen_spr_power8_ebb(env);
8573 gen_spr_power8_fscr(env);
8574 gen_spr_power8_pmu_sup(env);
8575 gen_spr_power8_pmu_user(env);
8576 gen_spr_power8_tm(env);
8577 gen_spr_power8_pspb(env);
8578 gen_spr_vtb(env);
8579 gen_spr_power8_ic(env);
8580 gen_spr_power8_book4(env);
8581 gen_spr_power8_rpr(env);
8582
8583 /* env variables */
8584 env->dcache_line_size = 128;
8585 env->icache_line_size = 128;
8586
8587 /* Allocate hardware IRQ controller */
8588 init_excp_POWER8(env);
8589 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8590 }
8591
8592 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8593 {
8594 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8595 return true;
8596 }
8597 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8598 return true;
8599 }
8600 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8601 return true;
8602 }
8603 return false;
8604 }
8605
8606 static bool cpu_has_work_POWER8(CPUState *cs)
8607 {
8608 PowerPCCPU *cpu = POWERPC_CPU(cs);
8609 CPUPPCState *env = &cpu->env;
8610
8611 if (cs->halted) {
8612 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8613 return false;
8614 }
8615 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8616 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8617 return true;
8618 }
8619 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8620 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8621 return true;
8622 }
8623 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8624 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8625 return true;
8626 }
8627 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8628 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8629 return true;
8630 }
8631 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8632 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8633 return true;
8634 }
8635 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8636 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8637 return true;
8638 }
8639 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8640 return true;
8641 }
8642 return false;
8643 } else {
8644 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8645 }
8646 }
8647
8648 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8649 {
8650 DeviceClass *dc = DEVICE_CLASS(oc);
8651 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8652 CPUClass *cc = CPU_CLASS(oc);
8653
8654 dc->fw_name = "PowerPC,POWER8";
8655 dc->desc = "POWER8";
8656 dc->props = powerpc_servercpu_properties;
8657 pcc->pvr_match = ppc_pvr_match_power8;
8658 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8659 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8660 pcc->init_proc = init_proc_POWER8;
8661 pcc->check_pow = check_pow_nocheck;
8662 cc->has_work = cpu_has_work_POWER8;
8663 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8665 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8666 PPC_FLOAT_FRSQRTES |
8667 PPC_FLOAT_STFIWX |
8668 PPC_FLOAT_EXT |
8669 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8670 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8671 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8672 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8673 PPC_SEGMENT_64B | PPC_SLBI |
8674 PPC_POPCNTB | PPC_POPCNTWD |
8675 PPC_CILDST;
8676 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8677 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8678 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8679 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8680 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8681 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8682 PPC2_TM | PPC2_PM_ISA206;
8683 pcc->msr_mask = (1ull << MSR_SF) |
8684 (1ull << MSR_SHV) |
8685 (1ull << MSR_TM) |
8686 (1ull << MSR_VR) |
8687 (1ull << MSR_VSX) |
8688 (1ull << MSR_EE) |
8689 (1ull << MSR_PR) |
8690 (1ull << MSR_FP) |
8691 (1ull << MSR_ME) |
8692 (1ull << MSR_FE0) |
8693 (1ull << MSR_SE) |
8694 (1ull << MSR_DE) |
8695 (1ull << MSR_FE1) |
8696 (1ull << MSR_IR) |
8697 (1ull << MSR_DR) |
8698 (1ull << MSR_PMM) |
8699 (1ull << MSR_RI) |
8700 (1ull << MSR_TS0) |
8701 (1ull << MSR_TS1) |
8702 (1ull << MSR_LE);
8703 pcc->mmu_model = POWERPC_MMU_2_07;
8704 #if defined(CONFIG_SOFTMMU)
8705 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8706 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8707 #endif
8708 pcc->excp_model = POWERPC_EXCP_POWER8;
8709 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8710 pcc->bfd_mach = bfd_mach_ppc64;
8711 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8712 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8713 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8714 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8715 pcc->l1_dcache_size = 0x8000;
8716 pcc->l1_icache_size = 0x8000;
8717 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8718 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
8719 LPCR_P8_PECE3 | LPCR_P8_PECE4;
8720 }
8721
8722 #ifdef CONFIG_SOFTMMU
8723 /*
8724 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8725 * Encoded as array of int_32s in the form:
8726 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8727 * x -> AP encoding
8728 * y -> radix mode supported page size (encoded as a shift)
8729 */
8730 static struct ppc_radix_page_info POWER9_radix_page_info = {
8731 .count = 4,
8732 .entries = {
8733 0x0000000c, /* 4K - enc: 0x0 */
8734 0xa0000010, /* 64K - enc: 0x5 */
8735 0x20000015, /* 2M - enc: 0x1 */
8736 0x4000001e /* 1G - enc: 0x2 */
8737 }
8738 };
8739 #endif /* CONFIG_SOFTMMU */
8740
8741 static void init_proc_POWER9(CPUPPCState *env)
8742 {
8743 /* Common Registers */
8744 init_proc_book3s_common(env);
8745 gen_spr_book3s_207_dbg(env);
8746
8747 /* POWER8 Specific Registers */
8748 gen_spr_book3s_ids(env);
8749 gen_spr_amr(env);
8750 gen_spr_iamr(env);
8751 gen_spr_book3s_purr(env);
8752 gen_spr_power5p_common(env);
8753 gen_spr_power5p_lpar(env);
8754 gen_spr_power5p_ear(env);
8755 gen_spr_power6_common(env);
8756 gen_spr_power6_dbg(env);
8757 gen_spr_power8_tce_address_control(env);
8758 gen_spr_power8_ids(env);
8759 gen_spr_power8_ebb(env);
8760 gen_spr_power8_fscr(env);
8761 gen_spr_power8_pmu_sup(env);
8762 gen_spr_power8_pmu_user(env);
8763 gen_spr_power8_tm(env);
8764 gen_spr_power8_pspb(env);
8765 gen_spr_vtb(env);
8766 gen_spr_power8_ic(env);
8767 gen_spr_power8_book4(env);
8768 gen_spr_power8_rpr(env);
8769 gen_spr_power9_mmu(env);
8770
8771 /* POWER9 Specific registers */
8772 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
8773 spr_read_generic, spr_write_generic,
8774 KVM_REG_PPC_TIDR, 0);
8775
8776 /* FIXME: Filter fields properly based on privilege level */
8777 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8778 spr_read_generic, spr_write_generic,
8779 KVM_REG_PPC_PSSCR, 0);
8780
8781 /* env variables */
8782 env->dcache_line_size = 128;
8783 env->icache_line_size = 128;
8784
8785 /* Allocate hardware IRQ controller */
8786 init_excp_POWER8(env);
8787 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8788 }
8789
8790 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8791 {
8792 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8793 return true;
8794 }
8795 return false;
8796 }
8797
8798 static bool cpu_has_work_POWER9(CPUState *cs)
8799 {
8800 PowerPCCPU *cpu = POWERPC_CPU(cs);
8801 CPUPPCState *env = &cpu->env;
8802
8803 if (cs->halted) {
8804 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8805 return false;
8806 }
8807 /* External Exception */
8808 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8809 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8810 return true;
8811 }
8812 /* Decrementer Exception */
8813 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8814 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8815 return true;
8816 }
8817 /* Machine Check or Hypervisor Maintenance Exception */
8818 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8819 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8820 return true;
8821 }
8822 /* Privileged Doorbell Exception */
8823 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8824 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8825 return true;
8826 }
8827 /* Hypervisor Doorbell Exception */
8828 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8829 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8830 return true;
8831 }
8832 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8833 return true;
8834 }
8835 return false;
8836 } else {
8837 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8838 }
8839 }
8840
8841 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8842 {
8843 DeviceClass *dc = DEVICE_CLASS(oc);
8844 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8845 CPUClass *cc = CPU_CLASS(oc);
8846
8847 dc->fw_name = "PowerPC,POWER9";
8848 dc->desc = "POWER9";
8849 dc->props = powerpc_servercpu_properties;
8850 pcc->pvr_match = ppc_pvr_match_power9;
8851 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8852 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8853 PCR_COMPAT_2_05;
8854 pcc->init_proc = init_proc_POWER9;
8855 pcc->check_pow = check_pow_nocheck;
8856 cc->has_work = cpu_has_work_POWER9;
8857 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8858 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8859 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8860 PPC_FLOAT_FRSQRTES |
8861 PPC_FLOAT_STFIWX |
8862 PPC_FLOAT_EXT |
8863 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8864 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8865 PPC_MEM_TLBSYNC |
8866 PPC_64B | PPC_64BX | PPC_ALTIVEC |
8867 PPC_SEGMENT_64B | PPC_SLBI |
8868 PPC_POPCNTB | PPC_POPCNTWD |
8869 PPC_CILDST;
8870 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8871 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8872 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8873 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8874 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8875 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8876 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8877 pcc->msr_mask = (1ull << MSR_SF) |
8878 (1ull << MSR_TM) |
8879 (1ull << MSR_VR) |
8880 (1ull << MSR_VSX) |
8881 (1ull << MSR_EE) |
8882 (1ull << MSR_PR) |
8883 (1ull << MSR_FP) |
8884 (1ull << MSR_ME) |
8885 (1ull << MSR_FE0) |
8886 (1ull << MSR_SE) |
8887 (1ull << MSR_DE) |
8888 (1ull << MSR_FE1) |
8889 (1ull << MSR_IR) |
8890 (1ull << MSR_DR) |
8891 (1ull << MSR_PMM) |
8892 (1ull << MSR_RI) |
8893 (1ull << MSR_LE);
8894 pcc->mmu_model = POWERPC_MMU_3_00;
8895 #if defined(CONFIG_SOFTMMU)
8896 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8897 /* segment page size remain the same */
8898 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8899 pcc->radix_page_info = &POWER9_radix_page_info;
8900 #endif
8901 pcc->excp_model = POWERPC_EXCP_POWER8;
8902 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8903 pcc->bfd_mach = bfd_mach_ppc64;
8904 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8905 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8906 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8907 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8908 pcc->l1_dcache_size = 0x8000;
8909 pcc->l1_icache_size = 0x8000;
8910 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8911 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8912 }
8913
8914 #if !defined(CONFIG_USER_ONLY)
8915 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8916 {
8917 CPUPPCState *env = &cpu->env;
8918
8919 cpu->vhyp = vhyp;
8920
8921 /*
8922 * With a virtual hypervisor mode we never allow the CPU to go
8923 * hypervisor mode itself
8924 */
8925 env->msr_mask &= ~MSR_HVB;
8926 }
8927
8928 #endif /* !defined(CONFIG_USER_ONLY) */
8929
8930 #endif /* defined(TARGET_PPC64) */
8931
8932 /*****************************************************************************/
8933 /* Generic CPU instantiation routine */
8934 static void init_ppc_proc(PowerPCCPU *cpu)
8935 {
8936 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8937 CPUPPCState *env = &cpu->env;
8938 #if !defined(CONFIG_USER_ONLY)
8939 int i;
8940
8941 env->irq_inputs = NULL;
8942 /* Set all exception vectors to an invalid address */
8943 for (i = 0; i < POWERPC_EXCP_NB; i++)
8944 env->excp_vectors[i] = (target_ulong)(-1ULL);
8945 env->ivor_mask = 0x00000000;
8946 env->ivpr_mask = 0x00000000;
8947 /* Default MMU definitions */
8948 env->nb_BATs = 0;
8949 env->nb_tlb = 0;
8950 env->nb_ways = 0;
8951 env->tlb_type = TLB_NONE;
8952 #endif
8953 /* Register SPR common to all PowerPC implementations */
8954 gen_spr_generic(env);
8955 spr_register(env, SPR_PVR, "PVR",
8956 /* Linux permits userspace to read PVR */
8957 #if defined(CONFIG_LINUX_USER)
8958 &spr_read_generic,
8959 #else
8960 SPR_NOACCESS,
8961 #endif
8962 SPR_NOACCESS,
8963 &spr_read_generic, SPR_NOACCESS,
8964 pcc->pvr);
8965 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8966 if (pcc->svr != POWERPC_SVR_NONE) {
8967 if (pcc->svr & POWERPC_SVR_E500) {
8968 spr_register(env, SPR_E500_SVR, "SVR",
8969 SPR_NOACCESS, SPR_NOACCESS,
8970 &spr_read_generic, SPR_NOACCESS,
8971 pcc->svr & ~POWERPC_SVR_E500);
8972 } else {
8973 spr_register(env, SPR_SVR, "SVR",
8974 SPR_NOACCESS, SPR_NOACCESS,
8975 &spr_read_generic, SPR_NOACCESS,
8976 pcc->svr);
8977 }
8978 }
8979 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8980 (*pcc->init_proc)(env);
8981
8982 #if !defined(CONFIG_USER_ONLY)
8983 ppc_gdb_gen_spr_xml(cpu);
8984 #endif
8985
8986 /* MSR bits & flags consistency checks */
8987 if (env->msr_mask & (1 << 25)) {
8988 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8989 case POWERPC_FLAG_SPE:
8990 case POWERPC_FLAG_VRE:
8991 break;
8992 default:
8993 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8994 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8995 exit(1);
8996 }
8997 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8998 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8999 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9000 exit(1);
9001 }
9002 if (env->msr_mask & (1 << 17)) {
9003 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9004 case POWERPC_FLAG_TGPR:
9005 case POWERPC_FLAG_CE:
9006 break;
9007 default:
9008 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9009 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9010 exit(1);
9011 }
9012 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9013 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9014 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9015 exit(1);
9016 }
9017 if (env->msr_mask & (1 << 10)) {
9018 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9019 POWERPC_FLAG_UBLE)) {
9020 case POWERPC_FLAG_SE:
9021 case POWERPC_FLAG_DWE:
9022 case POWERPC_FLAG_UBLE:
9023 break;
9024 default:
9025 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9026 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9027 "POWERPC_FLAG_UBLE\n");
9028 exit(1);
9029 }
9030 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9031 POWERPC_FLAG_UBLE)) {
9032 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9033 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9034 "POWERPC_FLAG_UBLE\n");
9035 exit(1);
9036 }
9037 if (env->msr_mask & (1 << 9)) {
9038 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9039 case POWERPC_FLAG_BE:
9040 case POWERPC_FLAG_DE:
9041 break;
9042 default:
9043 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9044 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9045 exit(1);
9046 }
9047 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9048 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9049 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9050 exit(1);
9051 }
9052 if (env->msr_mask & (1 << 2)) {
9053 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9054 case POWERPC_FLAG_PX:
9055 case POWERPC_FLAG_PMM:
9056 break;
9057 default:
9058 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9059 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9060 exit(1);
9061 }
9062 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9063 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9064 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9065 exit(1);
9066 }
9067 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9068 fprintf(stderr, "PowerPC flags inconsistency\n"
9069 "Should define the time-base and decrementer clock source\n");
9070 exit(1);
9071 }
9072 /* Allocate TLBs buffer when needed */
9073 #if !defined(CONFIG_USER_ONLY)
9074 if (env->nb_tlb != 0) {
9075 int nb_tlb = env->nb_tlb;
9076 if (env->id_tlbs != 0)
9077 nb_tlb *= 2;
9078 switch (env->tlb_type) {
9079 case TLB_6XX:
9080 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
9081 break;
9082 case TLB_EMB:
9083 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
9084 break;
9085 case TLB_MAS:
9086 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
9087 break;
9088 }
9089 /* Pre-compute some useful values */
9090 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9091 }
9092 if (env->irq_inputs == NULL) {
9093 warn_report("no internal IRQ controller registered."
9094 " Attempt QEMU to crash very soon !");
9095 }
9096 #endif
9097 if (env->check_pow == NULL) {
9098 warn_report("no power management check handler registered."
9099 " Attempt QEMU to crash very soon !");
9100 }
9101 }
9102
9103 #if defined(PPC_DUMP_CPU)
9104 static void dump_ppc_sprs(CPUPPCState *env)
9105 {
9106 ppc_spr_t *spr;
9107 #if !defined(CONFIG_USER_ONLY)
9108 uint32_t sr, sw;
9109 #endif
9110 uint32_t ur, uw;
9111 int i, j, n;
9112
9113 printf("Special purpose registers:\n");
9114 for (i = 0; i < 32; i++) {
9115 for (j = 0; j < 32; j++) {
9116 n = (i << 5) | j;
9117 spr = &env->spr_cb[n];
9118 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9119 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9120 #if !defined(CONFIG_USER_ONLY)
9121 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9122 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9123 if (sw || sr || uw || ur) {
9124 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9125 (i << 5) | j, (i << 5) | j, spr->name,
9126 sw ? 'w' : '-', sr ? 'r' : '-',
9127 uw ? 'w' : '-', ur ? 'r' : '-');
9128 }
9129 #else
9130 if (uw || ur) {
9131 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9132 (i << 5) | j, (i << 5) | j, spr->name,
9133 uw ? 'w' : '-', ur ? 'r' : '-');
9134 }
9135 #endif
9136 }
9137 }
9138 fflush(stdout);
9139 fflush(stderr);
9140 }
9141 #endif
9142
9143 /*****************************************************************************/
9144
9145 /* Opcode types */
9146 enum {
9147 PPC_DIRECT = 0, /* Opcode routine */
9148 PPC_INDIRECT = 1, /* Indirect opcode table */
9149 };
9150
9151 #define PPC_OPCODE_MASK 0x3
9152
9153 static inline int is_indirect_opcode(void *handler)
9154 {
9155 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
9156 }
9157
9158 static inline opc_handler_t **ind_table(void *handler)
9159 {
9160 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
9161 }
9162
9163 /* Instruction table creation */
9164 /* Opcodes tables creation */
9165 static void fill_new_table(opc_handler_t **table, int len)
9166 {
9167 int i;
9168
9169 for (i = 0; i < len; i++)
9170 table[i] = &invalid_handler;
9171 }
9172
9173 static int create_new_table(opc_handler_t **table, unsigned char idx)
9174 {
9175 opc_handler_t **tmp;
9176
9177 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9178 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
9179 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9180
9181 return 0;
9182 }
9183
9184 static int insert_in_table(opc_handler_t **table, unsigned char idx,
9185 opc_handler_t *handler)
9186 {
9187 if (table[idx] != &invalid_handler)
9188 return -1;
9189 table[idx] = handler;
9190
9191 return 0;
9192 }
9193
9194 static int register_direct_insn(opc_handler_t **ppc_opcodes,
9195 unsigned char idx, opc_handler_t *handler)
9196 {
9197 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9198 printf("*** ERROR: opcode %02x already assigned in main "
9199 "opcode table\n", idx);
9200 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9201 printf(" Registered handler '%s' - new handler '%s'\n",
9202 ppc_opcodes[idx]->oname, handler->oname);
9203 #endif
9204 return -1;
9205 }
9206
9207 return 0;
9208 }
9209
9210 static int register_ind_in_table(opc_handler_t **table,
9211 unsigned char idx1, unsigned char idx2,
9212 opc_handler_t *handler)
9213 {
9214 if (table[idx1] == &invalid_handler) {
9215 if (create_new_table(table, idx1) < 0) {
9216 printf("*** ERROR: unable to create indirect table "
9217 "idx=%02x\n", idx1);
9218 return -1;
9219 }
9220 } else {
9221 if (!is_indirect_opcode(table[idx1])) {
9222 printf("*** ERROR: idx %02x already assigned to a direct "
9223 "opcode\n", idx1);
9224 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9225 printf(" Registered handler '%s' - new handler '%s'\n",
9226 ind_table(table[idx1])[idx2]->oname, handler->oname);
9227 #endif
9228 return -1;
9229 }
9230 }
9231 if (handler != NULL &&
9232 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9233 printf("*** ERROR: opcode %02x already assigned in "
9234 "opcode table %02x\n", idx2, idx1);
9235 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9236 printf(" Registered handler '%s' - new handler '%s'\n",
9237 ind_table(table[idx1])[idx2]->oname, handler->oname);
9238 #endif
9239 return -1;
9240 }
9241
9242 return 0;
9243 }
9244
9245 static int register_ind_insn(opc_handler_t **ppc_opcodes,
9246 unsigned char idx1, unsigned char idx2,
9247 opc_handler_t *handler)
9248 {
9249 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9250 }
9251
9252 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
9253 unsigned char idx1, unsigned char idx2,
9254 unsigned char idx3, opc_handler_t *handler)
9255 {
9256 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9257 printf("*** ERROR: unable to join indirect table idx "
9258 "[%02x-%02x]\n", idx1, idx2);
9259 return -1;
9260 }
9261 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9262 handler) < 0) {
9263 printf("*** ERROR: unable to insert opcode "
9264 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9265 return -1;
9266 }
9267
9268 return 0;
9269 }
9270
9271 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9272 unsigned char idx1, unsigned char idx2,
9273 unsigned char idx3, unsigned char idx4,
9274 opc_handler_t *handler)
9275 {
9276 opc_handler_t **table;
9277
9278 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9279 printf("*** ERROR: unable to join indirect table idx "
9280 "[%02x-%02x]\n", idx1, idx2);
9281 return -1;
9282 }
9283 table = ind_table(ppc_opcodes[idx1]);
9284 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9285 printf("*** ERROR: unable to join 2nd-level indirect table idx "
9286 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9287 return -1;
9288 }
9289 table = ind_table(table[idx2]);
9290 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9291 printf("*** ERROR: unable to insert opcode "
9292 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9293 return -1;
9294 }
9295 return 0;
9296 }
9297 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
9298 {
9299 if (insn->opc2 != 0xFF) {
9300 if (insn->opc3 != 0xFF) {
9301 if (insn->opc4 != 0xFF) {
9302 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9303 insn->opc3, insn->opc4,
9304 &insn->handler) < 0) {
9305 return -1;
9306 }
9307 } else {
9308 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9309 insn->opc3, &insn->handler) < 0)
9310 return -1;
9311 }
9312 } else {
9313 if (register_ind_insn(ppc_opcodes, insn->opc1,
9314 insn->opc2, &insn->handler) < 0)
9315 return -1;
9316 }
9317 } else {
9318 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9319 return -1;
9320 }
9321
9322 return 0;
9323 }
9324
9325 static int test_opcode_table(opc_handler_t **table, int len)
9326 {
9327 int i, count, tmp;
9328
9329 for (i = 0, count = 0; i < len; i++) {
9330 /* Consistency fixup */
9331 if (table[i] == NULL)
9332 table[i] = &invalid_handler;
9333 if (table[i] != &invalid_handler) {
9334 if (is_indirect_opcode(table[i])) {
9335 tmp = test_opcode_table(ind_table(table[i]),
9336 PPC_CPU_INDIRECT_OPCODES_LEN);
9337 if (tmp == 0) {
9338 free(table[i]);
9339 table[i] = &invalid_handler;
9340 } else {
9341 count++;
9342 }
9343 } else {
9344 count++;
9345 }
9346 }
9347 }
9348
9349 return count;
9350 }
9351
9352 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9353 {
9354 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
9355 printf("*** WARNING: no opcode defined !\n");
9356 }
9357
9358 /*****************************************************************************/
9359 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9360 {
9361 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9362 CPUPPCState *env = &cpu->env;
9363 opcode_t *opc;
9364
9365 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
9366 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9367 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9368 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9369 if (register_insn(env->opcodes, opc) < 0) {
9370 error_setg(errp, "ERROR initializing PowerPC instruction "
9371 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9372 opc->opc3);
9373 return;
9374 }
9375 }
9376 }
9377 fix_opcode_tables(env->opcodes);
9378 fflush(stdout);
9379 fflush(stderr);
9380 }
9381
9382 #if defined(PPC_DUMP_CPU)
9383 static void dump_ppc_insns(CPUPPCState *env)
9384 {
9385 opc_handler_t **table, *handler;
9386 const char *p, *q;
9387 uint8_t opc1, opc2, opc3, opc4;
9388
9389 printf("Instructions set:\n");
9390 /* opc1 is 6 bits long */
9391 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9392 table = env->opcodes;
9393 handler = table[opc1];
9394 if (is_indirect_opcode(handler)) {
9395 /* opc2 is 5 bits long */
9396 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9397 table = env->opcodes;
9398 handler = env->opcodes[opc1];
9399 table = ind_table(handler);
9400 handler = table[opc2];
9401 if (is_indirect_opcode(handler)) {
9402 table = ind_table(handler);
9403 /* opc3 is 5 bits long */
9404 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9405 opc3++) {
9406 handler = table[opc3];
9407 if (is_indirect_opcode(handler)) {
9408 table = ind_table(handler);
9409 /* opc4 is 5 bits long */
9410 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9411 opc4++) {
9412 handler = table[opc4];
9413 if (handler->handler != &gen_invalid) {
9414 printf("INSN: %02x %02x %02x %02x -- "
9415 "(%02d %04d %02d) : %s\n",
9416 opc1, opc2, opc3, opc4,
9417 opc1, (opc3 << 5) | opc2, opc4,
9418 handler->oname);
9419 }
9420 }
9421 } else {
9422 if (handler->handler != &gen_invalid) {
9423 /* Special hack to properly dump SPE insns */
9424 p = strchr(handler->oname, '_');
9425 if (p == NULL) {
9426 printf("INSN: %02x %02x %02x (%02d %04d) : "
9427 "%s\n",
9428 opc1, opc2, opc3, opc1,
9429 (opc3 << 5) | opc2,
9430 handler->oname);
9431 } else {
9432 q = "speundef";
9433 if ((p - handler->oname) != strlen(q)
9434 || (memcmp(handler->oname, q, strlen(q))
9435 != 0)) {
9436 /* First instruction */
9437 printf("INSN: %02x %02x %02x"
9438 "(%02d %04d) : %.*s\n",
9439 opc1, opc2 << 1, opc3, opc1,
9440 (opc3 << 6) | (opc2 << 1),
9441 (int)(p - handler->oname),
9442 handler->oname);
9443 }
9444 if (strcmp(p + 1, q) != 0) {
9445 /* Second instruction */
9446 printf("INSN: %02x %02x %02x "
9447 "(%02d %04d) : %s\n", opc1,
9448 (opc2 << 1) | 1, opc3, opc1,
9449 (opc3 << 6) | (opc2 << 1) | 1,
9450 p + 1);
9451 }
9452 }
9453 }
9454 }
9455 }
9456 } else {
9457 if (handler->handler != &gen_invalid) {
9458 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9459 opc1, opc2, opc1, opc2, handler->oname);
9460 }
9461 }
9462 }
9463 } else {
9464 if (handler->handler != &gen_invalid) {
9465 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9466 opc1, opc1, handler->oname);
9467 }
9468 }
9469 }
9470 }
9471 #endif
9472
9473 static bool avr_need_swap(CPUPPCState *env)
9474 {
9475 #ifdef HOST_WORDS_BIGENDIAN
9476 return msr_le;
9477 #else
9478 return !msr_le;
9479 #endif
9480 }
9481
9482 #if !defined(CONFIG_USER_ONLY)
9483 static int gdb_find_spr_idx(CPUPPCState *env, int n)
9484 {
9485 int i;
9486
9487 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9488 ppc_spr_t *spr = &env->spr_cb[i];
9489
9490 if (spr->name && spr->gdb_id == n) {
9491 return i;
9492 }
9493 }
9494 return -1;
9495 }
9496
9497 static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9498 {
9499 int reg;
9500 int len;
9501
9502 reg = gdb_find_spr_idx(env, n);
9503 if (reg < 0) {
9504 return 0;
9505 }
9506
9507 len = TARGET_LONG_SIZE;
9508 stn_p(mem_buf, len, env->spr[reg]);
9509 ppc_maybe_bswap_register(env, mem_buf, len);
9510 return len;
9511 }
9512
9513 static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9514 {
9515 int reg;
9516 int len;
9517
9518 reg = gdb_find_spr_idx(env, n);
9519 if (reg < 0) {
9520 return 0;
9521 }
9522
9523 len = TARGET_LONG_SIZE;
9524 ppc_maybe_bswap_register(env, mem_buf, len);
9525 env->spr[reg] = ldn_p(mem_buf, len);
9526
9527 return len;
9528 }
9529 #endif
9530
9531 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9532 {
9533 if (n < 32) {
9534 stfq_p(mem_buf, *cpu_fpr_ptr(env, n));
9535 ppc_maybe_bswap_register(env, mem_buf, 8);
9536 return 8;
9537 }
9538 if (n == 32) {
9539 stl_p(mem_buf, env->fpscr);
9540 ppc_maybe_bswap_register(env, mem_buf, 4);
9541 return 4;
9542 }
9543 return 0;
9544 }
9545
9546 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9547 {
9548 if (n < 32) {
9549 ppc_maybe_bswap_register(env, mem_buf, 8);
9550 *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf);
9551 return 8;
9552 }
9553 if (n == 32) {
9554 ppc_maybe_bswap_register(env, mem_buf, 4);
9555 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9556 return 4;
9557 }
9558 return 0;
9559 }
9560
9561 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9562 {
9563 if (n < 32) {
9564 ppc_avr_t *avr = cpu_avr_ptr(env, n);
9565 if (!avr_need_swap(env)) {
9566 stq_p(mem_buf, avr->u64[0]);
9567 stq_p(mem_buf + 8, avr->u64[1]);
9568 } else {
9569 stq_p(mem_buf, avr->u64[1]);
9570 stq_p(mem_buf + 8, avr->u64[0]);
9571 }
9572 ppc_maybe_bswap_register(env, mem_buf, 8);
9573 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9574 return 16;
9575 }
9576 if (n == 32) {
9577 stl_p(mem_buf, helper_mfvscr(env));
9578 ppc_maybe_bswap_register(env, mem_buf, 4);
9579 return 4;
9580 }
9581 if (n == 33) {
9582 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9583 ppc_maybe_bswap_register(env, mem_buf, 4);
9584 return 4;
9585 }
9586 return 0;
9587 }
9588
9589 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9590 {
9591 if (n < 32) {
9592 ppc_avr_t *avr = cpu_avr_ptr(env, n);
9593 ppc_maybe_bswap_register(env, mem_buf, 8);
9594 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9595 if (!avr_need_swap(env)) {
9596 avr->u64[0] = ldq_p(mem_buf);
9597 avr->u64[1] = ldq_p(mem_buf + 8);
9598 } else {
9599 avr->u64[1] = ldq_p(mem_buf);
9600 avr->u64[0] = ldq_p(mem_buf + 8);
9601 }
9602 return 16;
9603 }
9604 if (n == 32) {
9605 ppc_maybe_bswap_register(env, mem_buf, 4);
9606 helper_mtvscr(env, ldl_p(mem_buf));
9607 return 4;
9608 }
9609 if (n == 33) {
9610 ppc_maybe_bswap_register(env, mem_buf, 4);
9611 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9612 return 4;
9613 }
9614 return 0;
9615 }
9616
9617 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9618 {
9619 if (n < 32) {
9620 #if defined(TARGET_PPC64)
9621 stl_p(mem_buf, env->gpr[n] >> 32);
9622 ppc_maybe_bswap_register(env, mem_buf, 4);
9623 #else
9624 stl_p(mem_buf, env->gprh[n]);
9625 #endif
9626 return 4;
9627 }
9628 if (n == 32) {
9629 stq_p(mem_buf, env->spe_acc);
9630 ppc_maybe_bswap_register(env, mem_buf, 8);
9631 return 8;
9632 }
9633 if (n == 33) {
9634 stl_p(mem_buf, env->spe_fscr);
9635 ppc_maybe_bswap_register(env, mem_buf, 4);
9636 return 4;
9637 }
9638 return 0;
9639 }
9640
9641 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9642 {
9643 if (n < 32) {
9644 #if defined(TARGET_PPC64)
9645 target_ulong lo = (uint32_t)env->gpr[n];
9646 target_ulong hi;
9647
9648 ppc_maybe_bswap_register(env, mem_buf, 4);
9649
9650 hi = (target_ulong)ldl_p(mem_buf) << 32;
9651 env->gpr[n] = lo | hi;
9652 #else
9653 env->gprh[n] = ldl_p(mem_buf);
9654 #endif
9655 return 4;
9656 }
9657 if (n == 32) {
9658 ppc_maybe_bswap_register(env, mem_buf, 8);
9659 env->spe_acc = ldq_p(mem_buf);
9660 return 8;
9661 }
9662 if (n == 33) {
9663 ppc_maybe_bswap_register(env, mem_buf, 4);
9664 env->spe_fscr = ldl_p(mem_buf);
9665 return 4;
9666 }
9667 return 0;
9668 }
9669
9670 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9671 {
9672 if (n < 32) {
9673 stq_p(mem_buf, *cpu_vsrl_ptr(env, n));
9674 ppc_maybe_bswap_register(env, mem_buf, 8);
9675 return 8;
9676 }
9677 return 0;
9678 }
9679
9680 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9681 {
9682 if (n < 32) {
9683 ppc_maybe_bswap_register(env, mem_buf, 8);
9684 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
9685 return 8;
9686 }
9687 return 0;
9688 }
9689
9690 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9691 {
9692 CPUPPCState *env = &cpu->env;
9693
9694 /* TCG doesn't (yet) emulate some groups of instructions that
9695 * are implemented on some otherwise supported CPUs (e.g. VSX
9696 * and decimal floating point instructions on POWER7). We
9697 * remove unsupported instruction groups from the cpu state's
9698 * instruction masks and hope the guest can cope. For at
9699 * least the pseries machine, the unavailability of these
9700 * instructions can be advertised to the guest via the device
9701 * tree. */
9702 if ((env->insns_flags & ~PPC_TCG_INSNS)
9703 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9704 warn_report("Disabling some instructions which are not "
9705 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9706 env->insns_flags & ~PPC_TCG_INSNS,
9707 env->insns_flags2 & ~PPC_TCG_INSNS2);
9708 }
9709 env->insns_flags &= PPC_TCG_INSNS;
9710 env->insns_flags2 &= PPC_TCG_INSNS2;
9711 return 0;
9712 }
9713
9714 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
9715 {
9716 CPUState *cs = CPU(dev);
9717 PowerPCCPU *cpu = POWERPC_CPU(dev);
9718 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9719 Error *local_err = NULL;
9720
9721 cpu_exec_realizefn(cs, &local_err);
9722 if (local_err != NULL) {
9723 error_propagate(errp, local_err);
9724 return;
9725 }
9726 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
9727 cpu->vcpu_id = cs->cpu_index;
9728 }
9729
9730 if (tcg_enabled()) {
9731 if (ppc_fixup_cpu(cpu) != 0) {
9732 error_setg(errp, "Unable to emulate selected CPU with TCG");
9733 goto unrealize;
9734 }
9735 }
9736
9737 create_ppc_opcodes(cpu, &local_err);
9738 if (local_err != NULL) {
9739 error_propagate(errp, local_err);
9740 goto unrealize;
9741 }
9742 init_ppc_proc(cpu);
9743
9744 if (pcc->insns_flags & PPC_FLOAT) {
9745 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9746 33, "power-fpu.xml", 0);
9747 }
9748 if (pcc->insns_flags & PPC_ALTIVEC) {
9749 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9750 34, "power-altivec.xml", 0);
9751 }
9752 if (pcc->insns_flags & PPC_SPE) {
9753 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9754 34, "power-spe.xml", 0);
9755 }
9756 if (pcc->insns_flags2 & PPC2_VSX) {
9757 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9758 32, "power-vsx.xml", 0);
9759 }
9760 #ifndef CONFIG_USER_ONLY
9761 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
9762 pcc->gdb_num_sprs, "power-spr.xml", 0);
9763 #endif
9764 qemu_init_vcpu(cs);
9765
9766 pcc->parent_realize(dev, errp);
9767
9768 #if defined(PPC_DUMP_CPU)
9769 {
9770 CPUPPCState *env = &cpu->env;
9771 const char *mmu_model, *excp_model, *bus_model;
9772 switch (env->mmu_model) {
9773 case POWERPC_MMU_32B:
9774 mmu_model = "PowerPC 32";
9775 break;
9776 case POWERPC_MMU_SOFT_6xx:
9777 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9778 break;
9779 case POWERPC_MMU_SOFT_74xx:
9780 mmu_model = "PowerPC 74xx with software driven TLBs";
9781 break;
9782 case POWERPC_MMU_SOFT_4xx:
9783 mmu_model = "PowerPC 4xx with software driven TLBs";
9784 break;
9785 case POWERPC_MMU_SOFT_4xx_Z:
9786 mmu_model = "PowerPC 4xx with software driven TLBs "
9787 "and zones protections";
9788 break;
9789 case POWERPC_MMU_REAL:
9790 mmu_model = "PowerPC real mode only";
9791 break;
9792 case POWERPC_MMU_MPC8xx:
9793 mmu_model = "PowerPC MPC8xx";
9794 break;
9795 case POWERPC_MMU_BOOKE:
9796 mmu_model = "PowerPC BookE";
9797 break;
9798 case POWERPC_MMU_BOOKE206:
9799 mmu_model = "PowerPC BookE 2.06";
9800 break;
9801 case POWERPC_MMU_601:
9802 mmu_model = "PowerPC 601";
9803 break;
9804 #if defined(TARGET_PPC64)
9805 case POWERPC_MMU_64B:
9806 mmu_model = "PowerPC 64";
9807 break;
9808 #endif
9809 default:
9810 mmu_model = "Unknown or invalid";
9811 break;
9812 }
9813 switch (env->excp_model) {
9814 case POWERPC_EXCP_STD:
9815 excp_model = "PowerPC";
9816 break;
9817 case POWERPC_EXCP_40x:
9818 excp_model = "PowerPC 40x";
9819 break;
9820 case POWERPC_EXCP_601:
9821 excp_model = "PowerPC 601";
9822 break;
9823 case POWERPC_EXCP_602:
9824 excp_model = "PowerPC 602";
9825 break;
9826 case POWERPC_EXCP_603:
9827 excp_model = "PowerPC 603";
9828 break;
9829 case POWERPC_EXCP_603E:
9830 excp_model = "PowerPC 603e";
9831 break;
9832 case POWERPC_EXCP_604:
9833 excp_model = "PowerPC 604";
9834 break;
9835 case POWERPC_EXCP_7x0:
9836 excp_model = "PowerPC 740/750";
9837 break;
9838 case POWERPC_EXCP_7x5:
9839 excp_model = "PowerPC 745/755";
9840 break;
9841 case POWERPC_EXCP_74xx:
9842 excp_model = "PowerPC 74xx";
9843 break;
9844 case POWERPC_EXCP_BOOKE:
9845 excp_model = "PowerPC BookE";
9846 break;
9847 #if defined(TARGET_PPC64)
9848 case POWERPC_EXCP_970:
9849 excp_model = "PowerPC 970";
9850 break;
9851 #endif
9852 default:
9853 excp_model = "Unknown or invalid";
9854 break;
9855 }
9856 switch (env->bus_model) {
9857 case PPC_FLAGS_INPUT_6xx:
9858 bus_model = "PowerPC 6xx";
9859 break;
9860 case PPC_FLAGS_INPUT_BookE:
9861 bus_model = "PowerPC BookE";
9862 break;
9863 case PPC_FLAGS_INPUT_405:
9864 bus_model = "PowerPC 405";
9865 break;
9866 case PPC_FLAGS_INPUT_401:
9867 bus_model = "PowerPC 401/403";
9868 break;
9869 case PPC_FLAGS_INPUT_RCPU:
9870 bus_model = "RCPU / MPC8xx";
9871 break;
9872 #if defined(TARGET_PPC64)
9873 case PPC_FLAGS_INPUT_970:
9874 bus_model = "PowerPC 970";
9875 break;
9876 #endif
9877 default:
9878 bus_model = "Unknown or invalid";
9879 break;
9880 }
9881 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9882 " MMU model : %s\n",
9883 object_class_get_name(OBJECT_CLASS(pcc)),
9884 pcc->pvr, pcc->msr_mask, mmu_model);
9885 #if !defined(CONFIG_USER_ONLY)
9886 if (env->tlb.tlb6) {
9887 printf(" %d %s TLB in %d ways\n",
9888 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9889 env->nb_ways);
9890 }
9891 #endif
9892 printf(" Exceptions model : %s\n"
9893 " Bus model : %s\n",
9894 excp_model, bus_model);
9895 printf(" MSR features :\n");
9896 if (env->flags & POWERPC_FLAG_SPE)
9897 printf(" signal processing engine enable"
9898 "\n");
9899 else if (env->flags & POWERPC_FLAG_VRE)
9900 printf(" vector processor enable\n");
9901 if (env->flags & POWERPC_FLAG_TGPR)
9902 printf(" temporary GPRs\n");
9903 else if (env->flags & POWERPC_FLAG_CE)
9904 printf(" critical input enable\n");
9905 if (env->flags & POWERPC_FLAG_SE)
9906 printf(" single-step trace mode\n");
9907 else if (env->flags & POWERPC_FLAG_DWE)
9908 printf(" debug wait enable\n");
9909 else if (env->flags & POWERPC_FLAG_UBLE)
9910 printf(" user BTB lock enable\n");
9911 if (env->flags & POWERPC_FLAG_BE)
9912 printf(" branch-step trace mode\n");
9913 else if (env->flags & POWERPC_FLAG_DE)
9914 printf(" debug interrupt enable\n");
9915 if (env->flags & POWERPC_FLAG_PX)
9916 printf(" inclusive protection\n");
9917 else if (env->flags & POWERPC_FLAG_PMM)
9918 printf(" performance monitor mark\n");
9919 if (env->flags == POWERPC_FLAG_NONE)
9920 printf(" none\n");
9921 printf(" Time-base/decrementer clock source: %s\n",
9922 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9923 dump_ppc_insns(env);
9924 dump_ppc_sprs(env);
9925 fflush(stdout);
9926 }
9927 #endif
9928 return;
9929
9930 unrealize:
9931 cpu_exec_unrealizefn(cs);
9932 }
9933
9934 static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
9935 {
9936 PowerPCCPU *cpu = POWERPC_CPU(dev);
9937 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9938 CPUPPCState *env = &cpu->env;
9939 Error *local_err = NULL;
9940 opc_handler_t **table, **table_2;
9941 int i, j, k;
9942
9943 pcc->parent_unrealize(dev, &local_err);
9944 if (local_err != NULL) {
9945 error_propagate(errp, local_err);
9946 return;
9947 }
9948
9949 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9950 if (env->opcodes[i] == &invalid_handler) {
9951 continue;
9952 }
9953 if (is_indirect_opcode(env->opcodes[i])) {
9954 table = ind_table(env->opcodes[i]);
9955 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9956 if (table[j] == &invalid_handler) {
9957 continue;
9958 }
9959 if (is_indirect_opcode(table[j])) {
9960 table_2 = ind_table(table[j]);
9961 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
9962 if (table_2[k] != &invalid_handler &&
9963 is_indirect_opcode(table_2[k])) {
9964 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
9965 ~PPC_INDIRECT));
9966 }
9967 }
9968 g_free((opc_handler_t *)((uintptr_t)table[j] &
9969 ~PPC_INDIRECT));
9970 }
9971 }
9972 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
9973 ~PPC_INDIRECT));
9974 }
9975 }
9976 }
9977
9978 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9979 {
9980 ObjectClass *oc = (ObjectClass *)a;
9981 uint32_t pvr = *(uint32_t *)b;
9982 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9983
9984 /* -cpu host does a PVR lookup during construction */
9985 if (unlikely(strcmp(object_class_get_name(oc),
9986 TYPE_HOST_POWERPC_CPU) == 0)) {
9987 return -1;
9988 }
9989
9990 return pcc->pvr == pvr ? 0 : -1;
9991 }
9992
9993 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9994 {
9995 GSList *list, *item;
9996 PowerPCCPUClass *pcc = NULL;
9997
9998 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9999 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10000 if (item != NULL) {
10001 pcc = POWERPC_CPU_CLASS(item->data);
10002 }
10003 g_slist_free(list);
10004
10005 return pcc;
10006 }
10007
10008 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
10009 {
10010 ObjectClass *oc = (ObjectClass *)a;
10011 uint32_t pvr = *(uint32_t *)b;
10012 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10013
10014 /* -cpu host does a PVR lookup during construction */
10015 if (unlikely(strcmp(object_class_get_name(oc),
10016 TYPE_HOST_POWERPC_CPU) == 0)) {
10017 return -1;
10018 }
10019
10020 if (pcc->pvr_match(pcc, pvr)) {
10021 return 0;
10022 }
10023
10024 return -1;
10025 }
10026
10027 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
10028 {
10029 GSList *list, *item;
10030 PowerPCCPUClass *pcc = NULL;
10031
10032 list = object_class_get_list(TYPE_POWERPC_CPU, true);
10033 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
10034 if (item != NULL) {
10035 pcc = POWERPC_CPU_CLASS(item->data);
10036 }
10037 g_slist_free(list);
10038
10039 return pcc;
10040 }
10041
10042 static const char *ppc_cpu_lookup_alias(const char *alias)
10043 {
10044 int ai;
10045
10046 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
10047 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
10048 return ppc_cpu_aliases[ai].model;
10049 }
10050 }
10051
10052 return NULL;
10053 }
10054
10055 static ObjectClass *ppc_cpu_class_by_name(const char *name)
10056 {
10057 char *cpu_model, *typename;
10058 ObjectClass *oc;
10059 const char *p;
10060 unsigned long pvr;
10061
10062 /* Lookup by PVR if cpu_model is valid 8 digit hex number
10063 * (excl: 0x prefix if present)
10064 */
10065 if (!qemu_strtoul(name, &p, 16, &pvr)) {
10066 int len = p - name;
10067 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
10068 if ((len == 8) && (*p == '\0')) {
10069 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
10070 }
10071 }
10072
10073 cpu_model = g_ascii_strdown(name, -1);
10074 p = ppc_cpu_lookup_alias(cpu_model);
10075 if (p) {
10076 g_free(cpu_model);
10077 cpu_model = g_strdup(p);
10078 }
10079
10080 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
10081 oc = object_class_by_name(typename);
10082 g_free(typename);
10083 g_free(cpu_model);
10084
10085 return oc;
10086 }
10087
10088 static void ppc_cpu_parse_featurestr(const char *type, char *features,
10089 Error **errp)
10090 {
10091 Object *machine = qdev_get_machine();
10092 const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type));
10093
10094 if (!features) {
10095 return;
10096 }
10097
10098 if (object_property_find(machine, "max-cpu-compat", NULL)) {
10099 int i;
10100 char **inpieces;
10101 char *s = features;
10102 Error *local_err = NULL;
10103 char *compat_str = NULL;
10104
10105 /*
10106 * Backwards compatibility hack:
10107 *
10108 * CPUs had a "compat=" property which didn't make sense for
10109 * anything except pseries. It was replaced by "max-cpu-compat"
10110 * machine option. This supports old command lines like
10111 * -cpu POWER8,compat=power7
10112 * By stripping the compat option and applying it to the machine
10113 * before passing it on to the cpu level parser.
10114 */
10115 inpieces = g_strsplit(features, ",", 0);
10116 *s = '\0';
10117 for (i = 0; inpieces[i]; i++) {
10118 if (g_str_has_prefix(inpieces[i], "compat=")) {
10119 compat_str = inpieces[i];
10120 continue;
10121 }
10122 if ((i != 0) && (s != features)) {
10123 s = g_stpcpy(s, ",");
10124 }
10125 s = g_stpcpy(s, inpieces[i]);
10126 }
10127
10128 if (compat_str) {
10129 char *v = compat_str + strlen("compat=");
10130 object_property_set_str(machine, v, "max-cpu-compat", &local_err);
10131 }
10132 g_strfreev(inpieces);
10133 if (local_err) {
10134 error_propagate(errp, local_err);
10135 return;
10136 }
10137 }
10138
10139 /* do property processing with generic handler */
10140 pcc->parent_parse_features(type, features, errp);
10141 }
10142
10143 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
10144 {
10145 ObjectClass *oc = OBJECT_CLASS(pcc);
10146
10147 while (oc && !object_class_is_abstract(oc)) {
10148 oc = object_class_get_parent(oc);
10149 }
10150 assert(oc);
10151
10152 return POWERPC_CPU_CLASS(oc);
10153 }
10154
10155 /* Sort by PVR, ordering special case "host" last. */
10156 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10157 {
10158 ObjectClass *oc_a = (ObjectClass *)a;
10159 ObjectClass *oc_b = (ObjectClass *)b;
10160 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10161 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10162 const char *name_a = object_class_get_name(oc_a);
10163 const char *name_b = object_class_get_name(oc_b);
10164
10165 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10166 return 1;
10167 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10168 return -1;
10169 } else {
10170 /* Avoid an integer overflow during subtraction */
10171 if (pcc_a->pvr < pcc_b->pvr) {
10172 return -1;
10173 } else if (pcc_a->pvr > pcc_b->pvr) {
10174 return 1;
10175 } else {
10176 return 0;
10177 }
10178 }
10179 }
10180
10181 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10182 {
10183 ObjectClass *oc = data;
10184 CPUListState *s = user_data;
10185 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10186 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
10187 const char *typename = object_class_get_name(oc);
10188 char *name;
10189 int i;
10190
10191 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10192 return;
10193 }
10194
10195 name = g_strndup(typename,
10196 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10197 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10198 name, pcc->pvr);
10199 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10200 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10201 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
10202
10203 if (alias_oc != oc) {
10204 continue;
10205 }
10206 /*
10207 * If running with KVM, we might update the family alias later, so
10208 * avoid printing the wrong alias here and use "preferred" instead
10209 */
10210 if (strcmp(alias->alias, family->desc) == 0) {
10211 (*s->cpu_fprintf)(s->file,
10212 "PowerPC %-16s (alias for preferred %s CPU)\n",
10213 alias->alias, family->desc);
10214 } else {
10215 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
10216 alias->alias, name);
10217 }
10218 }
10219 g_free(name);
10220 }
10221
10222 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10223 {
10224 CPUListState s = {
10225 .file = f,
10226 .cpu_fprintf = cpu_fprintf,
10227 };
10228 GSList *list;
10229
10230 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10231 list = g_slist_sort(list, ppc_cpu_list_compare);
10232 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10233 g_slist_free(list);
10234
10235 #ifdef CONFIG_KVM
10236 cpu_fprintf(f, "\n");
10237 cpu_fprintf(f, "PowerPC %-16s\n", "host");
10238 #endif
10239 }
10240
10241 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10242 {
10243 ObjectClass *oc = data;
10244 CpuDefinitionInfoList **first = user_data;
10245 const char *typename;
10246 CpuDefinitionInfoList *entry;
10247 CpuDefinitionInfo *info;
10248
10249 typename = object_class_get_name(oc);
10250 info = g_malloc0(sizeof(*info));
10251 info->name = g_strndup(typename,
10252 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10253
10254 entry = g_malloc0(sizeof(*entry));
10255 entry->value = info;
10256 entry->next = *first;
10257 *first = entry;
10258 }
10259
10260 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
10261 {
10262 CpuDefinitionInfoList *cpu_list = NULL;
10263 GSList *list;
10264 int i;
10265
10266 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10267 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10268 g_slist_free(list);
10269
10270 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10271 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10272 ObjectClass *oc;
10273 CpuDefinitionInfoList *entry;
10274 CpuDefinitionInfo *info;
10275
10276 oc = ppc_cpu_class_by_name(alias->model);
10277 if (oc == NULL) {
10278 continue;
10279 }
10280
10281 info = g_malloc0(sizeof(*info));
10282 info->name = g_strdup(alias->alias);
10283 info->q_typename = g_strdup(object_class_get_name(oc));
10284
10285 entry = g_malloc0(sizeof(*entry));
10286 entry->value = info;
10287 entry->next = cpu_list;
10288 cpu_list = entry;
10289 }
10290
10291 return cpu_list;
10292 }
10293
10294 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10295 {
10296 PowerPCCPU *cpu = POWERPC_CPU(cs);
10297
10298 cpu->env.nip = value;
10299 }
10300
10301 static bool ppc_cpu_has_work(CPUState *cs)
10302 {
10303 PowerPCCPU *cpu = POWERPC_CPU(cs);
10304 CPUPPCState *env = &cpu->env;
10305
10306 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10307 }
10308
10309 /* CPUClass::reset() */
10310 static void ppc_cpu_reset(CPUState *s)
10311 {
10312 PowerPCCPU *cpu = POWERPC_CPU(s);
10313 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10314 CPUPPCState *env = &cpu->env;
10315 target_ulong msr;
10316 int i;
10317
10318 pcc->parent_reset(s);
10319
10320 msr = (target_ulong)0;
10321 msr |= (target_ulong)MSR_HVB;
10322 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10323 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10324 msr |= (target_ulong)1 << MSR_EP;
10325 #if defined(DO_SINGLE_STEP) && 0
10326 /* Single step trace mode */
10327 msr |= (target_ulong)1 << MSR_SE;
10328 msr |= (target_ulong)1 << MSR_BE;
10329 #endif
10330 #if defined(CONFIG_USER_ONLY)
10331 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10332 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
10333 msr |= (target_ulong)1 << MSR_FE1;
10334 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10335 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
10336 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10337 msr |= (target_ulong)1 << MSR_PR;
10338 #if defined(TARGET_PPC64)
10339 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10340 #endif
10341 #if !defined(TARGET_WORDS_BIGENDIAN)
10342 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
10343 if (!((env->msr_mask >> MSR_LE) & 1)) {
10344 fprintf(stderr, "Selected CPU does not support little-endian.\n");
10345 exit(1);
10346 }
10347 #endif
10348 #endif
10349
10350 #if defined(TARGET_PPC64)
10351 if (env->mmu_model & POWERPC_MMU_64) {
10352 msr |= (1ULL << MSR_SF);
10353 }
10354 #endif
10355
10356 hreg_store_msr(env, msr, 1);
10357
10358 #if !defined(CONFIG_USER_ONLY)
10359 env->nip = env->hreset_vector | env->excp_prefix;
10360 if (env->mmu_model != POWERPC_MMU_REAL) {
10361 ppc_tlb_invalidate_all(env);
10362 }
10363 #endif
10364
10365 hreg_compute_hflags(env);
10366 env->reserve_addr = (target_ulong)-1ULL;
10367 /* Be sure no exception or interrupt is pending */
10368 env->pending_interrupts = 0;
10369 s->exception_index = POWERPC_EXCP_NONE;
10370 env->error_code = 0;
10371
10372 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10373 ppc_spr_t *spr = &env->spr_cb[i];
10374
10375 if (!spr->name) {
10376 continue;
10377 }
10378 env->spr[i] = spr->default_value;
10379 }
10380 }
10381
10382 #ifndef CONFIG_USER_ONLY
10383 static bool ppc_cpu_is_big_endian(CPUState *cs)
10384 {
10385 PowerPCCPU *cpu = POWERPC_CPU(cs);
10386 CPUPPCState *env = &cpu->env;
10387
10388 cpu_synchronize_state(cs);
10389
10390 return !msr_le;
10391 }
10392 #endif
10393
10394 static void ppc_cpu_instance_init(Object *obj)
10395 {
10396 CPUState *cs = CPU(obj);
10397 PowerPCCPU *cpu = POWERPC_CPU(obj);
10398 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10399 CPUPPCState *env = &cpu->env;
10400
10401 cs->env_ptr = env;
10402 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
10403
10404 env->msr_mask = pcc->msr_mask;
10405 env->mmu_model = pcc->mmu_model;
10406 env->excp_model = pcc->excp_model;
10407 env->bus_model = pcc->bus_model;
10408 env->insns_flags = pcc->insns_flags;
10409 env->insns_flags2 = pcc->insns_flags2;
10410 env->flags = pcc->flags;
10411 env->bfd_mach = pcc->bfd_mach;
10412 env->check_pow = pcc->check_pow;
10413
10414 /* Mark HV mode as supported if the CPU has an MSR_HV bit
10415 * in the msr_mask. The mask can later be cleared by PAPR
10416 * mode but the hv mode support will remain, thus enforcing
10417 * that we cannot use priv. instructions in guest in PAPR
10418 * mode. For 970 we currently simply don't set HV in msr_mask
10419 * thus simulating an "Apple mode" 970. If we ever want to
10420 * support 970 HV mode, we'll have to add a processor attribute
10421 * of some sort.
10422 */
10423 #if !defined(CONFIG_USER_ONLY)
10424 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10425 #endif
10426
10427 ppc_hash64_init(cpu);
10428 }
10429
10430 static void ppc_cpu_instance_finalize(Object *obj)
10431 {
10432 PowerPCCPU *cpu = POWERPC_CPU(obj);
10433
10434 ppc_hash64_finalize(cpu);
10435 }
10436
10437 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10438 {
10439 return pcc->pvr == pvr;
10440 }
10441
10442 static gchar *ppc_gdb_arch_name(CPUState *cs)
10443 {
10444 #if defined(TARGET_PPC64)
10445 return g_strdup("powerpc:common64");
10446 #else
10447 return g_strdup("powerpc:common");
10448 #endif
10449 }
10450
10451 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
10452 {
10453 PowerPCCPU *cpu = POWERPC_CPU(cs);
10454 CPUPPCState *env = &cpu->env;
10455
10456 if ((env->hflags >> MSR_LE) & 1) {
10457 info->endian = BFD_ENDIAN_LITTLE;
10458 }
10459 info->mach = env->bfd_mach;
10460 if (!env->bfd_mach) {
10461 #ifdef TARGET_PPC64
10462 info->mach = bfd_mach_ppc64;
10463 #else
10464 info->mach = bfd_mach_ppc;
10465 #endif
10466 }
10467 info->disassembler_options = (char *)"any";
10468 info->print_insn = print_insn_ppc;
10469
10470 info->cap_arch = CS_ARCH_PPC;
10471 #ifdef TARGET_PPC64
10472 info->cap_mode = CS_MODE_64;
10473 #endif
10474 }
10475
10476 static Property ppc_cpu_properties[] = {
10477 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10478 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
10479 false),
10480 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
10481 false),
10482 DEFINE_PROP_END_OF_LIST(),
10483 };
10484
10485 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10486 {
10487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10488 CPUClass *cc = CPU_CLASS(oc);
10489 DeviceClass *dc = DEVICE_CLASS(oc);
10490
10491 device_class_set_parent_realize(dc, ppc_cpu_realize,
10492 &pcc->parent_realize);
10493 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
10494 &pcc->parent_unrealize);
10495 pcc->pvr_match = ppc_pvr_match_default;
10496 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10497 dc->props = ppc_cpu_properties;
10498
10499 pcc->parent_reset = cc->reset;
10500 cc->reset = ppc_cpu_reset;
10501
10502 cc->class_by_name = ppc_cpu_class_by_name;
10503 pcc->parent_parse_features = cc->parse_features;
10504 cc->parse_features = ppc_cpu_parse_featurestr;
10505 cc->has_work = ppc_cpu_has_work;
10506 cc->do_interrupt = ppc_cpu_do_interrupt;
10507 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10508 cc->dump_state = ppc_cpu_dump_state;
10509 cc->dump_statistics = ppc_cpu_dump_statistics;
10510 cc->set_pc = ppc_cpu_set_pc;
10511 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10512 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10513 cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
10514 #ifdef CONFIG_USER_ONLY
10515 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10516 #else
10517 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10518 cc->vmsd = &vmstate_ppc_cpu;
10519 #endif
10520 #if defined(CONFIG_SOFTMMU)
10521 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10522 cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10523 #endif
10524
10525 cc->gdb_num_core_regs = 71;
10526 #ifndef CONFIG_USER_ONLY
10527 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
10528 #endif
10529 #ifdef USE_APPLE_GDB
10530 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10531 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10532 cc->gdb_num_core_regs = 71 + 32;
10533 #endif
10534
10535 cc->gdb_arch_name = ppc_gdb_arch_name;
10536 #if defined(TARGET_PPC64)
10537 cc->gdb_core_xml_file = "power64-core.xml";
10538 #else
10539 cc->gdb_core_xml_file = "power-core.xml";
10540 #endif
10541 #ifndef CONFIG_USER_ONLY
10542 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10543 #endif
10544 #ifdef CONFIG_TCG
10545 cc->tcg_initialize = ppc_translate_init;
10546 #endif
10547 cc->disas_set_info = ppc_disas_set_info;
10548
10549 dc->fw_name = "PowerPC,UNKNOWN";
10550 }
10551
10552 static const TypeInfo ppc_cpu_type_info = {
10553 .name = TYPE_POWERPC_CPU,
10554 .parent = TYPE_CPU,
10555 .instance_size = sizeof(PowerPCCPU),
10556 .instance_init = ppc_cpu_instance_init,
10557 .instance_finalize = ppc_cpu_instance_finalize,
10558 .abstract = true,
10559 .class_size = sizeof(PowerPCCPUClass),
10560 .class_init = ppc_cpu_class_init,
10561 };
10562
10563 static const TypeInfo ppc_vhyp_type_info = {
10564 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10565 .parent = TYPE_INTERFACE,
10566 .class_size = sizeof(PPCVirtualHypervisorClass),
10567 };
10568
10569 static void ppc_cpu_register_types(void)
10570 {
10571 type_register_static(&ppc_cpu_type_info);
10572 type_register_static(&ppc_vhyp_type_info);
10573 }
10574
10575 type_init(ppc_cpu_register_types)
AR7 emulation for QEMU