hw/dma/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Modifications:
   7  *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/hw.h"
  30 #include "hw/sparc/sparc32_dma.h"
  31 #include "hw/sparc/sun4m.h"
  32 #include "hw/sysbus.h"
  33 #include "qapi/error.h"
  34 #include "trace.h"
  35
  36 /*
  37  * This is the DMA controller part of chip STP2000 (Master I/O), also
  38  * produced as NCR89C100. See
  39  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  40  * and
  41  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  42  */
  43
  44 #define DMA_SIZE (4 * sizeof(uint32_t))
  45 /* We need the mask, because one instance of the device is not page
  46    aligned (ledma, start address 0x0010) */
  47 #define DMA_MASK (DMA_SIZE - 1)
  48 /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
  49 #define DMA_ETH_SIZE (8 * sizeof(uint32_t))
  50 #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
  51
  52 #define DMA_VER 0xa0000000
  53 #define DMA_INTR 1
  54 #define DMA_INTREN 0x10
  55 #define DMA_WRITE_MEM 0x100
  56 #define DMA_EN 0x200
  57 #define DMA_LOADED 0x04000000
  58 #define DMA_DRAIN_FIFO 0x40
  59 #define DMA_RESET 0x80
  60
  61 /* XXX SCSI and ethernet should have different read-only bit masks */
  62 #define DMA_CSR_RO_MASK 0xfe000007
  63
  64 enum {
  65     GPIO_RESET = 0,
  66     GPIO_DMA,
  67 };
  68
  69 /* Note: on sparc, the lance 16 bit bus is swapped */
  70 void ledma_memory_read(void *opaque, hwaddr addr,
  71                        uint8_t *buf, int len, int do_bswap)
  72 {
  73     DMADeviceState *s = opaque;
  74     int i;
  75
  76     addr |= s->dmaregs[3];
  77     trace_ledma_memory_read(addr, len);
  78     if (do_bswap) {
  79         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  80     } else {
  81         addr &= ~1;
  82         len &= ~1;
  83         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  84         for(i = 0; i < len; i += 2) {
  85             bswap16s((uint16_t *)(buf + i));
  86         }
  87     }
  88 }
  89
  90 void ledma_memory_write(void *opaque, hwaddr addr,
  91                         uint8_t *buf, int len, int do_bswap)
  92 {
  93     DMADeviceState *s = opaque;
  94     int l, i;
  95     uint16_t tmp_buf[32];
  96
  97     addr |= s->dmaregs[3];
  98     trace_ledma_memory_write(addr, len);
  99     if (do_bswap) {
 100         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 101     } else {
 102         addr &= ~1;
 103         len &= ~1;
 104         while (len > 0) {
 105             l = len;
 106             if (l > sizeof(tmp_buf))
 107                 l = sizeof(tmp_buf);
 108             for(i = 0; i < l; i += 2) {
 109                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 110             }
 111             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 112             len -= l;
 113             buf += l;
 114             addr += l;
 115         }
 116     }
 117 }
 118
 119 static void dma_set_irq(void *opaque, int irq, int level)
 120 {
 121     DMADeviceState *s = opaque;
 122     if (level) {
 123         s->dmaregs[0] |= DMA_INTR;
 124         if (s->dmaregs[0] & DMA_INTREN) {
 125             trace_sparc32_dma_set_irq_raise();
 126             qemu_irq_raise(s->irq);
 127         }
 128     } else {
 129         if (s->dmaregs[0] & DMA_INTR) {
 130             s->dmaregs[0] &= ~DMA_INTR;
 131             if (s->dmaregs[0] & DMA_INTREN) {
 132                 trace_sparc32_dma_set_irq_lower();
 133                 qemu_irq_lower(s->irq);
 134             }
 135         }
 136     }
 137 }
 138
 139 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 140 {
 141     DMADeviceState *s = opaque;
 142
 143     trace_espdma_memory_read(s->dmaregs[1], len);
 144     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 145     s->dmaregs[1] += len;
 146 }
 147
 148 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 149 {
 150     DMADeviceState *s = opaque;
 151
 152     trace_espdma_memory_write(s->dmaregs[1], len);
 153     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 154     s->dmaregs[1] += len;
 155 }
 156
 157 static uint64_t dma_mem_read(void *opaque, hwaddr addr,
 158                              unsigned size)
 159 {
 160     DMADeviceState *s = opaque;
 161     uint32_t saddr;
 162
 163     saddr = (addr & DMA_MASK) >> 2;
 164     trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
 165     return s->dmaregs[saddr];
 166 }
 167
 168 static void dma_mem_write(void *opaque, hwaddr addr,
 169                           uint64_t val, unsigned size)
 170 {
 171     DMADeviceState *s = opaque;
 172     uint32_t saddr;
 173
 174     saddr = (addr & DMA_MASK) >> 2;
 175     trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
 176     switch (saddr) {
 177     case 0:
 178         if (val & DMA_INTREN) {
 179             if (s->dmaregs[0] & DMA_INTR) {
 180                 trace_sparc32_dma_set_irq_raise();
 181                 qemu_irq_raise(s->irq);
 182             }
 183         } else {
 184             if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
 185                 trace_sparc32_dma_set_irq_lower();
 186                 qemu_irq_lower(s->irq);
 187             }
 188         }
 189         if (val & DMA_RESET) {
 190             qemu_irq_raise(s->gpio[GPIO_RESET]);
 191             qemu_irq_lower(s->gpio[GPIO_RESET]);
 192         } else if (val & DMA_DRAIN_FIFO) {
 193             val &= ~DMA_DRAIN_FIFO;
 194         } else if (val == 0)
 195             val = DMA_DRAIN_FIFO;
 196
 197         if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
 198             trace_sparc32_dma_enable_raise();
 199             qemu_irq_raise(s->gpio[GPIO_DMA]);
 200         } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
 201             trace_sparc32_dma_enable_lower();
 202             qemu_irq_lower(s->gpio[GPIO_DMA]);
 203         }
 204
 205         val &= ~DMA_CSR_RO_MASK;
 206         val |= DMA_VER;
 207         s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
 208         break;
 209     case 1:
 210         s->dmaregs[0] |= DMA_LOADED;
 211         /* fall through */
 212     default:
 213         s->dmaregs[saddr] = val;
 214         break;
 215     }
 216 }
 217
 218 static const MemoryRegionOps dma_mem_ops = {
 219     .read = dma_mem_read,
 220     .write = dma_mem_write,
 221     .endianness = DEVICE_NATIVE_ENDIAN,
 222     .valid = {
 223         .min_access_size = 4,
 224         .max_access_size = 4,
 225     },
 226 };
 227
 228 static void sparc32_dma_device_reset(DeviceState *d)
 229 {
 230     DMADeviceState *s = SPARC32_DMA_DEVICE(d);
 231
 232     memset(s->dmaregs, 0, DMA_SIZE);
 233     s->dmaregs[0] = DMA_VER;
 234 }
 235
 236 static const VMStateDescription vmstate_sparc32_dma_device = {
 237     .name ="sparc32_dma",
 238     .version_id = 2,
 239     .minimum_version_id = 2,
 240     .fields = (VMStateField[]) {
 241         VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
 242         VMSTATE_END_OF_LIST()
 243     }
 244 };
 245
 246 static void sparc32_dma_device_init(Object *obj)
 247 {
 248     DeviceState *dev = DEVICE(obj);
 249     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 250     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 251
 252     sysbus_init_irq(sbd, &s->irq);
 253
 254     sysbus_init_mmio(sbd, &s->iomem);
 255
 256     object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
 257                              (Object **) &s->iommu,
 258                              qdev_prop_allow_set_link_before_realize,
 259                              0, NULL);
 260
 261     qdev_init_gpio_in(dev, dma_set_irq, 1);
 262     qdev_init_gpio_out(dev, s->gpio, 2);
 263 }
 264
 265 static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
 266 {
 267     DeviceClass *dc = DEVICE_CLASS(klass);
 268
 269     dc->reset = sparc32_dma_device_reset;
 270     dc->vmsd = &vmstate_sparc32_dma_device;
 271 }
 272
 273 static const TypeInfo sparc32_dma_device_info = {
 274     .name          = TYPE_SPARC32_DMA_DEVICE,
 275     .parent        = TYPE_SYS_BUS_DEVICE,
 276     .abstract      = true,
 277     .instance_size = sizeof(DMADeviceState),
 278     .instance_init = sparc32_dma_device_init,
 279     .class_init    = sparc32_dma_device_class_init,
 280 };
 281
 282 static void sparc32_espdma_device_init(Object *obj)
 283 {
 284     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 285
 286     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 287                           "espdma-mmio", DMA_SIZE);
 288 }
 289
 290 static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
 291 {
 292     DeviceState *d;
 293     SysBusESPState *sysbus;
 294     ESPState *esp;
 295
 296     d = qdev_create(NULL, TYPE_ESP);
 297     object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);
 298     sysbus = ESP_STATE(d);
 299     esp = &sysbus->esp;
 300     esp->dma_memory_read = espdma_memory_read;
 301     esp->dma_memory_write = espdma_memory_write;
 302     esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
 303     sysbus->it_shift = 2;
 304     esp->dma_enabled = 1;
 305     qdev_init_nofail(d);
 306 }
 307
 308 static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
 309 {
 310     DeviceClass *dc = DEVICE_CLASS(klass);
 311
 312     dc->realize = sparc32_espdma_device_realize;
 313 }
 314
 315 static const TypeInfo sparc32_espdma_device_info = {
 316     .name          = TYPE_SPARC32_ESPDMA_DEVICE,
 317     .parent        = TYPE_SPARC32_DMA_DEVICE,
 318     .instance_size = sizeof(ESPDMADeviceState),
 319     .instance_init = sparc32_espdma_device_init,
 320     .class_init    = sparc32_espdma_device_class_init,
 321 };
 322
 323 static void sparc32_ledma_device_init(Object *obj)
 324 {
 325     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 326
 327     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 328                           "ledma-mmio", DMA_SIZE);
 329 }
 330
 331 static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
 332 {
 333     DeviceState *d;
 334     NICInfo *nd = &nd_table[0];
 335
 336     qemu_check_nic_model(nd, TYPE_LANCE);
 337
 338     d = qdev_create(NULL, TYPE_LANCE);
 339     object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
 340     qdev_set_nic_properties(d, nd);
 341     qdev_prop_set_ptr(d, "dma", dev);
 342     qdev_init_nofail(d);
 343 }
 344
 345 static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
 346 {
 347     DeviceClass *dc = DEVICE_CLASS(klass);
 348
 349     dc->realize = sparc32_ledma_device_realize;
 350 }
 351
 352 static const TypeInfo sparc32_ledma_device_info = {
 353     .name          = TYPE_SPARC32_LEDMA_DEVICE,
 354     .parent        = TYPE_SPARC32_DMA_DEVICE,
 355     .instance_size = sizeof(LEDMADeviceState),
 356     .instance_init = sparc32_ledma_device_init,
 357     .class_init    = sparc32_ledma_device_class_init,
 358 };
 359
 360 static void sparc32_dma_realize(DeviceState *dev, Error **errp)
 361 {
 362     SPARC32DMAState *s = SPARC32_DMA(dev);
 363     DeviceState *espdma, *esp, *ledma, *lance;
 364     SysBusDevice *sbd;
 365     Object *iommu;
 366
 367     iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
 368     if (!iommu) {
 369         error_setg(errp, "unable to locate sun4m IOMMU device");
 370         return;
 371     }
 372
 373     espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
 374     object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
 375     object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp);
 376     qdev_init_nofail(espdma);
 377
 378     esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
 379     sbd = SYS_BUS_DEVICE(esp);
 380     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
 381     qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
 382     qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
 383
 384     sbd = SYS_BUS_DEVICE(espdma);
 385     memory_region_add_subregion(&s->dmamem, 0x0,
 386                                 sysbus_mmio_get_region(sbd, 0));
 387
 388     ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
 389     object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
 390     object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp);
 391     qdev_init_nofail(ledma);
 392
 393     lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
 394     sbd = SYS_BUS_DEVICE(lance);
 395     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
 396     qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
 397
 398     sbd = SYS_BUS_DEVICE(ledma);
 399     memory_region_add_subregion(&s->dmamem, 0x10,
 400                                 sysbus_mmio_get_region(sbd, 0));
 401
 402     /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */
 403     memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
 404                              sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
 405     memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
 406 }
 407
 408 static void sparc32_dma_init(Object *obj)
 409 {
 410     SPARC32DMAState *s = SPARC32_DMA(obj);
 411     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 412
 413     memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
 414     sysbus_init_mmio(sbd, &s->dmamem);
 415 }
 416
 417 static void sparc32_dma_class_init(ObjectClass *klass, void *data)
 418 {
 419     DeviceClass *dc = DEVICE_CLASS(klass);
 420
 421     dc->realize = sparc32_dma_realize;
 422 }
 423
 424 static const TypeInfo sparc32_dma_info = {
 425     .name          = TYPE_SPARC32_DMA,
 426     .parent        = TYPE_SYS_BUS_DEVICE,
 427     .instance_size = sizeof(SPARC32DMAState),
 428     .instance_init = sparc32_dma_init,
 429     .class_init    = sparc32_dma_class_init,
 430 };
 431
 432
 433 static void sparc32_dma_register_types(void)
 434 {
 435     type_register_static(&sparc32_dma_device_info);
 436     type_register_static(&sparc32_espdma_device_info);
 437     type_register_static(&sparc32_ledma_device_info);
 438     type_register_static(&sparc32_dma_info);
 439 }
 440
 441 type_init(sparc32_dma_register_types)