hw/arm/virt-acpi-build: add all missing cpu_to_le's
[qemu/ar7.git] / hw / block / pflash_cfi01.c
blob5f0ee9db00ff5e05b079a04d313c9994c2c5d181
1 /*
2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
24 * - flash read
25 * - flash write
26 * - flash ID read
27 * - sector erase
28 * - CFI queries
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
39 #include "qemu/osdep.h"
40 #include "hw/hw.h"
41 #include "hw/block/flash.h"
42 #include "sysemu/block-backend.h"
43 #include "qapi/error.h"
44 #include "qemu/timer.h"
45 #include "qemu/bitops.h"
46 #include "exec/address-spaces.h"
47 #include "qemu/host-utils.h"
48 #include "qemu/log.h"
49 #include "hw/sysbus.h"
50 #include "sysemu/sysemu.h"
52 #define PFLASH_BUG(fmt, ...) \
53 do { \
54 fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
55 exit(1); \
56 } while(0)
58 /* #define PFLASH_DEBUG */
59 #ifdef PFLASH_DEBUG
60 #define DPRINTF(fmt, ...) \
61 do { \
62 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
63 } while (0)
64 #else
65 #define DPRINTF(fmt, ...) do { } while (0)
66 #endif
68 #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01)
70 #define PFLASH_BE 0
71 #define PFLASH_SECURE 1
73 struct pflash_t {
74 /*< private >*/
75 SysBusDevice parent_obj;
76 /*< public >*/
78 BlockBackend *blk;
79 uint32_t nb_blocs;
80 uint64_t sector_len;
81 uint8_t bank_width;
82 uint8_t device_width; /* If 0, device width not specified. */
83 uint8_t max_device_width; /* max device width in bytes */
84 uint32_t features;
85 uint8_t wcycle; /* if 0, the flash is read normally */
86 int ro;
87 uint8_t cmd;
88 uint8_t status;
89 uint16_t ident0;
90 uint16_t ident1;
91 uint16_t ident2;
92 uint16_t ident3;
93 uint8_t cfi_len;
94 uint8_t cfi_table[0x52];
95 uint64_t counter;
96 unsigned int writeblock_size;
97 QEMUTimer *timer;
98 MemoryRegion mem;
99 char *name;
100 void *storage;
101 VMChangeStateEntry *vmstate;
104 static int pflash_post_load(void *opaque, int version_id);
106 static const VMStateDescription vmstate_pflash = {
107 .name = "pflash_cfi01",
108 .version_id = 1,
109 .minimum_version_id = 1,
110 .post_load = pflash_post_load,
111 .fields = (VMStateField[]) {
112 VMSTATE_UINT8(wcycle, pflash_t),
113 VMSTATE_UINT8(cmd, pflash_t),
114 VMSTATE_UINT8(status, pflash_t),
115 VMSTATE_UINT64(counter, pflash_t),
116 VMSTATE_END_OF_LIST()
120 static void pflash_timer (void *opaque)
122 pflash_t *pfl = opaque;
124 DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
125 /* Reset flash */
126 pfl->status ^= 0x80;
127 memory_region_rom_device_set_romd(&pfl->mem, true);
128 pfl->wcycle = 0;
129 pfl->cmd = 0;
132 /* Perform a CFI query based on the bank width of the flash.
133 * If this code is called we know we have a device_width set for
134 * this flash.
136 static uint32_t pflash_cfi_query(pflash_t *pfl, hwaddr offset)
138 int i;
139 uint32_t resp = 0;
140 hwaddr boff;
142 /* Adjust incoming offset to match expected device-width
143 * addressing. CFI query addresses are always specified in terms of
144 * the maximum supported width of the device. This means that x8
145 * devices and x8/x16 devices in x8 mode behave differently. For
146 * devices that are not used at their max width, we will be
147 * provided with addresses that use higher address bits than
148 * expected (based on the max width), so we will shift them lower
149 * so that they will match the addresses used when
150 * device_width==max_device_width.
152 boff = offset >> (ctz32(pfl->bank_width) +
153 ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
155 if (boff > pfl->cfi_len) {
156 return 0;
158 /* Now we will construct the CFI response generated by a single
159 * device, then replicate that for all devices that make up the
160 * bus. For wide parts used in x8 mode, CFI query responses
161 * are different than native byte-wide parts.
163 resp = pfl->cfi_table[boff];
164 if (pfl->device_width != pfl->max_device_width) {
165 /* The only case currently supported is x8 mode for a
166 * wider part.
168 if (pfl->device_width != 1 || pfl->bank_width > 4) {
169 DPRINTF("%s: Unsupported device configuration: "
170 "device_width=%d, max_device_width=%d\n",
171 __func__, pfl->device_width,
172 pfl->max_device_width);
173 return 0;
175 /* CFI query data is repeated, rather than zero padded for
176 * wide devices used in x8 mode.
178 for (i = 1; i < pfl->max_device_width; i++) {
179 resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]);
182 /* Replicate responses for each device in bank. */
183 if (pfl->device_width < pfl->bank_width) {
184 for (i = pfl->device_width;
185 i < pfl->bank_width; i += pfl->device_width) {
186 resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp);
190 return resp;
195 /* Perform a device id query based on the bank width of the flash. */
196 static uint32_t pflash_devid_query(pflash_t *pfl, hwaddr offset)
198 int i;
199 uint32_t resp;
200 hwaddr boff;
202 /* Adjust incoming offset to match expected device-width
203 * addressing. Device ID read addresses are always specified in
204 * terms of the maximum supported width of the device. This means
205 * that x8 devices and x8/x16 devices in x8 mode behave
206 * differently. For devices that are not used at their max width,
207 * we will be provided with addresses that use higher address bits
208 * than expected (based on the max width), so we will shift them
209 * lower so that they will match the addresses used when
210 * device_width==max_device_width.
212 boff = offset >> (ctz32(pfl->bank_width) +
213 ctz32(pfl->max_device_width) - ctz32(pfl->device_width));
215 /* Mask off upper bits which may be used in to query block
216 * or sector lock status at other addresses.
217 * Offsets 2/3 are block lock status, is not emulated.
219 switch (boff & 0xFF) {
220 case 0:
221 resp = pfl->ident0;
222 DPRINTF("%s: Manufacturer Code %04x\n", __func__, resp);
223 break;
224 case 1:
225 resp = pfl->ident1;
226 DPRINTF("%s: Device ID Code %04x\n", __func__, resp);
227 break;
228 default:
229 DPRINTF("%s: Read Device Information offset=%x\n", __func__,
230 (unsigned)offset);
231 return 0;
232 break;
234 /* Replicate responses for each device in bank. */
235 if (pfl->device_width < pfl->bank_width) {
236 for (i = pfl->device_width;
237 i < pfl->bank_width; i += pfl->device_width) {
238 resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp);
242 return resp;
245 static uint32_t pflash_data_read(pflash_t *pfl, hwaddr offset,
246 int width, int be)
248 uint8_t *p;
249 uint32_t ret;
251 p = pfl->storage;
252 switch (width) {
253 case 1:
254 ret = p[offset];
255 DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
256 __func__, offset, ret);
257 break;
258 case 2:
259 if (be) {
260 ret = p[offset] << 8;
261 ret |= p[offset + 1];
262 } else {
263 ret = p[offset];
264 ret |= p[offset + 1] << 8;
266 DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
267 __func__, offset, ret);
268 break;
269 case 4:
270 if (be) {
271 ret = p[offset] << 24;
272 ret |= p[offset + 1] << 16;
273 ret |= p[offset + 2] << 8;
274 ret |= p[offset + 3];
275 } else {
276 ret = p[offset];
277 ret |= p[offset + 1] << 8;
278 ret |= p[offset + 2] << 16;
279 ret |= p[offset + 3] << 24;
281 DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
282 __func__, offset, ret);
283 break;
284 default:
285 DPRINTF("BUG in %s\n", __func__);
286 abort();
288 return ret;
291 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
292 int width, int be)
294 hwaddr boff;
295 uint32_t ret;
297 ret = -1;
299 #if 0
300 DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
301 __func__, offset, pfl->cmd, width);
302 #endif
303 switch (pfl->cmd) {
304 default:
305 /* This should never happen : reset state & treat it as a read */
306 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
307 pfl->wcycle = 0;
308 pfl->cmd = 0;
309 /* fall through to read code */
310 case 0x00:
311 /* Flash area read */
312 ret = pflash_data_read(pfl, offset, width, be);
313 break;
314 case 0x10: /* Single byte program */
315 case 0x20: /* Block erase */
316 case 0x28: /* Block erase */
317 case 0x40: /* single byte program */
318 case 0x50: /* Clear status register */
319 case 0x60: /* Block /un)lock */
320 case 0x70: /* Status Register */
321 case 0xe8: /* Write block */
322 /* Status register read. Return status from each device in
323 * bank.
325 ret = pfl->status;
326 if (pfl->device_width && width > pfl->device_width) {
327 int shift = pfl->device_width * 8;
328 while (shift + pfl->device_width * 8 <= width * 8) {
329 ret |= pfl->status << shift;
330 shift += pfl->device_width * 8;
332 } else if (!pfl->device_width && width > 2) {
333 /* Handle 32 bit flash cases where device width is not
334 * set. (Existing behavior before device width added.)
336 ret |= pfl->status << 16;
338 DPRINTF("%s: status %x\n", __func__, ret);
339 break;
340 case 0x90:
341 if (!pfl->device_width) {
342 /* Preserve old behavior if device width not specified */
343 boff = offset & 0xFF;
344 if (pfl->bank_width == 2) {
345 boff = boff >> 1;
346 } else if (pfl->bank_width == 4) {
347 boff = boff >> 2;
350 switch (boff) {
351 case 0:
352 ret = pfl->ident0 << 8 | pfl->ident1;
353 DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
354 break;
355 case 1:
356 ret = pfl->ident2 << 8 | pfl->ident3;
357 DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
358 break;
359 default:
360 DPRINTF("%s: Read Device Information boff=%x\n", __func__,
361 (unsigned)boff);
362 ret = 0;
363 break;
365 } else {
366 /* If we have a read larger than the bank_width, combine multiple
367 * manufacturer/device ID queries into a single response.
369 int i;
370 for (i = 0; i < width; i += pfl->bank_width) {
371 ret = deposit32(ret, i * 8, pfl->bank_width * 8,
372 pflash_devid_query(pfl,
373 offset + i * pfl->bank_width));
376 break;
377 case 0x98: /* Query mode */
378 if (!pfl->device_width) {
379 /* Preserve old behavior if device width not specified */
380 boff = offset & 0xFF;
381 if (pfl->bank_width == 2) {
382 boff = boff >> 1;
383 } else if (pfl->bank_width == 4) {
384 boff = boff >> 2;
387 if (boff > pfl->cfi_len) {
388 ret = 0;
389 } else {
390 ret = pfl->cfi_table[boff];
392 } else {
393 /* If we have a read larger than the bank_width, combine multiple
394 * CFI queries into a single response.
396 int i;
397 for (i = 0; i < width; i += pfl->bank_width) {
398 ret = deposit32(ret, i * 8, pfl->bank_width * 8,
399 pflash_cfi_query(pfl,
400 offset + i * pfl->bank_width));
404 break;
406 return ret;
409 /* update flash content on disk */
410 static void pflash_update(pflash_t *pfl, int offset,
411 int size)
413 int offset_end;
414 if (pfl->blk) {
415 offset_end = offset + size;
416 /* widen to sector boundaries */
417 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
418 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
419 blk_pwrite(pfl->blk, offset, pfl->storage + offset,
420 offset_end - offset, 0);
424 static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
425 uint32_t value, int width, int be)
427 uint8_t *p = pfl->storage;
429 DPRINTF("%s: block write offset " TARGET_FMT_plx
430 " value %x counter %016" PRIx64 "\n",
431 __func__, offset, value, pfl->counter);
432 switch (width) {
433 case 1:
434 p[offset] = value;
435 break;
436 case 2:
437 if (be) {
438 p[offset] = value >> 8;
439 p[offset + 1] = value;
440 } else {
441 p[offset] = value;
442 p[offset + 1] = value >> 8;
444 break;
445 case 4:
446 if (be) {
447 p[offset] = value >> 24;
448 p[offset + 1] = value >> 16;
449 p[offset + 2] = value >> 8;
450 p[offset + 3] = value;
451 } else {
452 p[offset] = value;
453 p[offset + 1] = value >> 8;
454 p[offset + 2] = value >> 16;
455 p[offset + 3] = value >> 24;
457 break;
462 static void pflash_write(pflash_t *pfl, hwaddr offset,
463 uint32_t value, int width, int be)
465 uint8_t *p;
466 uint8_t cmd;
468 cmd = value;
470 DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
471 __func__, offset, value, width, pfl->wcycle);
473 if (!pfl->wcycle) {
474 /* Set the device in I/O access mode */
475 memory_region_rom_device_set_romd(&pfl->mem, false);
478 switch (pfl->wcycle) {
479 case 0:
480 /* read mode */
481 switch (cmd) {
482 case 0x00: /* ??? */
483 goto reset_flash;
484 case 0x10: /* Single Byte Program */
485 case 0x40: /* Single Byte Program */
486 DPRINTF("%s: Single Byte Program\n", __func__);
487 break;
488 case 0x20: /* Block erase */
489 p = pfl->storage;
490 offset &= ~(pfl->sector_len - 1);
492 DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
493 __func__, offset, (unsigned)pfl->sector_len);
495 if (!pfl->ro) {
496 memset(p + offset, 0xff, pfl->sector_len);
497 pflash_update(pfl, offset, pfl->sector_len);
498 } else {
499 pfl->status |= 0x20; /* Block erase error */
501 pfl->status |= 0x80; /* Ready! */
502 break;
503 case 0x50: /* Clear status bits */
504 DPRINTF("%s: Clear status bits\n", __func__);
505 pfl->status = 0x0;
506 goto reset_flash;
507 case 0x60: /* Block (un)lock */
508 DPRINTF("%s: Block unlock\n", __func__);
509 break;
510 case 0x70: /* Status Register */
511 DPRINTF("%s: Read status register\n", __func__);
512 pfl->cmd = cmd;
513 return;
514 case 0x90: /* Read Device ID */
515 DPRINTF("%s: Read Device information\n", __func__);
516 pfl->cmd = cmd;
517 return;
518 case 0x98: /* CFI query */
519 DPRINTF("%s: CFI query\n", __func__);
520 break;
521 case 0xe8: /* Write to buffer */
522 DPRINTF("%s: Write to buffer\n", __func__);
523 pfl->status |= 0x80; /* Ready! */
524 break;
525 case 0xf0: /* Probe for AMD flash */
526 DPRINTF("%s: Probe for AMD flash\n", __func__);
527 goto reset_flash;
528 case 0xff: /* Read array mode */
529 DPRINTF("%s: Read array mode\n", __func__);
530 goto reset_flash;
531 default:
532 goto error_flash;
534 pfl->wcycle++;
535 pfl->cmd = cmd;
536 break;
537 case 1:
538 switch (pfl->cmd) {
539 case 0x10: /* Single Byte Program */
540 case 0x40: /* Single Byte Program */
541 DPRINTF("%s: Single Byte Program\n", __func__);
542 if (!pfl->ro) {
543 pflash_data_write(pfl, offset, value, width, be);
544 pflash_update(pfl, offset, width);
545 } else {
546 pfl->status |= 0x10; /* Programming error */
548 pfl->status |= 0x80; /* Ready! */
549 pfl->wcycle = 0;
550 break;
551 case 0x20: /* Block erase */
552 case 0x28:
553 if (cmd == 0xd0) { /* confirm */
554 pfl->wcycle = 0;
555 pfl->status |= 0x80;
556 } else if (cmd == 0xff) { /* read array mode */
557 goto reset_flash;
558 } else
559 goto error_flash;
561 break;
562 case 0xe8:
563 /* Mask writeblock size based on device width, or bank width if
564 * device width not specified.
566 if (pfl->device_width) {
567 value = extract32(value, 0, pfl->device_width * 8);
568 } else {
569 value = extract32(value, 0, pfl->bank_width * 8);
571 DPRINTF("%s: block write of %x bytes\n", __func__, value);
572 pfl->counter = value;
573 pfl->wcycle++;
574 break;
575 case 0x60:
576 if (cmd == 0xd0) {
577 pfl->wcycle = 0;
578 pfl->status |= 0x80;
579 } else if (cmd == 0x01) {
580 pfl->wcycle = 0;
581 pfl->status |= 0x80;
582 } else if (cmd == 0xff) {
583 goto reset_flash;
584 } else {
585 DPRINTF("%s: Unknown (un)locking command\n", __func__);
586 goto reset_flash;
588 break;
589 case 0x98:
590 if (cmd == 0xff) {
591 goto reset_flash;
592 } else {
593 DPRINTF("%s: leaving query mode\n", __func__);
595 break;
596 default:
597 goto error_flash;
599 break;
600 case 2:
601 switch (pfl->cmd) {
602 case 0xe8: /* Block write */
603 if (!pfl->ro) {
604 pflash_data_write(pfl, offset, value, width, be);
605 } else {
606 pfl->status |= 0x10; /* Programming error */
609 pfl->status |= 0x80;
611 if (!pfl->counter) {
612 hwaddr mask = pfl->writeblock_size - 1;
613 mask = ~mask;
615 DPRINTF("%s: block write finished\n", __func__);
616 pfl->wcycle++;
617 if (!pfl->ro) {
618 /* Flush the entire write buffer onto backing storage. */
619 pflash_update(pfl, offset & mask, pfl->writeblock_size);
620 } else {
621 pfl->status |= 0x10; /* Programming error */
625 pfl->counter--;
626 break;
627 default:
628 goto error_flash;
630 break;
631 case 3: /* Confirm mode */
632 switch (pfl->cmd) {
633 case 0xe8: /* Block write */
634 if (cmd == 0xd0) {
635 pfl->wcycle = 0;
636 pfl->status |= 0x80;
637 } else {
638 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
639 PFLASH_BUG("Write block confirm");
640 goto reset_flash;
642 break;
643 default:
644 goto error_flash;
646 break;
647 default:
648 /* Should never happen */
649 DPRINTF("%s: invalid write state\n", __func__);
650 goto reset_flash;
652 return;
654 error_flash:
655 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
656 "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
657 "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
659 reset_flash:
660 memory_region_rom_device_set_romd(&pfl->mem, true);
662 pfl->wcycle = 0;
663 pfl->cmd = 0;
667 static MemTxResult pflash_mem_read_with_attrs(void *opaque, hwaddr addr, uint64_t *value,
668 unsigned len, MemTxAttrs attrs)
670 pflash_t *pfl = opaque;
671 bool be = !!(pfl->features & (1 << PFLASH_BE));
673 if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) {
674 *value = pflash_data_read(opaque, addr, len, be);
675 } else {
676 *value = pflash_read(opaque, addr, len, be);
678 return MEMTX_OK;
681 static MemTxResult pflash_mem_write_with_attrs(void *opaque, hwaddr addr, uint64_t value,
682 unsigned len, MemTxAttrs attrs)
684 pflash_t *pfl = opaque;
685 bool be = !!(pfl->features & (1 << PFLASH_BE));
687 if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) {
688 return MEMTX_ERROR;
689 } else {
690 pflash_write(opaque, addr, value, len, be);
691 return MEMTX_OK;
695 static const MemoryRegionOps pflash_cfi01_ops = {
696 .read_with_attrs = pflash_mem_read_with_attrs,
697 .write_with_attrs = pflash_mem_write_with_attrs,
698 .endianness = DEVICE_NATIVE_ENDIAN,
701 static void pflash_cfi01_realize(DeviceState *dev, Error **errp)
703 pflash_t *pfl = CFI_PFLASH01(dev);
704 uint64_t total_len;
705 int ret;
706 uint64_t blocks_per_device, device_len;
707 int num_devices;
708 Error *local_err = NULL;
710 if (pfl->sector_len == 0) {
711 error_setg(errp, "attribute \"sector-length\" not specified or zero.");
712 return;
714 if (pfl->nb_blocs == 0) {
715 error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
716 return;
718 if (pfl->name == NULL) {
719 error_setg(errp, "attribute \"name\" not specified.");
720 return;
723 total_len = pfl->sector_len * pfl->nb_blocs;
725 /* These are only used to expose the parameters of each device
726 * in the cfi_table[].
728 num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1;
729 blocks_per_device = pfl->nb_blocs / num_devices;
730 device_len = pfl->sector_len * blocks_per_device;
732 /* XXX: to be fixed */
733 #if 0
734 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
735 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
736 return NULL;
737 #endif
739 memory_region_init_rom_device(
740 &pfl->mem, OBJECT(dev),
741 &pflash_cfi01_ops,
742 pfl,
743 pfl->name, total_len, &local_err);
744 if (local_err) {
745 error_propagate(errp, local_err);
746 return;
749 vmstate_register_ram(&pfl->mem, DEVICE(pfl));
750 pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
751 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
753 if (pfl->blk) {
754 /* read the initial flash content */
755 ret = blk_pread(pfl->blk, 0, pfl->storage, total_len);
757 if (ret < 0) {
758 vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
759 error_setg(errp, "failed to read the initial flash content");
760 return;
764 if (pfl->blk) {
765 pfl->ro = blk_is_read_only(pfl->blk);
766 } else {
767 pfl->ro = 0;
770 /* Default to devices being used at their maximum device width. This was
771 * assumed before the device_width support was added.
773 if (!pfl->max_device_width) {
774 pfl->max_device_width = pfl->device_width;
777 pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
778 pfl->wcycle = 0;
779 pfl->cmd = 0;
780 pfl->status = 0;
781 /* Hardcoded CFI table */
782 pfl->cfi_len = 0x52;
783 /* Standard "QRY" string */
784 pfl->cfi_table[0x10] = 'Q';
785 pfl->cfi_table[0x11] = 'R';
786 pfl->cfi_table[0x12] = 'Y';
787 /* Command set (Intel) */
788 pfl->cfi_table[0x13] = 0x01;
789 pfl->cfi_table[0x14] = 0x00;
790 /* Primary extended table address (none) */
791 pfl->cfi_table[0x15] = 0x31;
792 pfl->cfi_table[0x16] = 0x00;
793 /* Alternate command set (none) */
794 pfl->cfi_table[0x17] = 0x00;
795 pfl->cfi_table[0x18] = 0x00;
796 /* Alternate extended table (none) */
797 pfl->cfi_table[0x19] = 0x00;
798 pfl->cfi_table[0x1A] = 0x00;
799 /* Vcc min */
800 pfl->cfi_table[0x1B] = 0x45;
801 /* Vcc max */
802 pfl->cfi_table[0x1C] = 0x55;
803 /* Vpp min (no Vpp pin) */
804 pfl->cfi_table[0x1D] = 0x00;
805 /* Vpp max (no Vpp pin) */
806 pfl->cfi_table[0x1E] = 0x00;
807 /* Reserved */
808 pfl->cfi_table[0x1F] = 0x07;
809 /* Timeout for min size buffer write */
810 pfl->cfi_table[0x20] = 0x07;
811 /* Typical timeout for block erase */
812 pfl->cfi_table[0x21] = 0x0a;
813 /* Typical timeout for full chip erase (4096 ms) */
814 pfl->cfi_table[0x22] = 0x00;
815 /* Reserved */
816 pfl->cfi_table[0x23] = 0x04;
817 /* Max timeout for buffer write */
818 pfl->cfi_table[0x24] = 0x04;
819 /* Max timeout for block erase */
820 pfl->cfi_table[0x25] = 0x04;
821 /* Max timeout for chip erase */
822 pfl->cfi_table[0x26] = 0x00;
823 /* Device size */
824 pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */
825 /* Flash device interface (8 & 16 bits) */
826 pfl->cfi_table[0x28] = 0x02;
827 pfl->cfi_table[0x29] = 0x00;
828 /* Max number of bytes in multi-bytes write */
829 if (pfl->bank_width == 1) {
830 pfl->cfi_table[0x2A] = 0x08;
831 } else {
832 pfl->cfi_table[0x2A] = 0x0B;
834 pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
836 pfl->cfi_table[0x2B] = 0x00;
837 /* Number of erase block regions (uniform) */
838 pfl->cfi_table[0x2C] = 0x01;
839 /* Erase block region 1 */
840 pfl->cfi_table[0x2D] = blocks_per_device - 1;
841 pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8;
842 pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
843 pfl->cfi_table[0x30] = pfl->sector_len >> 16;
845 /* Extended */
846 pfl->cfi_table[0x31] = 'P';
847 pfl->cfi_table[0x32] = 'R';
848 pfl->cfi_table[0x33] = 'I';
850 pfl->cfi_table[0x34] = '1';
851 pfl->cfi_table[0x35] = '0';
853 pfl->cfi_table[0x36] = 0x00;
854 pfl->cfi_table[0x37] = 0x00;
855 pfl->cfi_table[0x38] = 0x00;
856 pfl->cfi_table[0x39] = 0x00;
858 pfl->cfi_table[0x3a] = 0x00;
860 pfl->cfi_table[0x3b] = 0x00;
861 pfl->cfi_table[0x3c] = 0x00;
863 pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
866 static Property pflash_cfi01_properties[] = {
867 DEFINE_PROP_DRIVE("drive", struct pflash_t, blk),
868 /* num-blocks is the number of blocks actually visible to the guest,
869 * ie the total size of the device divided by the sector length.
870 * If we're emulating flash devices wired in parallel the actual
871 * number of blocks per indvidual device will differ.
873 DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
874 DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0),
875 /* width here is the overall width of this QEMU device in bytes.
876 * The QEMU device may be emulating a number of flash devices
877 * wired up in parallel; the width of each individual flash
878 * device should be specified via device-width. If the individual
879 * devices have a maximum width which is greater than the width
880 * they are being used for, this maximum width should be set via
881 * max-device-width (which otherwise defaults to device-width).
882 * So for instance a 32-bit wide QEMU flash device made from four
883 * 16-bit flash devices used in 8-bit wide mode would be configured
884 * with width = 4, device-width = 1, max-device-width = 2.
886 * If device-width is not specified we default to backwards
887 * compatible behaviour which is a bad emulation of two
888 * 16 bit devices making up a 32 bit wide QEMU device. This
889 * is deprecated for new uses of this device.
891 DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0),
892 DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0),
893 DEFINE_PROP_UINT8("max-device-width", struct pflash_t, max_device_width, 0),
894 DEFINE_PROP_BIT("big-endian", struct pflash_t, features, PFLASH_BE, 0),
895 DEFINE_PROP_BIT("secure", struct pflash_t, features, PFLASH_SECURE, 0),
896 DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
897 DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
898 DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
899 DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
900 DEFINE_PROP_STRING("name", struct pflash_t, name),
901 DEFINE_PROP_END_OF_LIST(),
904 static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
906 DeviceClass *dc = DEVICE_CLASS(klass);
908 dc->realize = pflash_cfi01_realize;
909 dc->props = pflash_cfi01_properties;
910 dc->vmsd = &vmstate_pflash;
911 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
915 static const TypeInfo pflash_cfi01_info = {
916 .name = TYPE_CFI_PFLASH01,
917 .parent = TYPE_SYS_BUS_DEVICE,
918 .instance_size = sizeof(struct pflash_t),
919 .class_init = pflash_cfi01_class_init,
922 static void pflash_cfi01_register_types(void)
924 type_register_static(&pflash_cfi01_info);
927 type_init(pflash_cfi01_register_types)
929 pflash_t *pflash_cfi01_register(hwaddr base,
930 DeviceState *qdev, const char *name,
931 hwaddr size,
932 BlockBackend *blk,
933 uint32_t sector_len, int nb_blocs,
934 int bank_width, uint16_t id0, uint16_t id1,
935 uint16_t id2, uint16_t id3, int be)
937 DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01);
939 if (blk) {
940 qdev_prop_set_drive(dev, "drive", blk, &error_abort);
942 qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
943 qdev_prop_set_uint64(dev, "sector-length", sector_len);
944 qdev_prop_set_uint8(dev, "width", bank_width);
945 qdev_prop_set_bit(dev, "big-endian", !!be);
946 qdev_prop_set_uint16(dev, "id0", id0);
947 qdev_prop_set_uint16(dev, "id1", id1);
948 qdev_prop_set_uint16(dev, "id2", id2);
949 qdev_prop_set_uint16(dev, "id3", id3);
950 qdev_prop_set_string(dev, "name", name);
951 qdev_init_nofail(dev);
953 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
954 return CFI_PFLASH01(dev);
957 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
959 return &fl->mem;
962 static void postload_update_cb(void *opaque, int running, RunState state)
964 pflash_t *pfl = opaque;
966 /* This is called after bdrv_invalidate_cache_all. */
967 qemu_del_vm_change_state_handler(pfl->vmstate);
968 pfl->vmstate = NULL;
970 DPRINTF("%s: updating bdrv for %s\n", __func__, pfl->name);
971 pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs);
974 static int pflash_post_load(void *opaque, int version_id)
976 pflash_t *pfl = opaque;
978 if (!pfl->ro) {
979 pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
980 pfl);
982 return 0;