4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "translate.h"
29 #include "qemu/host-utils.h"
31 #include "exec/gen-icount.h"
37 static TCGv_i64 cpu_X
[32];
38 static TCGv_i64 cpu_pc
;
39 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
41 static const char *regnames
[] = {
42 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
43 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
44 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
45 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
49 A64_SHIFT_TYPE_LSL
= 0,
50 A64_SHIFT_TYPE_LSR
= 1,
51 A64_SHIFT_TYPE_ASR
= 2,
52 A64_SHIFT_TYPE_ROR
= 3
55 /* initialize TCG globals. */
56 void a64_translate_init(void)
60 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
61 offsetof(CPUARMState
, pc
),
63 for (i
= 0; i
< 32; i
++) {
64 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
65 offsetof(CPUARMState
, xregs
[i
]),
69 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
70 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
71 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
72 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
75 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
76 fprintf_function cpu_fprintf
, int flags
)
78 ARMCPU
*cpu
= ARM_CPU(cs
);
79 CPUARMState
*env
= &cpu
->env
;
80 uint32_t psr
= pstate_read(env
);
83 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
84 env
->pc
, env
->xregs
[31]);
85 for (i
= 0; i
< 31; i
++) {
86 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
93 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
95 psr
& PSTATE_N
? 'N' : '-',
96 psr
& PSTATE_Z
? 'Z' : '-',
97 psr
& PSTATE_C
? 'C' : '-',
98 psr
& PSTATE_V
? 'V' : '-');
102 static int get_mem_index(DisasContext
*s
)
104 #ifdef CONFIG_USER_ONLY
111 void gen_a64_set_pc_im(uint64_t val
)
113 tcg_gen_movi_i64(cpu_pc
, val
);
116 static void gen_exception(int excp
)
118 TCGv_i32 tmp
= tcg_temp_new_i32();
119 tcg_gen_movi_i32(tmp
, excp
);
120 gen_helper_exception(cpu_env
, tmp
);
121 tcg_temp_free_i32(tmp
);
124 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
126 gen_a64_set_pc_im(s
->pc
- offset
);
128 s
->is_jmp
= DISAS_EXC
;
131 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
133 /* No direct tb linking with singlestep or deterministic io */
134 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
138 /* Only link tbs from inside the same guest page */
139 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
146 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
148 TranslationBlock
*tb
;
151 if (use_goto_tb(s
, n
, dest
)) {
153 gen_a64_set_pc_im(dest
);
154 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
155 s
->is_jmp
= DISAS_TB_JUMP
;
157 gen_a64_set_pc_im(dest
);
158 if (s
->singlestep_enabled
) {
159 gen_exception(EXCP_DEBUG
);
162 s
->is_jmp
= DISAS_JUMP
;
166 static void unallocated_encoding(DisasContext
*s
)
168 gen_exception_insn(s
, 4, EXCP_UDEF
);
171 #define unsupported_encoding(s, insn) \
173 qemu_log_mask(LOG_UNIMP, \
174 "%s:%d: unsupported instruction encoding 0x%08x " \
175 "at pc=%016" PRIx64 "\n", \
176 __FILE__, __LINE__, insn, s->pc - 4); \
177 unallocated_encoding(s); \
180 static void init_tmp_a64_array(DisasContext
*s
)
182 #ifdef CONFIG_DEBUG_TCG
184 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
185 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
188 s
->tmp_a64_count
= 0;
191 static void free_tmp_a64(DisasContext
*s
)
194 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
195 tcg_temp_free_i64(s
->tmp_a64
[i
]);
197 init_tmp_a64_array(s
);
200 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
202 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
203 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
206 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
208 TCGv_i64 t
= new_tmp_a64(s
);
209 tcg_gen_movi_i64(t
, 0);
214 * Register access functions
216 * These functions are used for directly accessing a register in where
217 * changes to the final register value are likely to be made. If you
218 * need to use a register for temporary calculation (e.g. index type
219 * operations) use the read_* form.
221 * B1.2.1 Register mappings
223 * In instruction register encoding 31 can refer to ZR (zero register) or
224 * the SP (stack pointer) depending on context. In QEMU's case we map SP
225 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
226 * This is the point of the _sp forms.
228 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
231 return new_tmp_a64_zero(s
);
237 /* register access for when 31 == SP */
238 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
243 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
244 * representing the register contents. This TCGv is an auto-freed
245 * temporary so it need not be explicitly freed, and may be modified.
247 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
249 TCGv_i64 v
= new_tmp_a64(s
);
252 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
254 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
257 tcg_gen_movi_i64(v
, 0);
262 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
264 TCGv_i64 v
= new_tmp_a64(s
);
266 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
268 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
273 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
274 * than the 32 bit equivalent.
276 static inline void gen_set_NZ64(TCGv_i64 result
)
278 TCGv_i64 flag
= tcg_temp_new_i64();
280 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
281 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
282 tcg_gen_shri_i64(flag
, result
, 32);
283 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
284 tcg_temp_free_i64(flag
);
287 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
288 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
291 gen_set_NZ64(result
);
293 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
294 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
296 tcg_gen_movi_i32(cpu_CF
, 0);
297 tcg_gen_movi_i32(cpu_VF
, 0);
300 /* dest = T0 + T1; compute C, N, V and Z flags */
301 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
304 TCGv_i64 result
, flag
, tmp
;
305 result
= tcg_temp_new_i64();
306 flag
= tcg_temp_new_i64();
307 tmp
= tcg_temp_new_i64();
309 tcg_gen_movi_i64(tmp
, 0);
310 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
312 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
314 gen_set_NZ64(result
);
316 tcg_gen_xor_i64(flag
, result
, t0
);
317 tcg_gen_xor_i64(tmp
, t0
, t1
);
318 tcg_gen_andc_i64(flag
, flag
, tmp
);
319 tcg_temp_free_i64(tmp
);
320 tcg_gen_shri_i64(flag
, flag
, 32);
321 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
323 tcg_gen_mov_i64(dest
, result
);
324 tcg_temp_free_i64(result
);
325 tcg_temp_free_i64(flag
);
327 /* 32 bit arithmetic */
328 TCGv_i32 t0_32
= tcg_temp_new_i32();
329 TCGv_i32 t1_32
= tcg_temp_new_i32();
330 TCGv_i32 tmp
= tcg_temp_new_i32();
332 tcg_gen_movi_i32(tmp
, 0);
333 tcg_gen_trunc_i64_i32(t0_32
, t0
);
334 tcg_gen_trunc_i64_i32(t1_32
, t1
);
335 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
336 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
337 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
338 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
339 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
340 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
342 tcg_temp_free_i32(tmp
);
343 tcg_temp_free_i32(t0_32
);
344 tcg_temp_free_i32(t1_32
);
348 /* dest = T0 - T1; compute C, N, V and Z flags */
349 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
352 /* 64 bit arithmetic */
353 TCGv_i64 result
, flag
, tmp
;
355 result
= tcg_temp_new_i64();
356 flag
= tcg_temp_new_i64();
357 tcg_gen_sub_i64(result
, t0
, t1
);
359 gen_set_NZ64(result
);
361 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
362 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
364 tcg_gen_xor_i64(flag
, result
, t0
);
365 tmp
= tcg_temp_new_i64();
366 tcg_gen_xor_i64(tmp
, t0
, t1
);
367 tcg_gen_and_i64(flag
, flag
, tmp
);
368 tcg_temp_free_i64(tmp
);
369 tcg_gen_shri_i64(flag
, flag
, 32);
370 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
371 tcg_gen_mov_i64(dest
, result
);
372 tcg_temp_free_i64(flag
);
373 tcg_temp_free_i64(result
);
375 /* 32 bit arithmetic */
376 TCGv_i32 t0_32
= tcg_temp_new_i32();
377 TCGv_i32 t1_32
= tcg_temp_new_i32();
380 tcg_gen_trunc_i64_i32(t0_32
, t0
);
381 tcg_gen_trunc_i64_i32(t1_32
, t1
);
382 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
383 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
384 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
385 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
386 tmp
= tcg_temp_new_i32();
387 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
388 tcg_temp_free_i32(t0_32
);
389 tcg_temp_free_i32(t1_32
);
390 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
391 tcg_temp_free_i32(tmp
);
392 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
396 /* dest = T0 + T1 + CF; do not compute flags. */
397 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
399 TCGv_i64 flag
= tcg_temp_new_i64();
400 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
401 tcg_gen_add_i64(dest
, t0
, t1
);
402 tcg_gen_add_i64(dest
, dest
, flag
);
403 tcg_temp_free_i64(flag
);
406 tcg_gen_ext32u_i64(dest
, dest
);
410 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
411 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
414 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
415 result
= tcg_temp_new_i64();
416 cf_64
= tcg_temp_new_i64();
417 vf_64
= tcg_temp_new_i64();
418 tmp
= tcg_const_i64(0);
420 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
421 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
422 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
423 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
424 gen_set_NZ64(result
);
426 tcg_gen_xor_i64(vf_64
, result
, t0
);
427 tcg_gen_xor_i64(tmp
, t0
, t1
);
428 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
429 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
430 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
432 tcg_gen_mov_i64(dest
, result
);
434 tcg_temp_free_i64(tmp
);
435 tcg_temp_free_i64(vf_64
);
436 tcg_temp_free_i64(cf_64
);
437 tcg_temp_free_i64(result
);
439 TCGv_i32 t0_32
, t1_32
, tmp
;
440 t0_32
= tcg_temp_new_i32();
441 t1_32
= tcg_temp_new_i32();
442 tmp
= tcg_const_i32(0);
444 tcg_gen_trunc_i64_i32(t0_32
, t0
);
445 tcg_gen_trunc_i64_i32(t1_32
, t1
);
446 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
447 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
449 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
450 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
451 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
452 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
453 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
455 tcg_temp_free_i32(tmp
);
456 tcg_temp_free_i32(t1_32
);
457 tcg_temp_free_i32(t0_32
);
462 * Load/Store generators
466 * Store from GPR register to memory
468 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
469 TCGv_i64 tcg_addr
, int size
)
472 tcg_gen_qemu_st_i64(source
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
476 * Load from memory to GPR register
478 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
479 int size
, bool is_signed
, bool extend
)
481 TCGMemOp memop
= MO_TE
+ size
;
489 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, get_mem_index(s
), memop
);
491 if (extend
&& is_signed
) {
493 tcg_gen_ext32u_i64(dest
, dest
);
498 * Store from FP register to memory
500 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
502 /* This writes the bottom N bits of a 128 bit wide vector to memory */
503 int freg_offs
= offsetof(CPUARMState
, vfp
.regs
[srcidx
* 2]);
504 TCGv_i64 tmp
= tcg_temp_new_i64();
509 tcg_gen_ld8u_i64(tmp
, cpu_env
, freg_offs
);
512 tcg_gen_ld16u_i64(tmp
, cpu_env
, freg_offs
);
515 tcg_gen_ld32u_i64(tmp
, cpu_env
, freg_offs
);
518 tcg_gen_ld_i64(tmp
, cpu_env
, freg_offs
);
521 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
523 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
524 tcg_gen_ld_i64(tmp
, cpu_env
, freg_offs
);
525 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
526 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
527 tcg_gen_ld_i64(tmp
, cpu_env
, freg_offs
+ sizeof(float64
));
528 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
529 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
530 tcg_temp_free_i64(tcg_hiaddr
);
533 tcg_temp_free_i64(tmp
);
537 * Load from memory to FP register
539 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
541 /* This always zero-extends and writes to a full 128 bit wide vector */
542 int freg_offs
= offsetof(CPUARMState
, vfp
.regs
[destidx
* 2]);
543 TCGv_i64 tmplo
= tcg_temp_new_i64();
547 TCGMemOp memop
= MO_TE
+ size
;
548 tmphi
= tcg_const_i64(0);
549 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
552 tmphi
= tcg_temp_new_i64();
553 tcg_hiaddr
= tcg_temp_new_i64();
555 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
556 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
557 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
558 tcg_temp_free_i64(tcg_hiaddr
);
561 tcg_gen_st_i64(tmplo
, cpu_env
, freg_offs
);
562 tcg_gen_st_i64(tmphi
, cpu_env
, freg_offs
+ sizeof(float64
));
564 tcg_temp_free_i64(tmplo
);
565 tcg_temp_free_i64(tmphi
);
569 * This utility function is for doing register extension with an
570 * optional shift. You will likely want to pass a temporary for the
571 * destination register. See DecodeRegExtend() in the ARM ARM.
573 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
574 int option
, unsigned int shift
)
576 int extsize
= extract32(option
, 0, 2);
577 bool is_signed
= extract32(option
, 2, 1);
582 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
585 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
588 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
591 tcg_gen_mov_i64(tcg_out
, tcg_in
);
597 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
600 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
603 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
606 tcg_gen_mov_i64(tcg_out
, tcg_in
);
612 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
616 static inline void gen_check_sp_alignment(DisasContext
*s
)
618 /* The AArch64 architecture mandates that (if enabled via PSTATE
619 * or SCTLR bits) there is a check that SP is 16-aligned on every
620 * SP-relative load or store (with an exception generated if it is not).
621 * In line with general QEMU practice regarding misaligned accesses,
622 * we omit these checks for the sake of guest program performance.
623 * This function is provided as a hook so we can more easily add these
624 * checks in future (possibly as a "favour catching guest program bugs
625 * over speed" user selectable option).
630 * the instruction disassembly implemented here matches
631 * the instruction encoding classifications in chapter 3 (C3)
632 * of the ARM Architecture Reference Manual (DDI0487A_a)
635 /* C3.2.7 Unconditional branch (immediate)
637 * +----+-----------+-------------------------------------+
638 * | op | 0 0 1 0 1 | imm26 |
639 * +----+-----------+-------------------------------------+
641 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
643 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
645 if (insn
& (1 << 31)) {
646 /* C5.6.26 BL Branch with link */
647 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
650 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
651 gen_goto_tb(s
, 0, addr
);
654 /* C3.2.1 Compare & branch (immediate)
655 * 31 30 25 24 23 5 4 0
656 * +----+-------------+----+---------------------+--------+
657 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
658 * +----+-------------+----+---------------------+--------+
660 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
662 unsigned int sf
, op
, rt
;
667 sf
= extract32(insn
, 31, 1);
668 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
669 rt
= extract32(insn
, 0, 5);
670 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
672 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
673 label_match
= gen_new_label();
675 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
676 tcg_cmp
, 0, label_match
);
678 gen_goto_tb(s
, 0, s
->pc
);
679 gen_set_label(label_match
);
680 gen_goto_tb(s
, 1, addr
);
683 /* C3.2.5 Test & branch (immediate)
684 * 31 30 25 24 23 19 18 5 4 0
685 * +----+-------------+----+-------+-------------+------+
686 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
687 * +----+-------------+----+-------+-------------+------+
689 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
691 unsigned int bit_pos
, op
, rt
;
696 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
697 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
698 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
699 rt
= extract32(insn
, 0, 5);
701 tcg_cmp
= tcg_temp_new_i64();
702 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
703 label_match
= gen_new_label();
704 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
705 tcg_cmp
, 0, label_match
);
706 tcg_temp_free_i64(tcg_cmp
);
707 gen_goto_tb(s
, 0, s
->pc
);
708 gen_set_label(label_match
);
709 gen_goto_tb(s
, 1, addr
);
712 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
713 * 31 25 24 23 5 4 3 0
714 * +---------------+----+---------------------+----+------+
715 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
716 * +---------------+----+---------------------+----+------+
718 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
723 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
724 unallocated_encoding(s
);
727 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
728 cond
= extract32(insn
, 0, 4);
731 /* genuinely conditional branches */
732 int label_match
= gen_new_label();
733 arm_gen_test_cc(cond
, label_match
);
734 gen_goto_tb(s
, 0, s
->pc
);
735 gen_set_label(label_match
);
736 gen_goto_tb(s
, 1, addr
);
738 /* 0xe and 0xf are both "always" conditions */
739 gen_goto_tb(s
, 0, addr
);
744 static void handle_hint(DisasContext
*s
, uint32_t insn
,
745 unsigned int op1
, unsigned int op2
, unsigned int crm
)
747 unsigned int selector
= crm
<< 3 | op2
;
750 unallocated_encoding(s
);
762 /* we treat all as NOP at least for now */
765 /* default specified as NOP equivalent */
770 /* CLREX, DSB, DMB, ISB */
771 static void handle_sync(DisasContext
*s
, uint32_t insn
,
772 unsigned int op1
, unsigned int op2
, unsigned int crm
)
775 unallocated_encoding(s
);
781 unsupported_encoding(s
, insn
);
786 /* We don't emulate caches so barriers are no-ops */
789 unallocated_encoding(s
);
794 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
795 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
796 unsigned int op1
, unsigned int op2
, unsigned int crm
)
798 unsupported_encoding(s
, insn
);
801 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
803 TCGv_i32 tmp
= tcg_temp_new_i32();
804 TCGv_i32 nzcv
= tcg_temp_new_i32();
806 /* build bit 31, N */
807 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
808 /* build bit 30, Z */
809 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
810 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
811 /* build bit 29, C */
812 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
813 /* build bit 28, V */
814 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
815 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
816 /* generate result */
817 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
819 tcg_temp_free_i32(nzcv
);
820 tcg_temp_free_i32(tmp
);
823 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
826 TCGv_i32 nzcv
= tcg_temp_new_i32();
828 /* take NZCV from R[t] */
829 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
832 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
834 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
835 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
837 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
838 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
840 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
841 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
842 tcg_temp_free_i32(nzcv
);
845 /* C5.6.129 MRS - move from system register
846 * C5.6.131 MSR (register) - move to system register
849 * These are all essentially the same insn in 'read' and 'write'
850 * versions, with varying op0 fields.
852 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
853 unsigned int op0
, unsigned int op1
, unsigned int op2
,
854 unsigned int crn
, unsigned int crm
, unsigned int rt
)
856 const ARMCPRegInfo
*ri
;
859 ri
= get_arm_cp_reginfo(s
->cp_regs
,
860 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
861 crn
, crm
, op0
, op1
, op2
));
864 /* Unknown register */
865 unallocated_encoding(s
);
869 /* Check access permissions */
870 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
871 unallocated_encoding(s
);
875 /* Handle special cases first */
876 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
880 tcg_rt
= cpu_reg(s
, rt
);
882 gen_get_nzcv(tcg_rt
);
884 gen_set_nzcv(tcg_rt
);
891 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
895 tcg_rt
= cpu_reg(s
, rt
);
898 if (ri
->type
& ARM_CP_CONST
) {
899 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
900 } else if (ri
->readfn
) {
902 gen_a64_set_pc_im(s
->pc
- 4);
903 tmpptr
= tcg_const_ptr(ri
);
904 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
905 tcg_temp_free_ptr(tmpptr
);
907 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
910 if (ri
->type
& ARM_CP_CONST
) {
911 /* If not forbidden by access permissions, treat as WI */
913 } else if (ri
->writefn
) {
915 gen_a64_set_pc_im(s
->pc
- 4);
916 tmpptr
= tcg_const_ptr(ri
);
917 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
918 tcg_temp_free_ptr(tmpptr
);
920 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
924 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
925 /* I/O operations must end the TB here (whether read or write) */
927 s
->is_jmp
= DISAS_UPDATE
;
928 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
929 /* We default to ending the TB on a coprocessor register write,
930 * but allow this to be suppressed by the register definition
931 * (usually only necessary to work around guest bugs).
933 s
->is_jmp
= DISAS_UPDATE
;
938 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
939 * +---------------------+---+-----+-----+-------+-------+-----+------+
940 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
941 * +---------------------+---+-----+-----+-------+-------+-----+------+
943 static void disas_system(DisasContext
*s
, uint32_t insn
)
945 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
946 l
= extract32(insn
, 21, 1);
947 op0
= extract32(insn
, 19, 2);
948 op1
= extract32(insn
, 16, 3);
949 crn
= extract32(insn
, 12, 4);
950 crm
= extract32(insn
, 8, 4);
951 op2
= extract32(insn
, 5, 3);
952 rt
= extract32(insn
, 0, 5);
956 unallocated_encoding(s
);
960 case 2: /* C5.6.68 HINT */
961 handle_hint(s
, insn
, op1
, op2
, crm
);
963 case 3: /* CLREX, DSB, DMB, ISB */
964 handle_sync(s
, insn
, op1
, op2
, crm
);
966 case 4: /* C5.6.130 MSR (immediate) */
967 handle_msr_i(s
, insn
, op1
, op2
, crm
);
970 unallocated_encoding(s
);
975 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
978 /* C3.2.3 Exception generation
980 * 31 24 23 21 20 5 4 2 1 0
981 * +-----------------+-----+------------------------+-----+----+
982 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
983 * +-----------------------+------------------------+----------+
985 static void disas_exc(DisasContext
*s
, uint32_t insn
)
987 int opc
= extract32(insn
, 21, 3);
988 int op2_ll
= extract32(insn
, 0, 5);
992 /* SVC, HVC, SMC; since we don't support the Virtualization
993 * or TrustZone extensions these all UNDEF except SVC.
996 unallocated_encoding(s
);
999 gen_exception_insn(s
, 0, EXCP_SWI
);
1003 unallocated_encoding(s
);
1007 gen_exception_insn(s
, 0, EXCP_BKPT
);
1011 unallocated_encoding(s
);
1015 unsupported_encoding(s
, insn
);
1018 if (op2_ll
< 1 || op2_ll
> 3) {
1019 unallocated_encoding(s
);
1022 /* DCPS1, DCPS2, DCPS3 */
1023 unsupported_encoding(s
, insn
);
1026 unallocated_encoding(s
);
1031 /* C3.2.7 Unconditional branch (register)
1032 * 31 25 24 21 20 16 15 10 9 5 4 0
1033 * +---------------+-------+-------+-------+------+-------+
1034 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1035 * +---------------+-------+-------+-------+------+-------+
1037 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1039 unsigned int opc
, op2
, op3
, rn
, op4
;
1041 opc
= extract32(insn
, 21, 4);
1042 op2
= extract32(insn
, 16, 5);
1043 op3
= extract32(insn
, 10, 6);
1044 rn
= extract32(insn
, 5, 5);
1045 op4
= extract32(insn
, 0, 5);
1047 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1048 unallocated_encoding(s
);
1057 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1062 unallocated_encoding(s
);
1064 unsupported_encoding(s
, insn
);
1068 unallocated_encoding(s
);
1072 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1073 s
->is_jmp
= DISAS_JUMP
;
1076 /* C3.2 Branches, exception generating and system instructions */
1077 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1079 switch (extract32(insn
, 25, 7)) {
1080 case 0x0a: case 0x0b:
1081 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1082 disas_uncond_b_imm(s
, insn
);
1084 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1085 disas_comp_b_imm(s
, insn
);
1087 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1088 disas_test_b_imm(s
, insn
);
1090 case 0x2a: /* Conditional branch (immediate) */
1091 disas_cond_b_imm(s
, insn
);
1093 case 0x6a: /* Exception generation / System */
1094 if (insn
& (1 << 24)) {
1095 disas_system(s
, insn
);
1100 case 0x6b: /* Unconditional branch (register) */
1101 disas_uncond_b_reg(s
, insn
);
1104 unallocated_encoding(s
);
1109 /* Load/store exclusive */
1110 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1112 unsupported_encoding(s
, insn
);
1116 * C3.3.5 Load register (literal)
1118 * 31 30 29 27 26 25 24 23 5 4 0
1119 * +-----+-------+---+-----+-------------------+-------+
1120 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1121 * +-----+-------+---+-----+-------------------+-------+
1123 * V: 1 -> vector (simd/fp)
1124 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1125 * 10-> 32 bit signed, 11 -> prefetch
1126 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1128 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1130 int rt
= extract32(insn
, 0, 5);
1131 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1132 bool is_vector
= extract32(insn
, 26, 1);
1133 int opc
= extract32(insn
, 30, 2);
1134 bool is_signed
= false;
1136 TCGv_i64 tcg_rt
, tcg_addr
;
1140 unallocated_encoding(s
);
1146 /* PRFM (literal) : prefetch */
1149 size
= 2 + extract32(opc
, 0, 1);
1150 is_signed
= extract32(opc
, 1, 1);
1153 tcg_rt
= cpu_reg(s
, rt
);
1155 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1157 do_fp_ld(s
, rt
, tcg_addr
, size
);
1159 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1161 tcg_temp_free_i64(tcg_addr
);
1165 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1166 * C5.6.81 LDP (Load Pair - non vector)
1167 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1168 * C5.6.176 STNP (Store Pair - non-temporal hint)
1169 * C5.6.177 STP (Store Pair - non vector)
1170 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1171 * C6.3.165 LDP (Load Pair of SIMD&FP)
1172 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1173 * C6.3.284 STP (Store Pair of SIMD&FP)
1175 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1176 * +-----+-------+---+---+-------+---+-----------------------------+
1177 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1178 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1180 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1182 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1183 * V: 0 -> GPR, 1 -> Vector
1184 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1185 * 10 -> signed offset, 11 -> pre-index
1186 * L: 0 -> Store 1 -> Load
1188 * Rt, Rt2 = GPR or SIMD registers to be stored
1189 * Rn = general purpose register containing address
1190 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1192 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1194 int rt
= extract32(insn
, 0, 5);
1195 int rn
= extract32(insn
, 5, 5);
1196 int rt2
= extract32(insn
, 10, 5);
1197 int64_t offset
= sextract32(insn
, 15, 7);
1198 int index
= extract32(insn
, 23, 2);
1199 bool is_vector
= extract32(insn
, 26, 1);
1200 bool is_load
= extract32(insn
, 22, 1);
1201 int opc
= extract32(insn
, 30, 2);
1203 bool is_signed
= false;
1204 bool postindex
= false;
1207 TCGv_i64 tcg_addr
; /* calculated address */
1211 unallocated_encoding(s
);
1218 size
= 2 + extract32(opc
, 1, 1);
1219 is_signed
= extract32(opc
, 0, 1);
1220 if (!is_load
&& is_signed
) {
1221 unallocated_encoding(s
);
1227 case 1: /* post-index */
1232 /* signed offset with "non-temporal" hint. Since we don't emulate
1233 * caches we don't care about hints to the cache system about
1234 * data access patterns, and handle this identically to plain
1238 /* There is no non-temporal-hint version of LDPSW */
1239 unallocated_encoding(s
);
1244 case 2: /* signed offset, rn not updated */
1247 case 3: /* pre-index */
1256 gen_check_sp_alignment(s
);
1259 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1262 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1267 do_fp_ld(s
, rt
, tcg_addr
, size
);
1269 do_fp_st(s
, rt
, tcg_addr
, size
);
1272 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1274 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1276 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1279 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1282 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1284 do_fp_st(s
, rt2
, tcg_addr
, size
);
1287 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1289 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1291 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1297 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1299 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1301 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1306 * C3.3.8 Load/store (immediate post-indexed)
1307 * C3.3.9 Load/store (immediate pre-indexed)
1308 * C3.3.12 Load/store (unscaled immediate)
1310 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1311 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1312 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1313 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1315 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1316 * V = 0 -> non-vector
1317 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1318 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1320 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1322 int rt
= extract32(insn
, 0, 5);
1323 int rn
= extract32(insn
, 5, 5);
1324 int imm9
= sextract32(insn
, 12, 9);
1325 int opc
= extract32(insn
, 22, 2);
1326 int size
= extract32(insn
, 30, 2);
1327 int idx
= extract32(insn
, 10, 2);
1328 bool is_signed
= false;
1329 bool is_store
= false;
1330 bool is_extended
= false;
1331 bool is_vector
= extract32(insn
, 26, 1);
1338 size
|= (opc
& 2) << 1;
1340 unallocated_encoding(s
);
1343 is_store
= ((opc
& 1) == 0);
1345 if (size
== 3 && opc
== 2) {
1346 /* PRFM - prefetch */
1349 if (opc
== 3 && size
> 1) {
1350 unallocated_encoding(s
);
1353 is_store
= (opc
== 0);
1354 is_signed
= opc
& (1<<1);
1355 is_extended
= (size
< 3) && (opc
& 1);
1377 gen_check_sp_alignment(s
);
1379 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1382 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1387 do_fp_st(s
, rt
, tcg_addr
, size
);
1389 do_fp_ld(s
, rt
, tcg_addr
, size
);
1392 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1394 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1396 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
1401 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1403 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1405 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
1410 * C3.3.10 Load/store (register offset)
1412 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1413 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1414 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1415 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1418 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1419 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1421 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1422 * opc<0>: 0 -> store, 1 -> load
1423 * V: 1 -> vector/simd
1424 * opt: extend encoding (see DecodeRegExtend)
1425 * S: if S=1 then scale (essentially index by sizeof(size))
1426 * Rt: register to transfer into/out of
1427 * Rn: address register or SP for base
1428 * Rm: offset register or ZR for offset
1430 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
1432 int rt
= extract32(insn
, 0, 5);
1433 int rn
= extract32(insn
, 5, 5);
1434 int shift
= extract32(insn
, 12, 1);
1435 int rm
= extract32(insn
, 16, 5);
1436 int opc
= extract32(insn
, 22, 2);
1437 int opt
= extract32(insn
, 13, 3);
1438 int size
= extract32(insn
, 30, 2);
1439 bool is_signed
= false;
1440 bool is_store
= false;
1441 bool is_extended
= false;
1442 bool is_vector
= extract32(insn
, 26, 1);
1447 if (extract32(opt
, 1, 1) == 0) {
1448 unallocated_encoding(s
);
1453 size
|= (opc
& 2) << 1;
1455 unallocated_encoding(s
);
1458 is_store
= !extract32(opc
, 0, 1);
1460 if (size
== 3 && opc
== 2) {
1461 /* PRFM - prefetch */
1464 if (opc
== 3 && size
> 1) {
1465 unallocated_encoding(s
);
1468 is_store
= (opc
== 0);
1469 is_signed
= extract32(opc
, 1, 1);
1470 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
1474 gen_check_sp_alignment(s
);
1476 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1478 tcg_rm
= read_cpu_reg(s
, rm
, 1);
1479 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
1481 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
1485 do_fp_st(s
, rt
, tcg_addr
, size
);
1487 do_fp_ld(s
, rt
, tcg_addr
, size
);
1490 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1492 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1494 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
1500 * C3.3.13 Load/store (unsigned immediate)
1502 * 31 30 29 27 26 25 24 23 22 21 10 9 5
1503 * +----+-------+---+-----+-----+------------+-------+------+
1504 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
1505 * +----+-------+---+-----+-----+------------+-------+------+
1508 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1509 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1511 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1512 * opc<0>: 0 -> store, 1 -> load
1513 * Rn: base address register (inc SP)
1514 * Rt: target register
1516 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
1518 int rt
= extract32(insn
, 0, 5);
1519 int rn
= extract32(insn
, 5, 5);
1520 unsigned int imm12
= extract32(insn
, 10, 12);
1521 bool is_vector
= extract32(insn
, 26, 1);
1522 int size
= extract32(insn
, 30, 2);
1523 int opc
= extract32(insn
, 22, 2);
1524 unsigned int offset
;
1529 bool is_signed
= false;
1530 bool is_extended
= false;
1533 size
|= (opc
& 2) << 1;
1535 unallocated_encoding(s
);
1538 is_store
= !extract32(opc
, 0, 1);
1540 if (size
== 3 && opc
== 2) {
1541 /* PRFM - prefetch */
1544 if (opc
== 3 && size
> 1) {
1545 unallocated_encoding(s
);
1548 is_store
= (opc
== 0);
1549 is_signed
= extract32(opc
, 1, 1);
1550 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
1554 gen_check_sp_alignment(s
);
1556 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1557 offset
= imm12
<< size
;
1558 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1562 do_fp_st(s
, rt
, tcg_addr
, size
);
1564 do_fp_ld(s
, rt
, tcg_addr
, size
);
1567 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1569 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1571 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
1576 /* Load/store register (immediate forms) */
1577 static void disas_ldst_reg_imm(DisasContext
*s
, uint32_t insn
)
1579 switch (extract32(insn
, 10, 2)) {
1580 case 0: case 1: case 3:
1581 /* Load/store register (unscaled immediate) */
1582 /* Load/store immediate pre/post-indexed */
1583 disas_ldst_reg_imm9(s
, insn
);
1586 /* Load/store register unprivileged */
1587 unsupported_encoding(s
, insn
);
1590 unallocated_encoding(s
);
1595 /* Load/store register (all forms) */
1596 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
1598 switch (extract32(insn
, 24, 2)) {
1600 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
1601 disas_ldst_reg_roffset(s
, insn
);
1603 disas_ldst_reg_imm(s
, insn
);
1607 disas_ldst_reg_unsigned_imm(s
, insn
);
1610 unallocated_encoding(s
);
1615 /* AdvSIMD load/store multiple structures */
1616 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
1618 unsupported_encoding(s
, insn
);
1621 /* AdvSIMD load/store single structure */
1622 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
1624 unsupported_encoding(s
, insn
);
1627 /* C3.3 Loads and stores */
1628 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
1630 switch (extract32(insn
, 24, 6)) {
1631 case 0x08: /* Load/store exclusive */
1632 disas_ldst_excl(s
, insn
);
1634 case 0x18: case 0x1c: /* Load register (literal) */
1635 disas_ld_lit(s
, insn
);
1637 case 0x28: case 0x29:
1638 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
1639 disas_ldst_pair(s
, insn
);
1641 case 0x38: case 0x39:
1642 case 0x3c: case 0x3d: /* Load/store register (all forms) */
1643 disas_ldst_reg(s
, insn
);
1645 case 0x0c: /* AdvSIMD load/store multiple structures */
1646 disas_ldst_multiple_struct(s
, insn
);
1648 case 0x0d: /* AdvSIMD load/store single structure */
1649 disas_ldst_single_struct(s
, insn
);
1652 unallocated_encoding(s
);
1657 /* C3.4.6 PC-rel. addressing
1658 * 31 30 29 28 24 23 5 4 0
1659 * +----+-------+-----------+-------------------+------+
1660 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
1661 * +----+-------+-----------+-------------------+------+
1663 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
1665 unsigned int page
, rd
;
1669 page
= extract32(insn
, 31, 1);
1670 /* SignExtend(immhi:immlo) -> offset */
1671 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
1672 rd
= extract32(insn
, 0, 5);
1676 /* ADRP (page based) */
1681 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
1685 * C3.4.1 Add/subtract (immediate)
1687 * 31 30 29 28 24 23 22 21 10 9 5 4 0
1688 * +--+--+--+-----------+-----+-------------+-----+-----+
1689 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
1690 * +--+--+--+-----------+-----+-------------+-----+-----+
1692 * sf: 0 -> 32bit, 1 -> 64bit
1693 * op: 0 -> add , 1 -> sub
1695 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
1697 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
1699 int rd
= extract32(insn
, 0, 5);
1700 int rn
= extract32(insn
, 5, 5);
1701 uint64_t imm
= extract32(insn
, 10, 12);
1702 int shift
= extract32(insn
, 22, 2);
1703 bool setflags
= extract32(insn
, 29, 1);
1704 bool sub_op
= extract32(insn
, 30, 1);
1705 bool is_64bit
= extract32(insn
, 31, 1);
1707 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1708 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
1709 TCGv_i64 tcg_result
;
1718 unallocated_encoding(s
);
1722 tcg_result
= tcg_temp_new_i64();
1725 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
1727 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
1730 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
1732 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
1734 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
1736 tcg_temp_free_i64(tcg_imm
);
1740 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
1742 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
1745 tcg_temp_free_i64(tcg_result
);
1748 /* The input should be a value in the bottom e bits (with higher
1749 * bits zero); returns that value replicated into every element
1750 * of size e in a 64 bit integer.
1752 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
1762 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
1763 static inline uint64_t bitmask64(unsigned int length
)
1765 assert(length
> 0 && length
<= 64);
1766 return ~0ULL >> (64 - length
);
1769 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
1770 * only require the wmask. Returns false if the imms/immr/immn are a reserved
1771 * value (ie should cause a guest UNDEF exception), and true if they are
1772 * valid, in which case the decoded bit pattern is written to result.
1774 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
1775 unsigned int imms
, unsigned int immr
)
1778 unsigned e
, levels
, s
, r
;
1781 assert(immn
< 2 && imms
< 64 && immr
< 64);
1783 /* The bit patterns we create here are 64 bit patterns which
1784 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
1785 * 64 bits each. Each element contains the same value: a run
1786 * of between 1 and e-1 non-zero bits, rotated within the
1787 * element by between 0 and e-1 bits.
1789 * The element size and run length are encoded into immn (1 bit)
1790 * and imms (6 bits) as follows:
1791 * 64 bit elements: immn = 1, imms = <length of run - 1>
1792 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
1793 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
1794 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
1795 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
1796 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
1797 * Notice that immn = 0, imms = 11111x is the only combination
1798 * not covered by one of the above options; this is reserved.
1799 * Further, <length of run - 1> all-ones is a reserved pattern.
1801 * In all cases the rotation is by immr % e (and immr is 6 bits).
1804 /* First determine the element size */
1805 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
1807 /* This is the immn == 0, imms == 0x11111x case */
1817 /* <length of run - 1> mustn't be all-ones. */
1821 /* Create the value of one element: s+1 set bits rotated
1822 * by r within the element (which is e bits wide)...
1824 mask
= bitmask64(s
+ 1);
1825 mask
= (mask
>> r
) | (mask
<< (e
- r
));
1826 /* ...then replicate the element over the whole 64 bit value */
1827 mask
= bitfield_replicate(mask
, e
);
1832 /* C3.4.4 Logical (immediate)
1833 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
1834 * +----+-----+-------------+---+------+------+------+------+
1835 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
1836 * +----+-----+-------------+---+------+------+------+------+
1838 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
1840 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
1841 TCGv_i64 tcg_rd
, tcg_rn
;
1843 bool is_and
= false;
1845 sf
= extract32(insn
, 31, 1);
1846 opc
= extract32(insn
, 29, 2);
1847 is_n
= extract32(insn
, 22, 1);
1848 immr
= extract32(insn
, 16, 6);
1849 imms
= extract32(insn
, 10, 6);
1850 rn
= extract32(insn
, 5, 5);
1851 rd
= extract32(insn
, 0, 5);
1854 unallocated_encoding(s
);
1858 if (opc
== 0x3) { /* ANDS */
1859 tcg_rd
= cpu_reg(s
, rd
);
1861 tcg_rd
= cpu_reg_sp(s
, rd
);
1863 tcg_rn
= cpu_reg(s
, rn
);
1865 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
1866 /* some immediate field values are reserved */
1867 unallocated_encoding(s
);
1872 wmask
&= 0xffffffff;
1876 case 0x3: /* ANDS */
1878 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
1882 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
1885 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
1888 assert(FALSE
); /* must handle all above */
1892 if (!sf
&& !is_and
) {
1893 /* zero extend final result; we know we can skip this for AND
1894 * since the immediate had the high 32 bits clear.
1896 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
1899 if (opc
== 3) { /* ANDS */
1900 gen_logic_CC(sf
, tcg_rd
);
1905 * C3.4.5 Move wide (immediate)
1907 * 31 30 29 28 23 22 21 20 5 4 0
1908 * +--+-----+-------------+-----+----------------+------+
1909 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
1910 * +--+-----+-------------+-----+----------------+------+
1912 * sf: 0 -> 32 bit, 1 -> 64 bit
1913 * opc: 00 -> N, 10 -> Z, 11 -> K
1914 * hw: shift/16 (0,16, and sf only 32, 48)
1916 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
1918 int rd
= extract32(insn
, 0, 5);
1919 uint64_t imm
= extract32(insn
, 5, 16);
1920 int sf
= extract32(insn
, 31, 1);
1921 int opc
= extract32(insn
, 29, 2);
1922 int pos
= extract32(insn
, 21, 2) << 4;
1923 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
1926 if (!sf
&& (pos
>= 32)) {
1927 unallocated_encoding(s
);
1941 tcg_gen_movi_i64(tcg_rd
, imm
);
1944 tcg_imm
= tcg_const_i64(imm
);
1945 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
1946 tcg_temp_free_i64(tcg_imm
);
1948 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
1952 unallocated_encoding(s
);
1958 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
1959 * +----+-----+-------------+---+------+------+------+------+
1960 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
1961 * +----+-----+-------------+---+------+------+------+------+
1963 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
1965 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
1966 TCGv_i64 tcg_rd
, tcg_tmp
;
1968 sf
= extract32(insn
, 31, 1);
1969 opc
= extract32(insn
, 29, 2);
1970 n
= extract32(insn
, 22, 1);
1971 ri
= extract32(insn
, 16, 6);
1972 si
= extract32(insn
, 10, 6);
1973 rn
= extract32(insn
, 5, 5);
1974 rd
= extract32(insn
, 0, 5);
1975 bitsize
= sf
? 64 : 32;
1977 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
1978 unallocated_encoding(s
);
1982 tcg_rd
= cpu_reg(s
, rd
);
1983 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
1985 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
1987 if (opc
!= 1) { /* SBFM or UBFM */
1988 tcg_gen_movi_i64(tcg_rd
, 0);
1991 /* do the bit move operation */
1993 /* Wd<s-r:0> = Wn<s:r> */
1994 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
1996 len
= (si
- ri
) + 1;
1998 /* Wd<32+s-r,32-r> = Wn<s:0> */
2003 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2005 if (opc
== 0) { /* SBFM - sign extend the destination field */
2006 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2007 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2010 if (!sf
) { /* zero extend final result */
2011 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2016 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2017 * +----+------+-------------+---+----+------+--------+------+------+
2018 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2019 * +----+------+-------------+---+----+------+--------+------+------+
2021 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2023 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2025 sf
= extract32(insn
, 31, 1);
2026 n
= extract32(insn
, 22, 1);
2027 rm
= extract32(insn
, 16, 5);
2028 imm
= extract32(insn
, 10, 6);
2029 rn
= extract32(insn
, 5, 5);
2030 rd
= extract32(insn
, 0, 5);
2031 op21
= extract32(insn
, 29, 2);
2032 op0
= extract32(insn
, 21, 1);
2033 bitsize
= sf
? 64 : 32;
2035 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2036 unallocated_encoding(s
);
2038 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2040 tcg_rd
= cpu_reg(s
, rd
);
2043 /* OPTME: we can special case rm==rn as a rotate */
2044 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2045 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2046 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2047 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2048 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2050 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2053 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2054 * so an extract from bit 0 is a special case.
2057 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2059 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2066 /* C3.4 Data processing - immediate */
2067 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2069 switch (extract32(insn
, 23, 6)) {
2070 case 0x20: case 0x21: /* PC-rel. addressing */
2071 disas_pc_rel_adr(s
, insn
);
2073 case 0x22: case 0x23: /* Add/subtract (immediate) */
2074 disas_add_sub_imm(s
, insn
);
2076 case 0x24: /* Logical (immediate) */
2077 disas_logic_imm(s
, insn
);
2079 case 0x25: /* Move wide (immediate) */
2080 disas_movw_imm(s
, insn
);
2082 case 0x26: /* Bitfield */
2083 disas_bitfield(s
, insn
);
2085 case 0x27: /* Extract */
2086 disas_extract(s
, insn
);
2089 unallocated_encoding(s
);
2094 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2095 * Note that it is the caller's responsibility to ensure that the
2096 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2097 * mandated semantics for out of range shifts.
2099 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2100 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
2102 switch (shift_type
) {
2103 case A64_SHIFT_TYPE_LSL
:
2104 tcg_gen_shl_i64(dst
, src
, shift_amount
);
2106 case A64_SHIFT_TYPE_LSR
:
2107 tcg_gen_shr_i64(dst
, src
, shift_amount
);
2109 case A64_SHIFT_TYPE_ASR
:
2111 tcg_gen_ext32s_i64(dst
, src
);
2113 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
2115 case A64_SHIFT_TYPE_ROR
:
2117 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
2120 t0
= tcg_temp_new_i32();
2121 t1
= tcg_temp_new_i32();
2122 tcg_gen_trunc_i64_i32(t0
, src
);
2123 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
2124 tcg_gen_rotr_i32(t0
, t0
, t1
);
2125 tcg_gen_extu_i32_i64(dst
, t0
);
2126 tcg_temp_free_i32(t0
);
2127 tcg_temp_free_i32(t1
);
2131 assert(FALSE
); /* all shift types should be handled */
2135 if (!sf
) { /* zero extend final result */
2136 tcg_gen_ext32u_i64(dst
, dst
);
2140 /* Shift a TCGv src by immediate, put result in dst.
2141 * The shift amount must be in range (this should always be true as the
2142 * relevant instructions will UNDEF on bad shift immediates).
2144 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2145 enum a64_shift_type shift_type
, unsigned int shift_i
)
2147 assert(shift_i
< (sf
? 64 : 32));
2150 tcg_gen_mov_i64(dst
, src
);
2152 TCGv_i64 shift_const
;
2154 shift_const
= tcg_const_i64(shift_i
);
2155 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
2156 tcg_temp_free_i64(shift_const
);
2160 /* C3.5.10 Logical (shifted register)
2161 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2162 * +----+-----+-----------+-------+---+------+--------+------+------+
2163 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2164 * +----+-----+-----------+-------+---+------+--------+------+------+
2166 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
2168 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
2169 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
2171 sf
= extract32(insn
, 31, 1);
2172 opc
= extract32(insn
, 29, 2);
2173 shift_type
= extract32(insn
, 22, 2);
2174 invert
= extract32(insn
, 21, 1);
2175 rm
= extract32(insn
, 16, 5);
2176 shift_amount
= extract32(insn
, 10, 6);
2177 rn
= extract32(insn
, 5, 5);
2178 rd
= extract32(insn
, 0, 5);
2180 if (!sf
&& (shift_amount
& (1 << 5))) {
2181 unallocated_encoding(s
);
2185 tcg_rd
= cpu_reg(s
, rd
);
2187 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
2188 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
2189 * register-register MOV and MVN, so it is worth special casing.
2191 tcg_rm
= cpu_reg(s
, rm
);
2193 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
2195 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2199 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
2201 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
2207 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2210 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
2213 tcg_rn
= cpu_reg(s
, rn
);
2215 switch (opc
| (invert
<< 2)) {
2218 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2221 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2224 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2228 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2231 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2234 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2242 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2246 gen_logic_CC(sf
, tcg_rd
);
2251 * C3.5.1 Add/subtract (extended register)
2253 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
2254 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
2255 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
2256 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
2258 * sf: 0 -> 32bit, 1 -> 64bit
2259 * op: 0 -> add , 1 -> sub
2262 * option: extension type (see DecodeRegExtend)
2263 * imm3: optional shift to Rm
2265 * Rd = Rn + LSL(extend(Rm), amount)
2267 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
2269 int rd
= extract32(insn
, 0, 5);
2270 int rn
= extract32(insn
, 5, 5);
2271 int imm3
= extract32(insn
, 10, 3);
2272 int option
= extract32(insn
, 13, 3);
2273 int rm
= extract32(insn
, 16, 5);
2274 bool setflags
= extract32(insn
, 29, 1);
2275 bool sub_op
= extract32(insn
, 30, 1);
2276 bool sf
= extract32(insn
, 31, 1);
2278 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
2280 TCGv_i64 tcg_result
;
2283 unallocated_encoding(s
);
2287 /* non-flag setting ops may use SP */
2289 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
2290 tcg_rd
= cpu_reg_sp(s
, rd
);
2292 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2293 tcg_rd
= cpu_reg(s
, rd
);
2296 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2297 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
2299 tcg_result
= tcg_temp_new_i64();
2303 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
2305 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
2309 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2311 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2316 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2318 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2321 tcg_temp_free_i64(tcg_result
);
2325 * C3.5.2 Add/subtract (shifted register)
2327 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2328 * +--+--+--+-----------+-----+--+-------+---------+------+------+
2329 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
2330 * +--+--+--+-----------+-----+--+-------+---------+------+------+
2332 * sf: 0 -> 32bit, 1 -> 64bit
2333 * op: 0 -> add , 1 -> sub
2335 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
2336 * imm6: Shift amount to apply to Rm before the add/sub
2338 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
2340 int rd
= extract32(insn
, 0, 5);
2341 int rn
= extract32(insn
, 5, 5);
2342 int imm6
= extract32(insn
, 10, 6);
2343 int rm
= extract32(insn
, 16, 5);
2344 int shift_type
= extract32(insn
, 22, 2);
2345 bool setflags
= extract32(insn
, 29, 1);
2346 bool sub_op
= extract32(insn
, 30, 1);
2347 bool sf
= extract32(insn
, 31, 1);
2349 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2350 TCGv_i64 tcg_rn
, tcg_rm
;
2351 TCGv_i64 tcg_result
;
2353 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
2354 unallocated_encoding(s
);
2358 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2359 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2361 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
2363 tcg_result
= tcg_temp_new_i64();
2367 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
2369 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
2373 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2375 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2380 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2382 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2385 tcg_temp_free_i64(tcg_result
);
2388 /* C3.5.9 Data-processing (3 source)
2390 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
2391 +--+------+-----------+------+------+----+------+------+------+
2392 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
2393 +--+------+-----------+------+------+----+------+------+------+
2396 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
2398 int rd
= extract32(insn
, 0, 5);
2399 int rn
= extract32(insn
, 5, 5);
2400 int ra
= extract32(insn
, 10, 5);
2401 int rm
= extract32(insn
, 16, 5);
2402 int op_id
= (extract32(insn
, 29, 3) << 4) |
2403 (extract32(insn
, 21, 3) << 1) |
2404 extract32(insn
, 15, 1);
2405 bool sf
= extract32(insn
, 31, 1);
2406 bool is_sub
= extract32(op_id
, 0, 1);
2407 bool is_high
= extract32(op_id
, 2, 1);
2408 bool is_signed
= false;
2413 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
2415 case 0x42: /* SMADDL */
2416 case 0x43: /* SMSUBL */
2417 case 0x44: /* SMULH */
2420 case 0x0: /* MADD (32bit) */
2421 case 0x1: /* MSUB (32bit) */
2422 case 0x40: /* MADD (64bit) */
2423 case 0x41: /* MSUB (64bit) */
2424 case 0x4a: /* UMADDL */
2425 case 0x4b: /* UMSUBL */
2426 case 0x4c: /* UMULH */
2429 unallocated_encoding(s
);
2434 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
2435 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2436 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
2437 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
2440 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
2442 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
2445 tcg_temp_free_i64(low_bits
);
2449 tcg_op1
= tcg_temp_new_i64();
2450 tcg_op2
= tcg_temp_new_i64();
2451 tcg_tmp
= tcg_temp_new_i64();
2454 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
2455 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
2458 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
2459 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
2461 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
2462 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
2466 if (ra
== 31 && !is_sub
) {
2467 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
2468 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
2470 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
2472 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
2474 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
2479 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
2482 tcg_temp_free_i64(tcg_op1
);
2483 tcg_temp_free_i64(tcg_op2
);
2484 tcg_temp_free_i64(tcg_tmp
);
2487 /* C3.5.3 - Add/subtract (with carry)
2488 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
2489 * +--+--+--+------------------------+------+---------+------+-----+
2490 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
2491 * +--+--+--+------------------------+------+---------+------+-----+
2495 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
2497 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
2498 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
2500 if (extract32(insn
, 10, 6) != 0) {
2501 unallocated_encoding(s
);
2505 sf
= extract32(insn
, 31, 1);
2506 op
= extract32(insn
, 30, 1);
2507 setflags
= extract32(insn
, 29, 1);
2508 rm
= extract32(insn
, 16, 5);
2509 rn
= extract32(insn
, 5, 5);
2510 rd
= extract32(insn
, 0, 5);
2512 tcg_rd
= cpu_reg(s
, rd
);
2513 tcg_rn
= cpu_reg(s
, rn
);
2516 tcg_y
= new_tmp_a64(s
);
2517 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
2519 tcg_y
= cpu_reg(s
, rm
);
2523 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
2525 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
2529 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
2530 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
2531 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
2532 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
2533 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
2536 static void disas_cc(DisasContext
*s
, uint32_t insn
)
2538 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
2539 int label_continue
= -1;
2540 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
2542 if (!extract32(insn
, 29, 1)) {
2543 unallocated_encoding(s
);
2546 if (insn
& (1 << 10 | 1 << 4)) {
2547 unallocated_encoding(s
);
2550 sf
= extract32(insn
, 31, 1);
2551 op
= extract32(insn
, 30, 1);
2552 is_imm
= extract32(insn
, 11, 1);
2553 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
2554 cond
= extract32(insn
, 12, 4);
2555 rn
= extract32(insn
, 5, 5);
2556 nzcv
= extract32(insn
, 0, 4);
2558 if (cond
< 0x0e) { /* not always */
2559 int label_match
= gen_new_label();
2560 label_continue
= gen_new_label();
2561 arm_gen_test_cc(cond
, label_match
);
2563 tcg_tmp
= tcg_temp_new_i64();
2564 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
2565 gen_set_nzcv(tcg_tmp
);
2566 tcg_temp_free_i64(tcg_tmp
);
2567 tcg_gen_br(label_continue
);
2568 gen_set_label(label_match
);
2570 /* match, or condition is always */
2572 tcg_y
= new_tmp_a64(s
);
2573 tcg_gen_movi_i64(tcg_y
, y
);
2575 tcg_y
= cpu_reg(s
, y
);
2577 tcg_rn
= cpu_reg(s
, rn
);
2579 tcg_tmp
= tcg_temp_new_i64();
2581 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
2583 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
2585 tcg_temp_free_i64(tcg_tmp
);
2587 if (cond
< 0x0e) { /* continue */
2588 gen_set_label(label_continue
);
2592 /* C3.5.6 Conditional select
2593 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
2594 * +----+----+---+-----------------+------+------+-----+------+------+
2595 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
2596 * +----+----+---+-----------------+------+------+-----+------+------+
2598 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
2600 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
2601 TCGv_i64 tcg_rd
, tcg_src
;
2603 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
2604 /* S == 1 or op2<1> == 1 */
2605 unallocated_encoding(s
);
2608 sf
= extract32(insn
, 31, 1);
2609 else_inv
= extract32(insn
, 30, 1);
2610 rm
= extract32(insn
, 16, 5);
2611 cond
= extract32(insn
, 12, 4);
2612 else_inc
= extract32(insn
, 10, 1);
2613 rn
= extract32(insn
, 5, 5);
2614 rd
= extract32(insn
, 0, 5);
2617 /* silly no-op write; until we use movcond we must special-case
2618 * this to avoid a dead temporary across basic blocks.
2623 tcg_rd
= cpu_reg(s
, rd
);
2625 if (cond
>= 0x0e) { /* condition "always" */
2626 tcg_src
= read_cpu_reg(s
, rn
, sf
);
2627 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
2629 /* OPTME: we could use movcond here, at the cost of duplicating
2630 * a lot of the arm_gen_test_cc() logic.
2632 int label_match
= gen_new_label();
2633 int label_continue
= gen_new_label();
2635 arm_gen_test_cc(cond
, label_match
);
2637 tcg_src
= cpu_reg(s
, rm
);
2639 if (else_inv
&& else_inc
) {
2640 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
2641 } else if (else_inv
) {
2642 tcg_gen_not_i64(tcg_rd
, tcg_src
);
2643 } else if (else_inc
) {
2644 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
2646 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
2649 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2651 tcg_gen_br(label_continue
);
2653 gen_set_label(label_match
);
2654 tcg_src
= read_cpu_reg(s
, rn
, sf
);
2655 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
2657 gen_set_label(label_continue
);
2661 static void handle_clz(DisasContext
*s
, unsigned int sf
,
2662 unsigned int rn
, unsigned int rd
)
2664 TCGv_i64 tcg_rd
, tcg_rn
;
2665 tcg_rd
= cpu_reg(s
, rd
);
2666 tcg_rn
= cpu_reg(s
, rn
);
2669 gen_helper_clz64(tcg_rd
, tcg_rn
);
2671 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
2672 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
2673 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
2674 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
2675 tcg_temp_free_i32(tcg_tmp32
);
2679 static void handle_cls(DisasContext
*s
, unsigned int sf
,
2680 unsigned int rn
, unsigned int rd
)
2682 TCGv_i64 tcg_rd
, tcg_rn
;
2683 tcg_rd
= cpu_reg(s
, rd
);
2684 tcg_rn
= cpu_reg(s
, rn
);
2687 gen_helper_cls64(tcg_rd
, tcg_rn
);
2689 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
2690 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
2691 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
2692 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
2693 tcg_temp_free_i32(tcg_tmp32
);
2697 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
2698 unsigned int rn
, unsigned int rd
)
2700 TCGv_i64 tcg_rd
, tcg_rn
;
2701 tcg_rd
= cpu_reg(s
, rd
);
2702 tcg_rn
= cpu_reg(s
, rn
);
2705 gen_helper_rbit64(tcg_rd
, tcg_rn
);
2707 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
2708 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
2709 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
2710 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
2711 tcg_temp_free_i32(tcg_tmp32
);
2715 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
2716 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
2717 unsigned int rn
, unsigned int rd
)
2720 unallocated_encoding(s
);
2723 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
2726 /* C5.6.149 REV with sf==0, opcode==2
2727 * C5.6.151 REV32 (sf==1, opcode==2)
2729 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
2730 unsigned int rn
, unsigned int rd
)
2732 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2735 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2736 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2738 /* bswap32_i64 requires zero high word */
2739 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
2740 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
2741 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
2742 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
2743 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
2745 tcg_temp_free_i64(tcg_tmp
);
2747 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
2748 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
2752 /* C5.6.150 REV16 (opcode==1) */
2753 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
2754 unsigned int rn
, unsigned int rd
)
2756 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2757 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2758 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2760 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
2761 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
2763 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
2764 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
2765 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
2766 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
2769 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
2770 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
2771 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
2772 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
2774 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
2775 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
2776 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
2779 tcg_temp_free_i64(tcg_tmp
);
2782 /* C3.5.7 Data-processing (1 source)
2783 * 31 30 29 28 21 20 16 15 10 9 5 4 0
2784 * +----+---+---+-----------------+---------+--------+------+------+
2785 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
2786 * +----+---+---+-----------------+---------+--------+------+------+
2788 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
2790 unsigned int sf
, opcode
, rn
, rd
;
2792 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
2793 unallocated_encoding(s
);
2797 sf
= extract32(insn
, 31, 1);
2798 opcode
= extract32(insn
, 10, 6);
2799 rn
= extract32(insn
, 5, 5);
2800 rd
= extract32(insn
, 0, 5);
2804 handle_rbit(s
, sf
, rn
, rd
);
2807 handle_rev16(s
, sf
, rn
, rd
);
2810 handle_rev32(s
, sf
, rn
, rd
);
2813 handle_rev64(s
, sf
, rn
, rd
);
2816 handle_clz(s
, sf
, rn
, rd
);
2819 handle_cls(s
, sf
, rn
, rd
);
2824 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
2825 unsigned int rm
, unsigned int rn
, unsigned int rd
)
2827 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
2828 tcg_rd
= cpu_reg(s
, rd
);
2830 if (!sf
&& is_signed
) {
2831 tcg_n
= new_tmp_a64(s
);
2832 tcg_m
= new_tmp_a64(s
);
2833 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
2834 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
2836 tcg_n
= read_cpu_reg(s
, rn
, sf
);
2837 tcg_m
= read_cpu_reg(s
, rm
, sf
);
2841 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
2843 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
2846 if (!sf
) { /* zero extend final result */
2847 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2851 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
2852 static void handle_shift_reg(DisasContext
*s
,
2853 enum a64_shift_type shift_type
, unsigned int sf
,
2854 unsigned int rm
, unsigned int rn
, unsigned int rd
)
2856 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
2857 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2858 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2860 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
2861 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
2862 tcg_temp_free_i64(tcg_shift
);
2865 /* C3.5.8 Data-processing (2 source)
2866 * 31 30 29 28 21 20 16 15 10 9 5 4 0
2867 * +----+---+---+-----------------+------+--------+------+------+
2868 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
2869 * +----+---+---+-----------------+------+--------+------+------+
2871 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
2873 unsigned int sf
, rm
, opcode
, rn
, rd
;
2874 sf
= extract32(insn
, 31, 1);
2875 rm
= extract32(insn
, 16, 5);
2876 opcode
= extract32(insn
, 10, 6);
2877 rn
= extract32(insn
, 5, 5);
2878 rd
= extract32(insn
, 0, 5);
2880 if (extract32(insn
, 29, 1)) {
2881 unallocated_encoding(s
);
2887 handle_div(s
, false, sf
, rm
, rn
, rd
);
2890 handle_div(s
, true, sf
, rm
, rn
, rd
);
2893 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
2896 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
2899 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
2902 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
2911 case 23: /* CRC32 */
2912 unsupported_encoding(s
, insn
);
2915 unallocated_encoding(s
);
2920 /* C3.5 Data processing - register */
2921 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
2923 switch (extract32(insn
, 24, 5)) {
2924 case 0x0a: /* Logical (shifted register) */
2925 disas_logic_reg(s
, insn
);
2927 case 0x0b: /* Add/subtract */
2928 if (insn
& (1 << 21)) { /* (extended register) */
2929 disas_add_sub_ext_reg(s
, insn
);
2931 disas_add_sub_reg(s
, insn
);
2934 case 0x1b: /* Data-processing (3 source) */
2935 disas_data_proc_3src(s
, insn
);
2938 switch (extract32(insn
, 21, 3)) {
2939 case 0x0: /* Add/subtract (with carry) */
2940 disas_adc_sbc(s
, insn
);
2942 case 0x2: /* Conditional compare */
2943 disas_cc(s
, insn
); /* both imm and reg forms */
2945 case 0x4: /* Conditional select */
2946 disas_cond_select(s
, insn
);
2948 case 0x6: /* Data-processing */
2949 if (insn
& (1 << 30)) { /* (1 source) */
2950 disas_data_proc_1src(s
, insn
);
2951 } else { /* (2 source) */
2952 disas_data_proc_2src(s
, insn
);
2956 unallocated_encoding(s
);
2961 unallocated_encoding(s
);
2966 /* C3.6.22 Floating point compare
2967 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
2968 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
2969 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
2970 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
2972 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
2974 unsupported_encoding(s
, insn
);
2977 /* C3.6.23 Floating point conditional compare
2978 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
2979 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
2980 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
2981 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
2983 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
2985 unsupported_encoding(s
, insn
);
2988 /* C3.6.24 Floating point conditional select
2989 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
2990 * +---+---+---+-----------+------+---+------+------+-----+------+------+
2991 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
2992 * +---+---+---+-----------+------+---+------+------+-----+------+------+
2994 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
2996 unsupported_encoding(s
, insn
);
2999 /* C3.6.25 Floating point data-processing (1 source)
3000 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
3001 * +---+---+---+-----------+------+---+--------+-----------+------+------+
3002 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
3003 * +---+---+---+-----------+------+---+--------+-----------+------+------+
3005 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
3007 unsupported_encoding(s
, insn
);
3010 /* C3.6.26 Floating point data-processing (2 source)
3011 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
3012 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
3013 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
3014 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
3016 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
3018 unsupported_encoding(s
, insn
);
3021 /* C3.6.27 Floating point data-processing (3 source)
3022 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
3023 * +---+---+---+-----------+------+----+------+----+------+------+------+
3024 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
3025 * +---+---+---+-----------+------+----+------+----+------+------+------+
3027 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
3029 unsupported_encoding(s
, insn
);
3032 /* C3.6.28 Floating point immediate
3033 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
3034 * +---+---+---+-----------+------+---+------------+-------+------+------+
3035 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
3036 * +---+---+---+-----------+------+---+------------+-------+------+------+
3038 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
3040 unsupported_encoding(s
, insn
);
3043 /* C3.6.29 Floating point <-> fixed point conversions
3044 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
3045 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
3046 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
3047 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
3049 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
3051 unsupported_encoding(s
, insn
);
3054 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
3056 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
3057 * without conversion.
3061 int freg_offs
= offsetof(CPUARMState
, vfp
.regs
[rd
* 2]);
3062 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3068 TCGv_i64 tmp
= tcg_temp_new_i64();
3069 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
3070 tcg_gen_st_i64(tmp
, cpu_env
, freg_offs
);
3071 tcg_gen_movi_i64(tmp
, 0);
3072 tcg_gen_st_i64(tmp
, cpu_env
, freg_offs
+ sizeof(float64
));
3073 tcg_temp_free_i64(tmp
);
3079 TCGv_i64 tmp
= tcg_const_i64(0);
3080 tcg_gen_st_i64(tcg_rn
, cpu_env
, freg_offs
);
3081 tcg_gen_st_i64(tmp
, cpu_env
, freg_offs
+ sizeof(float64
));
3082 tcg_temp_free_i64(tmp
);
3086 /* 64 bit to top half. */
3087 tcg_gen_st_i64(tcg_rn
, cpu_env
, freg_offs
+ sizeof(float64
));
3091 int freg_offs
= offsetof(CPUARMState
, vfp
.regs
[rn
* 2]);
3092 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3097 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, freg_offs
);
3100 /* 64 bits from top half */
3101 freg_offs
+= sizeof(float64
);
3105 tcg_gen_ld_i64(tcg_rd
, cpu_env
, freg_offs
);
3111 /* C3.6.30 Floating point <-> integer conversions
3112 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
3113 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
3114 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
3115 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
3117 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
3119 int rd
= extract32(insn
, 0, 5);
3120 int rn
= extract32(insn
, 5, 5);
3121 int opcode
= extract32(insn
, 16, 3);
3122 int rmode
= extract32(insn
, 19, 2);
3123 int type
= extract32(insn
, 22, 2);
3124 bool sbit
= extract32(insn
, 29, 1);
3125 bool sf
= extract32(insn
, 31, 1);
3127 if (!sbit
&& (rmode
< 2) && (opcode
> 5)) {
3129 bool itof
= opcode
& 1;
3131 switch (sf
<< 3 | type
<< 1 | rmode
) {
3132 case 0x0: /* 32 bit */
3133 case 0xa: /* 64 bit */
3134 case 0xd: /* 64 bit to top half of quad */
3137 /* all other sf/type/rmode combinations are invalid */
3138 unallocated_encoding(s
);
3142 handle_fmov(s
, rd
, rn
, type
, itof
);
3144 /* actual FP conversions */
3145 unsupported_encoding(s
, insn
);
3149 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
3150 * 31 30 29 28 25 24 0
3151 * +---+---+---+---------+-----------------------------+
3152 * | | 0 | | 1 1 1 1 | |
3153 * +---+---+---+---------+-----------------------------+
3155 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
3157 if (extract32(insn
, 24, 1)) {
3158 /* Floating point data-processing (3 source) */
3159 disas_fp_3src(s
, insn
);
3160 } else if (extract32(insn
, 21, 1) == 0) {
3161 /* Floating point to fixed point conversions */
3162 disas_fp_fixed_conv(s
, insn
);
3164 switch (extract32(insn
, 10, 2)) {
3166 /* Floating point conditional compare */
3167 disas_fp_ccomp(s
, insn
);
3170 /* Floating point data-processing (2 source) */
3171 disas_fp_2src(s
, insn
);
3174 /* Floating point conditional select */
3175 disas_fp_csel(s
, insn
);
3178 switch (ctz32(extract32(insn
, 12, 4))) {
3179 case 0: /* [15:12] == xxx1 */
3180 /* Floating point immediate */
3181 disas_fp_imm(s
, insn
);
3183 case 1: /* [15:12] == xx10 */
3184 /* Floating point compare */
3185 disas_fp_compare(s
, insn
);
3187 case 2: /* [15:12] == x100 */
3188 /* Floating point data-processing (1 source) */
3189 disas_fp_1src(s
, insn
);
3191 case 3: /* [15:12] == 1000 */
3192 unallocated_encoding(s
);
3194 default: /* [15:12] == 0000 */
3195 /* Floating point <-> integer conversions */
3196 disas_fp_int_conv(s
, insn
);
3204 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
3206 /* Note that this is called with all non-FP cases from
3207 * table C3-6 so it must UNDEF for entries not specifically
3208 * allocated to instructions in that table.
3210 unsupported_encoding(s
, insn
);
3213 /* C3.6 Data processing - SIMD and floating point */
3214 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
3216 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
3217 disas_data_proc_fp(s
, insn
);
3219 /* SIMD, including crypto */
3220 disas_data_proc_simd(s
, insn
);
3224 /* C3.1 A64 instruction index by encoding */
3225 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
3229 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
3233 switch (extract32(insn
, 25, 4)) {
3234 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
3235 unallocated_encoding(s
);
3237 case 0x8: case 0x9: /* Data processing - immediate */
3238 disas_data_proc_imm(s
, insn
);
3240 case 0xa: case 0xb: /* Branch, exception generation and system insns */
3241 disas_b_exc_sys(s
, insn
);
3246 case 0xe: /* Loads and stores */
3247 disas_ldst(s
, insn
);
3250 case 0xd: /* Data processing - register */
3251 disas_data_proc_reg(s
, insn
);
3254 case 0xf: /* Data processing - SIMD and floating point */
3255 disas_data_proc_simd_fp(s
, insn
);
3258 assert(FALSE
); /* all 15 cases should be handled above */
3262 /* if we allocated any temporaries, free them here */
3266 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
3267 TranslationBlock
*tb
,
3270 CPUState
*cs
= CPU(cpu
);
3271 CPUARMState
*env
= &cpu
->env
;
3272 DisasContext dc1
, *dc
= &dc1
;
3274 uint16_t *gen_opc_end
;
3276 target_ulong pc_start
;
3277 target_ulong next_page_start
;
3285 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
3287 dc
->is_jmp
= DISAS_NEXT
;
3289 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3295 dc
->condexec_mask
= 0;
3296 dc
->condexec_cond
= 0;
3297 #if !defined(CONFIG_USER_ONLY)
3300 dc
->vfp_enabled
= 0;
3303 dc
->cp_regs
= cpu
->cp_regs
;
3304 dc
->current_pl
= arm_current_pl(env
);
3306 init_tmp_a64_array(dc
);
3308 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3311 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3312 if (max_insns
== 0) {
3313 max_insns
= CF_COUNT_MASK
;
3318 tcg_clear_temp_count();
3321 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
3322 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
3323 if (bp
->pc
== dc
->pc
) {
3324 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
3325 /* Advance PC so that clearing the breakpoint will
3326 invalidate this TB. */
3328 goto done_generating
;
3334 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
3338 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
3341 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
3342 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
3343 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
3346 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3350 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
3351 tcg_gen_debug_insn_start(dc
->pc
);
3354 disas_a64_insn(env
, dc
);
3356 if (tcg_check_temp_count()) {
3357 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
3361 /* Translation stops when a conditional branch is encountered.
3362 * Otherwise the subsequent code could get translated several times.
3363 * Also stop translation when a page boundary is reached. This
3364 * ensures prefetch aborts occur at the right place.
3367 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
3368 !cs
->singlestep_enabled
&&
3370 dc
->pc
< next_page_start
&&
3371 num_insns
< max_insns
);
3373 if (tb
->cflags
& CF_LAST_IO
) {
3377 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
3378 /* Note that this means single stepping WFI doesn't halt the CPU.
3379 * For conditional branch insns this is harmless unreachable code as
3380 * gen_goto_tb() has already handled emitting the debug exception
3381 * (and thus a tb-jump is not possible when singlestepping).
3383 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
3384 if (dc
->is_jmp
!= DISAS_JUMP
) {
3385 gen_a64_set_pc_im(dc
->pc
);
3387 gen_exception(EXCP_DEBUG
);
3389 switch (dc
->is_jmp
) {
3391 gen_goto_tb(dc
, 1, dc
->pc
);
3395 gen_a64_set_pc_im(dc
->pc
);
3398 /* indicate that the hash table must be used to find the next TB */
3406 /* This is a special case because we don't want to just halt the CPU
3407 * if trying to debug across a WFI.
3409 gen_helper_wfi(cpu_env
);
3415 gen_tb_end(tb
, num_insns
);
3416 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
3419 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3420 qemu_log("----------------\n");
3421 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3422 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
3423 dc
->thumb
| (dc
->bswap_code
<< 1));
3428 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
3431 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
3434 tb
->size
= dc
->pc
- pc_start
;
3435 tb
->icount
= num_insns
;