hw/opencores_eth.c

   1 /*
   2  * OpenCores Ethernet MAC 10/100 + subset of
   3  * National Semiconductors DP83848C 10/100 PHY
   4  *
   5  * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf
   6  * http://cache.national.com/ds/DP/DP83848C.pdf
   7  *
   8  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions are met:
  13  *     * Redistributions of source code must retain the above copyright
  14  *       notice, this list of conditions and the following disclaimer.
  15  *     * Redistributions in binary form must reproduce the above copyright
  16  *       notice, this list of conditions and the following disclaimer in the
  17  *       documentation and/or other materials provided with the distribution.
  18  *     * Neither the name of the Open Source and Linux Lab nor the
  19  *       names of its contributors may be used to endorse or promote products
  20  *       derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include "hw.h"
  35 #include "sysbus.h"
  36 #include "net.h"
  37 #include "sysemu.h"
  38 #include "trace.h"
  39
  40 /* RECSMALL is not used because it breaks tap networking in linux:
  41  * incoming ARP responses are too short
  42  */
  43 #undef USE_RECSMALL
  44
  45 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
  46 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
  47 #define GET_REGFIELD(s, reg, field) \
  48     GET_FIELD((s)->regs[reg], reg ## _ ## field)
  49
  50 #define SET_FIELD(v, field, data) \
  51     ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
  52 #define SET_REGFIELD(s, reg, field, data) \
  53     SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
  54
  55 /* PHY MII registers */
  56 enum {
  57     MII_BMCR,
  58     MII_BMSR,
  59     MII_PHYIDR1,
  60     MII_PHYIDR2,
  61     MII_ANAR,
  62     MII_ANLPAR,
  63     MII_REG_MAX = 16,
  64 };
  65
  66 typedef struct Mii {
  67     uint16_t regs[MII_REG_MAX];
  68     bool link_ok;
  69 } Mii;
  70
  71 static void mii_set_link(Mii *s, bool link_ok)
  72 {
  73     if (link_ok) {
  74         s->regs[MII_BMSR] |= 0x4;
  75         s->regs[MII_ANLPAR] |= 0x01e1;
  76     } else {
  77         s->regs[MII_BMSR] &= ~0x4;
  78         s->regs[MII_ANLPAR] &= 0x01ff;
  79     }
  80     s->link_ok = link_ok;
  81 }
  82
  83 static void mii_reset(Mii *s)
  84 {
  85     memset(s->regs, 0, sizeof(s->regs));
  86     s->regs[MII_BMCR] = 0x1000;
  87     s->regs[MII_BMSR] = 0x7848; /* no ext regs */
  88     s->regs[MII_PHYIDR1] = 0x2000;
  89     s->regs[MII_PHYIDR2] = 0x5c90;
  90     s->regs[MII_ANAR] = 0x01e1;
  91     mii_set_link(s, s->link_ok);
  92 }
  93
  94 static void mii_ro(Mii *s, uint16_t v)
  95 {
  96 }
  97
  98 static void mii_write_bmcr(Mii *s, uint16_t v)
  99 {
 100     if (v & 0x8000) {
 101         mii_reset(s);
 102     } else {
 103         s->regs[MII_BMCR] = v;
 104     }
 105 }
 106
 107 static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
 108 {
 109     static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
 110         [MII_BMCR] = mii_write_bmcr,
 111         [MII_BMSR] = mii_ro,
 112         [MII_PHYIDR1] = mii_ro,
 113         [MII_PHYIDR2] = mii_ro,
 114     };
 115
 116     if (idx < MII_REG_MAX) {
 117         trace_open_eth_mii_write(idx, v);
 118         if (reg_write[idx]) {
 119             reg_write[idx](s, v);
 120         } else {
 121             s->regs[idx] = v;
 122         }
 123     }
 124 }
 125
 126 static uint16_t mii_read_host(Mii *s, unsigned idx)
 127 {
 128     trace_open_eth_mii_read(idx, s->regs[idx]);
 129     return s->regs[idx];
 130 }
 131
 132 /* OpenCores Ethernet registers */
 133 enum {
 134     MODER,
 135     INT_SOURCE,
 136     INT_MASK,
 137     IPGT,
 138     IPGR1,
 139     IPGR2,
 140     PACKETLEN,
 141     COLLCONF,
 142     TX_BD_NUM,
 143     CTRLMODER,
 144     MIIMODER,
 145     MIICOMMAND,
 146     MIIADDRESS,
 147     MIITX_DATA,
 148     MIIRX_DATA,
 149     MIISTATUS,
 150     MAC_ADDR0,
 151     MAC_ADDR1,
 152     HASH0,
 153     HASH1,
 154     TXCTRL,
 155     REG_MAX,
 156 };
 157
 158 enum {
 159     MODER_RECSMALL = 0x10000,
 160     MODER_PAD = 0x8000,
 161     MODER_HUGEN = 0x4000,
 162     MODER_RST = 0x800,
 163     MODER_LOOPBCK = 0x80,
 164     MODER_PRO = 0x20,
 165     MODER_IAM = 0x10,
 166     MODER_BRO = 0x8,
 167     MODER_TXEN = 0x2,
 168     MODER_RXEN = 0x1,
 169 };
 170
 171 enum {
 172     INT_SOURCE_RXB = 0x4,
 173     INT_SOURCE_TXB = 0x1,
 174 };
 175
 176 enum {
 177     PACKETLEN_MINFL = 0xffff0000,
 178     PACKETLEN_MINFL_LBN = 16,
 179     PACKETLEN_MAXFL = 0xffff,
 180     PACKETLEN_MAXFL_LBN = 0,
 181 };
 182
 183 enum {
 184     MIICOMMAND_WCTRLDATA = 0x4,
 185     MIICOMMAND_RSTAT = 0x2,
 186     MIICOMMAND_SCANSTAT = 0x1,
 187 };
 188
 189 enum {
 190     MIIADDRESS_RGAD = 0x1f00,
 191     MIIADDRESS_RGAD_LBN = 8,
 192     MIIADDRESS_FIAD = 0x1f,
 193     MIIADDRESS_FIAD_LBN = 0,
 194 };
 195
 196 enum {
 197     MIITX_DATA_CTRLDATA = 0xffff,
 198     MIITX_DATA_CTRLDATA_LBN = 0,
 199 };
 200
 201 enum {
 202     MIIRX_DATA_PRSD = 0xffff,
 203     MIIRX_DATA_PRSD_LBN = 0,
 204 };
 205
 206 enum {
 207     MIISTATUS_LINKFAIL = 0x1,
 208     MIISTATUS_LINKFAIL_LBN = 0,
 209 };
 210
 211 enum {
 212     MAC_ADDR0_BYTE2 = 0xff000000,
 213     MAC_ADDR0_BYTE2_LBN = 24,
 214     MAC_ADDR0_BYTE3 = 0xff0000,
 215     MAC_ADDR0_BYTE3_LBN = 16,
 216     MAC_ADDR0_BYTE4 = 0xff00,
 217     MAC_ADDR0_BYTE4_LBN = 8,
 218     MAC_ADDR0_BYTE5 = 0xff,
 219     MAC_ADDR0_BYTE5_LBN = 0,
 220 };
 221
 222 enum {
 223     MAC_ADDR1_BYTE0 = 0xff00,
 224     MAC_ADDR1_BYTE0_LBN = 8,
 225     MAC_ADDR1_BYTE1 = 0xff,
 226     MAC_ADDR1_BYTE1_LBN = 0,
 227 };
 228
 229 enum {
 230     TXD_LEN = 0xffff0000,
 231     TXD_LEN_LBN = 16,
 232     TXD_RD = 0x8000,
 233     TXD_IRQ = 0x4000,
 234     TXD_WR = 0x2000,
 235     TXD_PAD = 0x1000,
 236     TXD_CRC = 0x800,
 237     TXD_UR = 0x100,
 238     TXD_RTRY = 0xf0,
 239     TXD_RTRY_LBN = 4,
 240     TXD_RL = 0x8,
 241     TXD_LC = 0x4,
 242     TXD_DF = 0x2,
 243     TXD_CS = 0x1,
 244 };
 245
 246 enum {
 247     RXD_LEN = 0xffff0000,
 248     RXD_LEN_LBN = 16,
 249     RXD_E = 0x8000,
 250     RXD_IRQ = 0x4000,
 251     RXD_WRAP = 0x2000,
 252     RXD_CF = 0x100,
 253     RXD_M = 0x80,
 254     RXD_OR = 0x40,
 255     RXD_IS = 0x20,
 256     RXD_DN = 0x10,
 257     RXD_TL = 0x8,
 258     RXD_SF = 0x4,
 259     RXD_CRC = 0x2,
 260     RXD_LC = 0x1,
 261 };
 262
 263 typedef struct desc {
 264     uint32_t len_flags;
 265     uint32_t buf_ptr;
 266 } desc;
 267
 268 #define DEFAULT_PHY 1
 269
 270 typedef struct OpenEthState {
 271     SysBusDevice dev;
 272     NICState *nic;
 273     NICConf conf;
 274     MemoryRegion reg_io;
 275     MemoryRegion desc_io;
 276     qemu_irq irq;
 277
 278     Mii mii;
 279     uint32_t regs[REG_MAX];
 280     unsigned tx_desc;
 281     unsigned rx_desc;
 282     desc desc[128];
 283 } OpenEthState;
 284
 285 static desc *rx_desc(OpenEthState *s)
 286 {
 287     return s->desc + s->rx_desc;
 288 }
 289
 290 static desc *tx_desc(OpenEthState *s)
 291 {
 292     return s->desc + s->tx_desc;
 293 }
 294
 295 static void open_eth_update_irq(OpenEthState *s,
 296         uint32_t old, uint32_t new)
 297 {
 298     if (!old != !new) {
 299         trace_open_eth_update_irq(new);
 300         qemu_set_irq(s->irq, new);
 301     }
 302 }
 303
 304 static void open_eth_int_source_write(OpenEthState *s,
 305         uint32_t val)
 306 {
 307     uint32_t old_val = s->regs[INT_SOURCE];
 308
 309     s->regs[INT_SOURCE] = val;
 310     open_eth_update_irq(s, old_val & s->regs[INT_MASK],
 311             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 312 }
 313
 314 static void open_eth_set_link_status(VLANClientState *nc)
 315 {
 316     OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque;
 317
 318     if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
 319         SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
 320     }
 321     mii_set_link(&s->mii, !nc->link_down);
 322 }
 323
 324 static void open_eth_reset(void *opaque)
 325 {
 326     OpenEthState *s = opaque;
 327
 328     memset(s->regs, 0, sizeof(s->regs));
 329     s->regs[MODER] = 0xa000;
 330     s->regs[IPGT] = 0x12;
 331     s->regs[IPGR1] = 0xc;
 332     s->regs[IPGR2] = 0x12;
 333     s->regs[PACKETLEN] = 0x400600;
 334     s->regs[COLLCONF] = 0xf003f;
 335     s->regs[TX_BD_NUM] = 0x40;
 336     s->regs[MIIMODER] = 0x64;
 337
 338     s->tx_desc = 0;
 339     s->rx_desc = 0x40;
 340
 341     mii_reset(&s->mii);
 342     open_eth_set_link_status(&s->nic->nc);
 343 }
 344
 345 static int open_eth_can_receive(VLANClientState *nc)
 346 {
 347     OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque;
 348
 349     return GET_REGBIT(s, MODER, RXEN) &&
 350         (s->regs[TX_BD_NUM] < 0x80) &&
 351         (rx_desc(s)->len_flags & RXD_E);
 352 }
 353
 354 #define POLYNOMIAL 0x04c11db6
 355
 356 /* From FreeBSD */
 357 /* XXX: optimize */
 358 static unsigned compute_mcast_idx(const uint8_t *ep)
 359 {
 360     uint32_t crc;
 361     int carry, i, j;
 362     uint8_t b;
 363
 364     crc = 0xffffffff;
 365     for (i = 0; i < 6; i++) {
 366         b = *ep++;
 367         for (j = 0; j < 8; j++) {
 368             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 369             crc <<= 1;
 370             b >>= 1;
 371             if (carry) {
 372                 crc = ((crc ^ POLYNOMIAL) | carry);
 373             }
 374         }
 375     }
 376     return crc >> 26;
 377 }
 378
 379 static ssize_t open_eth_receive(VLANClientState *nc,
 380         const uint8_t *buf, size_t size)
 381 {
 382     OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque;
 383     size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
 384     size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
 385     size_t fcsl = 4;
 386     bool miss = true;
 387
 388     trace_open_eth_receive((unsigned)size);
 389
 390     if (size >= 6) {
 391         static const uint8_t bcast_addr[] = {
 392             0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 393         };
 394         if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
 395             miss = GET_REGBIT(s, MODER, BRO);
 396         } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
 397             unsigned mcast_idx = compute_mcast_idx(buf);
 398             miss = !(s->regs[HASH0 + mcast_idx / 32] &
 399                     (1 << (mcast_idx % 32)));
 400             trace_open_eth_receive_mcast(
 401                     mcast_idx, s->regs[HASH0], s->regs[HASH1]);
 402         } else {
 403             miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
 404                 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
 405                 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
 406                 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
 407                 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
 408                 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
 409         }
 410     }
 411
 412     if (miss && !GET_REGBIT(s, MODER, PRO)) {
 413         trace_open_eth_receive_reject();
 414         return size;
 415     }
 416
 417 #ifdef USE_RECSMALL
 418     if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
 419 #else
 420     {
 421 #endif
 422         static const uint8_t zero[64] = {0};
 423         desc *desc = rx_desc(s);
 424         size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
 425
 426         desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
 427                 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
 428
 429         if (copy_size > size) {
 430             copy_size = size;
 431         } else {
 432             fcsl = 0;
 433         }
 434         if (miss) {
 435             desc->len_flags |= RXD_M;
 436         }
 437         if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) {
 438             desc->len_flags |= RXD_TL;
 439         }
 440 #ifdef USE_RECSMALL
 441         if (size < minfl) {
 442             desc->len_flags |= RXD_SF;
 443         }
 444 #endif
 445
 446         cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
 447
 448         if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
 449             if (minfl - copy_size > fcsl) {
 450                 fcsl = 0;
 451             } else {
 452                 fcsl -= minfl - copy_size;
 453             }
 454             while (copy_size < minfl) {
 455                 size_t zero_sz = minfl - copy_size < sizeof(zero) ?
 456                     minfl - copy_size : sizeof(zero);
 457
 458                 cpu_physical_memory_write(desc->buf_ptr + copy_size,
 459                         zero, zero_sz);
 460                 copy_size += zero_sz;
 461             }
 462         }
 463
 464         /* There's no FCS in the frames handed to us by the QEMU, zero fill it.
 465          * Don't do it if the frame is cut at the MAXFL or padded with 4 or
 466          * more bytes to the MINFL.
 467          */
 468         cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl);
 469         copy_size += fcsl;
 470
 471         SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
 472
 473         if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
 474             s->rx_desc = s->regs[TX_BD_NUM];
 475         } else {
 476             ++s->rx_desc;
 477         }
 478         desc->len_flags &= ~RXD_E;
 479
 480         trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
 481
 482         if (desc->len_flags & RXD_IRQ) {
 483             open_eth_int_source_write(s,
 484                     s->regs[INT_SOURCE] | INT_SOURCE_RXB);
 485         }
 486     }
 487     return size;
 488 }
 489
 490 static void open_eth_cleanup(VLANClientState *nc)
 491 {
 492 }
 493
 494 static NetClientInfo net_open_eth_info = {
 495     .type = NET_CLIENT_TYPE_NIC,
 496     .size = sizeof(NICState),
 497     .can_receive = open_eth_can_receive,
 498     .receive = open_eth_receive,
 499     .cleanup = open_eth_cleanup,
 500     .link_status_changed = open_eth_set_link_status,
 501 };
 502
 503 static void open_eth_start_xmit(OpenEthState *s, desc *tx)
 504 {
 505     uint8_t buf[65536];
 506     unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
 507     unsigned tx_len = len;
 508
 509     if ((tx->len_flags & TXD_PAD) &&
 510             tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
 511         tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
 512     }
 513     if (!GET_REGBIT(s, MODER, HUGEN) &&
 514             tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
 515         tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
 516     }
 517
 518     trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
 519
 520     if (len > tx_len) {
 521         len = tx_len;
 522     }
 523     cpu_physical_memory_read(tx->buf_ptr, buf, len);
 524     if (tx_len > len) {
 525         memset(buf + len, 0, tx_len - len);
 526     }
 527     qemu_send_packet(&s->nic->nc, buf, tx_len);
 528
 529     if (tx->len_flags & TXD_WR) {
 530         s->tx_desc = 0;
 531     } else {
 532         ++s->tx_desc;
 533         if (s->tx_desc >= s->regs[TX_BD_NUM]) {
 534             s->tx_desc = 0;
 535         }
 536     }
 537     tx->len_flags &= ~(TXD_RD | TXD_UR |
 538             TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
 539     if (tx->len_flags & TXD_IRQ) {
 540         open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
 541     }
 542
 543 }
 544
 545 static void open_eth_check_start_xmit(OpenEthState *s)
 546 {
 547     desc *tx = tx_desc(s);
 548     if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
 549             (tx->len_flags & TXD_RD) &&
 550             GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
 551         open_eth_start_xmit(s, tx);
 552     }
 553 }
 554
 555 static uint64_t open_eth_reg_read(void *opaque,
 556         target_phys_addr_t addr, unsigned int size)
 557 {
 558     static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
 559     };
 560     OpenEthState *s = opaque;
 561     unsigned idx = addr / 4;
 562     uint64_t v = 0;
 563
 564     if (idx < REG_MAX) {
 565         if (reg_read[idx]) {
 566             v = reg_read[idx](s);
 567         } else {
 568             v = s->regs[idx];
 569         }
 570     }
 571     trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
 572     return v;
 573 }
 574
 575 static void open_eth_ro(OpenEthState *s, uint32_t val)
 576 {
 577 }
 578
 579 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
 580 {
 581     uint32_t set = val & ~s->regs[MODER];
 582
 583     if (set & MODER_RST) {
 584         open_eth_reset(s);
 585     }
 586
 587     s->regs[MODER] = val;
 588
 589     if (set & MODER_RXEN) {
 590         s->rx_desc = s->regs[TX_BD_NUM];
 591     }
 592     if (set & MODER_TXEN) {
 593         s->tx_desc = 0;
 594         open_eth_check_start_xmit(s);
 595     }
 596 }
 597
 598 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
 599 {
 600     uint32_t old = s->regs[INT_SOURCE];
 601
 602     s->regs[INT_SOURCE] &= ~val;
 603     open_eth_update_irq(s, old & s->regs[INT_MASK],
 604             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 605 }
 606
 607 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
 608 {
 609     uint32_t old = s->regs[INT_MASK];
 610
 611     s->regs[INT_MASK] = val;
 612     open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
 613             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 614 }
 615
 616 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
 617 {
 618     unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
 619     unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
 620
 621     if (val & MIICOMMAND_WCTRLDATA) {
 622         if (fiad == DEFAULT_PHY) {
 623             mii_write_host(&s->mii, rgad,
 624                     GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 625         }
 626     }
 627     if (val & MIICOMMAND_RSTAT) {
 628         if (fiad == DEFAULT_PHY) {
 629             SET_REGFIELD(s, MIIRX_DATA, PRSD,
 630                     mii_read_host(&s->mii, rgad));
 631         } else {
 632             s->regs[MIIRX_DATA] = 0xffff;
 633         }
 634         SET_REGFIELD(s, MIISTATUS, LINKFAIL, s->nic->nc.link_down);
 635     }
 636 }
 637
 638 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
 639 {
 640     SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
 641     if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
 642         mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
 643                 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 644     }
 645 }
 646
 647 static void open_eth_reg_write(void *opaque,
 648         target_phys_addr_t addr, uint64_t val, unsigned int size)
 649 {
 650     static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
 651         [MODER] = open_eth_moder_host_write,
 652         [INT_SOURCE] = open_eth_int_source_host_write,
 653         [INT_MASK] = open_eth_int_mask_host_write,
 654         [MIICOMMAND] = open_eth_mii_command_host_write,
 655         [MIITX_DATA] = open_eth_mii_tx_host_write,
 656         [MIISTATUS] = open_eth_ro,
 657     };
 658     OpenEthState *s = opaque;
 659     unsigned idx = addr / 4;
 660
 661     if (idx < REG_MAX) {
 662         trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
 663         if (reg_write[idx]) {
 664             reg_write[idx](s, val);
 665         } else {
 666             s->regs[idx] = val;
 667         }
 668     }
 669 }
 670
 671 static uint64_t open_eth_desc_read(void *opaque,
 672         target_phys_addr_t addr, unsigned int size)
 673 {
 674     OpenEthState *s = opaque;
 675     uint64_t v = 0;
 676
 677     addr &= 0x3ff;
 678     memcpy(&v, (uint8_t *)s->desc + addr, size);
 679     trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
 680     return v;
 681 }
 682
 683 static void open_eth_desc_write(void *opaque,
 684         target_phys_addr_t addr, uint64_t val, unsigned int size)
 685 {
 686     OpenEthState *s = opaque;
 687
 688     addr &= 0x3ff;
 689     trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
 690     memcpy((uint8_t *)s->desc + addr, &val, size);
 691     open_eth_check_start_xmit(s);
 692 }
 693
 694
 695 static const MemoryRegionOps open_eth_reg_ops = {
 696     .read = open_eth_reg_read,
 697     .write = open_eth_reg_write,
 698 };
 699
 700 static const MemoryRegionOps open_eth_desc_ops = {
 701     .read = open_eth_desc_read,
 702     .write = open_eth_desc_write,
 703 };
 704
 705 static int sysbus_open_eth_init(SysBusDevice *dev)
 706 {
 707     OpenEthState *s = DO_UPCAST(OpenEthState, dev, dev);
 708
 709     memory_region_init_io(&s->reg_io, &open_eth_reg_ops, s,
 710             "open_eth.regs", 0x54);
 711     sysbus_init_mmio(dev, &s->reg_io);
 712
 713     memory_region_init_io(&s->desc_io, &open_eth_desc_ops, s,
 714             "open_eth.desc", 0x400);
 715     sysbus_init_mmio(dev, &s->desc_io);
 716
 717     sysbus_init_irq(dev, &s->irq);
 718
 719     s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
 720                           object_get_typename(OBJECT(s)), s->dev.qdev.id, s);
 721     return 0;
 722 }
 723
 724 static void qdev_open_eth_reset(DeviceState *dev)
 725 {
 726     OpenEthState *d = DO_UPCAST(OpenEthState, dev.qdev, dev);
 727     open_eth_reset(d);
 728 }
 729
 730 static Property open_eth_properties[] = {
 731     DEFINE_NIC_PROPERTIES(OpenEthState, conf),
 732     DEFINE_PROP_END_OF_LIST(),
 733 };
 734
 735 static void open_eth_class_init(ObjectClass *klass, void *data)
 736 {
 737     DeviceClass *dc = DEVICE_CLASS(klass);
 738     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 739
 740     k->init = sysbus_open_eth_init;
 741     dc->desc = "Opencores 10/100 Mbit Ethernet";
 742     dc->reset = qdev_open_eth_reset;
 743     dc->props = open_eth_properties;
 744 }
 745
 746 static TypeInfo open_eth_info = {
 747     .name          = "open_eth",
 748     .parent        = TYPE_SYS_BUS_DEVICE,
 749     .instance_size = sizeof(OpenEthState),
 750     .class_init    = open_eth_class_init,
 751 };
 752
 753 static void open_eth_register_types(void)
 754 {
 755     type_register_static(&open_eth_info);
 756 }
 757
 758 type_init(open_eth_register_types)