spapr, xics, xive: Move print_info from SpaprIrq to SpaprInterruptController
[qemu/ar7.git] / include / hw / ppc / spapr_irq.h
blobbdfeb3b10772e7213ede198a0f20385d4d24a5a2
1 /*
2 * QEMU PowerPC sPAPR IRQ backend definitions
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
10 #ifndef HW_SPAPR_IRQ_H
11 #define HW_SPAPR_IRQ_H
13 #include "target/ppc/cpu-qom.h"
16 * IRQ range offsets per device type
18 #define SPAPR_IRQ_IPI 0x0
20 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
21 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
22 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
23 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
24 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
26 /* Offset of the dynamic range covered by the bitmap allocator */
27 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
29 #define SPAPR_NR_XIRQS 0x1000
30 #define SPAPR_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
32 typedef struct SpaprMachineState SpaprMachineState;
34 typedef struct SpaprInterruptController SpaprInterruptController;
36 #define TYPE_SPAPR_INTC "spapr-interrupt-controller"
37 #define SPAPR_INTC(obj) \
38 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
39 #define SPAPR_INTC_CLASS(klass) \
40 OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC)
41 #define SPAPR_INTC_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC)
44 typedef struct SpaprInterruptControllerClass {
45 InterfaceClass parent;
47 int (*activate)(SpaprInterruptController *intc, Error **errp);
48 void (*deactivate)(SpaprInterruptController *intc);
51 * These methods will typically be called on all intcs, active and
52 * inactive
54 int (*cpu_intc_create)(SpaprInterruptController *intc,
55 PowerPCCPU *cpu, Error **errp);
56 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
57 Error **errp);
58 void (*free_irq)(SpaprInterruptController *intc, int irq);
60 /* These methods should only be called on the active intc */
61 void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
62 void (*print_info)(SpaprInterruptController *intc, Monitor *mon);
63 } SpaprInterruptControllerClass;
65 void spapr_irq_update_active_intc(SpaprMachineState *spapr);
67 int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
68 PowerPCCPU *cpu, Error **errp);
69 void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
71 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
72 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
73 Error **errp);
74 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
76 typedef struct SpaprIrq {
77 uint32_t nr_xirqs;
78 uint32_t nr_msis;
79 bool xics;
80 bool xive;
82 void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
83 void *fdt, uint32_t phandle);
84 int (*post_load)(SpaprMachineState *spapr, int version_id);
85 void (*reset)(SpaprMachineState *spapr, Error **errp);
86 void (*init_kvm)(SpaprMachineState *spapr, Error **errp);
87 } SpaprIrq;
89 extern SpaprIrq spapr_irq_xics;
90 extern SpaprIrq spapr_irq_xics_legacy;
91 extern SpaprIrq spapr_irq_xive;
92 extern SpaprIrq spapr_irq_dual;
94 void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
95 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
96 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
97 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
98 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
99 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
100 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
103 * XICS legacy routines
105 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
106 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
108 #endif