2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
13 * This is a model of the Arm "Subsystems for Embedded" family of
14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
15 * SSE-200. Currently we model:
16 * - the Arm IoT Kit which is documented in
17 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
18 * - the SSE-200 which is documented in
19 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
21 * The IoTKit contains:
24 * some timers and watchdogs
25 * two peripheral protection controllers
26 * a memory protection controller
27 * a security controller
28 * a bus fabric which arranges that some parts of the address
29 * space are secure and non-secure aliases of each other
30 * The SSE-200 additionally contains:
32 * two Message Handling Units (MHUs)
33 * an optional CryptoCell (which we do not model)
34 * more SRAM banks with associated MPCs
35 * multiple Power Policy Units (PPUs)
36 * a control interface for an icache for each CPU
37 * per-CPU identity and control register blocks
40 * + QOM property "memory" is a MemoryRegion containing the devices provided
42 * + QOM property "MAINCLK" is the frequency of the main system clock
43 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
44 * (In hardware, the SSE-200 permits the number of expansion interrupts
45 * for the two CPUs to be configured separately, but we restrict it to
46 * being the same for both, to avoid having to have separate Property
47 * lists for different variants. This restriction can be relaxed later
49 * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
50 * address of each SRAM bank (and thus the total amount of internal SRAM)
51 * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
52 * (where it expects to load the PC and SP from the vector table on reset)
53 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
54 * which are wired to its NVIC lines 32 .. n+32
55 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
56 * CPU 1, which are wired to its NVIC lines 32 .. n+32
57 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
58 * bus master devices in the board model to make transactions into
59 * all the devices and memory areas in the IoTKit
60 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
62 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
63 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
64 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
65 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
66 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
67 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
69 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
70 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
71 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
72 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
73 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
74 * Controlling each of the 16 expansion MPCs which a system using the IoTKit
76 * + named GPIO inputs mpcexp_status[0..15]
77 * Controlling each of the 16 expansion MSCs which a system using the IoTKit
79 * + named GPIO inputs mscexp_status[0..15]
80 * + named GPIO outputs mscexp_clear[0..15]
81 * + named GPIO outputs mscexp_ns[0..15]
87 #include "hw/sysbus.h"
88 #include "hw/arm/armv7m.h"
89 #include "hw/misc/iotkit-secctl.h"
90 #include "hw/misc/tz-ppc.h"
91 #include "hw/misc/tz-mpc.h"
92 #include "hw/timer/cmsdk-apb-timer.h"
93 #include "hw/timer/cmsdk-apb-dualtimer.h"
94 #include "hw/watchdog/cmsdk-apb-watchdog.h"
95 #include "hw/misc/iotkit-sysctl.h"
96 #include "hw/misc/iotkit-sysinfo.h"
97 #include "hw/misc/armsse-cpuid.h"
98 #include "hw/misc/unimp.h"
99 #include "hw/or-irq.h"
100 #include "hw/core/split-irq.h"
101 #include "hw/cpu/cluster.h"
103 #define TYPE_ARMSSE "arm-sse"
104 #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
107 * These type names are for specific IoTKit subsystems; other than
108 * instantiating them, code using these devices should always handle
109 * them via the ARMSSE base class, so they have no IOTKIT() etc macros.
111 #define TYPE_IOTKIT "iotkit"
112 #define TYPE_SSE200 "sse-200"
114 /* We have an IRQ splitter and an OR gate input for each external PPC
115 * and the 2 internal PPCs
117 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
118 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
120 #define MAX_SRAM_BANKS 4
121 #if MAX_SRAM_BANKS > IOTS_NUM_MPC
122 #error Too many SRAM banks
125 #define SSE_MAX_CPUS 2
127 /* These define what each PPU in the ppu[] index is for */
128 #define CPU0CORE_PPU 0
129 #define CPU1CORE_PPU 1
137 typedef struct ARMSSE
{
139 SysBusDevice parent_obj
;
142 ARMv7MState armv7m
[SSE_MAX_CPUS
];
143 CPUClusterState cluster
[SSE_MAX_CPUS
];
147 TZMPC mpc
[IOTS_NUM_MPC
];
148 CMSDKAPBTIMER timer0
;
149 CMSDKAPBTIMER timer1
;
150 CMSDKAPBTIMER s32ktimer
;
151 qemu_or_irq ppc_irq_orgate
;
152 SplitIRQ sec_resp_splitter
;
153 SplitIRQ ppc_irq_splitter
[NUM_PPCS
];
154 SplitIRQ mpc_irq_splitter
[IOTS_NUM_EXP_MPC
+ IOTS_NUM_MPC
];
155 qemu_or_irq mpc_irq_orgate
;
156 qemu_or_irq nmi_orgate
;
158 SplitIRQ cpu_irq_splitter
[32];
160 CMSDKAPBDualTimer dualtimer
;
162 CMSDKAPBWatchdog s32kwatchdog
;
163 CMSDKAPBWatchdog nswatchdog
;
164 CMSDKAPBWatchdog swatchdog
;
167 IoTKitSysCtl sysinfo
;
169 UnimplementedDeviceState mhu
[2];
170 UnimplementedDeviceState ppu
[NUM_PPUS
];
171 UnimplementedDeviceState cachectrl
[SSE_MAX_CPUS
];
172 UnimplementedDeviceState cpusecctrl
[SSE_MAX_CPUS
];
174 ARMSSECPUID cpuid
[SSE_MAX_CPUS
];
177 * 'container' holds all devices seen by all CPUs.
178 * 'cpu_container[i]' is the view that CPU i has: this has the
179 * per-CPU devices of that CPU, plus as the background 'container'
180 * (or an alias of it, since we can only use it directly once).
181 * container_alias[i] is the alias of 'container' used by CPU i+1;
182 * CPU 0 can use 'container' directly.
184 MemoryRegion container
;
185 MemoryRegion container_alias
[SSE_MAX_CPUS
- 1];
186 MemoryRegion cpu_container
[SSE_MAX_CPUS
];
190 MemoryRegion sram
[MAX_SRAM_BANKS
];
192 qemu_irq
*exp_irqs
[SSE_MAX_CPUS
];
195 qemu_irq sec_resp_cfg
;
196 qemu_irq sec_resp_cfg_in
;
199 qemu_irq irq_status_in
[NUM_EXTERNAL_PPCS
];
200 qemu_irq mpcexp_status_in
[IOTS_NUM_EXP_MPC
];
205 MemoryRegion
*board_memory
;
207 uint32_t mainclk_frq
;
208 uint32_t sram_addr_width
;
212 typedef struct ARMSSEInfo ARMSSEInfo
;
214 typedef struct ARMSSEClass
{
215 DeviceClass parent_class
;
216 const ARMSSEInfo
*info
;
219 #define ARMSSE_CLASS(klass) \
220 OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE)
221 #define ARMSSE_GET_CLASS(obj) \
222 OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE)