cpu-all.h

   1 /*
   2  * defines common to all virtual CPUs
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ALL_H
  20 #define CPU_ALL_H
  21
  22 #include "qemu-common.h"
  23 #include "qemu-tls.h"
  24 #include "cpu-common.h"
  25 #include "memory_mapping.h"
  26
  27 /* some important defines:
  28  *
  29  * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
  30  * memory accesses.
  31  *
  32  * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
  33  * otherwise little endian.
  34  *
  35  * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
  36  *
  37  * TARGET_WORDS_BIGENDIAN : same for target cpu
  38  */
  39
  40 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
  41 #define BSWAP_NEEDED
  42 #endif
  43
  44 #ifdef BSWAP_NEEDED
  45
  46 static inline uint16_t tswap16(uint16_t s)
  47 {
  48     return bswap16(s);
  49 }
  50
  51 static inline uint32_t tswap32(uint32_t s)
  52 {
  53     return bswap32(s);
  54 }
  55
  56 static inline uint64_t tswap64(uint64_t s)
  57 {
  58     return bswap64(s);
  59 }
  60
  61 static inline void tswap16s(uint16_t *s)
  62 {
  63     *s = bswap16(*s);
  64 }
  65
  66 static inline void tswap32s(uint32_t *s)
  67 {
  68     *s = bswap32(*s);
  69 }
  70
  71 static inline void tswap64s(uint64_t *s)
  72 {
  73     *s = bswap64(*s);
  74 }
  75
  76 #else
  77
  78 static inline uint16_t tswap16(uint16_t s)
  79 {
  80     return s;
  81 }
  82
  83 static inline uint32_t tswap32(uint32_t s)
  84 {
  85     return s;
  86 }
  87
  88 static inline uint64_t tswap64(uint64_t s)
  89 {
  90     return s;
  91 }
  92
  93 static inline void tswap16s(uint16_t *s)
  94 {
  95 }
  96
  97 static inline void tswap32s(uint32_t *s)
  98 {
  99 }
 100
 101 static inline void tswap64s(uint64_t *s)
 102 {
 103 }
 104
 105 #endif
 106
 107 #if TARGET_LONG_SIZE == 4
 108 #define tswapl(s) tswap32(s)
 109 #define tswapls(s) tswap32s((uint32_t *)(s))
 110 #define bswaptls(s) bswap32s(s)
 111 #else
 112 #define tswapl(s) tswap64(s)
 113 #define tswapls(s) tswap64s((uint64_t *)(s))
 114 #define bswaptls(s) bswap64s(s)
 115 #endif
 116
 117 /* CPU memory access without any memory or io remapping */
 118
 119 /*
 120  * the generic syntax for the memory accesses is:
 121  *
 122  * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 123  *
 124  * store: st{type}{size}{endian}_{access_type}(ptr, val)
 125  *
 126  * type is:
 127  * (empty): integer access
 128  *   f    : float access
 129  *
 130  * sign is:
 131  * (empty): for floats or 32 bit size
 132  *   u    : unsigned
 133  *   s    : signed
 134  *
 135  * size is:
 136  *   b: 8 bits
 137  *   w: 16 bits
 138  *   l: 32 bits
 139  *   q: 64 bits
 140  *
 141  * endian is:
 142  * (empty): target cpu endianness or 8 bit access
 143  *   r    : reversed target cpu endianness (not implemented yet)
 144  *   be   : big endian (not implemented yet)
 145  *   le   : little endian (not implemented yet)
 146  *
 147  * access_type is:
 148  *   raw    : host memory access
 149  *   user   : user mode access using soft MMU
 150  *   kernel : kernel mode access using soft MMU
 151  */
 152
 153 /* target-endianness CPU memory access functions */
 154 #if defined(TARGET_WORDS_BIGENDIAN)
 155 #define lduw_p(p) lduw_be_p(p)
 156 #define ldsw_p(p) ldsw_be_p(p)
 157 #define ldl_p(p) ldl_be_p(p)
 158 #define ldq_p(p) ldq_be_p(p)
 159 #define ldfl_p(p) ldfl_be_p(p)
 160 #define ldfq_p(p) ldfq_be_p(p)
 161 #define stw_p(p, v) stw_be_p(p, v)
 162 #define stl_p(p, v) stl_be_p(p, v)
 163 #define stq_p(p, v) stq_be_p(p, v)
 164 #define stfl_p(p, v) stfl_be_p(p, v)
 165 #define stfq_p(p, v) stfq_be_p(p, v)
 166 #else
 167 #define lduw_p(p) lduw_le_p(p)
 168 #define ldsw_p(p) ldsw_le_p(p)
 169 #define ldl_p(p) ldl_le_p(p)
 170 #define ldq_p(p) ldq_le_p(p)
 171 #define ldfl_p(p) ldfl_le_p(p)
 172 #define ldfq_p(p) ldfq_le_p(p)
 173 #define stw_p(p, v) stw_le_p(p, v)
 174 #define stl_p(p, v) stl_le_p(p, v)
 175 #define stq_p(p, v) stq_le_p(p, v)
 176 #define stfl_p(p, v) stfl_le_p(p, v)
 177 #define stfq_p(p, v) stfq_le_p(p, v)
 178 #endif
 179
 180 /* MMU memory access macros */
 181
 182 #if defined(CONFIG_USER_ONLY)
 183 #include <assert.h>
 184 #include "qemu-types.h"
 185
 186 /* On some host systems the guest address space is reserved on the host.
 187  * This allows the guest address space to be offset to a convenient location.
 188  */
 189 #if defined(CONFIG_USE_GUEST_BASE)
 190 extern unsigned long guest_base;
 191 extern int have_guest_base;
 192 extern unsigned long reserved_va;
 193 #define GUEST_BASE guest_base
 194 #define RESERVED_VA reserved_va
 195 #else
 196 #define GUEST_BASE 0ul
 197 #define RESERVED_VA 0ul
 198 #endif
 199
 200 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
 201 #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
 202
 203 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
 204 #define h2g_valid(x) 1
 205 #else
 206 #define h2g_valid(x) ({ \
 207     unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
 208     (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
 209     (!RESERVED_VA || (__guest < RESERVED_VA)); \
 210 })
 211 #endif
 212
 213 #define h2g(x) ({ \
 214     unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
 215     /* Check if given address fits target address space */ \
 216     assert(h2g_valid(x)); \
 217     (abi_ulong)__ret; \
 218 })
 219
 220 #define saddr(x) g2h(x)
 221 #define laddr(x) g2h(x)
 222
 223 #else /* !CONFIG_USER_ONLY */
 224 /* NOTE: we use double casts if pointers and target_ulong have
 225    different sizes */
 226 #define saddr(x) (uint8_t *)(intptr_t)(x)
 227 #define laddr(x) (uint8_t *)(intptr_t)(x)
 228 #endif
 229
 230 #define ldub_raw(p) ldub_p(laddr((p)))
 231 #define ldsb_raw(p) ldsb_p(laddr((p)))
 232 #define lduw_raw(p) lduw_p(laddr((p)))
 233 #define ldsw_raw(p) ldsw_p(laddr((p)))
 234 #define ldl_raw(p) ldl_p(laddr((p)))
 235 #define ldq_raw(p) ldq_p(laddr((p)))
 236 #define ldfl_raw(p) ldfl_p(laddr((p)))
 237 #define ldfq_raw(p) ldfq_p(laddr((p)))
 238 #define stb_raw(p, v) stb_p(saddr((p)), v)
 239 #define stw_raw(p, v) stw_p(saddr((p)), v)
 240 #define stl_raw(p, v) stl_p(saddr((p)), v)
 241 #define stq_raw(p, v) stq_p(saddr((p)), v)
 242 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
 243 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
 244
 245
 246 #if defined(CONFIG_USER_ONLY)
 247
 248 /* if user mode, no other memory access functions */
 249 #define ldub(p) ldub_raw(p)
 250 #define ldsb(p) ldsb_raw(p)
 251 #define lduw(p) lduw_raw(p)
 252 #define ldsw(p) ldsw_raw(p)
 253 #define ldl(p) ldl_raw(p)
 254 #define ldq(p) ldq_raw(p)
 255 #define ldfl(p) ldfl_raw(p)
 256 #define ldfq(p) ldfq_raw(p)
 257 #define stb(p, v) stb_raw(p, v)
 258 #define stw(p, v) stw_raw(p, v)
 259 #define stl(p, v) stl_raw(p, v)
 260 #define stq(p, v) stq_raw(p, v)
 261 #define stfl(p, v) stfl_raw(p, v)
 262 #define stfq(p, v) stfq_raw(p, v)
 263
 264 #ifndef CONFIG_TCG_PASS_AREG0
 265 #define ldub_code(p) ldub_raw(p)
 266 #define ldsb_code(p) ldsb_raw(p)
 267 #define lduw_code(p) lduw_raw(p)
 268 #define ldsw_code(p) ldsw_raw(p)
 269 #define ldl_code(p) ldl_raw(p)
 270 #define ldq_code(p) ldq_raw(p)
 271 #else
 272 #define cpu_ldub_code(env1, p) ldub_raw(p)
 273 #define cpu_ldsb_code(env1, p) ldsb_raw(p)
 274 #define cpu_lduw_code(env1, p) lduw_raw(p)
 275 #define cpu_ldsw_code(env1, p) ldsw_raw(p)
 276 #define cpu_ldl_code(env1, p) ldl_raw(p)
 277 #define cpu_ldq_code(env1, p) ldq_raw(p)
 278 #endif
 279
 280 #define ldub_kernel(p) ldub_raw(p)
 281 #define ldsb_kernel(p) ldsb_raw(p)
 282 #define lduw_kernel(p) lduw_raw(p)
 283 #define ldsw_kernel(p) ldsw_raw(p)
 284 #define ldl_kernel(p) ldl_raw(p)
 285 #define ldq_kernel(p) ldq_raw(p)
 286 #define ldfl_kernel(p) ldfl_raw(p)
 287 #define ldfq_kernel(p) ldfq_raw(p)
 288 #define stb_kernel(p, v) stb_raw(p, v)
 289 #define stw_kernel(p, v) stw_raw(p, v)
 290 #define stl_kernel(p, v) stl_raw(p, v)
 291 #define stq_kernel(p, v) stq_raw(p, v)
 292 #define stfl_kernel(p, v) stfl_raw(p, v)
 293 #define stfq_kernel(p, vt) stfq_raw(p, v)
 294
 295 #endif /* defined(CONFIG_USER_ONLY) */
 296
 297 /* page related stuff */
 298
 299 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
 300 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
 301 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
 302
 303 /* ??? These should be the larger of uintptr_t and target_ulong.  */
 304 extern uintptr_t qemu_real_host_page_size;
 305 extern uintptr_t qemu_host_page_size;
 306 extern uintptr_t qemu_host_page_mask;
 307
 308 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
 309
 310 /* same as PROT_xxx */
 311 #define PAGE_READ      0x0001
 312 #define PAGE_WRITE     0x0002
 313 #define PAGE_EXEC      0x0004
 314 #define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
 315 #define PAGE_VALID     0x0008
 316 /* original state of the write flag (used when tracking self-modifying
 317    code */
 318 #define PAGE_WRITE_ORG 0x0010
 319 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
 320 /* FIXME: Code that sets/uses this is broken and needs to go away.  */
 321 #define PAGE_RESERVED  0x0020
 322 #endif
 323
 324 #if defined(CONFIG_USER_ONLY)
 325 void page_dump(FILE *f);
 326
 327 typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
 328                                       abi_ulong, unsigned long);
 329 int walk_memory_regions(void *, walk_memory_regions_fn);
 330
 331 int page_get_flags(target_ulong address);
 332 void page_set_flags(target_ulong start, target_ulong end, int flags);
 333 int page_check_range(target_ulong start, target_ulong len, int flags);
 334 #endif
 335
 336 CPUArchState *cpu_copy(CPUArchState *env);
 337 CPUArchState *qemu_get_cpu(int cpu);
 338
 339 #define CPU_DUMP_CODE 0x00010000
 340
 341 void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
 342                     int flags);
 343 void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
 344                          int flags);
 345
 346 void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
 347     GCC_FMT_ATTR(2, 3);
 348 extern CPUArchState *first_cpu;
 349 DECLARE_TLS(CPUArchState *,cpu_single_env);
 350 #define cpu_single_env tls_var(cpu_single_env)
 351
 352 /* Flags for use in ENV->INTERRUPT_PENDING.
 353
 354    The numbers assigned here are non-sequential in order to preserve
 355    binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
 356    previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
 357    the vmstate dump.  */
 358
 359 /* External hardware interrupt pending.  This is typically used for
 360    interrupts from devices.  */
 361 #define CPU_INTERRUPT_HARD        0x0002
 362
 363 /* Exit the current TB.  This is typically used when some system-level device
 364    makes some change to the memory mapping.  E.g. the a20 line change.  */
 365 #define CPU_INTERRUPT_EXITTB      0x0004
 366
 367 /* Halt the CPU.  */
 368 #define CPU_INTERRUPT_HALT        0x0020
 369
 370 /* Debug event pending.  */
 371 #define CPU_INTERRUPT_DEBUG       0x0080
 372
 373 /* Several target-specific external hardware interrupts.  Each target/cpu.h
 374    should define proper names based on these defines.  */
 375 #define CPU_INTERRUPT_TGT_EXT_0   0x0008
 376 #define CPU_INTERRUPT_TGT_EXT_1   0x0010
 377 #define CPU_INTERRUPT_TGT_EXT_2   0x0040
 378 #define CPU_INTERRUPT_TGT_EXT_3   0x0200
 379 #define CPU_INTERRUPT_TGT_EXT_4   0x1000
 380
 381 /* Several target-specific internal interrupts.  These differ from the
 382    preceding target-specific interrupts in that they are intended to
 383    originate from within the cpu itself, typically in response to some
 384    instruction being executed.  These, therefore, are not masked while
 385    single-stepping within the debugger.  */
 386 #define CPU_INTERRUPT_TGT_INT_0   0x0100
 387 #define CPU_INTERRUPT_TGT_INT_1   0x0400
 388 #define CPU_INTERRUPT_TGT_INT_2   0x0800
 389 #define CPU_INTERRUPT_TGT_INT_3   0x2000
 390
 391 /* First unused bit: 0x4000.  */
 392
 393 /* The set of all bits that should be masked when single-stepping.  */
 394 #define CPU_INTERRUPT_SSTEP_MASK \
 395     (CPU_INTERRUPT_HARD          \
 396      | CPU_INTERRUPT_TGT_EXT_0   \
 397      | CPU_INTERRUPT_TGT_EXT_1   \
 398      | CPU_INTERRUPT_TGT_EXT_2   \
 399      | CPU_INTERRUPT_TGT_EXT_3   \
 400      | CPU_INTERRUPT_TGT_EXT_4)
 401
 402 #ifndef CONFIG_USER_ONLY
 403 typedef void (*CPUInterruptHandler)(CPUArchState *, int);
 404
 405 extern CPUInterruptHandler cpu_interrupt_handler;
 406
 407 static inline void cpu_interrupt(CPUArchState *s, int mask)
 408 {
 409     cpu_interrupt_handler(s, mask);
 410 }
 411 #else /* USER_ONLY */
 412 void cpu_interrupt(CPUArchState *env, int mask);
 413 #endif /* USER_ONLY */
 414
 415 void cpu_reset_interrupt(CPUArchState *env, int mask);
 416
 417 void cpu_exit(CPUArchState *s);
 418
 419 bool qemu_cpu_has_work(CPUArchState *env);
 420
 421 /* Breakpoint/watchpoint flags */
 422 #define BP_MEM_READ           0x01
 423 #define BP_MEM_WRITE          0x02
 424 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 425 #define BP_STOP_BEFORE_ACCESS 0x04
 426 #define BP_WATCHPOINT_HIT     0x08
 427 #define BP_GDB                0x10
 428 #define BP_CPU                0x20
 429
 430 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
 431                           CPUBreakpoint **breakpoint);
 432 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
 433 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
 434 void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
 435 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
 436                           int flags, CPUWatchpoint **watchpoint);
 437 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
 438                           target_ulong len, int flags);
 439 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
 440 void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
 441
 442 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 443 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 444 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 445
 446 void cpu_single_step(CPUArchState *env, int enabled);
 447 void cpu_state_reset(CPUArchState *s);
 448 int cpu_is_stopped(CPUArchState *env);
 449 void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
 450
 451 #define CPU_LOG_TB_OUT_ASM (1 << 0)
 452 #define CPU_LOG_TB_IN_ASM  (1 << 1)
 453 #define CPU_LOG_TB_OP      (1 << 2)
 454 #define CPU_LOG_TB_OP_OPT  (1 << 3)
 455 #define CPU_LOG_INT        (1 << 4)
 456 #define CPU_LOG_EXEC       (1 << 5)
 457 #define CPU_LOG_PCALL      (1 << 6)
 458 #define CPU_LOG_IOPORT     (1 << 7)
 459 #define CPU_LOG_TB_CPU     (1 << 8)
 460 #define CPU_LOG_RESET      (1 << 9)
 461
 462 /* define log items */
 463 typedef struct CPULogItem {
 464     int mask;
 465     const char *name;
 466     const char *help;
 467 } CPULogItem;
 468
 469 extern const CPULogItem cpu_log_items[];
 470
 471 void cpu_set_log(int log_flags);
 472 void cpu_set_log_filename(const char *filename);
 473 int cpu_str_to_log_mask(const char *str);
 474
 475 #if !defined(CONFIG_USER_ONLY)
 476
 477 /* Return the physical page corresponding to a virtual one. Use it
 478    only for debugging because no protection checks are done. Return -1
 479    if no page found. */
 480 target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
 481
 482 /* memory API */
 483
 484 extern int phys_ram_fd;
 485 extern ram_addr_t ram_size;
 486
 487 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
 488 #define RAM_PREALLOC_MASK   (1 << 0)
 489
 490 typedef struct RAMBlock {
 491     struct MemoryRegion *mr;
 492     uint8_t *host;
 493     ram_addr_t offset;
 494     ram_addr_t length;
 495     uint32_t flags;
 496     char idstr[256];
 497     QLIST_ENTRY(RAMBlock) next;
 498 #if defined(__linux__) && !defined(TARGET_S390X)
 499     int fd;
 500 #endif
 501 } RAMBlock;
 502
 503 typedef struct RAMList {
 504     uint8_t *phys_dirty;
 505     QLIST_HEAD(, RAMBlock) blocks;
 506 } RAMList;
 507 extern RAMList ram_list;
 508
 509 extern const char *mem_path;
 510 extern int mem_prealloc;
 511
 512 /* Flags stored in the low bits of the TLB virtual address.  These are
 513    defined so that fast path ram access is all zeros.  */
 514 /* Zero if TLB entry is valid.  */
 515 #define TLB_INVALID_MASK   (1 << 3)
 516 /* Set if TLB entry references a clean RAM page.  The iotlb entry will
 517    contain the page physical address.  */
 518 #define TLB_NOTDIRTY    (1 << 4)
 519 /* Set if TLB entry is an IO callback.  */
 520 #define TLB_MMIO        (1 << 5)
 521
 522 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
 523 #endif /* !CONFIG_USER_ONLY */
 524
 525 int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
 526                         uint8_t *buf, int len, int is_write);
 527
 528 #if defined(CONFIG_HAVE_GET_MEMORY_MAPPING)
 529 int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env);
 530 bool cpu_paging_enabled(CPUArchState *env);
 531 #else
 532 static inline int cpu_get_memory_mapping(MemoryMappingList *list,
 533                                          CPUArchState *env)
 534 {
 535     return -1;
 536 }
 537
 538 static inline bool cpu_paging_enabled(CPUArchState *env)
 539 {
 540     return true;
 541 }
 542 #endif
 543
 544 #endif /* CPU_ALL_H */