target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 void cpu_save(QEMUFile *f, void *opaque)
   5 {
   6     int i;
   7     CPUARMState *env = (CPUARMState *)opaque;
   8
   9     for (i = 0; i < 16; i++) {
  10         qemu_put_be32(f, env->regs[i]);
  11     }
  12     qemu_put_be32(f, cpsr_read(env));
  13     qemu_put_be32(f, env->spsr);
  14     for (i = 0; i < 6; i++) {
  15         qemu_put_be32(f, env->banked_spsr[i]);
  16         qemu_put_be32(f, env->banked_r13[i]);
  17         qemu_put_be32(f, env->banked_r14[i]);
  18     }
  19     for (i = 0; i < 5; i++) {
  20         qemu_put_be32(f, env->usr_regs[i]);
  21         qemu_put_be32(f, env->fiq_regs[i]);
  22     }
  23     qemu_put_be32(f, env->cp15.c0_cpuid);
  24     qemu_put_be32(f, env->cp15.c0_cachetype);
  25     qemu_put_be32(f, env->cp15.c0_cssel);
  26     qemu_put_be32(f, env->cp15.c1_sys);
  27     qemu_put_be32(f, env->cp15.c1_coproc);
  28     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
  29     qemu_put_be32(f, env->cp15.c1_scr);
  30     qemu_put_be32(f, env->cp15.c2_base0);
  31     qemu_put_be32(f, env->cp15.c2_base1);
  32     qemu_put_be32(f, env->cp15.c2_control);
  33     qemu_put_be32(f, env->cp15.c2_mask);
  34     qemu_put_be32(f, env->cp15.c2_base_mask);
  35     qemu_put_be32(f, env->cp15.c2_data);
  36     qemu_put_be32(f, env->cp15.c2_insn);
  37     qemu_put_be32(f, env->cp15.c3);
  38     qemu_put_be32(f, env->cp15.c5_insn);
  39     qemu_put_be32(f, env->cp15.c5_data);
  40     for (i = 0; i < 8; i++) {
  41         qemu_put_be32(f, env->cp15.c6_region[i]);
  42     }
  43     qemu_put_be32(f, env->cp15.c6_insn);
  44     qemu_put_be32(f, env->cp15.c6_data);
  45     qemu_put_be32(f, env->cp15.c7_par);
  46     qemu_put_be32(f, env->cp15.c9_insn);
  47     qemu_put_be32(f, env->cp15.c9_data);
  48     qemu_put_be32(f, env->cp15.c9_pmcr);
  49     qemu_put_be32(f, env->cp15.c9_pmcnten);
  50     qemu_put_be32(f, env->cp15.c9_pmovsr);
  51     qemu_put_be32(f, env->cp15.c9_pmxevtyper);
  52     qemu_put_be32(f, env->cp15.c9_pmuserenr);
  53     qemu_put_be32(f, env->cp15.c9_pminten);
  54     qemu_put_be32(f, env->cp15.c13_fcse);
  55     qemu_put_be32(f, env->cp15.c13_context);
  56     qemu_put_be32(f, env->cp15.c13_tls1);
  57     qemu_put_be32(f, env->cp15.c13_tls2);
  58     qemu_put_be32(f, env->cp15.c13_tls3);
  59     qemu_put_be32(f, env->cp15.c15_cpar);
  60     qemu_put_be32(f, env->cp15.c15_power_control);
  61     qemu_put_be32(f, env->cp15.c15_diagnostic);
  62     qemu_put_be32(f, env->cp15.c15_power_diagnostic);
  63
  64     qemu_put_be32(f, env->features);
  65
  66     if (arm_feature(env, ARM_FEATURE_VFP)) {
  67         for (i = 0;  i < 16; i++) {
  68             CPU_DoubleU u;
  69             u.d = env->vfp.regs[i];
  70             qemu_put_be32(f, u.l.upper);
  71             qemu_put_be32(f, u.l.lower);
  72         }
  73         for (i = 0; i < 16; i++) {
  74             qemu_put_be32(f, env->vfp.xregs[i]);
  75         }
  76
  77         /* TODO: Should use proper FPSCR access functions.  */
  78         qemu_put_be32(f, env->vfp.vec_len);
  79         qemu_put_be32(f, env->vfp.vec_stride);
  80
  81         if (arm_feature(env, ARM_FEATURE_VFP3)) {
  82             for (i = 16;  i < 32; i++) {
  83                 CPU_DoubleU u;
  84                 u.d = env->vfp.regs[i];
  85                 qemu_put_be32(f, u.l.upper);
  86                 qemu_put_be32(f, u.l.lower);
  87             }
  88         }
  89     }
  90
  91     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  92         for (i = 0; i < 16; i++) {
  93             qemu_put_be64(f, env->iwmmxt.regs[i]);
  94         }
  95         for (i = 0; i < 16; i++) {
  96             qemu_put_be32(f, env->iwmmxt.cregs[i]);
  97         }
  98     }
  99
 100     if (arm_feature(env, ARM_FEATURE_M)) {
 101         qemu_put_be32(f, env->v7m.other_sp);
 102         qemu_put_be32(f, env->v7m.vecbase);
 103         qemu_put_be32(f, env->v7m.basepri);
 104         qemu_put_be32(f, env->v7m.control);
 105         qemu_put_be32(f, env->v7m.current_sp);
 106         qemu_put_be32(f, env->v7m.exception);
 107     }
 108
 109     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
 110         qemu_put_be32(f, env->teecr);
 111         qemu_put_be32(f, env->teehbr);
 112     }
 113 }
 114
 115 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 116 {
 117     CPUARMState *env = (CPUARMState *)opaque;
 118     int i;
 119     uint32_t val;
 120
 121     if (version_id != CPU_SAVE_VERSION)
 122         return -EINVAL;
 123
 124     for (i = 0; i < 16; i++) {
 125         env->regs[i] = qemu_get_be32(f);
 126     }
 127     val = qemu_get_be32(f);
 128     /* Avoid mode switch when restoring CPSR.  */
 129     env->uncached_cpsr = val & CPSR_M;
 130     cpsr_write(env, val, 0xffffffff);
 131     env->spsr = qemu_get_be32(f);
 132     for (i = 0; i < 6; i++) {
 133         env->banked_spsr[i] = qemu_get_be32(f);
 134         env->banked_r13[i] = qemu_get_be32(f);
 135         env->banked_r14[i] = qemu_get_be32(f);
 136     }
 137     for (i = 0; i < 5; i++) {
 138         env->usr_regs[i] = qemu_get_be32(f);
 139         env->fiq_regs[i] = qemu_get_be32(f);
 140     }
 141     env->cp15.c0_cpuid = qemu_get_be32(f);
 142     env->cp15.c0_cachetype = qemu_get_be32(f);
 143     env->cp15.c0_cssel = qemu_get_be32(f);
 144     env->cp15.c1_sys = qemu_get_be32(f);
 145     env->cp15.c1_coproc = qemu_get_be32(f);
 146     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
 147     env->cp15.c1_scr = qemu_get_be32(f);
 148     env->cp15.c2_base0 = qemu_get_be32(f);
 149     env->cp15.c2_base1 = qemu_get_be32(f);
 150     env->cp15.c2_control = qemu_get_be32(f);
 151     env->cp15.c2_mask = qemu_get_be32(f);
 152     env->cp15.c2_base_mask = qemu_get_be32(f);
 153     env->cp15.c2_data = qemu_get_be32(f);
 154     env->cp15.c2_insn = qemu_get_be32(f);
 155     env->cp15.c3 = qemu_get_be32(f);
 156     env->cp15.c5_insn = qemu_get_be32(f);
 157     env->cp15.c5_data = qemu_get_be32(f);
 158     for (i = 0; i < 8; i++) {
 159         env->cp15.c6_region[i] = qemu_get_be32(f);
 160     }
 161     env->cp15.c6_insn = qemu_get_be32(f);
 162     env->cp15.c6_data = qemu_get_be32(f);
 163     env->cp15.c7_par = qemu_get_be32(f);
 164     env->cp15.c9_insn = qemu_get_be32(f);
 165     env->cp15.c9_data = qemu_get_be32(f);
 166     env->cp15.c9_pmcr = qemu_get_be32(f);
 167     env->cp15.c9_pmcnten = qemu_get_be32(f);
 168     env->cp15.c9_pmovsr = qemu_get_be32(f);
 169     env->cp15.c9_pmxevtyper = qemu_get_be32(f);
 170     env->cp15.c9_pmuserenr = qemu_get_be32(f);
 171     env->cp15.c9_pminten = qemu_get_be32(f);
 172     env->cp15.c13_fcse = qemu_get_be32(f);
 173     env->cp15.c13_context = qemu_get_be32(f);
 174     env->cp15.c13_tls1 = qemu_get_be32(f);
 175     env->cp15.c13_tls2 = qemu_get_be32(f);
 176     env->cp15.c13_tls3 = qemu_get_be32(f);
 177     env->cp15.c15_cpar = qemu_get_be32(f);
 178     env->cp15.c15_power_control = qemu_get_be32(f);
 179     env->cp15.c15_diagnostic = qemu_get_be32(f);
 180     env->cp15.c15_power_diagnostic = qemu_get_be32(f);
 181
 182     env->features = qemu_get_be32(f);
 183
 184     if (arm_feature(env, ARM_FEATURE_VFP)) {
 185         for (i = 0;  i < 16; i++) {
 186             CPU_DoubleU u;
 187             u.l.upper = qemu_get_be32(f);
 188             u.l.lower = qemu_get_be32(f);
 189             env->vfp.regs[i] = u.d;
 190         }
 191         for (i = 0; i < 16; i++) {
 192             env->vfp.xregs[i] = qemu_get_be32(f);
 193         }
 194
 195         /* TODO: Should use proper FPSCR access functions.  */
 196         env->vfp.vec_len = qemu_get_be32(f);
 197         env->vfp.vec_stride = qemu_get_be32(f);
 198
 199         if (arm_feature(env, ARM_FEATURE_VFP3)) {
 200             for (i = 16;  i < 32; i++) {
 201                 CPU_DoubleU u;
 202                 u.l.upper = qemu_get_be32(f);
 203                 u.l.lower = qemu_get_be32(f);
 204                 env->vfp.regs[i] = u.d;
 205             }
 206         }
 207     }
 208
 209     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 210         for (i = 0; i < 16; i++) {
 211             env->iwmmxt.regs[i] = qemu_get_be64(f);
 212         }
 213         for (i = 0; i < 16; i++) {
 214             env->iwmmxt.cregs[i] = qemu_get_be32(f);
 215         }
 216     }
 217
 218     if (arm_feature(env, ARM_FEATURE_M)) {
 219         env->v7m.other_sp = qemu_get_be32(f);
 220         env->v7m.vecbase = qemu_get_be32(f);
 221         env->v7m.basepri = qemu_get_be32(f);
 222         env->v7m.control = qemu_get_be32(f);
 223         env->v7m.current_sp = qemu_get_be32(f);
 224         env->v7m.exception = qemu_get_be32(f);
 225     }
 226
 227     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
 228         env->teecr = qemu_get_be32(f);
 229         env->teehbr = qemu_get_be32(f);
 230     }
 231
 232     return 0;
 233 }