hw/input/pckbd.c

   1 /*
   2  * QEMU PC keyboard emulation
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/log.h"
  28 #include "qemu/timer.h"
  29 #include "hw/isa/isa.h"
  30 #include "migration/vmstate.h"
  31 #include "hw/acpi/aml-build.h"
  32 #include "hw/input/ps2.h"
  33 #include "hw/irq.h"
  34 #include "hw/input/i8042.h"
  35 #include "hw/qdev-properties.h"
  36 #include "sysemu/reset.h"
  37 #include "sysemu/runstate.h"
  38
  39 #include "trace.h"
  40
  41 /*      Keyboard Controller Commands */
  42 #define KBD_CCMD_READ_MODE      0x20    /* Read mode bits */
  43 #define KBD_CCMD_WRITE_MODE     0x60    /* Write mode bits */
  44 #define KBD_CCMD_GET_VERSION    0xA1    /* Get controller version */
  45 #define KBD_CCMD_MOUSE_DISABLE  0xA7    /* Disable mouse interface */
  46 #define KBD_CCMD_MOUSE_ENABLE   0xA8    /* Enable mouse interface */
  47 #define KBD_CCMD_TEST_MOUSE     0xA9    /* Mouse interface test */
  48 #define KBD_CCMD_SELF_TEST      0xAA    /* Controller self test */
  49 #define KBD_CCMD_KBD_TEST       0xAB    /* Keyboard interface test */
  50 #define KBD_CCMD_KBD_DISABLE    0xAD    /* Keyboard interface disable */
  51 #define KBD_CCMD_KBD_ENABLE     0xAE    /* Keyboard interface enable */
  52 #define KBD_CCMD_READ_INPORT    0xC0    /* read input port */
  53 #define KBD_CCMD_READ_OUTPORT   0xD0    /* read output port */
  54 #define KBD_CCMD_WRITE_OUTPORT  0xD1    /* write output port */
  55 #define KBD_CCMD_WRITE_OBUF     0xD2
  56 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3    /* Write to output buffer as if
  57                                            initiated by the auxiliary device */
  58 #define KBD_CCMD_WRITE_MOUSE    0xD4    /* Write the following byte to the mouse */
  59 #define KBD_CCMD_DISABLE_A20    0xDD    /* HP vectra only ? */
  60 #define KBD_CCMD_ENABLE_A20     0xDF    /* HP vectra only ? */
  61 #define KBD_CCMD_PULSE_BITS_3_0 0xF0    /* Pulse bits 3-0 of the output port P2. */
  62 #define KBD_CCMD_RESET          0xFE    /* Pulse bit 0 of the output port P2 = CPU reset. */
  63 #define KBD_CCMD_NO_OP          0xFF    /* Pulse no bits of the output port P2. */
  64
  65 /* Status Register Bits */
  66 #define KBD_STAT_OBF            0x01    /* Keyboard output buffer full */
  67 #define KBD_STAT_IBF            0x02    /* Keyboard input buffer full */
  68 #define KBD_STAT_SELFTEST       0x04    /* Self test successful */
  69 #define KBD_STAT_CMD            0x08    /* Last write was a command write (0=data) */
  70 #define KBD_STAT_UNLOCKED       0x10    /* Zero if keyboard locked */
  71 #define KBD_STAT_MOUSE_OBF      0x20    /* Mouse output buffer full */
  72 #define KBD_STAT_GTO            0x40    /* General receive/xmit timeout */
  73 #define KBD_STAT_PERR           0x80    /* Parity error */
  74
  75 /* Controller Mode Register Bits */
  76 #define KBD_MODE_KBD_INT        0x01    /* Keyboard data generate IRQ1 */
  77 #define KBD_MODE_MOUSE_INT      0x02    /* Mouse data generate IRQ12 */
  78 #define KBD_MODE_SYS            0x04    /* The system flag (?) */
  79 #define KBD_MODE_NO_KEYLOCK     0x08    /* The keylock doesn't affect the keyboard if set */
  80 #define KBD_MODE_DISABLE_KBD    0x10    /* Disable keyboard interface */
  81 #define KBD_MODE_DISABLE_MOUSE  0x20    /* Disable mouse interface */
  82 #define KBD_MODE_KCC            0x40    /* Scan code conversion to PC format */
  83 #define KBD_MODE_RFU            0x80
  84
  85 /* Output Port Bits */
  86 #define KBD_OUT_RESET           0x01    /* 1=normal mode, 0=reset */
  87 #define KBD_OUT_A20             0x02    /* x86 only */
  88 #define KBD_OUT_OBF             0x10    /* Keyboard output buffer full */
  89 #define KBD_OUT_MOUSE_OBF       0x20    /* Mouse output buffer full */
  90
  91 /* OSes typically write 0xdd/0xdf to turn the A20 line off and on.
  92  * We make the default value of the outport include these four bits,
  93  * so that the subsection is rarely necessary.
  94  */
  95 #define KBD_OUT_ONES            0xcc
  96
  97 #define KBD_PENDING_KBD_COMPAT  0x01
  98 #define KBD_PENDING_AUX_COMPAT  0x02
  99 #define KBD_PENDING_CTRL_KBD    0x04
 100 #define KBD_PENDING_CTRL_AUX    0x08
 101 #define KBD_PENDING_KBD         KBD_MODE_DISABLE_KBD    /* 0x10 */
 102 #define KBD_PENDING_AUX         KBD_MODE_DISABLE_MOUSE  /* 0x20 */
 103
 104 #define KBD_MIGR_TIMER_PENDING  0x1
 105
 106 #define KBD_OBSRC_KBD           0x01
 107 #define KBD_OBSRC_MOUSE         0x02
 108 #define KBD_OBSRC_CTRL          0x04
 109
 110 typedef struct KBDState {
 111     uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
 112     uint8_t status;
 113     uint8_t mode;
 114     uint8_t outport;
 115     uint32_t migration_flags;
 116     uint32_t obsrc;
 117     bool outport_present;
 118     bool extended_state;
 119     bool extended_state_loaded;
 120     /* Bitmask of devices with data available.  */
 121     uint8_t pending;
 122     uint8_t obdata;
 123     uint8_t cbdata;
 124     uint8_t pending_tmp;
 125     void *kbd;
 126     void *mouse;
 127     QEMUTimer *throttle_timer;
 128
 129     qemu_irq irq_kbd;
 130     qemu_irq irq_mouse;
 131     qemu_irq a20_out;
 132     hwaddr mask;
 133 } KBDState;
 134
 135 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
 136    incorrect, but it avoids having to simulate exact delays */
 137 static void kbd_update_irq_lines(KBDState *s)
 138 {
 139     int irq_kbd_level, irq_mouse_level;
 140
 141     irq_kbd_level = 0;
 142     irq_mouse_level = 0;
 143
 144     if (s->status & KBD_STAT_OBF) {
 145         if (s->status & KBD_STAT_MOUSE_OBF) {
 146             if (s->mode & KBD_MODE_MOUSE_INT) {
 147                 irq_mouse_level = 1;
 148             }
 149         } else {
 150             if ((s->mode & KBD_MODE_KBD_INT) &&
 151                 !(s->mode & KBD_MODE_DISABLE_KBD)) {
 152                 irq_kbd_level = 1;
 153             }
 154         }
 155     }
 156     qemu_set_irq(s->irq_kbd, irq_kbd_level);
 157     qemu_set_irq(s->irq_mouse, irq_mouse_level);
 158 }
 159
 160 static void kbd_deassert_irq(KBDState *s)
 161 {
 162     s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
 163     s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
 164     kbd_update_irq_lines(s);
 165 }
 166
 167 static uint8_t kbd_pending(KBDState *s)
 168 {
 169     if (s->extended_state) {
 170         return s->pending & (~s->mode | ~(KBD_PENDING_KBD | KBD_PENDING_AUX));
 171     } else {
 172         return s->pending;
 173     }
 174 }
 175
 176 /* update irq and KBD_STAT_[MOUSE_]OBF */
 177 static void kbd_update_irq(KBDState *s)
 178 {
 179     uint8_t pending = kbd_pending(s);
 180
 181     s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
 182     s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
 183     if (pending) {
 184         s->status |= KBD_STAT_OBF;
 185         s->outport |= KBD_OUT_OBF;
 186         if (pending & KBD_PENDING_CTRL_KBD) {
 187             s->obsrc = KBD_OBSRC_CTRL;
 188         } else if (pending & KBD_PENDING_CTRL_AUX) {
 189             s->status |= KBD_STAT_MOUSE_OBF;
 190             s->outport |= KBD_OUT_MOUSE_OBF;
 191             s->obsrc = KBD_OBSRC_CTRL;
 192         } else if (pending & KBD_PENDING_KBD) {
 193             s->obsrc = KBD_OBSRC_KBD;
 194         } else {
 195             s->status |= KBD_STAT_MOUSE_OBF;
 196             s->outport |= KBD_OUT_MOUSE_OBF;
 197             s->obsrc = KBD_OBSRC_MOUSE;
 198         }
 199     }
 200     kbd_update_irq_lines(s);
 201 }
 202
 203 static void kbd_safe_update_irq(KBDState *s)
 204 {
 205     /*
 206      * with KBD_STAT_OBF set, a call to kbd_read_data() will eventually call
 207      * kbd_update_irq()
 208      */
 209     if (s->status & KBD_STAT_OBF) {
 210         return;
 211     }
 212     /* the throttle timer is pending and will call kbd_update_irq() */
 213     if (s->throttle_timer && timer_pending(s->throttle_timer)) {
 214         return;
 215     }
 216     if (kbd_pending(s)) {
 217         kbd_update_irq(s);
 218     }
 219 }
 220
 221 static void kbd_update_kbd_irq(void *opaque, int level)
 222 {
 223     KBDState *s = opaque;
 224
 225     if (level) {
 226         s->pending |= KBD_PENDING_KBD;
 227     } else {
 228         s->pending &= ~KBD_PENDING_KBD;
 229     }
 230     kbd_safe_update_irq(s);
 231 }
 232
 233 static void kbd_update_aux_irq(void *opaque, int level)
 234 {
 235     KBDState *s = opaque;
 236
 237     if (level) {
 238         s->pending |= KBD_PENDING_AUX;
 239     } else {
 240         s->pending &= ~KBD_PENDING_AUX;
 241     }
 242     kbd_safe_update_irq(s);
 243 }
 244
 245 static void kbd_throttle_timeout(void *opaque)
 246 {
 247     KBDState *s = opaque;
 248
 249     if (kbd_pending(s)) {
 250         kbd_update_irq(s);
 251     }
 252 }
 253
 254 static uint64_t kbd_read_status(void *opaque, hwaddr addr,
 255                                 unsigned size)
 256 {
 257     KBDState *s = opaque;
 258     int val;
 259     val = s->status;
 260     trace_pckbd_kbd_read_status(val);
 261     return val;
 262 }
 263
 264 static void kbd_queue(KBDState *s, int b, int aux)
 265 {
 266     if (s->extended_state) {
 267         s->cbdata = b;
 268         s->pending &= ~KBD_PENDING_CTRL_KBD & ~KBD_PENDING_CTRL_AUX;
 269         s->pending |= aux ? KBD_PENDING_CTRL_AUX : KBD_PENDING_CTRL_KBD;
 270         kbd_safe_update_irq(s);
 271     } else {
 272         ps2_queue(aux ? s->mouse : s->kbd, b);
 273     }
 274 }
 275
 276 static uint8_t kbd_dequeue(KBDState *s)
 277 {
 278     uint8_t b = s->cbdata;
 279
 280     s->pending &= ~KBD_PENDING_CTRL_KBD & ~KBD_PENDING_CTRL_AUX;
 281     if (kbd_pending(s)) {
 282         kbd_update_irq(s);
 283     }
 284     return b;
 285 }
 286
 287 static void outport_write(KBDState *s, uint32_t val)
 288 {
 289     trace_pckbd_outport_write(val);
 290     s->outport = val;
 291     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 292     if (!(val & 1)) {
 293         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 294     }
 295 }
 296
 297 static void kbd_write_command(void *opaque, hwaddr addr,
 298                               uint64_t val, unsigned size)
 299 {
 300     KBDState *s = opaque;
 301
 302     trace_pckbd_kbd_write_command(val);
 303
 304     /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
 305      * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
 306      * command specify the output port bits to be pulsed.
 307      * 0: Bit should be pulsed. 1: Bit should not be modified.
 308      * The only useful version of this command is pulsing bit 0,
 309      * which does a CPU reset.
 310      */
 311     if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
 312         if(!(val & 1))
 313             val = KBD_CCMD_RESET;
 314         else
 315             val = KBD_CCMD_NO_OP;
 316     }
 317
 318     switch(val) {
 319     case KBD_CCMD_READ_MODE:
 320         kbd_queue(s, s->mode, 0);
 321         break;
 322     case KBD_CCMD_WRITE_MODE:
 323     case KBD_CCMD_WRITE_OBUF:
 324     case KBD_CCMD_WRITE_AUX_OBUF:
 325     case KBD_CCMD_WRITE_MOUSE:
 326     case KBD_CCMD_WRITE_OUTPORT:
 327         s->write_cmd = val;
 328         break;
 329     case KBD_CCMD_MOUSE_DISABLE:
 330         s->mode |= KBD_MODE_DISABLE_MOUSE;
 331         break;
 332     case KBD_CCMD_MOUSE_ENABLE:
 333         s->mode &= ~KBD_MODE_DISABLE_MOUSE;
 334         kbd_safe_update_irq(s);
 335         break;
 336     case KBD_CCMD_TEST_MOUSE:
 337         kbd_queue(s, 0x00, 0);
 338         break;
 339     case KBD_CCMD_SELF_TEST:
 340         s->status |= KBD_STAT_SELFTEST;
 341         kbd_queue(s, 0x55, 0);
 342         break;
 343     case KBD_CCMD_KBD_TEST:
 344         kbd_queue(s, 0x00, 0);
 345         break;
 346     case KBD_CCMD_KBD_DISABLE:
 347         s->mode |= KBD_MODE_DISABLE_KBD;
 348         break;
 349     case KBD_CCMD_KBD_ENABLE:
 350         s->mode &= ~KBD_MODE_DISABLE_KBD;
 351         kbd_safe_update_irq(s);
 352         break;
 353     case KBD_CCMD_READ_INPORT:
 354         kbd_queue(s, 0x80, 0);
 355         break;
 356     case KBD_CCMD_READ_OUTPORT:
 357         kbd_queue(s, s->outport, 0);
 358         break;
 359     case KBD_CCMD_ENABLE_A20:
 360         qemu_irq_raise(s->a20_out);
 361         s->outport |= KBD_OUT_A20;
 362         break;
 363     case KBD_CCMD_DISABLE_A20:
 364         qemu_irq_lower(s->a20_out);
 365         s->outport &= ~KBD_OUT_A20;
 366         break;
 367     case KBD_CCMD_RESET:
 368         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 369         break;
 370     case KBD_CCMD_NO_OP:
 371         /* ignore that */
 372         break;
 373     default:
 374         qemu_log_mask(LOG_GUEST_ERROR,
 375                       "unsupported keyboard cmd=0x%02" PRIx64 "\n", val);
 376         break;
 377     }
 378 }
 379
 380 static uint64_t kbd_read_data(void *opaque, hwaddr addr,
 381                               unsigned size)
 382 {
 383     KBDState *s = opaque;
 384
 385     if (s->status & KBD_STAT_OBF) {
 386         kbd_deassert_irq(s);
 387         if (s->obsrc & KBD_OBSRC_KBD) {
 388             if (s->throttle_timer) {
 389                 timer_mod(s->throttle_timer,
 390                           qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) + 1000);
 391             }
 392             s->obdata = ps2_read_data(s->kbd);
 393         } else if (s->obsrc & KBD_OBSRC_MOUSE) {
 394             s->obdata = ps2_read_data(s->mouse);
 395         } else if (s->obsrc & KBD_OBSRC_CTRL) {
 396             s->obdata = kbd_dequeue(s);
 397         }
 398     }
 399
 400     trace_pckbd_kbd_read_data(s->obdata);
 401     return s->obdata;
 402 }
 403
 404 static void kbd_write_data(void *opaque, hwaddr addr,
 405                            uint64_t val, unsigned size)
 406 {
 407     KBDState *s = opaque;
 408
 409     trace_pckbd_kbd_write_data(val);
 410
 411     switch(s->write_cmd) {
 412     case 0:
 413         ps2_write_keyboard(s->kbd, val);
 414         /* sending data to the keyboard reenables PS/2 communication */
 415         s->mode &= ~KBD_MODE_DISABLE_KBD;
 416         kbd_safe_update_irq(s);
 417         break;
 418     case KBD_CCMD_WRITE_MODE:
 419         s->mode = val;
 420         ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
 421         /*
 422          * a write to the mode byte interrupt enable flags directly updates
 423          * the irq lines
 424          */
 425         kbd_update_irq_lines(s);
 426         /*
 427          * a write to the mode byte disable interface flags may raise
 428          * an irq if there is pending data in the PS/2 queues.
 429          */
 430         kbd_safe_update_irq(s);
 431         break;
 432     case KBD_CCMD_WRITE_OBUF:
 433         kbd_queue(s, val, 0);
 434         break;
 435     case KBD_CCMD_WRITE_AUX_OBUF:
 436         kbd_queue(s, val, 1);
 437         break;
 438     case KBD_CCMD_WRITE_OUTPORT:
 439         outport_write(s, val);
 440         break;
 441     case KBD_CCMD_WRITE_MOUSE:
 442         ps2_write_mouse(s->mouse, val);
 443         /* sending data to the mouse reenables PS/2 communication */
 444         s->mode &= ~KBD_MODE_DISABLE_MOUSE;
 445         kbd_safe_update_irq(s);
 446         break;
 447     default:
 448         break;
 449     }
 450     s->write_cmd = 0;
 451 }
 452
 453 static void kbd_reset(void *opaque)
 454 {
 455     KBDState *s = opaque;
 456
 457     s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
 458     s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
 459     s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES;
 460     s->outport_present = false;
 461     s->pending = 0;
 462     kbd_deassert_irq(s);
 463     if (s->throttle_timer) {
 464         timer_del(s->throttle_timer);
 465     }
 466 }
 467
 468 static uint8_t kbd_outport_default(KBDState *s)
 469 {
 470     return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES
 471            | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0)
 472            | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0);
 473 }
 474
 475 static int kbd_outport_post_load(void *opaque, int version_id)
 476 {
 477     KBDState *s = opaque;
 478     s->outport_present = true;
 479     return 0;
 480 }
 481
 482 static bool kbd_outport_needed(void *opaque)
 483 {
 484     KBDState *s = opaque;
 485     return s->outport != kbd_outport_default(s);
 486 }
 487
 488 static const VMStateDescription vmstate_kbd_outport = {
 489     .name = "pckbd_outport",
 490     .version_id = 1,
 491     .minimum_version_id = 1,
 492     .post_load = kbd_outport_post_load,
 493     .needed = kbd_outport_needed,
 494     .fields = (VMStateField[]) {
 495         VMSTATE_UINT8(outport, KBDState),
 496         VMSTATE_END_OF_LIST()
 497     }
 498 };
 499
 500 static int kbd_extended_state_pre_save(void *opaque)
 501 {
 502     KBDState *s = opaque;
 503
 504     s->migration_flags = 0;
 505     if (s->throttle_timer && timer_pending(s->throttle_timer)) {
 506         s->migration_flags |= KBD_MIGR_TIMER_PENDING;
 507     }
 508
 509     return 0;
 510 }
 511
 512 static int kbd_extended_state_post_load(void *opaque, int version_id)
 513 {
 514     KBDState *s = opaque;
 515
 516     if (s->migration_flags & KBD_MIGR_TIMER_PENDING) {
 517         kbd_throttle_timeout(s);
 518     }
 519     s->extended_state_loaded = true;
 520
 521     return 0;
 522 }
 523
 524 static bool kbd_extended_state_needed(void *opaque)
 525 {
 526     KBDState *s = opaque;
 527
 528     return s->extended_state;
 529 }
 530
 531 static const VMStateDescription vmstate_kbd_extended_state = {
 532     .name = "pckbd/extended_state",
 533     .post_load = kbd_extended_state_post_load,
 534     .pre_save = kbd_extended_state_pre_save,
 535     .needed = kbd_extended_state_needed,
 536     .fields = (VMStateField[]) {
 537         VMSTATE_UINT32(migration_flags, KBDState),
 538         VMSTATE_UINT32(obsrc, KBDState),
 539         VMSTATE_UINT8(obdata, KBDState),
 540         VMSTATE_UINT8(cbdata, KBDState),
 541         VMSTATE_END_OF_LIST()
 542     }
 543 };
 544
 545 static int kbd_pre_save(void *opaque)
 546 {
 547     KBDState *s = opaque;
 548
 549     if (s->extended_state) {
 550         s->pending_tmp = s->pending;
 551     } else {
 552         s->pending_tmp = 0;
 553         if (s->pending & KBD_PENDING_KBD) {
 554             s->pending_tmp |= KBD_PENDING_KBD_COMPAT;
 555         }
 556         if (s->pending & KBD_PENDING_AUX) {
 557             s->pending_tmp |= KBD_PENDING_AUX_COMPAT;
 558         }
 559     }
 560     return 0;
 561 }
 562
 563 static int kbd_pre_load(void *opaque)
 564 {
 565     KBDState *s = opaque;
 566
 567     s->extended_state_loaded = false;
 568     return 0;
 569 }
 570
 571 static int kbd_post_load(void *opaque, int version_id)
 572 {
 573     KBDState *s = opaque;
 574     if (!s->outport_present) {
 575         s->outport = kbd_outport_default(s);
 576     }
 577     s->outport_present = false;
 578     s->pending = s->pending_tmp;
 579     if (!s->extended_state_loaded) {
 580         s->obsrc = s->status & KBD_STAT_OBF ?
 581             (s->status & KBD_STAT_MOUSE_OBF ? KBD_OBSRC_MOUSE : KBD_OBSRC_KBD) :
 582             0;
 583         if (s->pending & KBD_PENDING_KBD_COMPAT) {
 584             s->pending |= KBD_PENDING_KBD;
 585         }
 586         if (s->pending & KBD_PENDING_AUX_COMPAT) {
 587             s->pending |= KBD_PENDING_AUX;
 588         }
 589     }
 590     /* clear all unused flags */
 591     s->pending &= KBD_PENDING_CTRL_KBD | KBD_PENDING_CTRL_AUX |
 592                   KBD_PENDING_KBD | KBD_PENDING_AUX;
 593     return 0;
 594 }
 595
 596 static const VMStateDescription vmstate_kbd = {
 597     .name = "pckbd",
 598     .version_id = 3,
 599     .minimum_version_id = 3,
 600     .pre_load = kbd_pre_load,
 601     .post_load = kbd_post_load,
 602     .pre_save = kbd_pre_save,
 603     .fields = (VMStateField[]) {
 604         VMSTATE_UINT8(write_cmd, KBDState),
 605         VMSTATE_UINT8(status, KBDState),
 606         VMSTATE_UINT8(mode, KBDState),
 607         VMSTATE_UINT8(pending_tmp, KBDState),
 608         VMSTATE_END_OF_LIST()
 609     },
 610     .subsections = (const VMStateDescription*[]) {
 611         &vmstate_kbd_outport,
 612         &vmstate_kbd_extended_state,
 613         NULL
 614     }
 615 };
 616
 617 /* Memory mapped interface */
 618 static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size)
 619 {
 620     KBDState *s = opaque;
 621
 622     if (addr & s->mask)
 623         return kbd_read_status(s, 0, 1) & 0xff;
 624     else
 625         return kbd_read_data(s, 0, 1) & 0xff;
 626 }
 627
 628 static void kbd_mm_writefn(void *opaque, hwaddr addr,
 629                            uint64_t value, unsigned size)
 630 {
 631     KBDState *s = opaque;
 632
 633     if (addr & s->mask)
 634         kbd_write_command(s, 0, value & 0xff, 1);
 635     else
 636         kbd_write_data(s, 0, value & 0xff, 1);
 637 }
 638
 639
 640 static const MemoryRegionOps i8042_mmio_ops = {
 641     .read = kbd_mm_readfn,
 642     .write = kbd_mm_writefn,
 643     .valid.min_access_size = 1,
 644     .valid.max_access_size = 4,
 645     .endianness = DEVICE_NATIVE_ENDIAN,
 646 };
 647
 648 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 649                    MemoryRegion *region, ram_addr_t size,
 650                    hwaddr mask)
 651 {
 652     KBDState *s = g_malloc0(sizeof(KBDState));
 653
 654     s->irq_kbd = kbd_irq;
 655     s->irq_mouse = mouse_irq;
 656     s->mask = mask;
 657
 658     s->extended_state = true;
 659
 660     vmstate_register(NULL, 0, &vmstate_kbd, s);
 661
 662     memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size);
 663
 664     s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
 665     s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
 666     qemu_register_reset(kbd_reset, s);
 667 }
 668
 669 struct ISAKBDState {
 670     ISADevice parent_obj;
 671
 672     KBDState kbd;
 673     bool kbd_throttle;
 674     MemoryRegion io[2];
 675 };
 676
 677 void i8042_isa_mouse_fake_event(ISAKBDState *isa)
 678 {
 679     KBDState *s = &isa->kbd;
 680
 681     ps2_mouse_fake_event(s->mouse);
 682 }
 683
 684 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out)
 685 {
 686     qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out);
 687 }
 688
 689 static const VMStateDescription vmstate_kbd_isa = {
 690     .name = "pckbd",
 691     .version_id = 3,
 692     .minimum_version_id = 3,
 693     .fields = (VMStateField[]) {
 694         VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
 695         VMSTATE_END_OF_LIST()
 696     }
 697 };
 698
 699 static const MemoryRegionOps i8042_data_ops = {
 700     .read = kbd_read_data,
 701     .write = kbd_write_data,
 702     .impl = {
 703         .min_access_size = 1,
 704         .max_access_size = 1,
 705     },
 706     .endianness = DEVICE_LITTLE_ENDIAN,
 707 };
 708
 709 static const MemoryRegionOps i8042_cmd_ops = {
 710     .read = kbd_read_status,
 711     .write = kbd_write_command,
 712     .impl = {
 713         .min_access_size = 1,
 714         .max_access_size = 1,
 715     },
 716     .endianness = DEVICE_LITTLE_ENDIAN,
 717 };
 718
 719 static void i8042_initfn(Object *obj)
 720 {
 721     ISAKBDState *isa_s = I8042(obj);
 722     KBDState *s = &isa_s->kbd;
 723
 724     memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
 725                           "i8042-data", 1);
 726     memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
 727                           "i8042-cmd", 1);
 728
 729     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
 730 }
 731
 732 static void i8042_realizefn(DeviceState *dev, Error **errp)
 733 {
 734     ISADevice *isadev = ISA_DEVICE(dev);
 735     ISAKBDState *isa_s = I8042(dev);
 736     KBDState *s = &isa_s->kbd;
 737
 738     isa_init_irq(isadev, &s->irq_kbd, 1);
 739     isa_init_irq(isadev, &s->irq_mouse, 12);
 740
 741     isa_register_ioport(isadev, isa_s->io + 0, 0x60);
 742     isa_register_ioport(isadev, isa_s->io + 1, 0x64);
 743
 744     s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
 745     s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
 746     if (isa_s->kbd_throttle && !isa_s->kbd.extended_state) {
 747         warn_report(TYPE_I8042 ": can't enable kbd-throttle without"
 748                     " extended-state, disabling kbd-throttle");
 749     } else if (isa_s->kbd_throttle) {
 750         s->throttle_timer = timer_new_us(QEMU_CLOCK_VIRTUAL,
 751                                          kbd_throttle_timeout, s);
 752     }
 753     qemu_register_reset(kbd_reset, s);
 754 }
 755
 756 static void i8042_build_aml(ISADevice *isadev, Aml *scope)
 757 {
 758     Aml *kbd;
 759     Aml *mou;
 760     Aml *crs;
 761
 762     crs = aml_resource_template();
 763     aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
 764     aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
 765     aml_append(crs, aml_irq_no_flags(1));
 766
 767     kbd = aml_device("KBD");
 768     aml_append(kbd, aml_name_decl("_HID", aml_eisaid("PNP0303")));
 769     aml_append(kbd, aml_name_decl("_STA", aml_int(0xf)));
 770     aml_append(kbd, aml_name_decl("_CRS", crs));
 771
 772     crs = aml_resource_template();
 773     aml_append(crs, aml_irq_no_flags(12));
 774
 775     mou = aml_device("MOU");
 776     aml_append(mou, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
 777     aml_append(mou, aml_name_decl("_STA", aml_int(0xf)));
 778     aml_append(mou, aml_name_decl("_CRS", crs));
 779
 780     aml_append(scope, kbd);
 781     aml_append(scope, mou);
 782 }
 783
 784 static Property i8042_properties[] = {
 785     DEFINE_PROP_BOOL("extended-state", ISAKBDState, kbd.extended_state, true),
 786     DEFINE_PROP_BOOL("kbd-throttle", ISAKBDState, kbd_throttle, false),
 787     DEFINE_PROP_END_OF_LIST(),
 788 };
 789
 790 static void i8042_class_initfn(ObjectClass *klass, void *data)
 791 {
 792     DeviceClass *dc = DEVICE_CLASS(klass);
 793     ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
 794
 795     device_class_set_props(dc, i8042_properties);
 796     dc->realize = i8042_realizefn;
 797     dc->vmsd = &vmstate_kbd_isa;
 798     isa->build_aml = i8042_build_aml;
 799     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 800 }
 801
 802 static const TypeInfo i8042_info = {
 803     .name          = TYPE_I8042,
 804     .parent        = TYPE_ISA_DEVICE,
 805     .instance_size = sizeof(ISAKBDState),
 806     .instance_init = i8042_initfn,
 807     .class_init    = i8042_class_initfn,
 808 };
 809
 810 static void i8042_register_types(void)
 811 {
 812     type_register_static(&i8042_info);
 813 }
 814
 815 type_init(i8042_register_types)