hw/misc/exynos4210_clk.c

   1 /*
   2  *  Exynos4210 Clock Controller Emulation
   3  *
   4  *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/sysbus.h"
  22 #include "migration/vmstate.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "qom/object.h"
  26
  27 #define TYPE_EXYNOS4210_CLK             "exynos4210.clk"
  28 typedef struct Exynos4210ClkState Exynos4210ClkState;
  29 DECLARE_INSTANCE_CHECKER(Exynos4210ClkState, EXYNOS4210_CLK,
  30                          TYPE_EXYNOS4210_CLK)
  31
  32 #define CLK_PLL_LOCKED                  BIT(29)
  33
  34 #define EXYNOS4210_CLK_REGS_MEM_SIZE    0x15104
  35
  36 typedef struct Exynos4210Reg {
  37     const char   *name; /* for debug only */
  38     uint32_t     offset;
  39     uint32_t     reset_value;
  40 } Exynos4210Reg;
  41
  42 /* Clock controller register base: 0x10030000 */
  43 static const Exynos4210Reg exynos4210_clk_regs[] = {
  44     {"EPLL_LOCK",                     0xc010, 0x00000fff},
  45     {"VPLL_LOCK",                     0xc020, 0x00000fff},
  46     {"EPLL_CON0",                     0xc110, 0x00300301 | CLK_PLL_LOCKED},
  47     {"EPLL_CON1",                     0xc114, 0x00000000},
  48     {"VPLL_CON0",                     0xc120, 0x00240201 | CLK_PLL_LOCKED},
  49     {"VPLL_CON1",                     0xc124, 0x66010464},
  50     {"APLL_LOCK",                    0x14000, 0x00000fff},
  51     {"MPLL_LOCK",                    0x14004, 0x00000fff},
  52     {"APLL_CON0",                    0x14100, 0x00c80601 | CLK_PLL_LOCKED},
  53     {"APLL_CON1",                    0x14104, 0x0000001c},
  54     {"MPLL_CON0",                    0x14108, 0x00c80601 | CLK_PLL_LOCKED},
  55     {"MPLL_CON1",                    0x1410c, 0x0000001c},
  56 };
  57
  58 #define EXYNOS4210_REGS_NUM       ARRAY_SIZE(exynos4210_clk_regs)
  59
  60 struct Exynos4210ClkState {
  61     SysBusDevice parent_obj;
  62
  63     MemoryRegion iomem;
  64     uint32_t reg[EXYNOS4210_REGS_NUM];
  65 };
  66
  67 static uint64_t exynos4210_clk_read(void *opaque, hwaddr offset,
  68                                     unsigned size)
  69 {
  70     const Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
  71     const Exynos4210Reg *regs = exynos4210_clk_regs;
  72     unsigned int i;
  73
  74     for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
  75         if (regs->offset == offset) {
  76             return s->reg[i];
  77         }
  78         regs++;
  79     }
  80     qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n",
  81                   __func__, (uint32_t)offset);
  82     return 0;
  83 }
  84
  85 static void exynos4210_clk_write(void *opaque, hwaddr offset,
  86                                  uint64_t val, unsigned size)
  87 {
  88     Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
  89     const Exynos4210Reg *regs = exynos4210_clk_regs;
  90     unsigned int i;
  91
  92     for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
  93         if (regs->offset == offset) {
  94             s->reg[i] = val;
  95             return;
  96         }
  97         regs++;
  98     }
  99     qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n",
 100                   __func__, (uint32_t)offset);
 101 }
 102
 103 static const MemoryRegionOps exynos4210_clk_ops = {
 104     .read = exynos4210_clk_read,
 105     .write = exynos4210_clk_write,
 106     .endianness = DEVICE_NATIVE_ENDIAN,
 107     .valid = {
 108         .min_access_size = 4,
 109         .max_access_size = 4,
 110         .unaligned = false
 111     }
 112 };
 113
 114 static void exynos4210_clk_reset(DeviceState *dev)
 115 {
 116     Exynos4210ClkState *s = EXYNOS4210_CLK(dev);
 117     unsigned int i;
 118
 119     /* Set default values for registers */
 120     for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
 121         s->reg[i] = exynos4210_clk_regs[i].reset_value;
 122     }
 123 }
 124
 125 static void exynos4210_clk_init(Object *obj)
 126 {
 127     Exynos4210ClkState *s = EXYNOS4210_CLK(obj);
 128     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 129
 130     /* memory mapping */
 131     memory_region_init_io(&s->iomem, obj, &exynos4210_clk_ops, s,
 132                           TYPE_EXYNOS4210_CLK, EXYNOS4210_CLK_REGS_MEM_SIZE);
 133     sysbus_init_mmio(dev, &s->iomem);
 134 }
 135
 136 static const VMStateDescription exynos4210_clk_vmstate = {
 137     .name = TYPE_EXYNOS4210_CLK,
 138     .version_id = 1,
 139     .minimum_version_id = 1,
 140     .fields = (VMStateField[]) {
 141         VMSTATE_UINT32_ARRAY(reg, Exynos4210ClkState, EXYNOS4210_REGS_NUM),
 142         VMSTATE_END_OF_LIST()
 143     }
 144 };
 145
 146 static void exynos4210_clk_class_init(ObjectClass *klass, void *data)
 147 {
 148     DeviceClass *dc = DEVICE_CLASS(klass);
 149
 150     dc->reset = exynos4210_clk_reset;
 151     dc->vmsd = &exynos4210_clk_vmstate;
 152 }
 153
 154 static const TypeInfo exynos4210_clk_info = {
 155     .name          = TYPE_EXYNOS4210_CLK,
 156     .parent        = TYPE_SYS_BUS_DEVICE,
 157     .instance_size = sizeof(Exynos4210ClkState),
 158     .instance_init = exynos4210_clk_init,
 159     .class_init    = exynos4210_clk_class_init,
 160 };
 161
 162 static void exynos4210_clk_register(void)
 163 {
 164     qemu_log_mask(LOG_GUEST_ERROR, "Clock init\n");
 165     type_register_static(&exynos4210_clk_info);
 166 }
 167
 168 type_init(exynos4210_clk_register)