hw/misc/arm_sysctl.c

   1 /*
   2  * Status and system control registers for ARM RealView/Versatile boards.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/irq.h"
  12 #include "hw/qdev-properties.h"
  13 #include "qemu/timer.h"
  14 #include "sysemu/runstate.h"
  15 #include "qemu/bitops.h"
  16 #include "hw/sysbus.h"
  17 #include "migration/vmstate.h"
  18 #include "hw/arm/primecell.h"
  19 #include "qemu/log.h"
  20 #include "qemu/module.h"
  21 #include "qom/object.h"
  22
  23 #define LOCK_VALUE 0xa05f
  24
  25 #define TYPE_ARM_SYSCTL "realview_sysctl"
  26 typedef struct arm_sysctl_state arm_sysctl_state;
  27 DECLARE_INSTANCE_CHECKER(arm_sysctl_state, ARM_SYSCTL,
  28                          TYPE_ARM_SYSCTL)
  29
  30 struct arm_sysctl_state {
  31     SysBusDevice parent_obj;
  32
  33     MemoryRegion iomem;
  34     qemu_irq pl110_mux_ctrl;
  35
  36     uint32_t sys_id;
  37     uint32_t leds;
  38     uint16_t lockval;
  39     uint32_t cfgdata1;
  40     uint32_t cfgdata2;
  41     uint32_t flags;
  42     uint32_t nvflags;
  43     uint32_t resetlevel;
  44     uint32_t proc_id;
  45     uint32_t sys_mci;
  46     uint32_t sys_cfgdata;
  47     uint32_t sys_cfgctrl;
  48     uint32_t sys_cfgstat;
  49     uint32_t sys_clcd;
  50     uint32_t mb_clock[6];
  51     uint32_t *db_clock;
  52     uint32_t db_num_vsensors;
  53     uint32_t *db_voltage;
  54     uint32_t db_num_clocks;
  55     uint32_t *db_clock_reset;
  56 };
  57
  58 static const VMStateDescription vmstate_arm_sysctl = {
  59     .name = "realview_sysctl",
  60     .version_id = 4,
  61     .minimum_version_id = 1,
  62     .fields = (VMStateField[]) {
  63         VMSTATE_UINT32(leds, arm_sysctl_state),
  64         VMSTATE_UINT16(lockval, arm_sysctl_state),
  65         VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  66         VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  67         VMSTATE_UINT32(flags, arm_sysctl_state),
  68         VMSTATE_UINT32(nvflags, arm_sysctl_state),
  69         VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  70         VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  71         VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  72         VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  73         VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  74         VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
  75         VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
  76         VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
  77                               4, vmstate_info_uint32, uint32_t),
  78         VMSTATE_END_OF_LIST()
  79     }
  80 };
  81
  82 /* The PB926 actually uses a different format for
  83  * its SYS_ID register. Fortunately the bits which are
  84  * board type on later boards are distinct.
  85  */
  86 #define BOARD_ID_PB926 0x100
  87 #define BOARD_ID_EB 0x140
  88 #define BOARD_ID_PBA8 0x178
  89 #define BOARD_ID_PBX 0x182
  90 #define BOARD_ID_VEXPRESS 0x190
  91
  92 static int board_id(arm_sysctl_state *s)
  93 {
  94     /* Extract the board ID field from the SYS_ID register value */
  95     return (s->sys_id >> 16) & 0xfff;
  96 }
  97
  98 static void arm_sysctl_reset(DeviceState *d)
  99 {
 100     arm_sysctl_state *s = ARM_SYSCTL(d);
 101     int i;
 102
 103     s->leds = 0;
 104     s->lockval = 0;
 105     s->cfgdata1 = 0;
 106     s->cfgdata2 = 0;
 107     s->flags = 0;
 108     s->resetlevel = 0;
 109     /* Motherboard oscillators (in Hz) */
 110     s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
 111     s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
 112     s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
 113     s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
 114     s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
 115     s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
 116     /* Daughterboard oscillators: reset from property values */
 117     for (i = 0; i < s->db_num_clocks; i++) {
 118         s->db_clock[i] = s->db_clock_reset[i];
 119     }
 120     if (board_id(s) == BOARD_ID_VEXPRESS) {
 121         /* On VExpress this register will RAZ/WI */
 122         s->sys_clcd = 0;
 123     } else {
 124         /* All others: CLCDID 0x1f, indicating VGA */
 125         s->sys_clcd = 0x1f00;
 126     }
 127 }
 128
 129 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
 130                                 unsigned size)
 131 {
 132     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 133
 134     switch (offset) {
 135     case 0x00: /* ID */
 136         return s->sys_id;
 137     case 0x04: /* SW */
 138         /* General purpose hardware switches.
 139            We don't have a useful way of exposing these to the user.  */
 140         return 0;
 141     case 0x08: /* LED */
 142         return s->leds;
 143     case 0x20: /* LOCK */
 144         return s->lockval;
 145     case 0x0c: /* OSC0 */
 146     case 0x10: /* OSC1 */
 147     case 0x14: /* OSC2 */
 148     case 0x18: /* OSC3 */
 149     case 0x1c: /* OSC4 */
 150     case 0x24: /* 100HZ */
 151         /* ??? Implement these.  */
 152         return 0;
 153     case 0x28: /* CFGDATA1 */
 154         return s->cfgdata1;
 155     case 0x2c: /* CFGDATA2 */
 156         return s->cfgdata2;
 157     case 0x30: /* FLAGS */
 158         return s->flags;
 159     case 0x38: /* NVFLAGS */
 160         return s->nvflags;
 161     case 0x40: /* RESETCTL */
 162         if (board_id(s) == BOARD_ID_VEXPRESS) {
 163             /* reserved: RAZ/WI */
 164             return 0;
 165         }
 166         return s->resetlevel;
 167     case 0x44: /* PCICTL */
 168         return 1;
 169     case 0x48: /* MCI */
 170         return s->sys_mci;
 171     case 0x4c: /* FLASH */
 172         return 0;
 173     case 0x50: /* CLCD */
 174         return s->sys_clcd;
 175     case 0x54: /* CLCDSER */
 176         return 0;
 177     case 0x58: /* BOOTCS */
 178         return 0;
 179     case 0x5c: /* 24MHz */
 180         return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000,
 181                         NANOSECONDS_PER_SECOND);
 182     case 0x60: /* MISC */
 183         return 0;
 184     case 0x84: /* PROCID0 */
 185         return s->proc_id;
 186     case 0x88: /* PROCID1 */
 187         return 0xff000000;
 188     case 0x64: /* DMAPSR0 */
 189     case 0x68: /* DMAPSR1 */
 190     case 0x6c: /* DMAPSR2 */
 191     case 0x70: /* IOSEL */
 192     case 0x74: /* PLDCTL */
 193     case 0x80: /* BUSID */
 194     case 0x8c: /* OSCRESET0 */
 195     case 0x90: /* OSCRESET1 */
 196     case 0x94: /* OSCRESET2 */
 197     case 0x98: /* OSCRESET3 */
 198     case 0x9c: /* OSCRESET4 */
 199     case 0xc0: /* SYS_TEST_OSC0 */
 200     case 0xc4: /* SYS_TEST_OSC1 */
 201     case 0xc8: /* SYS_TEST_OSC2 */
 202     case 0xcc: /* SYS_TEST_OSC3 */
 203     case 0xd0: /* SYS_TEST_OSC4 */
 204         return 0;
 205     case 0xa0: /* SYS_CFGDATA */
 206         if (board_id(s) != BOARD_ID_VEXPRESS) {
 207             goto bad_reg;
 208         }
 209         return s->sys_cfgdata;
 210     case 0xa4: /* SYS_CFGCTRL */
 211         if (board_id(s) != BOARD_ID_VEXPRESS) {
 212             goto bad_reg;
 213         }
 214         return s->sys_cfgctrl;
 215     case 0xa8: /* SYS_CFGSTAT */
 216         if (board_id(s) != BOARD_ID_VEXPRESS) {
 217             goto bad_reg;
 218         }
 219         return s->sys_cfgstat;
 220     default:
 221     bad_reg:
 222         qemu_log_mask(LOG_GUEST_ERROR,
 223                       "arm_sysctl_read: Bad register offset 0x%x\n",
 224                       (int)offset);
 225         return 0;
 226     }
 227 }
 228
 229 /* SYS_CFGCTRL functions */
 230 #define SYS_CFG_OSC 1
 231 #define SYS_CFG_VOLT 2
 232 #define SYS_CFG_AMP 3
 233 #define SYS_CFG_TEMP 4
 234 #define SYS_CFG_RESET 5
 235 #define SYS_CFG_SCC 6
 236 #define SYS_CFG_MUXFPGA 7
 237 #define SYS_CFG_SHUTDOWN 8
 238 #define SYS_CFG_REBOOT 9
 239 #define SYS_CFG_DVIMODE 11
 240 #define SYS_CFG_POWER 12
 241 #define SYS_CFG_ENERGY 13
 242
 243 /* SYS_CFGCTRL site field values */
 244 #define SYS_CFG_SITE_MB 0
 245 #define SYS_CFG_SITE_DB1 1
 246 #define SYS_CFG_SITE_DB2 2
 247
 248 /**
 249  * vexpress_cfgctrl_read:
 250  * @s: arm_sysctl_state pointer
 251  * @dcc, @function, @site, @position, @device: split out values from
 252  * SYS_CFGCTRL register
 253  * @val: pointer to where to put the read data on success
 254  *
 255  * Handle a VExpress SYS_CFGCTRL register read. On success, return true and
 256  * write the read value to *val. On failure, return false (and val may
 257  * or may not be written to).
 258  */
 259 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
 260                                   unsigned int function, unsigned int site,
 261                                   unsigned int position, unsigned int device,
 262                                   uint32_t *val)
 263 {
 264     /* We don't support anything other than DCC 0, board stack position 0
 265      * or sites other than motherboard/daughterboard:
 266      */
 267     if (dcc != 0 || position != 0 ||
 268         (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
 269         goto cfgctrl_unimp;
 270     }
 271
 272     switch (function) {
 273     case SYS_CFG_VOLT:
 274         if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
 275             *val = s->db_voltage[device];
 276             return true;
 277         }
 278         if (site == SYS_CFG_SITE_MB && device == 0) {
 279             /* There is only one motherboard voltage sensor:
 280              * VIO : 3.3V : bus voltage between mother and daughterboard
 281              */
 282             *val = 3300000;
 283             return true;
 284         }
 285         break;
 286     case SYS_CFG_OSC:
 287         if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {
 288             /* motherboard clock */
 289             *val = s->mb_clock[device];
 290             return true;
 291         }
 292         if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
 293             /* daughterboard clock */
 294             *val = s->db_clock[device];
 295             return true;
 296         }
 297         break;
 298     default:
 299         break;
 300     }
 301
 302 cfgctrl_unimp:
 303     qemu_log_mask(LOG_UNIMP,
 304                   "arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
 305                   "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
 306                   function, dcc, site, position, device);
 307     return false;
 308 }
 309
 310 /**
 311  * vexpress_cfgctrl_write:
 312  * @s: arm_sysctl_state pointer
 313  * @dcc, @function, @site, @position, @device: split out values from
 314  * SYS_CFGCTRL register
 315  * @val: data to write
 316  *
 317  * Handle a VExpress SYS_CFGCTRL register write. On success, return true.
 318  * On failure, return false.
 319  */
 320 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
 321                                    unsigned int function, unsigned int site,
 322                                    unsigned int position, unsigned int device,
 323                                    uint32_t val)
 324 {
 325     /* We don't support anything other than DCC 0, board stack position 0
 326      * or sites other than motherboard/daughterboard:
 327      */
 328     if (dcc != 0 || position != 0 ||
 329         (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
 330         goto cfgctrl_unimp;
 331     }
 332
 333     switch (function) {
 334     case SYS_CFG_OSC:
 335         if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {
 336             /* motherboard clock */
 337             s->mb_clock[device] = val;
 338             return true;
 339         }
 340         if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
 341             /* daughterboard clock */
 342             s->db_clock[device] = val;
 343             return true;
 344         }
 345         break;
 346     case SYS_CFG_MUXFPGA:
 347         if (site == SYS_CFG_SITE_MB && device == 0) {
 348             /* Select whether video output comes from motherboard
 349              * or daughterboard: log and ignore as QEMU doesn't
 350              * support this.
 351              */
 352             qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
 353                           "not supported, ignoring\n");
 354             return true;
 355         }
 356         break;
 357     case SYS_CFG_SHUTDOWN:
 358         if (site == SYS_CFG_SITE_MB && device == 0) {
 359             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 360             return true;
 361         }
 362         break;
 363     case SYS_CFG_REBOOT:
 364         if (site == SYS_CFG_SITE_MB && device == 0) {
 365             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 366             return true;
 367         }
 368         break;
 369     case SYS_CFG_DVIMODE:
 370         if (site == SYS_CFG_SITE_MB && device == 0) {
 371             /* Selecting DVI mode is meaningless for QEMU: we will
 372              * always display the output correctly according to the
 373              * pixel height/width programmed into the CLCD controller.
 374              */
 375             return true;
 376         }
 377     default:
 378         break;
 379     }
 380
 381 cfgctrl_unimp:
 382     qemu_log_mask(LOG_UNIMP,
 383                   "arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
 384                   "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
 385                   function, dcc, site, position, device);
 386     return false;
 387 }
 388
 389 static void arm_sysctl_write(void *opaque, hwaddr offset,
 390                              uint64_t val, unsigned size)
 391 {
 392     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 393
 394     switch (offset) {
 395     case 0x08: /* LED */
 396         s->leds = val;
 397         break;
 398     case 0x0c: /* OSC0 */
 399     case 0x10: /* OSC1 */
 400     case 0x14: /* OSC2 */
 401     case 0x18: /* OSC3 */
 402     case 0x1c: /* OSC4 */
 403         /* ??? */
 404         break;
 405     case 0x20: /* LOCK */
 406         if (val == LOCK_VALUE)
 407             s->lockval = val;
 408         else
 409             s->lockval = val & 0x7fff;
 410         break;
 411     case 0x28: /* CFGDATA1 */
 412         /* ??? Need to implement this.  */
 413         s->cfgdata1 = val;
 414         break;
 415     case 0x2c: /* CFGDATA2 */
 416         /* ??? Need to implement this.  */
 417         s->cfgdata2 = val;
 418         break;
 419     case 0x30: /* FLAGSSET */
 420         s->flags |= val;
 421         break;
 422     case 0x34: /* FLAGSCLR */
 423         s->flags &= ~val;
 424         break;
 425     case 0x38: /* NVFLAGSSET */
 426         s->nvflags |= val;
 427         break;
 428     case 0x3c: /* NVFLAGSCLR */
 429         s->nvflags &= ~val;
 430         break;
 431     case 0x40: /* RESETCTL */
 432         switch (board_id(s)) {
 433         case BOARD_ID_PB926:
 434             if (s->lockval == LOCK_VALUE) {
 435                 s->resetlevel = val;
 436                 if (val & 0x100) {
 437                     qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 438                 }
 439             }
 440             break;
 441         case BOARD_ID_PBX:
 442         case BOARD_ID_PBA8:
 443             if (s->lockval == LOCK_VALUE) {
 444                 s->resetlevel = val;
 445                 if (val & 0x04) {
 446                     qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 447                 }
 448             }
 449             break;
 450         case BOARD_ID_VEXPRESS:
 451         case BOARD_ID_EB:
 452         default:
 453             /* reserved: RAZ/WI */
 454             break;
 455         }
 456         break;
 457     case 0x44: /* PCICTL */
 458         /* nothing to do.  */
 459         break;
 460     case 0x4c: /* FLASH */
 461         break;
 462     case 0x50: /* CLCD */
 463         switch (board_id(s)) {
 464         case BOARD_ID_PB926:
 465             /* On 926 bits 13:8 are R/O, bits 1:0 control
 466              * the mux that defines how to interpret the PL110
 467              * graphics format, and other bits are r/w but we
 468              * don't implement them to do anything.
 469              */
 470             s->sys_clcd &= 0x3f00;
 471             s->sys_clcd |= val & ~0x3f00;
 472             qemu_set_irq(s->pl110_mux_ctrl, val & 3);
 473             break;
 474         case BOARD_ID_EB:
 475             /* The EB is the same except that there is no mux since
 476              * the EB has a PL111.
 477              */
 478             s->sys_clcd &= 0x3f00;
 479             s->sys_clcd |= val & ~0x3f00;
 480             break;
 481         case BOARD_ID_PBA8:
 482         case BOARD_ID_PBX:
 483             /* On PBA8 and PBX bit 7 is r/w and all other bits
 484              * are either r/o or RAZ/WI.
 485              */
 486             s->sys_clcd &= (1 << 7);
 487             s->sys_clcd |= val & ~(1 << 7);
 488             break;
 489         case BOARD_ID_VEXPRESS:
 490         default:
 491             /* On VExpress this register is unimplemented and will RAZ/WI */
 492             break;
 493         }
 494         break;
 495     case 0x54: /* CLCDSER */
 496     case 0x64: /* DMAPSR0 */
 497     case 0x68: /* DMAPSR1 */
 498     case 0x6c: /* DMAPSR2 */
 499     case 0x70: /* IOSEL */
 500     case 0x74: /* PLDCTL */
 501     case 0x80: /* BUSID */
 502     case 0x84: /* PROCID0 */
 503     case 0x88: /* PROCID1 */
 504     case 0x8c: /* OSCRESET0 */
 505     case 0x90: /* OSCRESET1 */
 506     case 0x94: /* OSCRESET2 */
 507     case 0x98: /* OSCRESET3 */
 508     case 0x9c: /* OSCRESET4 */
 509         break;
 510     case 0xa0: /* SYS_CFGDATA */
 511         if (board_id(s) != BOARD_ID_VEXPRESS) {
 512             goto bad_reg;
 513         }
 514         s->sys_cfgdata = val;
 515         return;
 516     case 0xa4: /* SYS_CFGCTRL */
 517         if (board_id(s) != BOARD_ID_VEXPRESS) {
 518             goto bad_reg;
 519         }
 520         /* Undefined bits [19:18] are RAZ/WI, and writing to
 521          * the start bit just triggers the action; it always reads
 522          * as zero.
 523          */
 524         s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
 525         if (val & (1 << 31)) {
 526             /* Start bit set -- actually do something */
 527             unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
 528             unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
 529             unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
 530             unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
 531             unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
 532             s->sys_cfgstat = 1;            /* complete */
 533             if (s->sys_cfgctrl & (1 << 30)) {
 534                 if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
 535                                             device, s->sys_cfgdata)) {
 536                     s->sys_cfgstat |= 2;        /* error */
 537                 }
 538             } else {
 539                 uint32_t val;
 540                 if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
 541                                            device, &val)) {
 542                     s->sys_cfgstat |= 2;        /* error */
 543                 } else {
 544                     s->sys_cfgdata = val;
 545                 }
 546             }
 547         }
 548         s->sys_cfgctrl &= ~(1 << 31);
 549         return;
 550     case 0xa8: /* SYS_CFGSTAT */
 551         if (board_id(s) != BOARD_ID_VEXPRESS) {
 552             goto bad_reg;
 553         }
 554         s->sys_cfgstat = val & 3;
 555         return;
 556     default:
 557     bad_reg:
 558         qemu_log_mask(LOG_GUEST_ERROR,
 559                       "arm_sysctl_write: Bad register offset 0x%x\n",
 560                       (int)offset);
 561         return;
 562     }
 563 }
 564
 565 static const MemoryRegionOps arm_sysctl_ops = {
 566     .read = arm_sysctl_read,
 567     .write = arm_sysctl_write,
 568     .endianness = DEVICE_NATIVE_ENDIAN,
 569 };
 570
 571 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 572 {
 573     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 574     switch (line) {
 575     case ARM_SYSCTL_GPIO_MMC_WPROT:
 576     {
 577         /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 578          * for all later boards it is bit 1.
 579          */
 580         int bit = 2;
 581         if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 582             bit = 4;
 583         }
 584         s->sys_mci &= ~bit;
 585         if (level) {
 586             s->sys_mci |= bit;
 587         }
 588         break;
 589     }
 590     case ARM_SYSCTL_GPIO_MMC_CARDIN:
 591         s->sys_mci &= ~1;
 592         if (level) {
 593             s->sys_mci |= 1;
 594         }
 595         break;
 596     }
 597 }
 598
 599 static void arm_sysctl_init(Object *obj)
 600 {
 601     DeviceState *dev = DEVICE(obj);
 602     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
 603     arm_sysctl_state *s = ARM_SYSCTL(obj);
 604
 605     memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s,
 606                           "arm-sysctl", 0x1000);
 607     sysbus_init_mmio(sd, &s->iomem);
 608     qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
 609     qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
 610 }
 611
 612 static void arm_sysctl_realize(DeviceState *d, Error **errp)
 613 {
 614     arm_sysctl_state *s = ARM_SYSCTL(d);
 615
 616     s->db_clock = g_new0(uint32_t, s->db_num_clocks);
 617 }
 618
 619 static void arm_sysctl_finalize(Object *obj)
 620 {
 621     arm_sysctl_state *s = ARM_SYSCTL(obj);
 622
 623     g_free(s->db_voltage);
 624     g_free(s->db_clock);
 625     g_free(s->db_clock_reset);
 626 }
 627
 628 static Property arm_sysctl_properties[] = {
 629     DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 630     DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 631     /* Daughterboard power supply voltages (as reported via SYS_CFG) */
 632     DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
 633                       db_voltage, qdev_prop_uint32, uint32_t),
 634     /* Daughterboard clock reset values (as reported via SYS_CFG) */
 635     DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks,
 636                       db_clock_reset, qdev_prop_uint32, uint32_t),
 637     DEFINE_PROP_END_OF_LIST(),
 638 };
 639
 640 static void arm_sysctl_class_init(ObjectClass *klass, void *data)
 641 {
 642     DeviceClass *dc = DEVICE_CLASS(klass);
 643
 644     dc->realize = arm_sysctl_realize;
 645     dc->reset = arm_sysctl_reset;
 646     dc->vmsd = &vmstate_arm_sysctl;
 647     device_class_set_props(dc, arm_sysctl_properties);
 648 }
 649
 650 static const TypeInfo arm_sysctl_info = {
 651     .name          = TYPE_ARM_SYSCTL,
 652     .parent        = TYPE_SYS_BUS_DEVICE,
 653     .instance_size = sizeof(arm_sysctl_state),
 654     .instance_init = arm_sysctl_init,
 655     .instance_finalize = arm_sysctl_finalize,
 656     .class_init    = arm_sysctl_class_init,
 657 };
 658
 659 static void arm_sysctl_register_types(void)
 660 {
 661     type_register_static(&arm_sysctl_info);
 662 }
 663
 664 type_init(arm_sysctl_register_types)