hw/misc/arm_l2x0.c

   1 /*
   2  * ARM dummy L210, L220, PL310 cache controller.
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or any later version, as published by the Free Software
   9  * Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/qdev-properties.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "qemu/log.h"
  26 #include "qemu/module.h"
  27 #include "qom/object.h"
  28
  29 /* L2C-310 r3p2 */
  30 #define CACHE_ID 0x410000c8
  31
  32 #define TYPE_ARM_L2X0 "l2x0"
  33 typedef struct L2x0State L2x0State;
  34 DECLARE_INSTANCE_CHECKER(L2x0State, ARM_L2X0,
  35                          TYPE_ARM_L2X0)
  36
  37 struct L2x0State {
  38     SysBusDevice parent_obj;
  39
  40     MemoryRegion iomem;
  41     uint32_t cache_type;
  42     uint32_t ctrl;
  43     uint32_t aux_ctrl;
  44     uint32_t data_ctrl;
  45     uint32_t tag_ctrl;
  46     uint32_t filter_start;
  47     uint32_t filter_end;
  48 };
  49
  50 static const VMStateDescription vmstate_l2x0 = {
  51     .name = "l2x0",
  52     .version_id = 1,
  53     .minimum_version_id = 1,
  54     .fields = (VMStateField[]) {
  55         VMSTATE_UINT32(ctrl, L2x0State),
  56         VMSTATE_UINT32(aux_ctrl, L2x0State),
  57         VMSTATE_UINT32(data_ctrl, L2x0State),
  58         VMSTATE_UINT32(tag_ctrl, L2x0State),
  59         VMSTATE_UINT32(filter_start, L2x0State),
  60         VMSTATE_UINT32(filter_end, L2x0State),
  61         VMSTATE_END_OF_LIST()
  62     }
  63 };
  64
  65
  66 static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
  67                                unsigned size)
  68 {
  69     uint32_t cache_data;
  70     L2x0State *s = (L2x0State *)opaque;
  71     offset &= 0xfff;
  72     if (offset >= 0x730 && offset < 0x800) {
  73         return 0; /* cache ops complete */
  74     }
  75     switch (offset) {
  76     case 0:
  77         return CACHE_ID;
  78     case 0x4:
  79         /* aux_ctrl values affect cache_type values */
  80         cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
  81         cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
  82         return s->cache_type |= (cache_data << 18) | (cache_data << 6);
  83     case 0x100:
  84         return s->ctrl;
  85     case 0x104:
  86         return s->aux_ctrl;
  87     case 0x108:
  88         return s->tag_ctrl;
  89     case 0x10C:
  90         return s->data_ctrl;
  91     case 0xC00:
  92         return s->filter_start;
  93     case 0xC04:
  94         return s->filter_end;
  95     case 0xF40:
  96         return 0;
  97     case 0xF60:
  98         return 0;
  99     case 0xF80:
 100         return 0;
 101     default:
 102         qemu_log_mask(LOG_GUEST_ERROR,
 103                       "l2x0_priv_read: Bad offset %x\n", (int)offset);
 104         break;
 105     }
 106     return 0;
 107 }
 108
 109 static void l2x0_priv_write(void *opaque, hwaddr offset,
 110                             uint64_t value, unsigned size)
 111 {
 112     L2x0State *s = (L2x0State *)opaque;
 113     offset &= 0xfff;
 114     if (offset >= 0x730 && offset < 0x800) {
 115         /* ignore */
 116         return;
 117     }
 118     switch (offset) {
 119     case 0x100:
 120         s->ctrl = value & 1;
 121         break;
 122     case 0x104:
 123         s->aux_ctrl = value;
 124         break;
 125     case 0x108:
 126         s->tag_ctrl = value;
 127         break;
 128     case 0x10C:
 129         s->data_ctrl = value;
 130         break;
 131     case 0xC00:
 132         s->filter_start = value;
 133         break;
 134     case 0xC04:
 135         s->filter_end = value;
 136         break;
 137     case 0xF40:
 138         return;
 139     case 0xF60:
 140         return;
 141     case 0xF80:
 142         return;
 143     default:
 144         qemu_log_mask(LOG_GUEST_ERROR,
 145                       "l2x0_priv_write: Bad offset %x\n", (int)offset);
 146         break;
 147     }
 148 }
 149
 150 static void l2x0_priv_reset(DeviceState *dev)
 151 {
 152     L2x0State *s = ARM_L2X0(dev);
 153
 154     s->ctrl = 0;
 155     s->aux_ctrl = 0x02020000;
 156     s->tag_ctrl = 0;
 157     s->data_ctrl = 0;
 158     s->filter_start = 0;
 159     s->filter_end = 0;
 160 }
 161
 162 static const MemoryRegionOps l2x0_mem_ops = {
 163     .read = l2x0_priv_read,
 164     .write = l2x0_priv_write,
 165     .endianness = DEVICE_NATIVE_ENDIAN,
 166  };
 167
 168 static void l2x0_priv_init(Object *obj)
 169 {
 170     L2x0State *s = ARM_L2X0(obj);
 171     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 172
 173     memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s,
 174                           "l2x0_cc", 0x1000);
 175     sysbus_init_mmio(dev, &s->iomem);
 176 }
 177
 178 static Property l2x0_properties[] = {
 179     DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
 180     DEFINE_PROP_END_OF_LIST(),
 181 };
 182
 183 static void l2x0_class_init(ObjectClass *klass, void *data)
 184 {
 185     DeviceClass *dc = DEVICE_CLASS(klass);
 186
 187     dc->vmsd = &vmstate_l2x0;
 188     device_class_set_props(dc, l2x0_properties);
 189     dc->reset = l2x0_priv_reset;
 190 }
 191
 192 static const TypeInfo l2x0_info = {
 193     .name = TYPE_ARM_L2X0,
 194     .parent = TYPE_SYS_BUS_DEVICE,
 195     .instance_size = sizeof(L2x0State),
 196     .instance_init = l2x0_priv_init,
 197     .class_init = l2x0_class_init,
 198 };
 199
 200 static void l2x0_register_types(void)
 201 {
 202     type_register_static(&l2x0_info);
 203 }
 204
 205 type_init(l2x0_register_types)