target-mips/kvm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10 */
  11
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "cpu.h"
  24 #include "sysemu/cpus.h"
  25 #include "kvm_mips.h"
  26 #include "exec/memattrs.h"
  27
  28 #define DEBUG_KVM 0
  29
  30 #define DPRINTF(fmt, ...) \
  31     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
  32
  33 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  34     KVM_CAP_LAST_INFO
  35 };
  36
  37 static void kvm_mips_update_state(void *opaque, int running, RunState state);
  38
  39 unsigned long kvm_arch_vcpu_id(CPUState *cs)
  40 {
  41     return cs->cpu_index;
  42 }
  43
  44 int kvm_arch_init(MachineState *ms, KVMState *s)
  45 {
  46     /* MIPS has 128 signals */
  47     kvm_set_sigmask_len(s, 16);
  48
  49     DPRINTF("%s\n", __func__);
  50     return 0;
  51 }
  52
  53 int kvm_arch_init_vcpu(CPUState *cs)
  54 {
  55     int ret = 0;
  56
  57     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
  58
  59     DPRINTF("%s\n", __func__);
  60     return ret;
  61 }
  62
  63 void kvm_mips_reset_vcpu(MIPSCPU *cpu)
  64 {
  65     CPUMIPSState *env = &cpu->env;
  66
  67     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  68         fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
  69         env->CP0_Config1 &= ~(1 << CP0C1_FP);
  70     }
  71
  72     DPRINTF("%s\n", __func__);
  73 }
  74
  75 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  76 {
  77     DPRINTF("%s\n", __func__);
  78     return 0;
  79 }
  80
  81 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  82 {
  83     DPRINTF("%s\n", __func__);
  84     return 0;
  85 }
  86
  87 static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
  88 {
  89     CPUMIPSState *env = &cpu->env;
  90
  91     DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
  92     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
  93 }
  94
  95
  96 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  97 {
  98     MIPSCPU *cpu = MIPS_CPU(cs);
  99     int r;
 100     struct kvm_mips_interrupt intr;
 101
 102     qemu_mutex_lock_iothread();
 103
 104     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 105             cpu_mips_io_interrupts_pending(cpu)) {
 106         intr.cpu = -1;
 107         intr.irq = 2;
 108         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 109         if (r < 0) {
 110             error_report("%s: cpu %d: failed to inject IRQ %x",
 111                          __func__, cs->cpu_index, intr.irq);
 112         }
 113     }
 114
 115     qemu_mutex_unlock_iothread();
 116 }
 117
 118 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 119 {
 120     DPRINTF("%s\n", __func__);
 121     return MEMTXATTRS_UNSPECIFIED;
 122 }
 123
 124 int kvm_arch_process_async_events(CPUState *cs)
 125 {
 126     return cs->halted;
 127 }
 128
 129 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 130 {
 131     int ret;
 132
 133     DPRINTF("%s\n", __func__);
 134     switch (run->exit_reason) {
 135     default:
 136         error_report("%s: unknown exit reason %d",
 137                      __func__, run->exit_reason);
 138         ret = -1;
 139         break;
 140     }
 141
 142     return ret;
 143 }
 144
 145 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 146 {
 147     DPRINTF("%s\n", __func__);
 148     return true;
 149 }
 150
 151 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 152 {
 153     DPRINTF("%s\n", __func__);
 154     return 1;
 155 }
 156
 157 int kvm_arch_on_sigbus(int code, void *addr)
 158 {
 159     DPRINTF("%s\n", __func__);
 160     return 1;
 161 }
 162
 163 void kvm_arch_init_irq_routing(KVMState *s)
 164 {
 165 }
 166
 167 int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
 168 {
 169     CPUState *cs = CPU(cpu);
 170     struct kvm_mips_interrupt intr;
 171
 172     if (!kvm_enabled()) {
 173         return 0;
 174     }
 175
 176     intr.cpu = -1;
 177
 178     if (level) {
 179         intr.irq = irq;
 180     } else {
 181         intr.irq = -irq;
 182     }
 183
 184     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 185
 186     return 0;
 187 }
 188
 189 int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 190 {
 191     CPUState *cs = current_cpu;
 192     CPUState *dest_cs = CPU(cpu);
 193     struct kvm_mips_interrupt intr;
 194
 195     if (!kvm_enabled()) {
 196         return 0;
 197     }
 198
 199     intr.cpu = dest_cs->cpu_index;
 200
 201     if (level) {
 202         intr.irq = irq;
 203     } else {
 204         intr.irq = -irq;
 205     }
 206
 207     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
 208
 209     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 210
 211     return 0;
 212 }
 213
 214 #define MIPS_CP0_32(_R, _S)                                     \
 215     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
 216
 217 #define MIPS_CP0_64(_R, _S)                                     \
 218     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
 219
 220 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
 221 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
 222 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
 223 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
 224 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
 225 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
 226 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
 227 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
 228 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
 229 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
 230 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 231 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 232 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
 233 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 234
 235 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
 236                                        int32_t *addr)
 237 {
 238     uint64_t val64 = *addr;
 239     struct kvm_one_reg cp0reg = {
 240         .id = reg_id,
 241         .addr = (uintptr_t)&val64
 242     };
 243
 244     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 245 }
 246
 247 static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
 248                                          target_ulong *addr)
 249 {
 250     uint64_t val64 = *addr;
 251     struct kvm_one_reg cp0reg = {
 252         .id = reg_id,
 253         .addr = (uintptr_t)&val64
 254     };
 255
 256     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 257 }
 258
 259 static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
 260                                          uint64_t *addr)
 261 {
 262     struct kvm_one_reg cp0reg = {
 263         .id = reg_id,
 264         .addr = (uintptr_t)addr
 265     };
 266
 267     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 268 }
 269
 270 static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
 271                                        int32_t *addr)
 272 {
 273     int ret;
 274     uint64_t val64 = 0;
 275     struct kvm_one_reg cp0reg = {
 276         .id = reg_id,
 277         .addr = (uintptr_t)&val64
 278     };
 279
 280     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 281     if (ret >= 0) {
 282         *addr = val64;
 283     }
 284     return ret;
 285 }
 286
 287 static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id,
 288                                          target_ulong *addr)
 289 {
 290     int ret;
 291     uint64_t val64 = 0;
 292     struct kvm_one_reg cp0reg = {
 293         .id = reg_id,
 294         .addr = (uintptr_t)&val64
 295     };
 296
 297     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 298     if (ret >= 0) {
 299         *addr = val64;
 300     }
 301     return ret;
 302 }
 303
 304 static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64 reg_id,
 305                                          uint64_t *addr)
 306 {
 307     struct kvm_one_reg cp0reg = {
 308         .id = reg_id,
 309         .addr = (uintptr_t)addr
 310     };
 311
 312     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 313 }
 314
 315 /*
 316  * We freeze the KVM timer when either the VM clock is stopped or the state is
 317  * saved (the state is dirty).
 318  */
 319
 320 /*
 321  * Save the state of the KVM timer when VM clock is stopped or state is synced
 322  * to QEMU.
 323  */
 324 static int kvm_mips_save_count(CPUState *cs)
 325 {
 326     MIPSCPU *cpu = MIPS_CPU(cs);
 327     CPUMIPSState *env = &cpu->env;
 328     uint64_t count_ctl;
 329     int err, ret = 0;
 330
 331     /* freeze KVM timer */
 332     err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 333     if (err < 0) {
 334         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
 335         ret = err;
 336     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 337         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 338         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 339         if (err < 0) {
 340             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 341             ret = err;
 342         }
 343     }
 344
 345     /* read CP0_Cause */
 346     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 347     if (err < 0) {
 348         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
 349         ret = err;
 350     }
 351
 352     /* read CP0_Count */
 353     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 354     if (err < 0) {
 355         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
 356         ret = err;
 357     }
 358
 359     return ret;
 360 }
 361
 362 /*
 363  * Restore the state of the KVM timer when VM clock is restarted or state is
 364  * synced to KVM.
 365  */
 366 static int kvm_mips_restore_count(CPUState *cs)
 367 {
 368     MIPSCPU *cpu = MIPS_CPU(cs);
 369     CPUMIPSState *env = &cpu->env;
 370     uint64_t count_ctl;
 371     int err_dc, err, ret = 0;
 372
 373     /* check the timer is frozen */
 374     err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 375     if (err_dc < 0) {
 376         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
 377         ret = err_dc;
 378     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 379         /* freeze timer (sets COUNT_RESUME for us) */
 380         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 381         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 382         if (err < 0) {
 383             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 384             ret = err;
 385         }
 386     }
 387
 388     /* load CP0_Cause */
 389     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 390     if (err < 0) {
 391         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
 392         ret = err;
 393     }
 394
 395     /* load CP0_Count */
 396     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 397     if (err < 0) {
 398         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
 399         ret = err;
 400     }
 401
 402     /* resume KVM timer */
 403     if (err_dc >= 0) {
 404         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
 405         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 406         if (err < 0) {
 407             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
 408             ret = err;
 409         }
 410     }
 411
 412     return ret;
 413 }
 414
 415 /*
 416  * Handle the VM clock being started or stopped
 417  */
 418 static void kvm_mips_update_state(void *opaque, int running, RunState state)
 419 {
 420     CPUState *cs = opaque;
 421     int ret;
 422     uint64_t count_resume;
 423
 424     /*
 425      * If state is already dirty (synced to QEMU) then the KVM timer state is
 426      * already saved and can be restored when it is synced back to KVM.
 427      */
 428     if (!running) {
 429         if (!cs->kvm_vcpu_dirty) {
 430             ret = kvm_mips_save_count(cs);
 431             if (ret < 0) {
 432                 fprintf(stderr, "Failed saving count\n");
 433             }
 434         }
 435     } else {
 436         /* Set clock restore time to now */
 437         count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
 438         ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
 439                                      &count_resume);
 440         if (ret < 0) {
 441             fprintf(stderr, "Failed setting COUNT_RESUME\n");
 442             return;
 443         }
 444
 445         if (!cs->kvm_vcpu_dirty) {
 446             ret = kvm_mips_restore_count(cs);
 447             if (ret < 0) {
 448                 fprintf(stderr, "Failed restoring count\n");
 449             }
 450         }
 451     }
 452 }
 453
 454 static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
 455 {
 456     MIPSCPU *cpu = MIPS_CPU(cs);
 457     CPUMIPSState *env = &cpu->env;
 458     int err, ret = 0;
 459
 460     (void)level;
 461
 462     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 463     if (err < 0) {
 464         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 465         ret = err;
 466     }
 467     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 468                                  &env->CP0_Context);
 469     if (err < 0) {
 470         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
 471         ret = err;
 472     }
 473     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 474                                  &env->active_tc.CP0_UserLocal);
 475     if (err < 0) {
 476         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
 477         ret = err;
 478     }
 479     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 480                                &env->CP0_PageMask);
 481     if (err < 0) {
 482         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
 483         ret = err;
 484     }
 485     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 486     if (err < 0) {
 487         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
 488         ret = err;
 489     }
 490     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 491     if (err < 0) {
 492         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
 493         ret = err;
 494     }
 495     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 496                                  &env->CP0_BadVAddr);
 497     if (err < 0) {
 498         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
 499         ret = err;
 500     }
 501
 502     /* If VM clock stopped then state will be restored when it is restarted */
 503     if (runstate_is_running()) {
 504         err = kvm_mips_restore_count(cs);
 505         if (err < 0) {
 506             ret = err;
 507         }
 508     }
 509
 510     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 511                                  &env->CP0_EntryHi);
 512     if (err < 0) {
 513         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
 514         ret = err;
 515     }
 516     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 517                                &env->CP0_Compare);
 518     if (err < 0) {
 519         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
 520         ret = err;
 521     }
 522     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 523     if (err < 0) {
 524         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
 525         ret = err;
 526     }
 527     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 528     if (err < 0) {
 529         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
 530         ret = err;
 531     }
 532     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 533                                  &env->CP0_ErrorEPC);
 534     if (err < 0) {
 535         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
 536         ret = err;
 537     }
 538
 539     return ret;
 540 }
 541
 542 static int kvm_mips_get_cp0_registers(CPUState *cs)
 543 {
 544     MIPSCPU *cpu = MIPS_CPU(cs);
 545     CPUMIPSState *env = &cpu->env;
 546     int err, ret = 0;
 547
 548     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 549     if (err < 0) {
 550         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
 551         ret = err;
 552     }
 553     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 554                                  &env->CP0_Context);
 555     if (err < 0) {
 556         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
 557         ret = err;
 558     }
 559     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 560                                  &env->active_tc.CP0_UserLocal);
 561     if (err < 0) {
 562         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
 563         ret = err;
 564     }
 565     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 566                                &env->CP0_PageMask);
 567     if (err < 0) {
 568         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
 569         ret = err;
 570     }
 571     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 572     if (err < 0) {
 573         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
 574         ret = err;
 575     }
 576     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 577     if (err < 0) {
 578         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
 579         ret = err;
 580     }
 581     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 582                                  &env->CP0_BadVAddr);
 583     if (err < 0) {
 584         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
 585         ret = err;
 586     }
 587     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 588                                  &env->CP0_EntryHi);
 589     if (err < 0) {
 590         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
 591         ret = err;
 592     }
 593     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 594                                &env->CP0_Compare);
 595     if (err < 0) {
 596         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
 597         ret = err;
 598     }
 599     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 600     if (err < 0) {
 601         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
 602         ret = err;
 603     }
 604
 605     /* If VM clock stopped then state was already saved when it was stopped */
 606     if (runstate_is_running()) {
 607         err = kvm_mips_save_count(cs);
 608         if (err < 0) {
 609             ret = err;
 610         }
 611     }
 612
 613     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 614     if (err < 0) {
 615         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
 616         ret = err;
 617     }
 618     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 619                                  &env->CP0_ErrorEPC);
 620     if (err < 0) {
 621         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
 622         ret = err;
 623     }
 624
 625     return ret;
 626 }
 627
 628 int kvm_arch_put_registers(CPUState *cs, int level)
 629 {
 630     MIPSCPU *cpu = MIPS_CPU(cs);
 631     CPUMIPSState *env = &cpu->env;
 632     struct kvm_regs regs;
 633     int ret;
 634     int i;
 635
 636     /* Set the registers based on QEMU's view of things */
 637     for (i = 0; i < 32; i++) {
 638         regs.gpr[i] = env->active_tc.gpr[i];
 639     }
 640
 641     regs.hi = env->active_tc.HI[0];
 642     regs.lo = env->active_tc.LO[0];
 643     regs.pc = env->active_tc.PC;
 644
 645     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
 646
 647     if (ret < 0) {
 648         return ret;
 649     }
 650
 651     ret = kvm_mips_put_cp0_registers(cs, level);
 652     if (ret < 0) {
 653         return ret;
 654     }
 655
 656     return ret;
 657 }
 658
 659 int kvm_arch_get_registers(CPUState *cs)
 660 {
 661     MIPSCPU *cpu = MIPS_CPU(cs);
 662     CPUMIPSState *env = &cpu->env;
 663     int ret = 0;
 664     struct kvm_regs regs;
 665     int i;
 666
 667     /* Get the current register set as KVM seems it */
 668     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
 669
 670     if (ret < 0) {
 671         return ret;
 672     }
 673
 674     for (i = 0; i < 32; i++) {
 675         env->active_tc.gpr[i] = regs.gpr[i];
 676     }
 677
 678     env->active_tc.HI[0] = regs.hi;
 679     env->active_tc.LO[0] = regs.lo;
 680     env->active_tc.PC = regs.pc;
 681
 682     kvm_mips_get_cp0_registers(cs);
 683
 684     return ret;
 685 }
 686
 687 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 688                              uint64_t address, uint32_t data)
 689 {
 690     return 0;
 691 }
 692
 693 int kvm_arch_msi_data_to_gsi(uint32_t data)
 694 {
 695     abort();
 696 }