4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci.h"
29 #include "qemu/error-report.h"
30 #include "sysemu/block-backend.h"
31 #include "sysemu/dma.h"
32 #include "hw/ide/internal.h"
33 #include "hw/ide/pci.h"
34 #include "hw/ide/ahci_internal.h"
38 static void check_cmd(AHCIState
*s
, int port
);
39 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
);
40 static void ahci_reset_port(AHCIState
*s
, int port
);
41 static bool ahci_write_fis_d2h(AHCIDevice
*ad
);
42 static void ahci_init_d2h(AHCIDevice
*ad
);
43 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
);
44 static bool ahci_map_clb_address(AHCIDevice
*ad
);
45 static bool ahci_map_fis_address(AHCIDevice
*ad
);
46 static void ahci_unmap_clb_address(AHCIDevice
*ad
);
47 static void ahci_unmap_fis_address(AHCIDevice
*ad
);
49 static const char *AHCIPortIRQ_lookup
[AHCI_PORT_IRQ__COUNT
] = {
50 [AHCI_PORT_IRQ_BIT_DHRS
] = "DHRS",
51 [AHCI_PORT_IRQ_BIT_PSS
] = "PSS",
52 [AHCI_PORT_IRQ_BIT_DSS
] = "DSS",
53 [AHCI_PORT_IRQ_BIT_SDBS
] = "SDBS",
54 [AHCI_PORT_IRQ_BIT_UFS
] = "UFS",
55 [AHCI_PORT_IRQ_BIT_DPS
] = "DPS",
56 [AHCI_PORT_IRQ_BIT_PCS
] = "PCS",
57 [AHCI_PORT_IRQ_BIT_DMPS
] = "DMPS",
58 [8 ... 21] = "RESERVED",
59 [AHCI_PORT_IRQ_BIT_PRCS
] = "PRCS",
60 [AHCI_PORT_IRQ_BIT_IPMS
] = "IPMS",
61 [AHCI_PORT_IRQ_BIT_OFS
] = "OFS",
63 [AHCI_PORT_IRQ_BIT_INFS
] = "INFS",
64 [AHCI_PORT_IRQ_BIT_IFS
] = "IFS",
65 [AHCI_PORT_IRQ_BIT_HBDS
] = "HBDS",
66 [AHCI_PORT_IRQ_BIT_HBFS
] = "HBFS",
67 [AHCI_PORT_IRQ_BIT_TFES
] = "TFES",
68 [AHCI_PORT_IRQ_BIT_CPDS
] = "CPDS"
71 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
75 pr
= &s
->dev
[port
].port_regs
;
81 case PORT_LST_ADDR_HI
:
82 val
= pr
->lst_addr_hi
;
87 case PORT_FIS_ADDR_HI
:
88 val
= pr
->fis_addr_hi
;
106 if (s
->dev
[port
].port
.ifs
[0].blk
) {
107 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
108 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
110 val
= SATA_SCR_SSTATUS_DET_NODEV
;
130 trace_ahci_port_read(s
, port
, offset
, val
);
134 static void ahci_irq_raise(AHCIState
*s
, AHCIDevice
*dev
)
136 DeviceState
*dev_state
= s
->container
;
137 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
140 trace_ahci_irq_raise(s
);
142 if (pci_dev
&& msi_enabled(pci_dev
)) {
143 msi_notify(pci_dev
, 0);
145 qemu_irq_raise(s
->irq
);
149 static void ahci_irq_lower(AHCIState
*s
, AHCIDevice
*dev
)
151 DeviceState
*dev_state
= s
->container
;
152 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
155 trace_ahci_irq_lower(s
);
157 if (!pci_dev
|| !msi_enabled(pci_dev
)) {
158 qemu_irq_lower(s
->irq
);
162 static void ahci_check_irq(AHCIState
*s
)
165 uint32_t old_irq
= s
->control_regs
.irqstatus
;
167 s
->control_regs
.irqstatus
= 0;
168 for (i
= 0; i
< s
->ports
; i
++) {
169 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
170 if (pr
->irq_stat
& pr
->irq_mask
) {
171 s
->control_regs
.irqstatus
|= (1 << i
);
174 trace_ahci_check_irq(s
, old_irq
, s
->control_regs
.irqstatus
);
175 if (s
->control_regs
.irqstatus
&&
176 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
177 ahci_irq_raise(s
, NULL
);
179 ahci_irq_lower(s
, NULL
);
183 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
184 enum AHCIPortIRQ irqbit
)
186 g_assert((unsigned)irqbit
< 32);
187 uint32_t irq
= 1U << irqbit
;
188 uint32_t irqstat
= d
->port_regs
.irq_stat
| irq
;
190 trace_ahci_trigger_irq(s
, d
->port_no
,
191 AHCIPortIRQ_lookup
[irqbit
], irq
,
192 d
->port_regs
.irq_stat
, irqstat
,
193 irqstat
& d
->port_regs
.irq_mask
);
195 d
->port_regs
.irq_stat
= irqstat
;
199 static void map_page(AddressSpace
*as
, uint8_t **ptr
, uint64_t addr
,
205 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
208 *ptr
= dma_memory_map(as
, addr
, &len
, DMA_DIRECTION_FROM_DEVICE
);
210 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
216 * Check the cmd register to see if we should start or stop
217 * the DMA or FIS RX engines.
219 * @ad: Device to dis/engage.
221 * @return 0 on success, -1 on error.
223 static int ahci_cond_start_engines(AHCIDevice
*ad
)
225 AHCIPortRegs
*pr
= &ad
->port_regs
;
226 bool cmd_start
= pr
->cmd
& PORT_CMD_START
;
227 bool cmd_on
= pr
->cmd
& PORT_CMD_LIST_ON
;
228 bool fis_start
= pr
->cmd
& PORT_CMD_FIS_RX
;
229 bool fis_on
= pr
->cmd
& PORT_CMD_FIS_ON
;
231 if (cmd_start
&& !cmd_on
) {
232 if (!ahci_map_clb_address(ad
)) {
233 pr
->cmd
&= ~PORT_CMD_START
;
234 error_report("AHCI: Failed to start DMA engine: "
235 "bad command list buffer address");
238 } else if (!cmd_start
&& cmd_on
) {
239 ahci_unmap_clb_address(ad
);
242 if (fis_start
&& !fis_on
) {
243 if (!ahci_map_fis_address(ad
)) {
244 pr
->cmd
&= ~PORT_CMD_FIS_RX
;
245 error_report("AHCI: Failed to start FIS receive engine: "
246 "bad FIS receive buffer address");
249 } else if (!fis_start
&& fis_on
) {
250 ahci_unmap_fis_address(ad
);
256 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
258 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
260 trace_ahci_port_write(s
, port
, offset
, val
);
265 case PORT_LST_ADDR_HI
:
266 pr
->lst_addr_hi
= val
;
271 case PORT_FIS_ADDR_HI
:
272 pr
->fis_addr_hi
= val
;
275 pr
->irq_stat
&= ~val
;
279 pr
->irq_mask
= val
& 0xfdc000ff;
283 /* Block any Read-only fields from being set;
284 * including LIST_ON and FIS_ON.
285 * The spec requires to set ICC bits to zero after the ICC change
286 * is done. We don't support ICC state changes, therefore always
287 * force the ICC bits to zero.
289 pr
->cmd
= (pr
->cmd
& PORT_CMD_RO_MASK
) |
290 (val
& ~(PORT_CMD_RO_MASK
|PORT_CMD_ICC_MASK
));
292 /* Check FIS RX and CLB engines */
293 ahci_cond_start_engines(&s
->dev
[port
]);
295 /* XXX usually the FIS would be pending on the bus here and
296 issuing deferred until the OS enables FIS receival.
297 Instead, we only submit it once - which works in most
298 cases, but is a hack. */
299 if ((pr
->cmd
& PORT_CMD_FIS_ON
) &&
300 !s
->dev
[port
].init_d2h_sent
) {
301 ahci_init_d2h(&s
->dev
[port
]);
316 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
317 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
318 ahci_reset_port(s
, port
);
330 pr
->cmd_issue
|= val
;
338 static uint64_t ahci_mem_read_32(void *opaque
, hwaddr addr
)
340 AHCIState
*s
= opaque
;
343 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
346 val
= s
->control_regs
.cap
;
349 val
= s
->control_regs
.ghc
;
352 val
= s
->control_regs
.irqstatus
;
354 case HOST_PORTS_IMPL
:
355 val
= s
->control_regs
.impl
;
358 val
= s
->control_regs
.version
;
361 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
362 (addr
< (AHCI_PORT_REGS_START_ADDR
+
363 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
364 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
365 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
368 trace_ahci_mem_read_32(s
, addr
, val
);
374 * AHCI 1.3 section 3 ("HBA Memory Registers")
375 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
376 * Caller is responsible for masking unwanted higher order bytes.
378 static uint64_t ahci_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
380 hwaddr aligned
= addr
& ~0x3;
381 int ofst
= addr
- aligned
;
382 uint64_t lo
= ahci_mem_read_32(opaque
, aligned
);
386 /* if < 8 byte read does not cross 4 byte boundary */
387 if (ofst
+ size
<= 4) {
388 val
= lo
>> (ofst
* 8);
390 g_assert_cmpint(size
, >, 1);
392 /* If the 64bit read is unaligned, we will produce undefined
393 * results. AHCI does not support unaligned 64bit reads. */
394 hi
= ahci_mem_read_32(opaque
, aligned
+ 4);
395 val
= (hi
<< 32 | lo
) >> (ofst
* 8);
398 trace_ahci_mem_read(opaque
, size
, addr
, val
);
403 static void ahci_mem_write(void *opaque
, hwaddr addr
,
404 uint64_t val
, unsigned size
)
406 AHCIState
*s
= opaque
;
408 trace_ahci_mem_write(s
, size
, addr
, val
);
410 /* Only aligned reads are allowed on AHCI */
412 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
413 TARGET_FMT_plx
"\n", addr
);
417 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
419 case HOST_CAP
: /* R/WO, RO */
420 /* FIXME handle R/WO */
422 case HOST_CTL
: /* R/W */
423 if (val
& HOST_CTL_RESET
) {
426 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
430 case HOST_IRQ_STAT
: /* R/WC, RO */
431 s
->control_regs
.irqstatus
&= ~val
;
434 case HOST_PORTS_IMPL
: /* R/WO, RO */
435 /* FIXME handle R/WO */
437 case HOST_VERSION
: /* RO */
438 /* FIXME report write? */
441 trace_ahci_mem_write_unknown(s
, size
, addr
, val
);
443 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
444 (addr
< (AHCI_PORT_REGS_START_ADDR
+
445 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
446 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
447 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
452 static const MemoryRegionOps ahci_mem_ops
= {
453 .read
= ahci_mem_read
,
454 .write
= ahci_mem_write
,
455 .endianness
= DEVICE_LITTLE_ENDIAN
,
458 static uint64_t ahci_idp_read(void *opaque
, hwaddr addr
,
461 AHCIState
*s
= opaque
;
463 if (addr
== s
->idp_offset
) {
466 } else if (addr
== s
->idp_offset
+ 4) {
467 /* data register - do memory read at location selected by index */
468 return ahci_mem_read(opaque
, s
->idp_index
, size
);
474 static void ahci_idp_write(void *opaque
, hwaddr addr
,
475 uint64_t val
, unsigned size
)
477 AHCIState
*s
= opaque
;
479 if (addr
== s
->idp_offset
) {
480 /* index register - mask off reserved bits */
481 s
->idp_index
= (uint32_t)val
& ((AHCI_MEM_BAR_SIZE
- 1) & ~3);
482 } else if (addr
== s
->idp_offset
+ 4) {
483 /* data register - do memory write at location selected by index */
484 ahci_mem_write(opaque
, s
->idp_index
, val
, size
);
488 static const MemoryRegionOps ahci_idp_ops
= {
489 .read
= ahci_idp_read
,
490 .write
= ahci_idp_write
,
491 .endianness
= DEVICE_LITTLE_ENDIAN
,
495 static void ahci_reg_init(AHCIState
*s
)
499 s
->control_regs
.cap
= (s
->ports
- 1) |
500 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
501 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
502 HOST_CAP_NCQ
| HOST_CAP_AHCI
| HOST_CAP_64
;
504 s
->control_regs
.impl
= (1 << s
->ports
) - 1;
506 s
->control_regs
.version
= AHCI_VERSION_1_0
;
508 for (i
= 0; i
< s
->ports
; i
++) {
509 s
->dev
[i
].port_state
= STATE_RUN
;
513 static void check_cmd(AHCIState
*s
, int port
)
515 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
518 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
519 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
520 if ((pr
->cmd_issue
& (1U << slot
)) &&
521 !handle_cmd(s
, port
, slot
)) {
522 pr
->cmd_issue
&= ~(1U << slot
);
528 static void ahci_check_cmd_bh(void *opaque
)
530 AHCIDevice
*ad
= opaque
;
532 qemu_bh_delete(ad
->check_bh
);
535 if ((ad
->busy_slot
!= -1) &&
536 !(ad
->port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
))) {
538 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
542 check_cmd(ad
->hba
, ad
->port_no
);
545 static void ahci_init_d2h(AHCIDevice
*ad
)
547 IDEState
*ide_state
= &ad
->port
.ifs
[0];
548 AHCIPortRegs
*pr
= &ad
->port_regs
;
550 if (ad
->init_d2h_sent
) {
554 if (ahci_write_fis_d2h(ad
)) {
555 ad
->init_d2h_sent
= true;
556 /* We're emulating receiving the first Reg H2D Fis from the device;
557 * Update the SIG register, but otherwise proceed as normal. */
558 pr
->sig
= ((uint32_t)ide_state
->hcyl
<< 24) |
559 (ide_state
->lcyl
<< 16) |
560 (ide_state
->sector
<< 8) |
561 (ide_state
->nsector
& 0xFF);
565 static void ahci_set_signature(AHCIDevice
*ad
, uint32_t sig
)
567 IDEState
*s
= &ad
->port
.ifs
[0];
568 s
->hcyl
= sig
>> 24 & 0xFF;
569 s
->lcyl
= sig
>> 16 & 0xFF;
570 s
->sector
= sig
>> 8 & 0xFF;
571 s
->nsector
= sig
& 0xFF;
573 trace_ahci_set_signature(ad
->hba
, ad
->port_no
, s
->nsector
, s
->sector
,
574 s
->lcyl
, s
->hcyl
, sig
);
577 static void ahci_reset_port(AHCIState
*s
, int port
)
579 AHCIDevice
*d
= &s
->dev
[port
];
580 AHCIPortRegs
*pr
= &d
->port_regs
;
581 IDEState
*ide_state
= &d
->port
.ifs
[0];
584 trace_ahci_reset_port(s
, port
);
586 ide_bus_reset(&d
->port
);
587 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
593 pr
->sig
= 0xFFFFFFFF;
595 d
->init_d2h_sent
= false;
597 ide_state
= &s
->dev
[port
].port
.ifs
[0];
598 if (!ide_state
->blk
) {
602 /* reset ncq queue */
603 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
604 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
605 ncq_tfs
->halt
= false;
606 if (!ncq_tfs
->used
) {
610 if (ncq_tfs
->aiocb
) {
611 blk_aio_cancel(ncq_tfs
->aiocb
);
612 ncq_tfs
->aiocb
= NULL
;
615 /* Maybe we just finished the request thanks to blk_aio_cancel() */
616 if (!ncq_tfs
->used
) {
620 qemu_sglist_destroy(&ncq_tfs
->sglist
);
624 s
->dev
[port
].port_state
= STATE_RUN
;
625 if (ide_state
->drive_kind
== IDE_CD
) {
626 ahci_set_signature(d
, SATA_SIGNATURE_CDROM
);\
627 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
629 ahci_set_signature(d
, SATA_SIGNATURE_DISK
);
630 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
633 ide_state
->error
= 1;
637 /* Buffer pretty output based on a raw FIS structure. */
638 static char *ahci_pretty_buffer_fis(uint8_t *fis
, int cmd_len
)
641 GString
*s
= g_string_new("FIS:");
643 for (i
= 0; i
< cmd_len
; i
++) {
644 if ((i
& 0xf) == 0) {
645 g_string_append_printf(s
, "\n0x%02x: ", i
);
647 g_string_append_printf(s
, "%02x ", fis
[i
]);
649 g_string_append_c(s
, '\n');
651 return g_string_free(s
, FALSE
);
654 static bool ahci_map_fis_address(AHCIDevice
*ad
)
656 AHCIPortRegs
*pr
= &ad
->port_regs
;
657 map_page(ad
->hba
->as
, &ad
->res_fis
,
658 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
659 if (ad
->res_fis
!= NULL
) {
660 pr
->cmd
|= PORT_CMD_FIS_ON
;
664 pr
->cmd
&= ~PORT_CMD_FIS_ON
;
668 static void ahci_unmap_fis_address(AHCIDevice
*ad
)
670 if (ad
->res_fis
== NULL
) {
671 trace_ahci_unmap_fis_address_null(ad
->hba
, ad
->port_no
);
674 ad
->port_regs
.cmd
&= ~PORT_CMD_FIS_ON
;
675 dma_memory_unmap(ad
->hba
->as
, ad
->res_fis
, 256,
676 DMA_DIRECTION_FROM_DEVICE
, 256);
680 static bool ahci_map_clb_address(AHCIDevice
*ad
)
682 AHCIPortRegs
*pr
= &ad
->port_regs
;
684 map_page(ad
->hba
->as
, &ad
->lst
,
685 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
686 if (ad
->lst
!= NULL
) {
687 pr
->cmd
|= PORT_CMD_LIST_ON
;
691 pr
->cmd
&= ~PORT_CMD_LIST_ON
;
695 static void ahci_unmap_clb_address(AHCIDevice
*ad
)
697 if (ad
->lst
== NULL
) {
698 trace_ahci_unmap_clb_address_null(ad
->hba
, ad
->port_no
);
701 ad
->port_regs
.cmd
&= ~PORT_CMD_LIST_ON
;
702 dma_memory_unmap(ad
->hba
->as
, ad
->lst
, 1024,
703 DMA_DIRECTION_FROM_DEVICE
, 1024);
707 static void ahci_write_fis_sdb(AHCIState
*s
, NCQTransferState
*ncq_tfs
)
709 AHCIDevice
*ad
= ncq_tfs
->drive
;
710 AHCIPortRegs
*pr
= &ad
->port_regs
;
715 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
719 sdb_fis
= (SDBFIS
*)&ad
->res_fis
[RES_FIS_SDBFIS
];
720 ide_state
= &ad
->port
.ifs
[0];
722 sdb_fis
->type
= SATA_FIS_TYPE_SDB
;
723 /* Interrupt pending & Notification bit */
724 sdb_fis
->flags
= 0x40; /* Interrupt bit, always 1 for NCQ */
725 sdb_fis
->status
= ide_state
->status
& 0x77;
726 sdb_fis
->error
= ide_state
->error
;
727 /* update SAct field in SDB_FIS */
728 sdb_fis
->payload
= cpu_to_le32(ad
->finished
);
730 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
731 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
732 (ad
->port
.ifs
[0].status
& 0x77) |
734 pr
->scr_act
&= ~ad
->finished
;
737 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
738 if (sdb_fis
->flags
& 0x40) {
739 ahci_trigger_irq(s
, ad
, AHCI_PORT_IRQ_BIT_SDBS
);
743 static void ahci_write_fis_pio(AHCIDevice
*ad
, uint16_t len
)
745 AHCIPortRegs
*pr
= &ad
->port_regs
;
747 IDEState
*s
= &ad
->port
.ifs
[0];
749 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
753 pio_fis
= &ad
->res_fis
[RES_FIS_PSFIS
];
755 pio_fis
[0] = SATA_FIS_TYPE_PIO_SETUP
;
756 pio_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
757 pio_fis
[2] = s
->status
;
758 pio_fis
[3] = s
->error
;
760 pio_fis
[4] = s
->sector
;
761 pio_fis
[5] = s
->lcyl
;
762 pio_fis
[6] = s
->hcyl
;
763 pio_fis
[7] = s
->select
;
764 pio_fis
[8] = s
->hob_sector
;
765 pio_fis
[9] = s
->hob_lcyl
;
766 pio_fis
[10] = s
->hob_hcyl
;
768 pio_fis
[12] = s
->nsector
& 0xFF;
769 pio_fis
[13] = (s
->nsector
>> 8) & 0xFF;
771 pio_fis
[15] = s
->status
;
772 pio_fis
[16] = len
& 255;
773 pio_fis
[17] = len
>> 8;
777 /* Update shadow registers: */
778 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
779 ad
->port
.ifs
[0].status
;
781 if (pio_fis
[2] & ERR_STAT
) {
782 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_TFES
);
785 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_PSS
);
788 static bool ahci_write_fis_d2h(AHCIDevice
*ad
)
790 AHCIPortRegs
*pr
= &ad
->port_regs
;
793 IDEState
*s
= &ad
->port
.ifs
[0];
795 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
799 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
801 d2h_fis
[0] = SATA_FIS_TYPE_REGISTER_D2H
;
802 d2h_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
803 d2h_fis
[2] = s
->status
;
804 d2h_fis
[3] = s
->error
;
806 d2h_fis
[4] = s
->sector
;
807 d2h_fis
[5] = s
->lcyl
;
808 d2h_fis
[6] = s
->hcyl
;
809 d2h_fis
[7] = s
->select
;
810 d2h_fis
[8] = s
->hob_sector
;
811 d2h_fis
[9] = s
->hob_lcyl
;
812 d2h_fis
[10] = s
->hob_hcyl
;
814 d2h_fis
[12] = s
->nsector
& 0xFF;
815 d2h_fis
[13] = (s
->nsector
>> 8) & 0xFF;
816 for (i
= 14; i
< 20; i
++) {
820 /* Update shadow registers: */
821 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
822 ad
->port
.ifs
[0].status
;
824 if (d2h_fis
[2] & ERR_STAT
) {
825 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_TFES
);
828 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_DHRS
);
832 static int prdt_tbl_entry_size(const AHCI_SG
*tbl
)
834 /* flags_size is zero-based */
835 return (le32_to_cpu(tbl
->flags_size
) & AHCI_PRDT_SIZE_MASK
) + 1;
839 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
840 * @ad: The AHCIDevice for whom we are building the SGList.
841 * @sglist: The SGList target to add PRD entries to.
842 * @cmd: The AHCI Command Header that describes where the PRDT is.
843 * @limit: The remaining size of the S/ATA transaction, in bytes.
844 * @offset: The number of bytes already transferred, in bytes.
846 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
847 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
848 * building the sglist from the PRDT as soon as we hit @limit bytes,
849 * which is <= INT32_MAX/2GiB.
851 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
,
852 AHCICmdHdr
*cmd
, int64_t limit
, uint64_t offset
)
854 uint16_t opts
= le16_to_cpu(cmd
->opts
);
855 uint16_t prdtl
= le16_to_cpu(cmd
->prdtl
);
856 uint64_t cfis_addr
= le64_to_cpu(cmd
->tbl_addr
);
857 uint64_t prdt_addr
= cfis_addr
+ 0x80;
858 dma_addr_t prdt_len
= (prdtl
* sizeof(AHCI_SG
));
859 dma_addr_t real_prdt_len
= prdt_len
;
865 int64_t off_pos
= -1;
867 IDEBus
*bus
= &ad
->port
;
868 BusState
*qbus
= BUS(bus
);
870 trace_ahci_populate_sglist(ad
->hba
, ad
->port_no
);
873 trace_ahci_populate_sglist_no_prdtl(ad
->hba
, ad
->port_no
, opts
);
878 if (!(prdt
= dma_memory_map(ad
->hba
->as
, prdt_addr
, &prdt_len
,
879 DMA_DIRECTION_TO_DEVICE
))){
880 trace_ahci_populate_sglist_no_map(ad
->hba
, ad
->port_no
);
884 if (prdt_len
< real_prdt_len
) {
885 trace_ahci_populate_sglist_short_map(ad
->hba
, ad
->port_no
);
890 /* Get entries in the PRDT, init a qemu sglist accordingly */
892 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
894 for (i
= 0; i
< prdtl
; i
++) {
895 tbl_entry_size
= prdt_tbl_entry_size(&tbl
[i
]);
896 if (offset
< (sum
+ tbl_entry_size
)) {
898 off_pos
= offset
- sum
;
901 sum
+= tbl_entry_size
;
903 if ((off_idx
== -1) || (off_pos
< 0) || (off_pos
> tbl_entry_size
)) {
904 trace_ahci_populate_sglist_bad_offset(ad
->hba
, ad
->port_no
,
910 qemu_sglist_init(sglist
, qbus
->parent
, (prdtl
- off_idx
),
912 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[off_idx
].addr
) + off_pos
,
913 MIN(prdt_tbl_entry_size(&tbl
[off_idx
]) - off_pos
,
916 for (i
= off_idx
+ 1; i
< prdtl
&& sglist
->size
< limit
; i
++) {
917 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
918 MIN(prdt_tbl_entry_size(&tbl
[i
]),
919 limit
- sglist
->size
));
924 dma_memory_unmap(ad
->hba
->as
, prdt
, prdt_len
,
925 DMA_DIRECTION_TO_DEVICE
, prdt_len
);
929 static void ncq_err(NCQTransferState
*ncq_tfs
)
931 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
933 ide_state
->error
= ABRT_ERR
;
934 ide_state
->status
= READY_STAT
| ERR_STAT
;
935 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
936 qemu_sglist_destroy(&ncq_tfs
->sglist
);
940 static void ncq_finish(NCQTransferState
*ncq_tfs
)
942 /* If we didn't error out, set our finished bit. Errored commands
943 * do not get a bit set for the SDB FIS ACT register, nor do they
944 * clear the outstanding bit in scr_act (PxSACT). */
945 if (!(ncq_tfs
->drive
->port_regs
.scr_err
& (1 << ncq_tfs
->tag
))) {
946 ncq_tfs
->drive
->finished
|= (1 << ncq_tfs
->tag
);
949 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
);
951 trace_ncq_finish(ncq_tfs
->drive
->hba
, ncq_tfs
->drive
->port_no
,
954 block_acct_done(blk_get_stats(ncq_tfs
->drive
->port
.ifs
[0].blk
),
956 qemu_sglist_destroy(&ncq_tfs
->sglist
);
960 static void ncq_cb(void *opaque
, int ret
)
962 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
963 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
965 ncq_tfs
->aiocb
= NULL
;
966 if (ret
== -ECANCELED
) {
971 bool is_read
= ncq_tfs
->cmd
== READ_FPDMA_QUEUED
;
972 BlockErrorAction action
= blk_get_error_action(ide_state
->blk
,
974 if (action
== BLOCK_ERROR_ACTION_STOP
) {
975 ncq_tfs
->halt
= true;
976 ide_state
->bus
->error_status
= IDE_RETRY_HBA
;
977 } else if (action
== BLOCK_ERROR_ACTION_REPORT
) {
980 blk_error_action(ide_state
->blk
, action
, is_read
, -ret
);
982 ide_state
->status
= READY_STAT
| SEEK_STAT
;
985 if (!ncq_tfs
->halt
) {
990 static int is_ncq(uint8_t ata_cmd
)
992 /* Based on SATA 3.2 section 13.6.3.2 */
994 case READ_FPDMA_QUEUED
:
995 case WRITE_FPDMA_QUEUED
:
997 case RECEIVE_FPDMA_QUEUED
:
998 case SEND_FPDMA_QUEUED
:
1005 static void execute_ncq_command(NCQTransferState
*ncq_tfs
)
1007 AHCIDevice
*ad
= ncq_tfs
->drive
;
1008 IDEState
*ide_state
= &ad
->port
.ifs
[0];
1009 int port
= ad
->port_no
;
1011 g_assert(is_ncq(ncq_tfs
->cmd
));
1012 ncq_tfs
->halt
= false;
1014 switch (ncq_tfs
->cmd
) {
1015 case READ_FPDMA_QUEUED
:
1016 trace_execute_ncq_command_read(ad
->hba
, port
, ncq_tfs
->tag
,
1017 ncq_tfs
->sector_count
, ncq_tfs
->lba
);
1018 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1019 &ncq_tfs
->sglist
, BLOCK_ACCT_READ
);
1020 ncq_tfs
->aiocb
= dma_blk_read(ide_state
->blk
, &ncq_tfs
->sglist
,
1021 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1025 case WRITE_FPDMA_QUEUED
:
1026 trace_execute_ncq_command_read(ad
->hba
, port
, ncq_tfs
->tag
,
1027 ncq_tfs
->sector_count
, ncq_tfs
->lba
);
1028 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1029 &ncq_tfs
->sglist
, BLOCK_ACCT_WRITE
);
1030 ncq_tfs
->aiocb
= dma_blk_write(ide_state
->blk
, &ncq_tfs
->sglist
,
1031 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1036 trace_execute_ncq_command_unsup(ad
->hba
, port
,
1037 ncq_tfs
->tag
, ncq_tfs
->cmd
);
1043 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
1046 AHCIDevice
*ad
= &s
->dev
[port
];
1047 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
1048 uint8_t tag
= ncq_fis
->tag
>> 3;
1049 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[tag
];
1052 g_assert(is_ncq(ncq_fis
->command
));
1053 if (ncq_tfs
->used
) {
1054 /* error - already in use */
1055 fprintf(stderr
, "%s: tag %d already used\n", __func__
, tag
);
1060 ncq_tfs
->drive
= ad
;
1061 ncq_tfs
->slot
= slot
;
1062 ncq_tfs
->cmdh
= &((AHCICmdHdr
*)ad
->lst
)[slot
];
1063 ncq_tfs
->cmd
= ncq_fis
->command
;
1064 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
1065 ((uint64_t)ncq_fis
->lba4
<< 32) |
1066 ((uint64_t)ncq_fis
->lba3
<< 24) |
1067 ((uint64_t)ncq_fis
->lba2
<< 16) |
1068 ((uint64_t)ncq_fis
->lba1
<< 8) |
1069 (uint64_t)ncq_fis
->lba0
;
1072 /* Sanity-check the NCQ packet */
1074 trace_process_ncq_command_mismatch(s
, port
, tag
, slot
);
1077 if (ncq_fis
->aux0
|| ncq_fis
->aux1
|| ncq_fis
->aux2
|| ncq_fis
->aux3
) {
1078 trace_process_ncq_command_aux(s
, port
, tag
);
1080 if (ncq_fis
->prio
|| ncq_fis
->icc
) {
1081 trace_process_ncq_command_prioicc(s
, port
, tag
);
1083 if (ncq_fis
->fua
& NCQ_FIS_FUA_MASK
) {
1084 trace_process_ncq_command_fua(s
, port
, tag
);
1086 if (ncq_fis
->tag
& NCQ_FIS_RARC_MASK
) {
1087 trace_process_ncq_command_rarc(s
, port
, tag
);
1090 ncq_tfs
->sector_count
= ((ncq_fis
->sector_count_high
<< 8) |
1091 ncq_fis
->sector_count_low
);
1092 if (!ncq_tfs
->sector_count
) {
1093 ncq_tfs
->sector_count
= 0x10000;
1095 size
= ncq_tfs
->sector_count
* 512;
1096 ahci_populate_sglist(ad
, &ncq_tfs
->sglist
, ncq_tfs
->cmdh
, size
, 0);
1098 if (ncq_tfs
->sglist
.size
< size
) {
1099 error_report("ahci: PRDT length for NCQ command (0x%zx) "
1100 "is smaller than the requested size (0x%zx)",
1101 ncq_tfs
->sglist
.size
, size
);
1103 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_OFS
);
1105 } else if (ncq_tfs
->sglist
.size
!= size
) {
1106 trace_process_ncq_command_large(s
, port
, tag
,
1107 ncq_tfs
->sglist
.size
, size
);
1110 trace_process_ncq_command(s
, port
, tag
,
1113 ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 1);
1114 execute_ncq_command(ncq_tfs
);
1117 static AHCICmdHdr
*get_cmd_header(AHCIState
*s
, uint8_t port
, uint8_t slot
)
1119 if (port
>= s
->ports
|| slot
>= AHCI_MAX_CMDS
) {
1123 return s
->dev
[port
].lst
? &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
] : NULL
;
1126 static void handle_reg_h2d_fis(AHCIState
*s
, int port
,
1127 uint8_t slot
, uint8_t *cmd_fis
)
1129 IDEState
*ide_state
= &s
->dev
[port
].port
.ifs
[0];
1130 AHCICmdHdr
*cmd
= get_cmd_header(s
, port
, slot
);
1131 uint16_t opts
= le16_to_cpu(cmd
->opts
);
1133 if (cmd_fis
[1] & 0x0F) {
1134 trace_handle_reg_h2d_fis_pmp(s
, port
, cmd_fis
[1],
1135 cmd_fis
[2], cmd_fis
[3]);
1139 if (cmd_fis
[1] & 0x70) {
1140 trace_handle_reg_h2d_fis_res(s
, port
, cmd_fis
[1],
1141 cmd_fis
[2], cmd_fis
[3]);
1145 if (!(cmd_fis
[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
)) {
1146 switch (s
->dev
[port
].port_state
) {
1148 if (cmd_fis
[15] & ATA_SRST
) {
1149 s
->dev
[port
].port_state
= STATE_RESET
;
1153 if (!(cmd_fis
[15] & ATA_SRST
)) {
1154 ahci_reset_port(s
, port
);
1161 /* Check for NCQ command */
1162 if (is_ncq(cmd_fis
[2])) {
1163 process_ncq_command(s
, port
, cmd_fis
, slot
);
1167 /* Decompose the FIS:
1168 * AHCI does not interpret FIS packets, it only forwards them.
1169 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1170 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1172 * ATA4 describes sector number for LBA28/CHS commands.
1173 * ATA6 describes sector number for LBA48 commands.
1174 * ATA8 deprecates CHS fully, describing only LBA28/48.
1176 * We dutifully convert the FIS into IDE registers, and allow the
1177 * core layer to interpret them as needed. */
1178 ide_state
->feature
= cmd_fis
[3];
1179 ide_state
->sector
= cmd_fis
[4]; /* LBA 7:0 */
1180 ide_state
->lcyl
= cmd_fis
[5]; /* LBA 15:8 */
1181 ide_state
->hcyl
= cmd_fis
[6]; /* LBA 23:16 */
1182 ide_state
->select
= cmd_fis
[7]; /* LBA 27:24 (LBA28) */
1183 ide_state
->hob_sector
= cmd_fis
[8]; /* LBA 31:24 */
1184 ide_state
->hob_lcyl
= cmd_fis
[9]; /* LBA 39:32 */
1185 ide_state
->hob_hcyl
= cmd_fis
[10]; /* LBA 47:40 */
1186 ide_state
->hob_feature
= cmd_fis
[11];
1187 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
1188 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1189 /* 15: Only valid when UPDATE_COMMAND not set. */
1191 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1192 * table to ide_state->io_buffer */
1193 if (opts
& AHCI_CMD_ATAPI
) {
1194 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
1195 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP
)) {
1196 char *pretty_fis
= ahci_pretty_buffer_fis(ide_state
->io_buffer
, 0x10);
1197 trace_handle_reg_h2d_fis_dump(s
, port
, pretty_fis
);
1200 s
->dev
[port
].done_atapi_packet
= false;
1201 /* XXX send PIO setup FIS */
1204 ide_state
->error
= 0;
1206 /* Reset transferred byte counter */
1209 /* We're ready to process the command in FIS byte 2. */
1210 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
1213 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
)
1215 IDEState
*ide_state
;
1221 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1222 /* Engine currently busy, try again later */
1223 trace_handle_cmd_busy(s
, port
);
1227 if (!s
->dev
[port
].lst
) {
1228 trace_handle_cmd_nolist(s
, port
);
1231 cmd
= get_cmd_header(s
, port
, slot
);
1232 /* remember current slot handle for later */
1233 s
->dev
[port
].cur_cmd
= cmd
;
1235 /* The device we are working for */
1236 ide_state
= &s
->dev
[port
].port
.ifs
[0];
1237 if (!ide_state
->blk
) {
1238 trace_handle_cmd_badport(s
, port
);
1242 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
1244 cmd_fis
= dma_memory_map(s
->as
, tbl_addr
, &cmd_len
,
1245 DMA_DIRECTION_FROM_DEVICE
);
1247 trace_handle_cmd_badfis(s
, port
);
1249 } else if (cmd_len
!= 0x80) {
1250 ahci_trigger_irq(s
, &s
->dev
[port
], AHCI_PORT_IRQ_BIT_HBFS
);
1251 trace_handle_cmd_badmap(s
, port
, cmd_len
);
1254 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP
)) {
1255 char *pretty_fis
= ahci_pretty_buffer_fis(cmd_fis
, 0x80);
1256 trace_handle_cmd_fis_dump(s
, port
, pretty_fis
);
1259 switch (cmd_fis
[0]) {
1260 case SATA_FIS_TYPE_REGISTER_H2D
:
1261 handle_reg_h2d_fis(s
, port
, slot
, cmd_fis
);
1264 trace_handle_cmd_unhandled_fis(s
, port
,
1265 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1270 dma_memory_unmap(s
->as
, cmd_fis
, cmd_len
, DMA_DIRECTION_FROM_DEVICE
,
1273 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1274 /* async command, complete later */
1275 s
->dev
[port
].busy_slot
= slot
;
1279 /* done handling the command */
1283 /* DMA dev <-> ram */
1284 static void ahci_start_transfer(IDEDMA
*dma
)
1286 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1287 IDEState
*s
= &ad
->port
.ifs
[0];
1288 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
1289 /* write == ram -> device */
1290 uint16_t opts
= le16_to_cpu(ad
->cur_cmd
->opts
);
1291 int is_write
= opts
& AHCI_CMD_WRITE
;
1292 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
1295 if (is_atapi
&& !ad
->done_atapi_packet
) {
1296 /* already prepopulated iobuffer */
1297 ad
->done_atapi_packet
= true;
1302 if (ahci_dma_prepare_buf(dma
, size
)) {
1306 trace_ahci_start_transfer(ad
->hba
, ad
->port_no
, is_write
? "writ" : "read",
1307 size
, is_atapi
? "atapi" : "ata",
1308 has_sglist
? "" : "o");
1310 if (has_sglist
&& size
) {
1312 dma_buf_write(s
->data_ptr
, size
, &s
->sg
);
1314 dma_buf_read(s
->data_ptr
, size
, &s
->sg
);
1319 /* declare that we processed everything */
1320 s
->data_ptr
= s
->data_end
;
1322 /* Update number of transferred bytes, destroy sglist */
1323 dma_buf_commit(s
, size
);
1325 s
->end_transfer_func(s
);
1327 if (!(s
->status
& DRQ_STAT
)) {
1328 /* done with PIO send/receive */
1329 ahci_write_fis_pio(ad
, le32_to_cpu(ad
->cur_cmd
->status
));
1333 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1334 BlockCompletionFunc
*dma_cb
)
1336 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1337 trace_ahci_start_dma(ad
->hba
, ad
->port_no
);
1338 s
->io_buffer_offset
= 0;
1342 static void ahci_restart_dma(IDEDMA
*dma
)
1344 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1348 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1349 * need an extra kick from the AHCI HBA.
1351 static void ahci_restart(IDEDMA
*dma
)
1353 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1356 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
1357 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[i
];
1358 if (ncq_tfs
->halt
) {
1359 execute_ncq_command(ncq_tfs
);
1365 * Called in DMA and PIO R/W chains to read the PRDT.
1366 * Not shared with NCQ pathways.
1368 static int32_t ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
)
1370 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1371 IDEState
*s
= &ad
->port
.ifs
[0];
1373 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
,
1374 limit
, s
->io_buffer_offset
) == -1) {
1375 trace_ahci_dma_prepare_buf_fail(ad
->hba
, ad
->port_no
);
1378 s
->io_buffer_size
= s
->sg
.size
;
1380 trace_ahci_dma_prepare_buf(ad
->hba
, ad
->port_no
, limit
, s
->io_buffer_size
);
1381 return s
->io_buffer_size
;
1385 * Updates the command header with a bytes-read value.
1386 * Called via dma_buf_commit, for both DMA and PIO paths.
1387 * sglist destruction is handled within dma_buf_commit.
1389 static void ahci_commit_buf(IDEDMA
*dma
, uint32_t tx_bytes
)
1391 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1393 tx_bytes
+= le32_to_cpu(ad
->cur_cmd
->status
);
1394 ad
->cur_cmd
->status
= cpu_to_le32(tx_bytes
);
1397 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1399 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1400 IDEState
*s
= &ad
->port
.ifs
[0];
1401 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1402 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1404 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
, l
, s
->io_buffer_offset
)) {
1409 dma_buf_read(p
, l
, &s
->sg
);
1411 dma_buf_write(p
, l
, &s
->sg
);
1414 /* free sglist, update byte count */
1415 dma_buf_commit(s
, l
);
1416 s
->io_buffer_index
+= l
;
1418 trace_ahci_dma_rw_buf(ad
->hba
, ad
->port_no
, l
);
1422 static void ahci_cmd_done(IDEDMA
*dma
)
1424 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1426 trace_ahci_cmd_done(ad
->hba
, ad
->port_no
);
1428 /* update d2h status */
1429 ahci_write_fis_d2h(ad
);
1431 if (!ad
->check_bh
) {
1432 /* maybe we still have something to process, check later */
1433 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1434 qemu_bh_schedule(ad
->check_bh
);
1438 static void ahci_irq_set(void *opaque
, int n
, int level
)
1442 static const IDEDMAOps ahci_dma_ops
= {
1443 .start_dma
= ahci_start_dma
,
1444 .restart
= ahci_restart
,
1445 .restart_dma
= ahci_restart_dma
,
1446 .start_transfer
= ahci_start_transfer
,
1447 .prepare_buf
= ahci_dma_prepare_buf
,
1448 .commit_buf
= ahci_commit_buf
,
1449 .rw_buf
= ahci_dma_rw_buf
,
1450 .cmd_done
= ahci_cmd_done
,
1453 void ahci_init(AHCIState
*s
, DeviceState
*qdev
)
1455 s
->container
= qdev
;
1456 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1457 memory_region_init_io(&s
->mem
, OBJECT(qdev
), &ahci_mem_ops
, s
,
1458 "ahci", AHCI_MEM_BAR_SIZE
);
1459 memory_region_init_io(&s
->idp
, OBJECT(qdev
), &ahci_idp_ops
, s
,
1463 void ahci_realize(AHCIState
*s
, DeviceState
*qdev
, AddressSpace
*as
, int ports
)
1470 s
->dev
= g_new0(AHCIDevice
, ports
);
1472 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, s
->ports
);
1473 for (i
= 0; i
< s
->ports
; i
++) {
1474 AHCIDevice
*ad
= &s
->dev
[i
];
1476 ide_bus_new(&ad
->port
, sizeof(ad
->port
), qdev
, i
, 1);
1477 ide_init2(&ad
->port
, irqs
[i
]);
1481 ad
->port
.dma
= &ad
->dma
;
1482 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1483 ide_register_restart_cb(&ad
->port
);
1488 void ahci_uninit(AHCIState
*s
)
1492 for (i
= 0; i
< s
->ports
; i
++) {
1493 AHCIDevice
*ad
= &s
->dev
[i
];
1495 for (j
= 0; j
< 2; j
++) {
1496 IDEState
*s
= &ad
->port
.ifs
[j
];
1500 object_unparent(OBJECT(&ad
->port
));
1506 void ahci_reset(AHCIState
*s
)
1511 trace_ahci_reset(s
);
1513 s
->control_regs
.irqstatus
= 0;
1515 * The implementation of this bit is dependent upon the value of the
1516 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1517 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1518 * read-only and shall have a reset value of '1'.
1520 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1522 s
->control_regs
.ghc
= HOST_CTL_AHCI_EN
;
1524 for (i
= 0; i
< s
->ports
; i
++) {
1525 pr
= &s
->dev
[i
].port_regs
;
1529 pr
->cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1530 ahci_reset_port(s
, i
);
1534 static const VMStateDescription vmstate_ncq_tfs
= {
1535 .name
= "ncq state",
1537 .fields
= (VMStateField
[]) {
1538 VMSTATE_UINT32(sector_count
, NCQTransferState
),
1539 VMSTATE_UINT64(lba
, NCQTransferState
),
1540 VMSTATE_UINT8(tag
, NCQTransferState
),
1541 VMSTATE_UINT8(cmd
, NCQTransferState
),
1542 VMSTATE_UINT8(slot
, NCQTransferState
),
1543 VMSTATE_BOOL(used
, NCQTransferState
),
1544 VMSTATE_BOOL(halt
, NCQTransferState
),
1545 VMSTATE_END_OF_LIST()
1549 static const VMStateDescription vmstate_ahci_device
= {
1550 .name
= "ahci port",
1552 .fields
= (VMStateField
[]) {
1553 VMSTATE_IDE_BUS(port
, AHCIDevice
),
1554 VMSTATE_IDE_DRIVE(port
.ifs
[0], AHCIDevice
),
1555 VMSTATE_UINT32(port_state
, AHCIDevice
),
1556 VMSTATE_UINT32(finished
, AHCIDevice
),
1557 VMSTATE_UINT32(port_regs
.lst_addr
, AHCIDevice
),
1558 VMSTATE_UINT32(port_regs
.lst_addr_hi
, AHCIDevice
),
1559 VMSTATE_UINT32(port_regs
.fis_addr
, AHCIDevice
),
1560 VMSTATE_UINT32(port_regs
.fis_addr_hi
, AHCIDevice
),
1561 VMSTATE_UINT32(port_regs
.irq_stat
, AHCIDevice
),
1562 VMSTATE_UINT32(port_regs
.irq_mask
, AHCIDevice
),
1563 VMSTATE_UINT32(port_regs
.cmd
, AHCIDevice
),
1564 VMSTATE_UINT32(port_regs
.tfdata
, AHCIDevice
),
1565 VMSTATE_UINT32(port_regs
.sig
, AHCIDevice
),
1566 VMSTATE_UINT32(port_regs
.scr_stat
, AHCIDevice
),
1567 VMSTATE_UINT32(port_regs
.scr_ctl
, AHCIDevice
),
1568 VMSTATE_UINT32(port_regs
.scr_err
, AHCIDevice
),
1569 VMSTATE_UINT32(port_regs
.scr_act
, AHCIDevice
),
1570 VMSTATE_UINT32(port_regs
.cmd_issue
, AHCIDevice
),
1571 VMSTATE_BOOL(done_atapi_packet
, AHCIDevice
),
1572 VMSTATE_INT32(busy_slot
, AHCIDevice
),
1573 VMSTATE_BOOL(init_d2h_sent
, AHCIDevice
),
1574 VMSTATE_STRUCT_ARRAY(ncq_tfs
, AHCIDevice
, AHCI_MAX_CMDS
,
1575 1, vmstate_ncq_tfs
, NCQTransferState
),
1576 VMSTATE_END_OF_LIST()
1580 static int ahci_state_post_load(void *opaque
, int version_id
)
1583 struct AHCIDevice
*ad
;
1584 NCQTransferState
*ncq_tfs
;
1586 AHCIState
*s
= opaque
;
1588 for (i
= 0; i
< s
->ports
; i
++) {
1590 pr
= &ad
->port_regs
;
1592 if (!(pr
->cmd
& PORT_CMD_START
) && (pr
->cmd
& PORT_CMD_LIST_ON
)) {
1593 error_report("AHCI: DMA engine should be off, but status bit "
1594 "indicates it is still running.");
1597 if (!(pr
->cmd
& PORT_CMD_FIS_RX
) && (pr
->cmd
& PORT_CMD_FIS_ON
)) {
1598 error_report("AHCI: FIS RX engine should be off, but status bit "
1599 "indicates it is still running.");
1603 /* After a migrate, the DMA/FIS engines are "off" and
1604 * need to be conditionally restarted */
1605 pr
->cmd
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
);
1606 if (ahci_cond_start_engines(ad
) != 0) {
1610 for (j
= 0; j
< AHCI_MAX_CMDS
; j
++) {
1611 ncq_tfs
= &ad
->ncq_tfs
[j
];
1612 ncq_tfs
->drive
= ad
;
1614 if (ncq_tfs
->used
!= ncq_tfs
->halt
) {
1617 if (!ncq_tfs
->halt
) {
1620 if (!is_ncq(ncq_tfs
->cmd
)) {
1623 if (ncq_tfs
->slot
!= ncq_tfs
->tag
) {
1626 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1627 * and the command list buffer should be mapped. */
1628 ncq_tfs
->cmdh
= get_cmd_header(s
, i
, ncq_tfs
->slot
);
1629 if (!ncq_tfs
->cmdh
) {
1632 ahci_populate_sglist(ncq_tfs
->drive
, &ncq_tfs
->sglist
,
1633 ncq_tfs
->cmdh
, ncq_tfs
->sector_count
* 512,
1635 if (ncq_tfs
->sector_count
!= ncq_tfs
->sglist
.size
>> 9) {
1642 * If an error is present, ad->busy_slot will be valid and not -1.
1643 * In this case, an operation is waiting to resume and will re-check
1644 * for additional AHCI commands to execute upon completion.
1646 * In the case where no error was present, busy_slot will be -1,
1647 * and we should check to see if there are additional commands waiting.
1649 if (ad
->busy_slot
== -1) {
1652 /* We are in the middle of a command, and may need to access
1653 * the command header in guest memory again. */
1654 if (ad
->busy_slot
< 0 || ad
->busy_slot
>= AHCI_MAX_CMDS
) {
1657 ad
->cur_cmd
= get_cmd_header(s
, i
, ad
->busy_slot
);
1664 const VMStateDescription vmstate_ahci
= {
1667 .post_load
= ahci_state_post_load
,
1668 .fields
= (VMStateField
[]) {
1669 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev
, AHCIState
, ports
,
1670 vmstate_ahci_device
, AHCIDevice
),
1671 VMSTATE_UINT32(control_regs
.cap
, AHCIState
),
1672 VMSTATE_UINT32(control_regs
.ghc
, AHCIState
),
1673 VMSTATE_UINT32(control_regs
.irqstatus
, AHCIState
),
1674 VMSTATE_UINT32(control_regs
.impl
, AHCIState
),
1675 VMSTATE_UINT32(control_regs
.version
, AHCIState
),
1676 VMSTATE_UINT32(idp_index
, AHCIState
),
1677 VMSTATE_INT32_EQUAL(ports
, AHCIState
, NULL
),
1678 VMSTATE_END_OF_LIST()
1682 static const VMStateDescription vmstate_sysbus_ahci
= {
1683 .name
= "sysbus-ahci",
1684 .fields
= (VMStateField
[]) {
1685 VMSTATE_AHCI(ahci
, SysbusAHCIState
),
1686 VMSTATE_END_OF_LIST()
1690 static void sysbus_ahci_reset(DeviceState
*dev
)
1692 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1694 ahci_reset(&s
->ahci
);
1697 static void sysbus_ahci_init(Object
*obj
)
1699 SysbusAHCIState
*s
= SYSBUS_AHCI(obj
);
1700 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1702 ahci_init(&s
->ahci
, DEVICE(obj
));
1704 sysbus_init_mmio(sbd
, &s
->ahci
.mem
);
1705 sysbus_init_irq(sbd
, &s
->ahci
.irq
);
1708 static void sysbus_ahci_realize(DeviceState
*dev
, Error
**errp
)
1710 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1712 ahci_realize(&s
->ahci
, dev
, &address_space_memory
, s
->num_ports
);
1715 static Property sysbus_ahci_properties
[] = {
1716 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState
, num_ports
, 1),
1717 DEFINE_PROP_END_OF_LIST(),
1720 static void sysbus_ahci_class_init(ObjectClass
*klass
, void *data
)
1722 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1724 dc
->realize
= sysbus_ahci_realize
;
1725 dc
->vmsd
= &vmstate_sysbus_ahci
;
1726 dc
->props
= sysbus_ahci_properties
;
1727 dc
->reset
= sysbus_ahci_reset
;
1728 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1731 static const TypeInfo sysbus_ahci_info
= {
1732 .name
= TYPE_SYSBUS_AHCI
,
1733 .parent
= TYPE_SYS_BUS_DEVICE
,
1734 .instance_size
= sizeof(SysbusAHCIState
),
1735 .instance_init
= sysbus_ahci_init
,
1736 .class_init
= sysbus_ahci_class_init
,
1739 static void sysbus_ahci_register_types(void)
1741 type_register_static(&sysbus_ahci_info
);
1744 type_init(sysbus_ahci_register_types
)
1746 int32_t ahci_get_num_ports(PCIDevice
*dev
)
1748 AHCIPCIState
*d
= ICH_AHCI(dev
);
1749 AHCIState
*ahci
= &d
->ahci
;
1754 void ahci_ide_create_devs(PCIDevice
*dev
, DriveInfo
**hd
)
1756 AHCIPCIState
*d
= ICH_AHCI(dev
);
1757 AHCIState
*ahci
= &d
->ahci
;
1760 for (i
= 0; i
< ahci
->ports
; i
++) {
1761 if (hd
[i
] == NULL
) {
1764 ide_create_drive(&ahci
->dev
[i
].port
, 0, hd
[i
]);