4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
155 fprintf_function cpu_fprintf
, int flags
)
157 ARMCPU
*cpu
= ARM_CPU(cs
);
158 CPUARMState
*env
= &cpu
->env
;
159 uint32_t psr
= pstate_read(env
);
161 int el
= arm_current_el(env
);
162 const char *ns_status
;
164 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
165 for (i
= 0; i
< 32; i
++) {
167 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
169 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
170 (i
+ 2) % 3 ? " " : "\n");
174 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
175 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
179 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
181 psr
& PSTATE_N
? 'N' : '-',
182 psr
& PSTATE_Z
? 'Z' : '-',
183 psr
& PSTATE_C
? 'C' : '-',
184 psr
& PSTATE_V
? 'V' : '-',
187 psr
& PSTATE_SP
? 'h' : 't');
189 if (cpu_isar_feature(aa64_bti
, cpu
)) {
190 cpu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
192 if (!(flags
& CPU_DUMP_FPU
)) {
193 cpu_fprintf(f
, "\n");
196 if (fp_exception_el(env
, el
) != 0) {
197 cpu_fprintf(f
, " FPU disabled\n");
200 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
201 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
203 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
204 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
206 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
208 if (i
== FFR_PRED_NUM
) {
209 cpu_fprintf(f
, "FFR=");
210 /* It's last, so end the line. */
213 cpu_fprintf(f
, "P%02d=", i
);
226 /* More than one quadword per predicate. */
231 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
233 if (j
* 4 + 4 <= zcr_len
+ 1) {
236 digits
= (zcr_len
% 4 + 1) * 4;
238 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
239 env
->vfp
.pregs
[i
].p
[j
],
240 j
? ":" : eol
? "\n" : " ");
244 for (i
= 0; i
< 32; i
++) {
246 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
247 i
, env
->vfp
.zregs
[i
].d
[1],
248 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
249 } else if (zcr_len
== 1) {
250 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
251 ":%016" PRIx64
":%016" PRIx64
"\n",
252 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
253 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
255 for (j
= zcr_len
; j
>= 0; j
--) {
256 bool odd
= (zcr_len
- j
) % 2 != 0;
258 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
261 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
263 cpu_fprintf(f
, " [%x]=", j
);
266 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
267 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
268 env
->vfp
.zregs
[i
].d
[j
* 2],
269 odd
|| j
== 0 ? "\n" : ":");
274 for (i
= 0; i
< 32; i
++) {
275 uint64_t *q
= aa64_vfp_qreg(env
, i
);
276 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
277 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
282 void gen_a64_set_pc_im(uint64_t val
)
284 tcg_gen_movi_i64(cpu_pc
, val
);
288 * Handle Top Byte Ignore (TBI) bits.
290 * If address tagging is enabled via the TCR TBI bits:
291 * + for EL2 and EL3 there is only one TBI bit, and if it is set
292 * then the address is zero-extended, clearing bits [63:56]
293 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
294 * and TBI1 controls addressses with bit 55 == 1.
295 * If the appropriate TBI bit is set for the address then
296 * the address is sign-extended from bit 55 into bits [63:56]
298 * Here We have concatenated TBI{1,0} into tbi.
300 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
301 TCGv_i64 src
, int tbi
)
304 /* Load unmodified address */
305 tcg_gen_mov_i64(dst
, src
);
306 } else if (s
->current_el
>= 2) {
307 /* FIXME: ARMv8.1-VHE S2 translation regime. */
308 /* Force tag byte to all zero */
309 tcg_gen_extract_i64(dst
, src
, 0, 56);
311 /* Sign-extend from bit 55. */
312 tcg_gen_sextract_i64(dst
, src
, 0, 56);
315 TCGv_i64 tcg_zero
= tcg_const_i64(0);
318 * The two TBI bits differ.
319 * If tbi0, then !tbi1: only use the extension if positive.
320 * if !tbi0, then tbi1: only use the extension if negative.
322 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
323 dst
, dst
, tcg_zero
, dst
, src
);
324 tcg_temp_free_i64(tcg_zero
);
329 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
332 * If address tagging is enabled for instructions via the TCR TBI bits,
333 * then loading an address into the PC will clear out any tag.
335 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
339 * Return a "clean" address for ADDR according to TBID.
340 * This is always a fresh temporary, as we need to be able to
341 * increment this independently of a dirty write-back address.
343 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
345 TCGv_i64 clean
= new_tmp_a64(s
);
346 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
350 typedef struct DisasCompare64
{
355 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
359 arm_test_cc(&c32
, cc
);
361 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
362 * properly. The NE/EQ comparisons are also fine with this choice. */
363 c64
->cond
= c32
.cond
;
364 c64
->value
= tcg_temp_new_i64();
365 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
370 static void a64_free_cc(DisasCompare64
*c64
)
372 tcg_temp_free_i64(c64
->value
);
375 static void gen_exception_internal(int excp
)
377 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
379 assert(excp_is_internal(excp
));
380 gen_helper_exception_internal(cpu_env
, tcg_excp
);
381 tcg_temp_free_i32(tcg_excp
);
384 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
386 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
387 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
388 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
390 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
392 tcg_temp_free_i32(tcg_el
);
393 tcg_temp_free_i32(tcg_syn
);
394 tcg_temp_free_i32(tcg_excp
);
397 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
399 gen_a64_set_pc_im(s
->pc
- offset
);
400 gen_exception_internal(excp
);
401 s
->base
.is_jmp
= DISAS_NORETURN
;
404 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
405 uint32_t syndrome
, uint32_t target_el
)
407 gen_a64_set_pc_im(s
->pc
- offset
);
408 gen_exception(excp
, syndrome
, target_el
);
409 s
->base
.is_jmp
= DISAS_NORETURN
;
412 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
417 gen_a64_set_pc_im(s
->pc
- offset
);
418 tcg_syn
= tcg_const_i32(syndrome
);
419 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
420 tcg_temp_free_i32(tcg_syn
);
421 s
->base
.is_jmp
= DISAS_NORETURN
;
424 static void gen_step_complete_exception(DisasContext
*s
)
426 /* We just completed step of an insn. Move from Active-not-pending
427 * to Active-pending, and then also take the swstep exception.
428 * This corresponds to making the (IMPDEF) choice to prioritize
429 * swstep exceptions over asynchronous exceptions taken to an exception
430 * level where debug is disabled. This choice has the advantage that
431 * we do not need to maintain internal state corresponding to the
432 * ISV/EX syndrome bits between completion of the step and generation
433 * of the exception, and our syndrome information is always correct.
436 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
437 default_exception_el(s
));
438 s
->base
.is_jmp
= DISAS_NORETURN
;
441 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
443 /* No direct tb linking with singlestep (either QEMU's or the ARM
444 * debug architecture kind) or deterministic io
446 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
447 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
451 #ifndef CONFIG_USER_ONLY
452 /* Only link tbs from inside the same guest page */
453 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
461 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
463 TranslationBlock
*tb
;
466 if (use_goto_tb(s
, n
, dest
)) {
468 gen_a64_set_pc_im(dest
);
469 tcg_gen_exit_tb(tb
, n
);
470 s
->base
.is_jmp
= DISAS_NORETURN
;
472 gen_a64_set_pc_im(dest
);
474 gen_step_complete_exception(s
);
475 } else if (s
->base
.singlestep_enabled
) {
476 gen_exception_internal(EXCP_DEBUG
);
478 tcg_gen_lookup_and_goto_ptr();
479 s
->base
.is_jmp
= DISAS_NORETURN
;
484 void unallocated_encoding(DisasContext
*s
)
486 /* Unallocated and reserved encodings are uncategorized */
487 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
488 default_exception_el(s
));
491 static void init_tmp_a64_array(DisasContext
*s
)
493 #ifdef CONFIG_DEBUG_TCG
494 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
496 s
->tmp_a64_count
= 0;
499 static void free_tmp_a64(DisasContext
*s
)
502 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
503 tcg_temp_free_i64(s
->tmp_a64
[i
]);
505 init_tmp_a64_array(s
);
508 TCGv_i64
new_tmp_a64(DisasContext
*s
)
510 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
511 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
514 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
516 TCGv_i64 t
= new_tmp_a64(s
);
517 tcg_gen_movi_i64(t
, 0);
522 * Register access functions
524 * These functions are used for directly accessing a register in where
525 * changes to the final register value are likely to be made. If you
526 * need to use a register for temporary calculation (e.g. index type
527 * operations) use the read_* form.
529 * B1.2.1 Register mappings
531 * In instruction register encoding 31 can refer to ZR (zero register) or
532 * the SP (stack pointer) depending on context. In QEMU's case we map SP
533 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
534 * This is the point of the _sp forms.
536 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
539 return new_tmp_a64_zero(s
);
545 /* register access for when 31 == SP */
546 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
551 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
552 * representing the register contents. This TCGv is an auto-freed
553 * temporary so it need not be explicitly freed, and may be modified.
555 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
557 TCGv_i64 v
= new_tmp_a64(s
);
560 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
562 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
565 tcg_gen_movi_i64(v
, 0);
570 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
572 TCGv_i64 v
= new_tmp_a64(s
);
574 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
576 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
581 /* Return the offset into CPUARMState of a slice (from
582 * the least significant end) of FP register Qn (ie
584 * (Note that this is not the same mapping as for A32; see cpu.h)
586 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
588 return vec_reg_offset(s
, regno
, 0, size
);
591 /* Offset of the high half of the 128 bit vector Qn */
592 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
594 return vec_reg_offset(s
, regno
, 1, MO_64
);
597 /* Convenience accessors for reading and writing single and double
598 * FP registers. Writing clears the upper parts of the associated
599 * 128 bit vector register, as required by the architecture.
600 * Note that unlike the GP register accessors, the values returned
601 * by the read functions must be manually freed.
603 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
605 TCGv_i64 v
= tcg_temp_new_i64();
607 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
611 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
613 TCGv_i32 v
= tcg_temp_new_i32();
615 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
619 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
621 TCGv_i32 v
= tcg_temp_new_i32();
623 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
627 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
628 * If SVE is not enabled, then there are only 128 bits in the vector.
630 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
632 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
633 unsigned vsz
= vec_full_reg_size(s
);
636 TCGv_i64 tcg_zero
= tcg_const_i64(0);
637 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
638 tcg_temp_free_i64(tcg_zero
);
641 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
645 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
647 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
649 tcg_gen_st_i64(v
, cpu_env
, ofs
);
650 clear_vec_high(s
, false, reg
);
653 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
655 TCGv_i64 tmp
= tcg_temp_new_i64();
657 tcg_gen_extu_i32_i64(tmp
, v
);
658 write_fp_dreg(s
, reg
, tmp
);
659 tcg_temp_free_i64(tmp
);
662 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
664 TCGv_ptr statusptr
= tcg_temp_new_ptr();
667 /* In A64 all instructions (both FP and Neon) use the FPCR; there
668 * is no equivalent of the A32 Neon "standard FPSCR value".
669 * However half-precision operations operate under a different
670 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
673 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
675 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
677 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
681 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
682 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
683 GVecGen2Fn
*gvec_fn
, int vece
)
685 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
686 is_q
? 16 : 8, vec_full_reg_size(s
));
689 /* Expand a 2-operand + immediate AdvSIMD vector operation using
690 * an expander function.
692 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
693 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
695 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
699 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
700 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
701 GVecGen3Fn
*gvec_fn
, int vece
)
703 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
704 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
707 /* Expand a 2-operand + immediate AdvSIMD vector operation using
710 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
711 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
713 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
714 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
717 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
718 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
719 int rn
, int rm
, const GVecGen3
*gvec_op
)
721 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
722 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
723 vec_full_reg_size(s
), gvec_op
);
726 /* Expand a 3-operand operation using an out-of-line helper. */
727 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
728 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
730 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
731 vec_full_reg_offset(s
, rn
),
732 vec_full_reg_offset(s
, rm
),
733 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
736 /* Expand a 3-operand + env pointer operation using
737 * an out-of-line helper.
739 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
740 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
742 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
743 vec_full_reg_offset(s
, rn
),
744 vec_full_reg_offset(s
, rm
), cpu_env
,
745 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
748 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
749 * an out-of-line helper.
751 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
752 int rm
, bool is_fp16
, int data
,
753 gen_helper_gvec_3_ptr
*fn
)
755 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
756 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
757 vec_full_reg_offset(s
, rn
),
758 vec_full_reg_offset(s
, rm
), fpst
,
759 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
760 tcg_temp_free_ptr(fpst
);
763 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
764 * than the 32 bit equivalent.
766 static inline void gen_set_NZ64(TCGv_i64 result
)
768 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
769 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
772 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
773 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
776 gen_set_NZ64(result
);
778 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
779 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
781 tcg_gen_movi_i32(cpu_CF
, 0);
782 tcg_gen_movi_i32(cpu_VF
, 0);
785 /* dest = T0 + T1; compute C, N, V and Z flags */
786 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
789 TCGv_i64 result
, flag
, tmp
;
790 result
= tcg_temp_new_i64();
791 flag
= tcg_temp_new_i64();
792 tmp
= tcg_temp_new_i64();
794 tcg_gen_movi_i64(tmp
, 0);
795 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
797 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
799 gen_set_NZ64(result
);
801 tcg_gen_xor_i64(flag
, result
, t0
);
802 tcg_gen_xor_i64(tmp
, t0
, t1
);
803 tcg_gen_andc_i64(flag
, flag
, tmp
);
804 tcg_temp_free_i64(tmp
);
805 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
807 tcg_gen_mov_i64(dest
, result
);
808 tcg_temp_free_i64(result
);
809 tcg_temp_free_i64(flag
);
811 /* 32 bit arithmetic */
812 TCGv_i32 t0_32
= tcg_temp_new_i32();
813 TCGv_i32 t1_32
= tcg_temp_new_i32();
814 TCGv_i32 tmp
= tcg_temp_new_i32();
816 tcg_gen_movi_i32(tmp
, 0);
817 tcg_gen_extrl_i64_i32(t0_32
, t0
);
818 tcg_gen_extrl_i64_i32(t1_32
, t1
);
819 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
820 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
821 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
822 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
823 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
824 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
826 tcg_temp_free_i32(tmp
);
827 tcg_temp_free_i32(t0_32
);
828 tcg_temp_free_i32(t1_32
);
832 /* dest = T0 - T1; compute C, N, V and Z flags */
833 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
836 /* 64 bit arithmetic */
837 TCGv_i64 result
, flag
, tmp
;
839 result
= tcg_temp_new_i64();
840 flag
= tcg_temp_new_i64();
841 tcg_gen_sub_i64(result
, t0
, t1
);
843 gen_set_NZ64(result
);
845 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
846 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
848 tcg_gen_xor_i64(flag
, result
, t0
);
849 tmp
= tcg_temp_new_i64();
850 tcg_gen_xor_i64(tmp
, t0
, t1
);
851 tcg_gen_and_i64(flag
, flag
, tmp
);
852 tcg_temp_free_i64(tmp
);
853 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
854 tcg_gen_mov_i64(dest
, result
);
855 tcg_temp_free_i64(flag
);
856 tcg_temp_free_i64(result
);
858 /* 32 bit arithmetic */
859 TCGv_i32 t0_32
= tcg_temp_new_i32();
860 TCGv_i32 t1_32
= tcg_temp_new_i32();
863 tcg_gen_extrl_i64_i32(t0_32
, t0
);
864 tcg_gen_extrl_i64_i32(t1_32
, t1
);
865 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
866 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
867 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
868 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
869 tmp
= tcg_temp_new_i32();
870 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
871 tcg_temp_free_i32(t0_32
);
872 tcg_temp_free_i32(t1_32
);
873 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
874 tcg_temp_free_i32(tmp
);
875 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
879 /* dest = T0 + T1 + CF; do not compute flags. */
880 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
882 TCGv_i64 flag
= tcg_temp_new_i64();
883 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
884 tcg_gen_add_i64(dest
, t0
, t1
);
885 tcg_gen_add_i64(dest
, dest
, flag
);
886 tcg_temp_free_i64(flag
);
889 tcg_gen_ext32u_i64(dest
, dest
);
893 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
894 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
897 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
898 result
= tcg_temp_new_i64();
899 cf_64
= tcg_temp_new_i64();
900 vf_64
= tcg_temp_new_i64();
901 tmp
= tcg_const_i64(0);
903 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
904 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
905 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
906 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
907 gen_set_NZ64(result
);
909 tcg_gen_xor_i64(vf_64
, result
, t0
);
910 tcg_gen_xor_i64(tmp
, t0
, t1
);
911 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
912 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
914 tcg_gen_mov_i64(dest
, result
);
916 tcg_temp_free_i64(tmp
);
917 tcg_temp_free_i64(vf_64
);
918 tcg_temp_free_i64(cf_64
);
919 tcg_temp_free_i64(result
);
921 TCGv_i32 t0_32
, t1_32
, tmp
;
922 t0_32
= tcg_temp_new_i32();
923 t1_32
= tcg_temp_new_i32();
924 tmp
= tcg_const_i32(0);
926 tcg_gen_extrl_i64_i32(t0_32
, t0
);
927 tcg_gen_extrl_i64_i32(t1_32
, t1
);
928 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
929 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
931 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
932 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
933 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
934 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
935 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
937 tcg_temp_free_i32(tmp
);
938 tcg_temp_free_i32(t1_32
);
939 tcg_temp_free_i32(t0_32
);
944 * Load/Store generators
948 * Store from GPR register to memory.
950 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
951 TCGv_i64 tcg_addr
, int size
, int memidx
,
953 unsigned int iss_srt
,
954 bool iss_sf
, bool iss_ar
)
957 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
962 syn
= syn_data_abort_with_iss(0,
968 0, 0, 0, 0, 0, false);
969 disas_set_insn_syndrome(s
, syn
);
973 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
974 TCGv_i64 tcg_addr
, int size
,
976 unsigned int iss_srt
,
977 bool iss_sf
, bool iss_ar
)
979 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
980 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
984 * Load from memory to GPR register
986 static void do_gpr_ld_memidx(DisasContext
*s
,
987 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
988 int size
, bool is_signed
,
989 bool extend
, int memidx
,
990 bool iss_valid
, unsigned int iss_srt
,
991 bool iss_sf
, bool iss_ar
)
993 TCGMemOp memop
= s
->be_data
+ size
;
1001 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
1003 if (extend
&& is_signed
) {
1005 tcg_gen_ext32u_i64(dest
, dest
);
1011 syn
= syn_data_abort_with_iss(0,
1017 0, 0, 0, 0, 0, false);
1018 disas_set_insn_syndrome(s
, syn
);
1022 static void do_gpr_ld(DisasContext
*s
,
1023 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1024 int size
, bool is_signed
, bool extend
,
1025 bool iss_valid
, unsigned int iss_srt
,
1026 bool iss_sf
, bool iss_ar
)
1028 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1030 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1034 * Store from FP register to memory
1036 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1038 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1039 TCGv_i64 tmp
= tcg_temp_new_i64();
1040 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1042 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1045 bool be
= s
->be_data
== MO_BE
;
1046 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1048 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1049 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1051 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1052 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1054 tcg_temp_free_i64(tcg_hiaddr
);
1057 tcg_temp_free_i64(tmp
);
1061 * Load from memory to FP register
1063 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1065 /* This always zero-extends and writes to a full 128 bit wide vector */
1066 TCGv_i64 tmplo
= tcg_temp_new_i64();
1070 TCGMemOp memop
= s
->be_data
+ size
;
1071 tmphi
= tcg_const_i64(0);
1072 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1074 bool be
= s
->be_data
== MO_BE
;
1075 TCGv_i64 tcg_hiaddr
;
1077 tmphi
= tcg_temp_new_i64();
1078 tcg_hiaddr
= tcg_temp_new_i64();
1080 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1081 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1083 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1085 tcg_temp_free_i64(tcg_hiaddr
);
1088 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1089 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1091 tcg_temp_free_i64(tmplo
);
1092 tcg_temp_free_i64(tmphi
);
1094 clear_vec_high(s
, true, destidx
);
1098 * Vector load/store helpers.
1100 * The principal difference between this and a FP load is that we don't
1101 * zero extend as we are filling a partial chunk of the vector register.
1102 * These functions don't support 128 bit loads/stores, which would be
1103 * normal load/store operations.
1105 * The _i32 versions are useful when operating on 32 bit quantities
1106 * (eg for floating point single or using Neon helper functions).
1109 /* Get value of an element within a vector register */
1110 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1111 int element
, TCGMemOp memop
)
1113 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1116 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1119 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1122 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1125 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1128 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1131 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1135 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1138 g_assert_not_reached();
1142 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1143 int element
, TCGMemOp memop
)
1145 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1148 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1151 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1154 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1157 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1161 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1164 g_assert_not_reached();
1168 /* Set value of an element within a vector register */
1169 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1170 int element
, TCGMemOp memop
)
1172 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1175 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1178 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1181 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1184 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1187 g_assert_not_reached();
1191 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1192 int destidx
, int element
, TCGMemOp memop
)
1194 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1197 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1200 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1203 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1206 g_assert_not_reached();
1210 /* Store from vector register to memory */
1211 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1212 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1214 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1216 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1217 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1219 tcg_temp_free_i64(tcg_tmp
);
1222 /* Load from memory to vector register */
1223 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1224 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1226 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1228 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1229 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1231 tcg_temp_free_i64(tcg_tmp
);
1234 /* Check that FP/Neon access is enabled. If it is, return
1235 * true. If not, emit code to generate an appropriate exception,
1236 * and return false; the caller should not emit any code for
1237 * the instruction. Note that this check must happen after all
1238 * unallocated-encoding checks (otherwise the syndrome information
1239 * for the resulting exception will be incorrect).
1241 static inline bool fp_access_check(DisasContext
*s
)
1243 assert(!s
->fp_access_checked
);
1244 s
->fp_access_checked
= true;
1246 if (!s
->fp_excp_el
) {
1250 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1255 /* Check that SVE access is enabled. If it is, return true.
1256 * If not, emit code to generate an appropriate exception and return false.
1258 bool sve_access_check(DisasContext
*s
)
1260 if (s
->sve_excp_el
) {
1261 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1265 return fp_access_check(s
);
1269 * This utility function is for doing register extension with an
1270 * optional shift. You will likely want to pass a temporary for the
1271 * destination register. See DecodeRegExtend() in the ARM ARM.
1273 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1274 int option
, unsigned int shift
)
1276 int extsize
= extract32(option
, 0, 2);
1277 bool is_signed
= extract32(option
, 2, 1);
1282 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1285 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1288 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1291 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1297 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1300 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1303 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1306 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1312 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1316 static inline void gen_check_sp_alignment(DisasContext
*s
)
1318 /* The AArch64 architecture mandates that (if enabled via PSTATE
1319 * or SCTLR bits) there is a check that SP is 16-aligned on every
1320 * SP-relative load or store (with an exception generated if it is not).
1321 * In line with general QEMU practice regarding misaligned accesses,
1322 * we omit these checks for the sake of guest program performance.
1323 * This function is provided as a hook so we can more easily add these
1324 * checks in future (possibly as a "favour catching guest program bugs
1325 * over speed" user selectable option).
1330 * This provides a simple table based table lookup decoder. It is
1331 * intended to be used when the relevant bits for decode are too
1332 * awkwardly placed and switch/if based logic would be confusing and
1333 * deeply nested. Since it's a linear search through the table, tables
1334 * should be kept small.
1336 * It returns the first handler where insn & mask == pattern, or
1337 * NULL if there is no match.
1338 * The table is terminated by an empty mask (i.e. 0)
1340 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1343 const AArch64DecodeTable
*tptr
= table
;
1345 while (tptr
->mask
) {
1346 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1347 return tptr
->disas_fn
;
1355 * The instruction disassembly implemented here matches
1356 * the instruction encoding classifications in chapter C4
1357 * of the ARM Architecture Reference Manual (DDI0487B_a);
1358 * classification names and decode diagrams here should generally
1359 * match up with those in the manual.
1362 /* Unconditional branch (immediate)
1364 * +----+-----------+-------------------------------------+
1365 * | op | 0 0 1 0 1 | imm26 |
1366 * +----+-----------+-------------------------------------+
1368 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1370 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1372 if (insn
& (1U << 31)) {
1373 /* BL Branch with link */
1374 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1377 /* B Branch / BL Branch with link */
1379 gen_goto_tb(s
, 0, addr
);
1382 /* Compare and branch (immediate)
1383 * 31 30 25 24 23 5 4 0
1384 * +----+-------------+----+---------------------+--------+
1385 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1386 * +----+-------------+----+---------------------+--------+
1388 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1390 unsigned int sf
, op
, rt
;
1392 TCGLabel
*label_match
;
1395 sf
= extract32(insn
, 31, 1);
1396 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1397 rt
= extract32(insn
, 0, 5);
1398 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1400 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1401 label_match
= gen_new_label();
1404 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1405 tcg_cmp
, 0, label_match
);
1407 gen_goto_tb(s
, 0, s
->pc
);
1408 gen_set_label(label_match
);
1409 gen_goto_tb(s
, 1, addr
);
1412 /* Test and branch (immediate)
1413 * 31 30 25 24 23 19 18 5 4 0
1414 * +----+-------------+----+-------+-------------+------+
1415 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1416 * +----+-------------+----+-------+-------------+------+
1418 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1420 unsigned int bit_pos
, op
, rt
;
1422 TCGLabel
*label_match
;
1425 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1426 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1427 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1428 rt
= extract32(insn
, 0, 5);
1430 tcg_cmp
= tcg_temp_new_i64();
1431 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1432 label_match
= gen_new_label();
1435 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1436 tcg_cmp
, 0, label_match
);
1437 tcg_temp_free_i64(tcg_cmp
);
1438 gen_goto_tb(s
, 0, s
->pc
);
1439 gen_set_label(label_match
);
1440 gen_goto_tb(s
, 1, addr
);
1443 /* Conditional branch (immediate)
1444 * 31 25 24 23 5 4 3 0
1445 * +---------------+----+---------------------+----+------+
1446 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1447 * +---------------+----+---------------------+----+------+
1449 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1454 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1455 unallocated_encoding(s
);
1458 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1459 cond
= extract32(insn
, 0, 4);
1463 /* genuinely conditional branches */
1464 TCGLabel
*label_match
= gen_new_label();
1465 arm_gen_test_cc(cond
, label_match
);
1466 gen_goto_tb(s
, 0, s
->pc
);
1467 gen_set_label(label_match
);
1468 gen_goto_tb(s
, 1, addr
);
1470 /* 0xe and 0xf are both "always" conditions */
1471 gen_goto_tb(s
, 0, addr
);
1475 /* HINT instruction group, including various allocated HINTs */
1476 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1477 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1479 unsigned int selector
= crm
<< 3 | op2
;
1482 unallocated_encoding(s
);
1487 case 0b00000: /* NOP */
1489 case 0b00011: /* WFI */
1490 s
->base
.is_jmp
= DISAS_WFI
;
1492 case 0b00001: /* YIELD */
1493 /* When running in MTTCG we don't generate jumps to the yield and
1494 * WFE helpers as it won't affect the scheduling of other vCPUs.
1495 * If we wanted to more completely model WFE/SEV so we don't busy
1496 * spin unnecessarily we would need to do something more involved.
1498 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1499 s
->base
.is_jmp
= DISAS_YIELD
;
1502 case 0b00010: /* WFE */
1503 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1504 s
->base
.is_jmp
= DISAS_WFE
;
1507 case 0b00100: /* SEV */
1508 case 0b00101: /* SEVL */
1509 /* we treat all as NOP at least for now */
1511 case 0b00111: /* XPACLRI */
1512 if (s
->pauth_active
) {
1513 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1516 case 0b01000: /* PACIA1716 */
1517 if (s
->pauth_active
) {
1518 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1521 case 0b01010: /* PACIB1716 */
1522 if (s
->pauth_active
) {
1523 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1526 case 0b01100: /* AUTIA1716 */
1527 if (s
->pauth_active
) {
1528 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1531 case 0b01110: /* AUTIB1716 */
1532 if (s
->pauth_active
) {
1533 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1536 case 0b11000: /* PACIAZ */
1537 if (s
->pauth_active
) {
1538 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1539 new_tmp_a64_zero(s
));
1542 case 0b11001: /* PACIASP */
1543 if (s
->pauth_active
) {
1544 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1547 case 0b11010: /* PACIBZ */
1548 if (s
->pauth_active
) {
1549 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1550 new_tmp_a64_zero(s
));
1553 case 0b11011: /* PACIBSP */
1554 if (s
->pauth_active
) {
1555 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1558 case 0b11100: /* AUTIAZ */
1559 if (s
->pauth_active
) {
1560 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1561 new_tmp_a64_zero(s
));
1564 case 0b11101: /* AUTIASP */
1565 if (s
->pauth_active
) {
1566 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1569 case 0b11110: /* AUTIBZ */
1570 if (s
->pauth_active
) {
1571 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1572 new_tmp_a64_zero(s
));
1575 case 0b11111: /* AUTIBSP */
1576 if (s
->pauth_active
) {
1577 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1581 /* default specified as NOP equivalent */
1586 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1588 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1591 /* CLREX, DSB, DMB, ISB */
1592 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1593 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1598 unallocated_encoding(s
);
1609 case 1: /* MBReqTypes_Reads */
1610 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1612 case 2: /* MBReqTypes_Writes */
1613 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1615 default: /* MBReqTypes_All */
1616 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1622 /* We need to break the TB after this insn to execute
1623 * a self-modified code correctly and also to take
1624 * any pending interrupts immediately.
1627 gen_goto_tb(s
, 0, s
->pc
);
1631 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1632 goto do_unallocated
;
1635 * TODO: There is no speculation barrier opcode for TCG;
1636 * MB and end the TB instead.
1638 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1639 gen_goto_tb(s
, 0, s
->pc
);
1644 unallocated_encoding(s
);
1649 /* MSR (immediate) - move immediate to processor state field */
1650 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1651 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1654 int op
= op1
<< 3 | op2
;
1656 /* End the TB by default, chaining is ok. */
1657 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1660 case 0x05: /* SPSel */
1661 if (s
->current_el
== 0) {
1662 goto do_unallocated
;
1664 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1665 gen_helper_msr_i_spsel(cpu_env
, t1
);
1666 tcg_temp_free_i32(t1
);
1669 case 0x1e: /* DAIFSet */
1670 t1
= tcg_const_i32(crm
);
1671 gen_helper_msr_i_daifset(cpu_env
, t1
);
1672 tcg_temp_free_i32(t1
);
1675 case 0x1f: /* DAIFClear */
1676 t1
= tcg_const_i32(crm
);
1677 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1678 tcg_temp_free_i32(t1
);
1679 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1680 s
->base
.is_jmp
= DISAS_UPDATE
;
1685 unallocated_encoding(s
);
1690 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1692 TCGv_i32 tmp
= tcg_temp_new_i32();
1693 TCGv_i32 nzcv
= tcg_temp_new_i32();
1695 /* build bit 31, N */
1696 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1697 /* build bit 30, Z */
1698 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1699 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1700 /* build bit 29, C */
1701 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1702 /* build bit 28, V */
1703 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1704 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1705 /* generate result */
1706 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1708 tcg_temp_free_i32(nzcv
);
1709 tcg_temp_free_i32(tmp
);
1712 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1715 TCGv_i32 nzcv
= tcg_temp_new_i32();
1717 /* take NZCV from R[t] */
1718 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1721 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1723 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1724 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1726 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1727 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1729 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1730 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1731 tcg_temp_free_i32(nzcv
);
1734 /* MRS - move from system register
1735 * MSR (register) - move to system register
1738 * These are all essentially the same insn in 'read' and 'write'
1739 * versions, with varying op0 fields.
1741 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1742 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1743 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1745 const ARMCPRegInfo
*ri
;
1748 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1749 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1750 crn
, crm
, op0
, op1
, op2
));
1753 /* Unknown register; this might be a guest error or a QEMU
1754 * unimplemented feature.
1756 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1757 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1758 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1759 unallocated_encoding(s
);
1763 /* Check access permissions */
1764 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1765 unallocated_encoding(s
);
1770 /* Emit code to perform further access permissions checks at
1771 * runtime; this may result in an exception.
1774 TCGv_i32 tcg_syn
, tcg_isread
;
1777 gen_a64_set_pc_im(s
->pc
- 4);
1778 tmpptr
= tcg_const_ptr(ri
);
1779 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1780 tcg_syn
= tcg_const_i32(syndrome
);
1781 tcg_isread
= tcg_const_i32(isread
);
1782 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1783 tcg_temp_free_ptr(tmpptr
);
1784 tcg_temp_free_i32(tcg_syn
);
1785 tcg_temp_free_i32(tcg_isread
);
1788 /* Handle special cases first */
1789 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1793 tcg_rt
= cpu_reg(s
, rt
);
1795 gen_get_nzcv(tcg_rt
);
1797 gen_set_nzcv(tcg_rt
);
1800 case ARM_CP_CURRENTEL
:
1801 /* Reads as current EL value from pstate, which is
1802 * guaranteed to be constant by the tb flags.
1804 tcg_rt
= cpu_reg(s
, rt
);
1805 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1808 /* Writes clear the aligned block of memory which rt points into. */
1809 tcg_rt
= cpu_reg(s
, rt
);
1810 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1815 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1817 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1821 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1825 tcg_rt
= cpu_reg(s
, rt
);
1828 if (ri
->type
& ARM_CP_CONST
) {
1829 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1830 } else if (ri
->readfn
) {
1832 tmpptr
= tcg_const_ptr(ri
);
1833 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1834 tcg_temp_free_ptr(tmpptr
);
1836 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1839 if (ri
->type
& ARM_CP_CONST
) {
1840 /* If not forbidden by access permissions, treat as WI */
1842 } else if (ri
->writefn
) {
1844 tmpptr
= tcg_const_ptr(ri
);
1845 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1846 tcg_temp_free_ptr(tmpptr
);
1848 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1852 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1853 /* I/O operations must end the TB here (whether read or write) */
1855 s
->base
.is_jmp
= DISAS_UPDATE
;
1856 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1857 /* We default to ending the TB on a coprocessor register write,
1858 * but allow this to be suppressed by the register definition
1859 * (usually only necessary to work around guest bugs).
1861 s
->base
.is_jmp
= DISAS_UPDATE
;
1866 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1867 * +---------------------+---+-----+-----+-------+-------+-----+------+
1868 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1869 * +---------------------+---+-----+-----+-------+-------+-----+------+
1871 static void disas_system(DisasContext
*s
, uint32_t insn
)
1873 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1874 l
= extract32(insn
, 21, 1);
1875 op0
= extract32(insn
, 19, 2);
1876 op1
= extract32(insn
, 16, 3);
1877 crn
= extract32(insn
, 12, 4);
1878 crm
= extract32(insn
, 8, 4);
1879 op2
= extract32(insn
, 5, 3);
1880 rt
= extract32(insn
, 0, 5);
1883 if (l
|| rt
!= 31) {
1884 unallocated_encoding(s
);
1888 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1889 handle_hint(s
, insn
, op1
, op2
, crm
);
1891 case 3: /* CLREX, DSB, DMB, ISB */
1892 handle_sync(s
, insn
, op1
, op2
, crm
);
1894 case 4: /* MSR (immediate) */
1895 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1898 unallocated_encoding(s
);
1903 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1906 /* Exception generation
1908 * 31 24 23 21 20 5 4 2 1 0
1909 * +-----------------+-----+------------------------+-----+----+
1910 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1911 * +-----------------------+------------------------+----------+
1913 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1915 int opc
= extract32(insn
, 21, 3);
1916 int op2_ll
= extract32(insn
, 0, 5);
1917 int imm16
= extract32(insn
, 5, 16);
1922 /* For SVC, HVC and SMC we advance the single-step state
1923 * machine before taking the exception. This is architecturally
1924 * mandated, to ensure that single-stepping a system call
1925 * instruction works properly.
1930 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1931 default_exception_el(s
));
1934 if (s
->current_el
== 0) {
1935 unallocated_encoding(s
);
1938 /* The pre HVC helper handles cases when HVC gets trapped
1939 * as an undefined insn by runtime configuration.
1941 gen_a64_set_pc_im(s
->pc
- 4);
1942 gen_helper_pre_hvc(cpu_env
);
1944 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1947 if (s
->current_el
== 0) {
1948 unallocated_encoding(s
);
1951 gen_a64_set_pc_im(s
->pc
- 4);
1952 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1953 gen_helper_pre_smc(cpu_env
, tmp
);
1954 tcg_temp_free_i32(tmp
);
1956 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1959 unallocated_encoding(s
);
1965 unallocated_encoding(s
);
1969 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1973 unallocated_encoding(s
);
1976 /* HLT. This has two purposes.
1977 * Architecturally, it is an external halting debug instruction.
1978 * Since QEMU doesn't implement external debug, we treat this as
1979 * it is required for halting debug disabled: it will UNDEF.
1980 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1982 if (semihosting_enabled() && imm16
== 0xf000) {
1983 #ifndef CONFIG_USER_ONLY
1984 /* In system mode, don't allow userspace access to semihosting,
1985 * to provide some semblance of security (and for consistency
1986 * with our 32-bit semihosting).
1988 if (s
->current_el
== 0) {
1989 unsupported_encoding(s
, insn
);
1993 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1995 unsupported_encoding(s
, insn
);
1999 if (op2_ll
< 1 || op2_ll
> 3) {
2000 unallocated_encoding(s
);
2003 /* DCPS1, DCPS2, DCPS3 */
2004 unsupported_encoding(s
, insn
);
2007 unallocated_encoding(s
);
2012 /* Unconditional branch (register)
2013 * 31 25 24 21 20 16 15 10 9 5 4 0
2014 * +---------------+-------+-------+-------+------+-------+
2015 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2016 * +---------------+-------+-------+-------+------+-------+
2018 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2020 unsigned int opc
, op2
, op3
, rn
, op4
;
2021 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2025 opc
= extract32(insn
, 21, 4);
2026 op2
= extract32(insn
, 16, 5);
2027 op3
= extract32(insn
, 10, 6);
2028 rn
= extract32(insn
, 5, 5);
2029 op4
= extract32(insn
, 0, 5);
2032 goto do_unallocated
;
2044 goto do_unallocated
;
2046 dst
= cpu_reg(s
, rn
);
2051 if (!dc_isar_feature(aa64_pauth
, s
)) {
2052 goto do_unallocated
;
2056 if (rn
!= 0x1f || op4
!= 0x1f) {
2057 goto do_unallocated
;
2060 modifier
= cpu_X
[31];
2062 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2064 goto do_unallocated
;
2066 modifier
= new_tmp_a64_zero(s
);
2068 if (s
->pauth_active
) {
2069 dst
= new_tmp_a64(s
);
2071 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2073 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2076 dst
= cpu_reg(s
, rn
);
2081 goto do_unallocated
;
2083 gen_a64_set_pc(s
, dst
);
2084 /* BLR also needs to load return address */
2086 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2092 if (!dc_isar_feature(aa64_pauth
, s
)) {
2093 goto do_unallocated
;
2095 if ((op3
& ~1) != 2) {
2096 goto do_unallocated
;
2098 btype_mod
= opc
& 1;
2099 if (s
->pauth_active
) {
2100 dst
= new_tmp_a64(s
);
2101 modifier
= cpu_reg_sp(s
, op4
);
2103 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2105 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2108 dst
= cpu_reg(s
, rn
);
2110 gen_a64_set_pc(s
, dst
);
2111 /* BLRAA also needs to load return address */
2113 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2118 if (s
->current_el
== 0) {
2119 goto do_unallocated
;
2124 goto do_unallocated
;
2126 dst
= tcg_temp_new_i64();
2127 tcg_gen_ld_i64(dst
, cpu_env
,
2128 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2131 case 2: /* ERETAA */
2132 case 3: /* ERETAB */
2133 if (!dc_isar_feature(aa64_pauth
, s
)) {
2134 goto do_unallocated
;
2136 if (rn
!= 0x1f || op4
!= 0x1f) {
2137 goto do_unallocated
;
2139 dst
= tcg_temp_new_i64();
2140 tcg_gen_ld_i64(dst
, cpu_env
,
2141 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2142 if (s
->pauth_active
) {
2143 modifier
= cpu_X
[31];
2145 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2147 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2153 goto do_unallocated
;
2155 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2159 gen_helper_exception_return(cpu_env
, dst
);
2160 tcg_temp_free_i64(dst
);
2161 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2164 /* Must exit loop to check un-masked IRQs */
2165 s
->base
.is_jmp
= DISAS_EXIT
;
2169 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2170 goto do_unallocated
;
2172 unsupported_encoding(s
, insn
);
2178 unallocated_encoding(s
);
2182 switch (btype_mod
) {
2184 if (dc_isar_feature(aa64_bti
, s
)) {
2185 /* BR to {x16,x17} or !guard -> 1, else 3. */
2186 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2191 if (dc_isar_feature(aa64_bti
, s
)) {
2192 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2197 default: /* RET or none of the above. */
2198 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2202 s
->base
.is_jmp
= DISAS_JUMP
;
2205 /* Branches, exception generating and system instructions */
2206 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2208 switch (extract32(insn
, 25, 7)) {
2209 case 0x0a: case 0x0b:
2210 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2211 disas_uncond_b_imm(s
, insn
);
2213 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2214 disas_comp_b_imm(s
, insn
);
2216 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2217 disas_test_b_imm(s
, insn
);
2219 case 0x2a: /* Conditional branch (immediate) */
2220 disas_cond_b_imm(s
, insn
);
2222 case 0x6a: /* Exception generation / System */
2223 if (insn
& (1 << 24)) {
2224 if (extract32(insn
, 22, 2) == 0) {
2225 disas_system(s
, insn
);
2227 unallocated_encoding(s
);
2233 case 0x6b: /* Unconditional branch (register) */
2234 disas_uncond_b_reg(s
, insn
);
2237 unallocated_encoding(s
);
2243 * Load/Store exclusive instructions are implemented by remembering
2244 * the value/address loaded, and seeing if these are the same
2245 * when the store is performed. This is not actually the architecturally
2246 * mandated semantics, but it works for typical guest code sequences
2247 * and avoids having to monitor regular stores.
2249 * The store exclusive uses the atomic cmpxchg primitives to avoid
2250 * races in multi-threaded linux-user and when MTTCG softmmu is
2253 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2254 TCGv_i64 addr
, int size
, bool is_pair
)
2256 int idx
= get_mem_index(s
);
2257 TCGMemOp memop
= s
->be_data
;
2259 g_assert(size
<= 3);
2261 g_assert(size
>= 2);
2263 /* The pair must be single-copy atomic for the doubleword. */
2264 memop
|= MO_64
| MO_ALIGN
;
2265 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2266 if (s
->be_data
== MO_LE
) {
2267 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2268 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2270 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2271 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2274 /* The pair must be single-copy atomic for *each* doubleword, not
2275 the entire quadword, however it must be quadword aligned. */
2277 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2278 memop
| MO_ALIGN_16
);
2280 TCGv_i64 addr2
= tcg_temp_new_i64();
2281 tcg_gen_addi_i64(addr2
, addr
, 8);
2282 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2283 tcg_temp_free_i64(addr2
);
2285 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2286 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2289 memop
|= size
| MO_ALIGN
;
2290 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2291 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2293 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2296 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2297 TCGv_i64 addr
, int size
, int is_pair
)
2299 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2300 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2303 * [addr + datasize] = {Rt2};
2309 * env->exclusive_addr = -1;
2311 TCGLabel
*fail_label
= gen_new_label();
2312 TCGLabel
*done_label
= gen_new_label();
2315 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2317 tmp
= tcg_temp_new_i64();
2320 if (s
->be_data
== MO_LE
) {
2321 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2323 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2325 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2326 cpu_exclusive_val
, tmp
,
2328 MO_64
| MO_ALIGN
| s
->be_data
);
2329 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2330 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2331 if (!HAVE_CMPXCHG128
) {
2332 gen_helper_exit_atomic(cpu_env
);
2333 s
->base
.is_jmp
= DISAS_NORETURN
;
2334 } else if (s
->be_data
== MO_LE
) {
2335 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2340 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2345 } else if (s
->be_data
== MO_LE
) {
2346 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2347 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2349 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2350 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2353 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2354 cpu_reg(s
, rt
), get_mem_index(s
),
2355 size
| MO_ALIGN
| s
->be_data
);
2356 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2358 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2359 tcg_temp_free_i64(tmp
);
2360 tcg_gen_br(done_label
);
2362 gen_set_label(fail_label
);
2363 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2364 gen_set_label(done_label
);
2365 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2368 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2371 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2372 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2373 int memidx
= get_mem_index(s
);
2374 TCGv_i64 clean_addr
;
2377 gen_check_sp_alignment(s
);
2379 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2380 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2381 size
| MO_ALIGN
| s
->be_data
);
2384 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2387 TCGv_i64 s1
= cpu_reg(s
, rs
);
2388 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2389 TCGv_i64 t1
= cpu_reg(s
, rt
);
2390 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2391 TCGv_i64 clean_addr
;
2392 int memidx
= get_mem_index(s
);
2395 gen_check_sp_alignment(s
);
2397 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2400 TCGv_i64 cmp
= tcg_temp_new_i64();
2401 TCGv_i64 val
= tcg_temp_new_i64();
2403 if (s
->be_data
== MO_LE
) {
2404 tcg_gen_concat32_i64(val
, t1
, t2
);
2405 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2407 tcg_gen_concat32_i64(val
, t2
, t1
);
2408 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2411 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2412 MO_64
| MO_ALIGN
| s
->be_data
);
2413 tcg_temp_free_i64(val
);
2415 if (s
->be_data
== MO_LE
) {
2416 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2418 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2420 tcg_temp_free_i64(cmp
);
2421 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2422 if (HAVE_CMPXCHG128
) {
2423 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2424 if (s
->be_data
== MO_LE
) {
2425 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2426 clean_addr
, t1
, t2
);
2428 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2429 clean_addr
, t1
, t2
);
2431 tcg_temp_free_i32(tcg_rs
);
2433 gen_helper_exit_atomic(cpu_env
);
2434 s
->base
.is_jmp
= DISAS_NORETURN
;
2437 TCGv_i64 d1
= tcg_temp_new_i64();
2438 TCGv_i64 d2
= tcg_temp_new_i64();
2439 TCGv_i64 a2
= tcg_temp_new_i64();
2440 TCGv_i64 c1
= tcg_temp_new_i64();
2441 TCGv_i64 c2
= tcg_temp_new_i64();
2442 TCGv_i64 zero
= tcg_const_i64(0);
2444 /* Load the two words, in memory order. */
2445 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2446 MO_64
| MO_ALIGN_16
| s
->be_data
);
2447 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2448 tcg_gen_qemu_ld_i64(d2
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2450 /* Compare the two words, also in memory order. */
2451 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2452 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2453 tcg_gen_and_i64(c2
, c2
, c1
);
2455 /* If compare equal, write back new data, else write back old data. */
2456 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2457 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2458 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2459 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2460 tcg_temp_free_i64(a2
);
2461 tcg_temp_free_i64(c1
);
2462 tcg_temp_free_i64(c2
);
2463 tcg_temp_free_i64(zero
);
2465 /* Write back the data from memory to Rs. */
2466 tcg_gen_mov_i64(s1
, d1
);
2467 tcg_gen_mov_i64(s2
, d2
);
2468 tcg_temp_free_i64(d1
);
2469 tcg_temp_free_i64(d2
);
2473 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2474 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2476 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2478 int opc0
= extract32(opc
, 0, 1);
2482 regsize
= opc0
? 32 : 64;
2484 regsize
= size
== 3 ? 64 : 32;
2486 return regsize
== 64;
2489 /* Load/store exclusive
2491 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2492 * +-----+-------------+----+---+----+------+----+-------+------+------+
2493 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2494 * +-----+-------------+----+---+----+------+----+-------+------+------+
2496 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2497 * L: 0 -> store, 1 -> load
2498 * o2: 0 -> exclusive, 1 -> not
2499 * o1: 0 -> single register, 1 -> register pair
2500 * o0: 1 -> load-acquire/store-release, 0 -> not
2502 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2504 int rt
= extract32(insn
, 0, 5);
2505 int rn
= extract32(insn
, 5, 5);
2506 int rt2
= extract32(insn
, 10, 5);
2507 int rs
= extract32(insn
, 16, 5);
2508 int is_lasr
= extract32(insn
, 15, 1);
2509 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2510 int size
= extract32(insn
, 30, 2);
2511 TCGv_i64 clean_addr
;
2513 switch (o2_L_o1_o0
) {
2514 case 0x0: /* STXR */
2515 case 0x1: /* STLXR */
2517 gen_check_sp_alignment(s
);
2520 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2522 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2523 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2526 case 0x4: /* LDXR */
2527 case 0x5: /* LDAXR */
2529 gen_check_sp_alignment(s
);
2531 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2533 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2535 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2539 case 0x8: /* STLLR */
2540 if (!dc_isar_feature(aa64_lor
, s
)) {
2543 /* StoreLORelease is the same as Store-Release for QEMU. */
2545 case 0x9: /* STLR */
2546 /* Generate ISS for non-exclusive accesses including LASR. */
2548 gen_check_sp_alignment(s
);
2550 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2551 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2552 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2553 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2556 case 0xc: /* LDLAR */
2557 if (!dc_isar_feature(aa64_lor
, s
)) {
2560 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2562 case 0xd: /* LDAR */
2563 /* Generate ISS for non-exclusive accesses including LASR. */
2565 gen_check_sp_alignment(s
);
2567 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2568 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2569 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2570 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2573 case 0x2: case 0x3: /* CASP / STXP */
2574 if (size
& 2) { /* STXP / STLXP */
2576 gen_check_sp_alignment(s
);
2579 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2581 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2582 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2586 && ((rt
| rs
) & 1) == 0
2587 && dc_isar_feature(aa64_atomics
, s
)) {
2589 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2594 case 0x6: case 0x7: /* CASPA / LDXP */
2595 if (size
& 2) { /* LDXP / LDAXP */
2597 gen_check_sp_alignment(s
);
2599 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2601 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2603 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2608 && ((rt
| rs
) & 1) == 0
2609 && dc_isar_feature(aa64_atomics
, s
)) {
2610 /* CASPA / CASPAL */
2611 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2617 case 0xb: /* CASL */
2618 case 0xe: /* CASA */
2619 case 0xf: /* CASAL */
2620 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2621 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2626 unallocated_encoding(s
);
2630 * Load register (literal)
2632 * 31 30 29 27 26 25 24 23 5 4 0
2633 * +-----+-------+---+-----+-------------------+-------+
2634 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2635 * +-----+-------+---+-----+-------------------+-------+
2637 * V: 1 -> vector (simd/fp)
2638 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2639 * 10-> 32 bit signed, 11 -> prefetch
2640 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2642 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2644 int rt
= extract32(insn
, 0, 5);
2645 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2646 bool is_vector
= extract32(insn
, 26, 1);
2647 int opc
= extract32(insn
, 30, 2);
2648 bool is_signed
= false;
2650 TCGv_i64 tcg_rt
, clean_addr
;
2654 unallocated_encoding(s
);
2658 if (!fp_access_check(s
)) {
2663 /* PRFM (literal) : prefetch */
2666 size
= 2 + extract32(opc
, 0, 1);
2667 is_signed
= extract32(opc
, 1, 1);
2670 tcg_rt
= cpu_reg(s
, rt
);
2672 clean_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2674 do_fp_ld(s
, rt
, clean_addr
, size
);
2676 /* Only unsigned 32bit loads target 32bit registers. */
2677 bool iss_sf
= opc
!= 0;
2679 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2680 true, rt
, iss_sf
, false);
2682 tcg_temp_free_i64(clean_addr
);
2686 * LDNP (Load Pair - non-temporal hint)
2687 * LDP (Load Pair - non vector)
2688 * LDPSW (Load Pair Signed Word - non vector)
2689 * STNP (Store Pair - non-temporal hint)
2690 * STP (Store Pair - non vector)
2691 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2692 * LDP (Load Pair of SIMD&FP)
2693 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2694 * STP (Store Pair of SIMD&FP)
2696 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2697 * +-----+-------+---+---+-------+---+-----------------------------+
2698 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2699 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2701 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2703 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2704 * V: 0 -> GPR, 1 -> Vector
2705 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2706 * 10 -> signed offset, 11 -> pre-index
2707 * L: 0 -> Store 1 -> Load
2709 * Rt, Rt2 = GPR or SIMD registers to be stored
2710 * Rn = general purpose register containing address
2711 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2713 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2715 int rt
= extract32(insn
, 0, 5);
2716 int rn
= extract32(insn
, 5, 5);
2717 int rt2
= extract32(insn
, 10, 5);
2718 uint64_t offset
= sextract64(insn
, 15, 7);
2719 int index
= extract32(insn
, 23, 2);
2720 bool is_vector
= extract32(insn
, 26, 1);
2721 bool is_load
= extract32(insn
, 22, 1);
2722 int opc
= extract32(insn
, 30, 2);
2724 bool is_signed
= false;
2725 bool postindex
= false;
2728 TCGv_i64 clean_addr
, dirty_addr
;
2733 unallocated_encoding(s
);
2740 size
= 2 + extract32(opc
, 1, 1);
2741 is_signed
= extract32(opc
, 0, 1);
2742 if (!is_load
&& is_signed
) {
2743 unallocated_encoding(s
);
2749 case 1: /* post-index */
2754 /* signed offset with "non-temporal" hint. Since we don't emulate
2755 * caches we don't care about hints to the cache system about
2756 * data access patterns, and handle this identically to plain
2760 /* There is no non-temporal-hint version of LDPSW */
2761 unallocated_encoding(s
);
2766 case 2: /* signed offset, rn not updated */
2769 case 3: /* pre-index */
2775 if (is_vector
&& !fp_access_check(s
)) {
2782 gen_check_sp_alignment(s
);
2785 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2787 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2789 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2793 do_fp_ld(s
, rt
, clean_addr
, size
);
2795 do_fp_st(s
, rt
, clean_addr
, size
);
2797 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2799 do_fp_ld(s
, rt2
, clean_addr
, size
);
2801 do_fp_st(s
, rt2
, clean_addr
, size
);
2804 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2805 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2808 TCGv_i64 tmp
= tcg_temp_new_i64();
2810 /* Do not modify tcg_rt before recognizing any exception
2811 * from the second load.
2813 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2814 false, 0, false, false);
2815 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2816 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2817 false, 0, false, false);
2819 tcg_gen_mov_i64(tcg_rt
, tmp
);
2820 tcg_temp_free_i64(tmp
);
2822 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2823 false, 0, false, false);
2824 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2825 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2826 false, 0, false, false);
2832 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2834 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2839 * Load/store (immediate post-indexed)
2840 * Load/store (immediate pre-indexed)
2841 * Load/store (unscaled immediate)
2843 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2844 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2845 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2846 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2848 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2850 * V = 0 -> non-vector
2851 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2852 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2854 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2860 int rn
= extract32(insn
, 5, 5);
2861 int imm9
= sextract32(insn
, 12, 9);
2862 int idx
= extract32(insn
, 10, 2);
2863 bool is_signed
= false;
2864 bool is_store
= false;
2865 bool is_extended
= false;
2866 bool is_unpriv
= (idx
== 2);
2867 bool iss_valid
= !is_vector
;
2871 TCGv_i64 clean_addr
, dirty_addr
;
2874 size
|= (opc
& 2) << 1;
2875 if (size
> 4 || is_unpriv
) {
2876 unallocated_encoding(s
);
2879 is_store
= ((opc
& 1) == 0);
2880 if (!fp_access_check(s
)) {
2884 if (size
== 3 && opc
== 2) {
2885 /* PRFM - prefetch */
2887 unallocated_encoding(s
);
2892 if (opc
== 3 && size
> 1) {
2893 unallocated_encoding(s
);
2896 is_store
= (opc
== 0);
2897 is_signed
= extract32(opc
, 1, 1);
2898 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2916 g_assert_not_reached();
2920 gen_check_sp_alignment(s
);
2923 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2925 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2927 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2931 do_fp_st(s
, rt
, clean_addr
, size
);
2933 do_fp_ld(s
, rt
, clean_addr
, size
);
2936 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2937 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2938 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2941 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2942 iss_valid
, rt
, iss_sf
, false);
2944 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2945 is_signed
, is_extended
, memidx
,
2946 iss_valid
, rt
, iss_sf
, false);
2951 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2953 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2955 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2960 * Load/store (register offset)
2962 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2963 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2964 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2965 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2968 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2969 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2971 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2972 * opc<0>: 0 -> store, 1 -> load
2973 * V: 1 -> vector/simd
2974 * opt: extend encoding (see DecodeRegExtend)
2975 * S: if S=1 then scale (essentially index by sizeof(size))
2976 * Rt: register to transfer into/out of
2977 * Rn: address register or SP for base
2978 * Rm: offset register or ZR for offset
2980 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2986 int rn
= extract32(insn
, 5, 5);
2987 int shift
= extract32(insn
, 12, 1);
2988 int rm
= extract32(insn
, 16, 5);
2989 int opt
= extract32(insn
, 13, 3);
2990 bool is_signed
= false;
2991 bool is_store
= false;
2992 bool is_extended
= false;
2994 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2996 if (extract32(opt
, 1, 1) == 0) {
2997 unallocated_encoding(s
);
3002 size
|= (opc
& 2) << 1;
3004 unallocated_encoding(s
);
3007 is_store
= !extract32(opc
, 0, 1);
3008 if (!fp_access_check(s
)) {
3012 if (size
== 3 && opc
== 2) {
3013 /* PRFM - prefetch */
3016 if (opc
== 3 && size
> 1) {
3017 unallocated_encoding(s
);
3020 is_store
= (opc
== 0);
3021 is_signed
= extract32(opc
, 1, 1);
3022 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3026 gen_check_sp_alignment(s
);
3028 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3030 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3031 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3033 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3034 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3038 do_fp_st(s
, rt
, clean_addr
, size
);
3040 do_fp_ld(s
, rt
, clean_addr
, size
);
3043 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3044 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3046 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3047 true, rt
, iss_sf
, false);
3049 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3050 is_signed
, is_extended
,
3051 true, rt
, iss_sf
, false);
3057 * Load/store (unsigned immediate)
3059 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3060 * +----+-------+---+-----+-----+------------+-------+------+
3061 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3062 * +----+-------+---+-----+-----+------------+-------+------+
3065 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3066 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3068 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3069 * opc<0>: 0 -> store, 1 -> load
3070 * Rn: base address register (inc SP)
3071 * Rt: target register
3073 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3079 int rn
= extract32(insn
, 5, 5);
3080 unsigned int imm12
= extract32(insn
, 10, 12);
3081 unsigned int offset
;
3083 TCGv_i64 clean_addr
, dirty_addr
;
3086 bool is_signed
= false;
3087 bool is_extended
= false;
3090 size
|= (opc
& 2) << 1;
3092 unallocated_encoding(s
);
3095 is_store
= !extract32(opc
, 0, 1);
3096 if (!fp_access_check(s
)) {
3100 if (size
== 3 && opc
== 2) {
3101 /* PRFM - prefetch */
3104 if (opc
== 3 && size
> 1) {
3105 unallocated_encoding(s
);
3108 is_store
= (opc
== 0);
3109 is_signed
= extract32(opc
, 1, 1);
3110 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3114 gen_check_sp_alignment(s
);
3116 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3117 offset
= imm12
<< size
;
3118 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3119 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3123 do_fp_st(s
, rt
, clean_addr
, size
);
3125 do_fp_ld(s
, rt
, clean_addr
, size
);
3128 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3129 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3131 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3132 true, rt
, iss_sf
, false);
3134 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3135 true, rt
, iss_sf
, false);
3140 /* Atomic memory operations
3142 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3143 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3144 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3145 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3147 * Rt: the result register
3148 * Rn: base address or SP
3149 * Rs: the source register for the operation
3150 * V: vector flag (always 0 as of v8.3)
3154 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3155 int size
, int rt
, bool is_vector
)
3157 int rs
= extract32(insn
, 16, 5);
3158 int rn
= extract32(insn
, 5, 5);
3159 int o3_opc
= extract32(insn
, 12, 4);
3160 TCGv_i64 tcg_rs
, clean_addr
;
3161 AtomicThreeOpFn
*fn
;
3163 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3164 unallocated_encoding(s
);
3168 case 000: /* LDADD */
3169 fn
= tcg_gen_atomic_fetch_add_i64
;
3171 case 001: /* LDCLR */
3172 fn
= tcg_gen_atomic_fetch_and_i64
;
3174 case 002: /* LDEOR */
3175 fn
= tcg_gen_atomic_fetch_xor_i64
;
3177 case 003: /* LDSET */
3178 fn
= tcg_gen_atomic_fetch_or_i64
;
3180 case 004: /* LDSMAX */
3181 fn
= tcg_gen_atomic_fetch_smax_i64
;
3183 case 005: /* LDSMIN */
3184 fn
= tcg_gen_atomic_fetch_smin_i64
;
3186 case 006: /* LDUMAX */
3187 fn
= tcg_gen_atomic_fetch_umax_i64
;
3189 case 007: /* LDUMIN */
3190 fn
= tcg_gen_atomic_fetch_umin_i64
;
3193 fn
= tcg_gen_atomic_xchg_i64
;
3196 unallocated_encoding(s
);
3201 gen_check_sp_alignment(s
);
3203 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3204 tcg_rs
= read_cpu_reg(s
, rs
, true);
3206 if (o3_opc
== 1) { /* LDCLR */
3207 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3210 /* The tcg atomic primitives are all full barriers. Therefore we
3211 * can ignore the Acquire and Release bits of this instruction.
3213 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3214 s
->be_data
| size
| MO_ALIGN
);
3218 * PAC memory operations
3220 * 31 30 27 26 24 22 21 12 11 10 5 0
3221 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3222 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3223 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3225 * Rt: the result register
3226 * Rn: base address or SP
3227 * V: vector flag (always 0 as of v8.3)
3228 * M: clear for key DA, set for key DB
3229 * W: pre-indexing flag
3232 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3233 int size
, int rt
, bool is_vector
)
3235 int rn
= extract32(insn
, 5, 5);
3236 bool is_wback
= extract32(insn
, 11, 1);
3237 bool use_key_a
= !extract32(insn
, 23, 1);
3239 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3241 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3242 unallocated_encoding(s
);
3247 gen_check_sp_alignment(s
);
3249 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3251 if (s
->pauth_active
) {
3253 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3255 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3259 /* Form the 10-bit signed, scaled offset. */
3260 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3261 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3262 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3264 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3265 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3267 tcg_rt
= cpu_reg(s
, rt
);
3268 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3269 /* extend */ false, /* iss_valid */ !is_wback
,
3270 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3273 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3277 /* Load/store register (all forms) */
3278 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3280 int rt
= extract32(insn
, 0, 5);
3281 int opc
= extract32(insn
, 22, 2);
3282 bool is_vector
= extract32(insn
, 26, 1);
3283 int size
= extract32(insn
, 30, 2);
3285 switch (extract32(insn
, 24, 2)) {
3287 if (extract32(insn
, 21, 1) == 0) {
3288 /* Load/store register (unscaled immediate)
3289 * Load/store immediate pre/post-indexed
3290 * Load/store register unprivileged
3292 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3295 switch (extract32(insn
, 10, 2)) {
3297 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3300 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3303 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3308 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3311 unallocated_encoding(s
);
3314 /* AdvSIMD load/store multiple structures
3316 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3317 * +---+---+---------------+---+-------------+--------+------+------+------+
3318 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3319 * +---+---+---------------+---+-------------+--------+------+------+------+
3321 * AdvSIMD load/store multiple structures (post-indexed)
3323 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3324 * +---+---+---------------+---+---+---------+--------+------+------+------+
3325 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3326 * +---+---+---------------+---+---+---------+--------+------+------+------+
3328 * Rt: first (or only) SIMD&FP register to be transferred
3329 * Rn: base address or SP
3330 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3332 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3334 int rt
= extract32(insn
, 0, 5);
3335 int rn
= extract32(insn
, 5, 5);
3336 int rm
= extract32(insn
, 16, 5);
3337 int size
= extract32(insn
, 10, 2);
3338 int opcode
= extract32(insn
, 12, 4);
3339 bool is_store
= !extract32(insn
, 22, 1);
3340 bool is_postidx
= extract32(insn
, 23, 1);
3341 bool is_q
= extract32(insn
, 30, 1);
3342 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3343 TCGMemOp endian
= s
->be_data
;
3345 int ebytes
; /* bytes per element */
3346 int elements
; /* elements per vector */
3347 int rpt
; /* num iterations */
3348 int selem
; /* structure elements */
3351 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3352 unallocated_encoding(s
);
3356 if (!is_postidx
&& rm
!= 0) {
3357 unallocated_encoding(s
);
3361 /* From the shared decode logic */
3392 unallocated_encoding(s
);
3396 if (size
== 3 && !is_q
&& selem
!= 1) {
3398 unallocated_encoding(s
);
3402 if (!fp_access_check(s
)) {
3407 gen_check_sp_alignment(s
);
3410 /* For our purposes, bytes are always little-endian. */
3415 /* Consecutive little-endian elements from a single register
3416 * can be promoted to a larger little-endian operation.
3418 if (selem
== 1 && endian
== MO_LE
) {
3422 elements
= (is_q
? 16 : 8) / ebytes
;
3424 tcg_rn
= cpu_reg_sp(s
, rn
);
3425 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3426 tcg_ebytes
= tcg_const_i64(ebytes
);
3428 for (r
= 0; r
< rpt
; r
++) {
3430 for (e
= 0; e
< elements
; e
++) {
3432 for (xs
= 0; xs
< selem
; xs
++) {
3433 int tt
= (rt
+ r
+ xs
) % 32;
3435 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3437 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3439 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3443 tcg_temp_free_i64(tcg_ebytes
);
3446 /* For non-quad operations, setting a slice of the low
3447 * 64 bits of the register clears the high 64 bits (in
3448 * the ARM ARM pseudocode this is implicit in the fact
3449 * that 'rval' is a 64 bit wide variable).
3450 * For quad operations, we might still need to zero the
3453 for (r
= 0; r
< rpt
* selem
; r
++) {
3454 int tt
= (rt
+ r
) % 32;
3455 clear_vec_high(s
, is_q
, tt
);
3461 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3463 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3468 /* AdvSIMD load/store single structure
3470 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3471 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3472 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3473 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3475 * AdvSIMD load/store single structure (post-indexed)
3477 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3478 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3479 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3480 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3482 * Rt: first (or only) SIMD&FP register to be transferred
3483 * Rn: base address or SP
3484 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3485 * index = encoded in Q:S:size dependent on size
3487 * lane_size = encoded in R, opc
3488 * transfer width = encoded in opc, S, size
3490 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3492 int rt
= extract32(insn
, 0, 5);
3493 int rn
= extract32(insn
, 5, 5);
3494 int rm
= extract32(insn
, 16, 5);
3495 int size
= extract32(insn
, 10, 2);
3496 int S
= extract32(insn
, 12, 1);
3497 int opc
= extract32(insn
, 13, 3);
3498 int R
= extract32(insn
, 21, 1);
3499 int is_load
= extract32(insn
, 22, 1);
3500 int is_postidx
= extract32(insn
, 23, 1);
3501 int is_q
= extract32(insn
, 30, 1);
3503 int scale
= extract32(opc
, 1, 2);
3504 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3505 bool replicate
= false;
3506 int index
= is_q
<< 3 | S
<< 2 | size
;
3508 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3510 if (extract32(insn
, 31, 1)) {
3511 unallocated_encoding(s
);
3514 if (!is_postidx
&& rm
!= 0) {
3515 unallocated_encoding(s
);
3521 if (!is_load
|| S
) {
3522 unallocated_encoding(s
);
3531 if (extract32(size
, 0, 1)) {
3532 unallocated_encoding(s
);
3538 if (extract32(size
, 1, 1)) {
3539 unallocated_encoding(s
);
3542 if (!extract32(size
, 0, 1)) {
3546 unallocated_encoding(s
);
3554 g_assert_not_reached();
3557 if (!fp_access_check(s
)) {
3561 ebytes
= 1 << scale
;
3564 gen_check_sp_alignment(s
);
3567 tcg_rn
= cpu_reg_sp(s
, rn
);
3568 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3569 tcg_ebytes
= tcg_const_i64(ebytes
);
3571 for (xs
= 0; xs
< selem
; xs
++) {
3573 /* Load and replicate to all elements */
3574 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3576 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3577 get_mem_index(s
), s
->be_data
+ scale
);
3578 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3579 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3581 tcg_temp_free_i64(tcg_tmp
);
3583 /* Load/store one element per register */
3585 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3587 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3590 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3593 tcg_temp_free_i64(tcg_ebytes
);
3597 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3599 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3604 /* Loads and stores */
3605 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3607 switch (extract32(insn
, 24, 6)) {
3608 case 0x08: /* Load/store exclusive */
3609 disas_ldst_excl(s
, insn
);
3611 case 0x18: case 0x1c: /* Load register (literal) */
3612 disas_ld_lit(s
, insn
);
3614 case 0x28: case 0x29:
3615 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3616 disas_ldst_pair(s
, insn
);
3618 case 0x38: case 0x39:
3619 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3620 disas_ldst_reg(s
, insn
);
3622 case 0x0c: /* AdvSIMD load/store multiple structures */
3623 disas_ldst_multiple_struct(s
, insn
);
3625 case 0x0d: /* AdvSIMD load/store single structure */
3626 disas_ldst_single_struct(s
, insn
);
3629 unallocated_encoding(s
);
3634 /* PC-rel. addressing
3635 * 31 30 29 28 24 23 5 4 0
3636 * +----+-------+-----------+-------------------+------+
3637 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3638 * +----+-------+-----------+-------------------+------+
3640 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3642 unsigned int page
, rd
;
3646 page
= extract32(insn
, 31, 1);
3647 /* SignExtend(immhi:immlo) -> offset */
3648 offset
= sextract64(insn
, 5, 19);
3649 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3650 rd
= extract32(insn
, 0, 5);
3654 /* ADRP (page based) */
3659 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3663 * Add/subtract (immediate)
3665 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3666 * +--+--+--+-----------+-----+-------------+-----+-----+
3667 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3668 * +--+--+--+-----------+-----+-------------+-----+-----+
3670 * sf: 0 -> 32bit, 1 -> 64bit
3671 * op: 0 -> add , 1 -> sub
3673 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3675 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3677 int rd
= extract32(insn
, 0, 5);
3678 int rn
= extract32(insn
, 5, 5);
3679 uint64_t imm
= extract32(insn
, 10, 12);
3680 int shift
= extract32(insn
, 22, 2);
3681 bool setflags
= extract32(insn
, 29, 1);
3682 bool sub_op
= extract32(insn
, 30, 1);
3683 bool is_64bit
= extract32(insn
, 31, 1);
3685 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3686 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3687 TCGv_i64 tcg_result
;
3696 unallocated_encoding(s
);
3700 tcg_result
= tcg_temp_new_i64();
3703 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3705 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3708 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3710 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3712 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3714 tcg_temp_free_i64(tcg_imm
);
3718 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3720 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3723 tcg_temp_free_i64(tcg_result
);
3726 /* The input should be a value in the bottom e bits (with higher
3727 * bits zero); returns that value replicated into every element
3728 * of size e in a 64 bit integer.
3730 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3740 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3741 static inline uint64_t bitmask64(unsigned int length
)
3743 assert(length
> 0 && length
<= 64);
3744 return ~0ULL >> (64 - length
);
3747 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3748 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3749 * value (ie should cause a guest UNDEF exception), and true if they are
3750 * valid, in which case the decoded bit pattern is written to result.
3752 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3753 unsigned int imms
, unsigned int immr
)
3756 unsigned e
, levels
, s
, r
;
3759 assert(immn
< 2 && imms
< 64 && immr
< 64);
3761 /* The bit patterns we create here are 64 bit patterns which
3762 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3763 * 64 bits each. Each element contains the same value: a run
3764 * of between 1 and e-1 non-zero bits, rotated within the
3765 * element by between 0 and e-1 bits.
3767 * The element size and run length are encoded into immn (1 bit)
3768 * and imms (6 bits) as follows:
3769 * 64 bit elements: immn = 1, imms = <length of run - 1>
3770 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3771 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3772 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3773 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3774 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3775 * Notice that immn = 0, imms = 11111x is the only combination
3776 * not covered by one of the above options; this is reserved.
3777 * Further, <length of run - 1> all-ones is a reserved pattern.
3779 * In all cases the rotation is by immr % e (and immr is 6 bits).
3782 /* First determine the element size */
3783 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3785 /* This is the immn == 0, imms == 0x11111x case */
3795 /* <length of run - 1> mustn't be all-ones. */
3799 /* Create the value of one element: s+1 set bits rotated
3800 * by r within the element (which is e bits wide)...
3802 mask
= bitmask64(s
+ 1);
3804 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3805 mask
&= bitmask64(e
);
3807 /* ...then replicate the element over the whole 64 bit value */
3808 mask
= bitfield_replicate(mask
, e
);
3813 /* Logical (immediate)
3814 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3815 * +----+-----+-------------+---+------+------+------+------+
3816 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3817 * +----+-----+-------------+---+------+------+------+------+
3819 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3821 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3822 TCGv_i64 tcg_rd
, tcg_rn
;
3824 bool is_and
= false;
3826 sf
= extract32(insn
, 31, 1);
3827 opc
= extract32(insn
, 29, 2);
3828 is_n
= extract32(insn
, 22, 1);
3829 immr
= extract32(insn
, 16, 6);
3830 imms
= extract32(insn
, 10, 6);
3831 rn
= extract32(insn
, 5, 5);
3832 rd
= extract32(insn
, 0, 5);
3835 unallocated_encoding(s
);
3839 if (opc
== 0x3) { /* ANDS */
3840 tcg_rd
= cpu_reg(s
, rd
);
3842 tcg_rd
= cpu_reg_sp(s
, rd
);
3844 tcg_rn
= cpu_reg(s
, rn
);
3846 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3847 /* some immediate field values are reserved */
3848 unallocated_encoding(s
);
3853 wmask
&= 0xffffffff;
3857 case 0x3: /* ANDS */
3859 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3863 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3866 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3869 assert(FALSE
); /* must handle all above */
3873 if (!sf
&& !is_and
) {
3874 /* zero extend final result; we know we can skip this for AND
3875 * since the immediate had the high 32 bits clear.
3877 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3880 if (opc
== 3) { /* ANDS */
3881 gen_logic_CC(sf
, tcg_rd
);
3886 * Move wide (immediate)
3888 * 31 30 29 28 23 22 21 20 5 4 0
3889 * +--+-----+-------------+-----+----------------+------+
3890 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3891 * +--+-----+-------------+-----+----------------+------+
3893 * sf: 0 -> 32 bit, 1 -> 64 bit
3894 * opc: 00 -> N, 10 -> Z, 11 -> K
3895 * hw: shift/16 (0,16, and sf only 32, 48)
3897 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3899 int rd
= extract32(insn
, 0, 5);
3900 uint64_t imm
= extract32(insn
, 5, 16);
3901 int sf
= extract32(insn
, 31, 1);
3902 int opc
= extract32(insn
, 29, 2);
3903 int pos
= extract32(insn
, 21, 2) << 4;
3904 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3907 if (!sf
&& (pos
>= 32)) {
3908 unallocated_encoding(s
);
3922 tcg_gen_movi_i64(tcg_rd
, imm
);
3925 tcg_imm
= tcg_const_i64(imm
);
3926 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3927 tcg_temp_free_i64(tcg_imm
);
3929 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3933 unallocated_encoding(s
);
3939 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3940 * +----+-----+-------------+---+------+------+------+------+
3941 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3942 * +----+-----+-------------+---+------+------+------+------+
3944 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3946 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3947 TCGv_i64 tcg_rd
, tcg_tmp
;
3949 sf
= extract32(insn
, 31, 1);
3950 opc
= extract32(insn
, 29, 2);
3951 n
= extract32(insn
, 22, 1);
3952 ri
= extract32(insn
, 16, 6);
3953 si
= extract32(insn
, 10, 6);
3954 rn
= extract32(insn
, 5, 5);
3955 rd
= extract32(insn
, 0, 5);
3956 bitsize
= sf
? 64 : 32;
3958 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3959 unallocated_encoding(s
);
3963 tcg_rd
= cpu_reg(s
, rd
);
3965 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3966 to be smaller than bitsize, we'll never reference data outside the
3967 low 32-bits anyway. */
3968 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3970 /* Recognize simple(r) extractions. */
3972 /* Wd<s-r:0> = Wn<s:r> */
3973 len
= (si
- ri
) + 1;
3974 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3975 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3977 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3978 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3981 /* opc == 1, BXFIL fall through to deposit */
3982 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3985 /* Handle the ri > si case with a deposit
3986 * Wd<32+s-r,32-r> = Wn<s:0>
3989 pos
= (bitsize
- ri
) & (bitsize
- 1);
3992 if (opc
== 0 && len
< ri
) {
3993 /* SBFM: sign extend the destination field from len to fill
3994 the balance of the word. Let the deposit below insert all
3995 of those sign bits. */
3996 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4000 if (opc
== 1) { /* BFM, BXFIL */
4001 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4003 /* SBFM or UBFM: We start with zero, and we haven't modified
4004 any bits outside bitsize, therefore the zero-extension
4005 below is unneeded. */
4006 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4011 if (!sf
) { /* zero extend final result */
4012 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4017 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4018 * +----+------+-------------+---+----+------+--------+------+------+
4019 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4020 * +----+------+-------------+---+----+------+--------+------+------+
4022 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4024 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4026 sf
= extract32(insn
, 31, 1);
4027 n
= extract32(insn
, 22, 1);
4028 rm
= extract32(insn
, 16, 5);
4029 imm
= extract32(insn
, 10, 6);
4030 rn
= extract32(insn
, 5, 5);
4031 rd
= extract32(insn
, 0, 5);
4032 op21
= extract32(insn
, 29, 2);
4033 op0
= extract32(insn
, 21, 1);
4034 bitsize
= sf
? 64 : 32;
4036 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4037 unallocated_encoding(s
);
4039 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4041 tcg_rd
= cpu_reg(s
, rd
);
4043 if (unlikely(imm
== 0)) {
4044 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4045 * so an extract from bit 0 is a special case.
4048 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4050 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4052 } else if (rm
== rn
) { /* ROR */
4053 tcg_rm
= cpu_reg(s
, rm
);
4055 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
4057 TCGv_i32 tmp
= tcg_temp_new_i32();
4058 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
4059 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
4060 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
4061 tcg_temp_free_i32(tmp
);
4064 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4065 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4066 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
4067 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
4068 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
4070 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4076 /* Data processing - immediate */
4077 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4079 switch (extract32(insn
, 23, 6)) {
4080 case 0x20: case 0x21: /* PC-rel. addressing */
4081 disas_pc_rel_adr(s
, insn
);
4083 case 0x22: case 0x23: /* Add/subtract (immediate) */
4084 disas_add_sub_imm(s
, insn
);
4086 case 0x24: /* Logical (immediate) */
4087 disas_logic_imm(s
, insn
);
4089 case 0x25: /* Move wide (immediate) */
4090 disas_movw_imm(s
, insn
);
4092 case 0x26: /* Bitfield */
4093 disas_bitfield(s
, insn
);
4095 case 0x27: /* Extract */
4096 disas_extract(s
, insn
);
4099 unallocated_encoding(s
);
4104 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4105 * Note that it is the caller's responsibility to ensure that the
4106 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4107 * mandated semantics for out of range shifts.
4109 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4110 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4112 switch (shift_type
) {
4113 case A64_SHIFT_TYPE_LSL
:
4114 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4116 case A64_SHIFT_TYPE_LSR
:
4117 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4119 case A64_SHIFT_TYPE_ASR
:
4121 tcg_gen_ext32s_i64(dst
, src
);
4123 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4125 case A64_SHIFT_TYPE_ROR
:
4127 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4130 t0
= tcg_temp_new_i32();
4131 t1
= tcg_temp_new_i32();
4132 tcg_gen_extrl_i64_i32(t0
, src
);
4133 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4134 tcg_gen_rotr_i32(t0
, t0
, t1
);
4135 tcg_gen_extu_i32_i64(dst
, t0
);
4136 tcg_temp_free_i32(t0
);
4137 tcg_temp_free_i32(t1
);
4141 assert(FALSE
); /* all shift types should be handled */
4145 if (!sf
) { /* zero extend final result */
4146 tcg_gen_ext32u_i64(dst
, dst
);
4150 /* Shift a TCGv src by immediate, put result in dst.
4151 * The shift amount must be in range (this should always be true as the
4152 * relevant instructions will UNDEF on bad shift immediates).
4154 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4155 enum a64_shift_type shift_type
, unsigned int shift_i
)
4157 assert(shift_i
< (sf
? 64 : 32));
4160 tcg_gen_mov_i64(dst
, src
);
4162 TCGv_i64 shift_const
;
4164 shift_const
= tcg_const_i64(shift_i
);
4165 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4166 tcg_temp_free_i64(shift_const
);
4170 /* Logical (shifted register)
4171 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4172 * +----+-----+-----------+-------+---+------+--------+------+------+
4173 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4174 * +----+-----+-----------+-------+---+------+--------+------+------+
4176 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4178 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4179 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4181 sf
= extract32(insn
, 31, 1);
4182 opc
= extract32(insn
, 29, 2);
4183 shift_type
= extract32(insn
, 22, 2);
4184 invert
= extract32(insn
, 21, 1);
4185 rm
= extract32(insn
, 16, 5);
4186 shift_amount
= extract32(insn
, 10, 6);
4187 rn
= extract32(insn
, 5, 5);
4188 rd
= extract32(insn
, 0, 5);
4190 if (!sf
&& (shift_amount
& (1 << 5))) {
4191 unallocated_encoding(s
);
4195 tcg_rd
= cpu_reg(s
, rd
);
4197 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4198 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4199 * register-register MOV and MVN, so it is worth special casing.
4201 tcg_rm
= cpu_reg(s
, rm
);
4203 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4205 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4209 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4211 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4217 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4220 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4223 tcg_rn
= cpu_reg(s
, rn
);
4225 switch (opc
| (invert
<< 2)) {
4228 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4231 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4234 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4238 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4241 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4244 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4252 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4256 gen_logic_CC(sf
, tcg_rd
);
4261 * Add/subtract (extended register)
4263 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4264 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4265 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4266 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4268 * sf: 0 -> 32bit, 1 -> 64bit
4269 * op: 0 -> add , 1 -> sub
4272 * option: extension type (see DecodeRegExtend)
4273 * imm3: optional shift to Rm
4275 * Rd = Rn + LSL(extend(Rm), amount)
4277 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4279 int rd
= extract32(insn
, 0, 5);
4280 int rn
= extract32(insn
, 5, 5);
4281 int imm3
= extract32(insn
, 10, 3);
4282 int option
= extract32(insn
, 13, 3);
4283 int rm
= extract32(insn
, 16, 5);
4284 int opt
= extract32(insn
, 22, 2);
4285 bool setflags
= extract32(insn
, 29, 1);
4286 bool sub_op
= extract32(insn
, 30, 1);
4287 bool sf
= extract32(insn
, 31, 1);
4289 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4291 TCGv_i64 tcg_result
;
4293 if (imm3
> 4 || opt
!= 0) {
4294 unallocated_encoding(s
);
4298 /* non-flag setting ops may use SP */
4300 tcg_rd
= cpu_reg_sp(s
, rd
);
4302 tcg_rd
= cpu_reg(s
, rd
);
4304 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4306 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4307 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4309 tcg_result
= tcg_temp_new_i64();
4313 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4315 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4319 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4321 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4326 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4328 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4331 tcg_temp_free_i64(tcg_result
);
4335 * Add/subtract (shifted register)
4337 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4338 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4339 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4340 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4342 * sf: 0 -> 32bit, 1 -> 64bit
4343 * op: 0 -> add , 1 -> sub
4345 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4346 * imm6: Shift amount to apply to Rm before the add/sub
4348 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4350 int rd
= extract32(insn
, 0, 5);
4351 int rn
= extract32(insn
, 5, 5);
4352 int imm6
= extract32(insn
, 10, 6);
4353 int rm
= extract32(insn
, 16, 5);
4354 int shift_type
= extract32(insn
, 22, 2);
4355 bool setflags
= extract32(insn
, 29, 1);
4356 bool sub_op
= extract32(insn
, 30, 1);
4357 bool sf
= extract32(insn
, 31, 1);
4359 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4360 TCGv_i64 tcg_rn
, tcg_rm
;
4361 TCGv_i64 tcg_result
;
4363 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4364 unallocated_encoding(s
);
4368 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4369 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4371 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4373 tcg_result
= tcg_temp_new_i64();
4377 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4379 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4383 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4385 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4390 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4392 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4395 tcg_temp_free_i64(tcg_result
);
4398 /* Data-processing (3 source)
4400 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4401 * +--+------+-----------+------+------+----+------+------+------+
4402 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4403 * +--+------+-----------+------+------+----+------+------+------+
4405 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4407 int rd
= extract32(insn
, 0, 5);
4408 int rn
= extract32(insn
, 5, 5);
4409 int ra
= extract32(insn
, 10, 5);
4410 int rm
= extract32(insn
, 16, 5);
4411 int op_id
= (extract32(insn
, 29, 3) << 4) |
4412 (extract32(insn
, 21, 3) << 1) |
4413 extract32(insn
, 15, 1);
4414 bool sf
= extract32(insn
, 31, 1);
4415 bool is_sub
= extract32(op_id
, 0, 1);
4416 bool is_high
= extract32(op_id
, 2, 1);
4417 bool is_signed
= false;
4422 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4424 case 0x42: /* SMADDL */
4425 case 0x43: /* SMSUBL */
4426 case 0x44: /* SMULH */
4429 case 0x0: /* MADD (32bit) */
4430 case 0x1: /* MSUB (32bit) */
4431 case 0x40: /* MADD (64bit) */
4432 case 0x41: /* MSUB (64bit) */
4433 case 0x4a: /* UMADDL */
4434 case 0x4b: /* UMSUBL */
4435 case 0x4c: /* UMULH */
4438 unallocated_encoding(s
);
4443 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4444 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4445 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4446 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4449 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4451 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4454 tcg_temp_free_i64(low_bits
);
4458 tcg_op1
= tcg_temp_new_i64();
4459 tcg_op2
= tcg_temp_new_i64();
4460 tcg_tmp
= tcg_temp_new_i64();
4463 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4464 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4467 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4468 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4470 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4471 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4475 if (ra
== 31 && !is_sub
) {
4476 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4477 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4479 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4481 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4483 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4488 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4491 tcg_temp_free_i64(tcg_op1
);
4492 tcg_temp_free_i64(tcg_op2
);
4493 tcg_temp_free_i64(tcg_tmp
);
4496 /* Add/subtract (with carry)
4497 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4498 * +--+--+--+------------------------+------+-------------+------+-----+
4499 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4500 * +--+--+--+------------------------+------+-------------+------+-----+
4503 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4505 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4506 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4508 sf
= extract32(insn
, 31, 1);
4509 op
= extract32(insn
, 30, 1);
4510 setflags
= extract32(insn
, 29, 1);
4511 rm
= extract32(insn
, 16, 5);
4512 rn
= extract32(insn
, 5, 5);
4513 rd
= extract32(insn
, 0, 5);
4515 tcg_rd
= cpu_reg(s
, rd
);
4516 tcg_rn
= cpu_reg(s
, rn
);
4519 tcg_y
= new_tmp_a64(s
);
4520 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4522 tcg_y
= cpu_reg(s
, rm
);
4526 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4528 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4532 /* Conditional compare (immediate / register)
4533 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4534 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4535 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4536 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4539 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4541 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4542 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4543 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4546 if (!extract32(insn
, 29, 1)) {
4547 unallocated_encoding(s
);
4550 if (insn
& (1 << 10 | 1 << 4)) {
4551 unallocated_encoding(s
);
4554 sf
= extract32(insn
, 31, 1);
4555 op
= extract32(insn
, 30, 1);
4556 is_imm
= extract32(insn
, 11, 1);
4557 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4558 cond
= extract32(insn
, 12, 4);
4559 rn
= extract32(insn
, 5, 5);
4560 nzcv
= extract32(insn
, 0, 4);
4562 /* Set T0 = !COND. */
4563 tcg_t0
= tcg_temp_new_i32();
4564 arm_test_cc(&c
, cond
);
4565 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4568 /* Load the arguments for the new comparison. */
4570 tcg_y
= new_tmp_a64(s
);
4571 tcg_gen_movi_i64(tcg_y
, y
);
4573 tcg_y
= cpu_reg(s
, y
);
4575 tcg_rn
= cpu_reg(s
, rn
);
4577 /* Set the flags for the new comparison. */
4578 tcg_tmp
= tcg_temp_new_i64();
4580 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4582 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4584 tcg_temp_free_i64(tcg_tmp
);
4586 /* If COND was false, force the flags to #nzcv. Compute two masks
4587 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4588 * For tcg hosts that support ANDC, we can make do with just T1.
4589 * In either case, allow the tcg optimizer to delete any unused mask.
4591 tcg_t1
= tcg_temp_new_i32();
4592 tcg_t2
= tcg_temp_new_i32();
4593 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4594 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4596 if (nzcv
& 8) { /* N */
4597 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4599 if (TCG_TARGET_HAS_andc_i32
) {
4600 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4602 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4605 if (nzcv
& 4) { /* Z */
4606 if (TCG_TARGET_HAS_andc_i32
) {
4607 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4609 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4612 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4614 if (nzcv
& 2) { /* C */
4615 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4617 if (TCG_TARGET_HAS_andc_i32
) {
4618 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4620 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4623 if (nzcv
& 1) { /* V */
4624 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4626 if (TCG_TARGET_HAS_andc_i32
) {
4627 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4629 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4632 tcg_temp_free_i32(tcg_t0
);
4633 tcg_temp_free_i32(tcg_t1
);
4634 tcg_temp_free_i32(tcg_t2
);
4637 /* Conditional select
4638 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4639 * +----+----+---+-----------------+------+------+-----+------+------+
4640 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4641 * +----+----+---+-----------------+------+------+-----+------+------+
4643 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4645 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4646 TCGv_i64 tcg_rd
, zero
;
4649 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4650 /* S == 1 or op2<1> == 1 */
4651 unallocated_encoding(s
);
4654 sf
= extract32(insn
, 31, 1);
4655 else_inv
= extract32(insn
, 30, 1);
4656 rm
= extract32(insn
, 16, 5);
4657 cond
= extract32(insn
, 12, 4);
4658 else_inc
= extract32(insn
, 10, 1);
4659 rn
= extract32(insn
, 5, 5);
4660 rd
= extract32(insn
, 0, 5);
4662 tcg_rd
= cpu_reg(s
, rd
);
4664 a64_test_cc(&c
, cond
);
4665 zero
= tcg_const_i64(0);
4667 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4669 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4671 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4674 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4675 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4676 if (else_inv
&& else_inc
) {
4677 tcg_gen_neg_i64(t_false
, t_false
);
4678 } else if (else_inv
) {
4679 tcg_gen_not_i64(t_false
, t_false
);
4680 } else if (else_inc
) {
4681 tcg_gen_addi_i64(t_false
, t_false
, 1);
4683 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4686 tcg_temp_free_i64(zero
);
4690 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4694 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4695 unsigned int rn
, unsigned int rd
)
4697 TCGv_i64 tcg_rd
, tcg_rn
;
4698 tcg_rd
= cpu_reg(s
, rd
);
4699 tcg_rn
= cpu_reg(s
, rn
);
4702 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4704 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4705 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4706 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4707 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4708 tcg_temp_free_i32(tcg_tmp32
);
4712 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4713 unsigned int rn
, unsigned int rd
)
4715 TCGv_i64 tcg_rd
, tcg_rn
;
4716 tcg_rd
= cpu_reg(s
, rd
);
4717 tcg_rn
= cpu_reg(s
, rn
);
4720 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4722 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4723 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4724 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4725 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4726 tcg_temp_free_i32(tcg_tmp32
);
4730 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4731 unsigned int rn
, unsigned int rd
)
4733 TCGv_i64 tcg_rd
, tcg_rn
;
4734 tcg_rd
= cpu_reg(s
, rd
);
4735 tcg_rn
= cpu_reg(s
, rn
);
4738 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4740 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4741 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4742 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4743 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4744 tcg_temp_free_i32(tcg_tmp32
);
4748 /* REV with sf==1, opcode==3 ("REV64") */
4749 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4750 unsigned int rn
, unsigned int rd
)
4753 unallocated_encoding(s
);
4756 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4759 /* REV with sf==0, opcode==2
4760 * REV32 (sf==1, opcode==2)
4762 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4763 unsigned int rn
, unsigned int rd
)
4765 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4768 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4769 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4771 /* bswap32_i64 requires zero high word */
4772 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4773 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4774 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4775 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4776 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4778 tcg_temp_free_i64(tcg_tmp
);
4780 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4781 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4785 /* REV16 (opcode==1) */
4786 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4787 unsigned int rn
, unsigned int rd
)
4789 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4790 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4791 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4792 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4794 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4795 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4796 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4797 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4798 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4800 tcg_temp_free_i64(mask
);
4801 tcg_temp_free_i64(tcg_tmp
);
4804 /* Data-processing (1 source)
4805 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4806 * +----+---+---+-----------------+---------+--------+------+------+
4807 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4808 * +----+---+---+-----------------+---------+--------+------+------+
4810 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4812 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4815 if (extract32(insn
, 29, 1)) {
4816 unallocated_encoding(s
);
4820 sf
= extract32(insn
, 31, 1);
4821 opcode
= extract32(insn
, 10, 6);
4822 opcode2
= extract32(insn
, 16, 5);
4823 rn
= extract32(insn
, 5, 5);
4824 rd
= extract32(insn
, 0, 5);
4826 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4828 switch (MAP(sf
, opcode2
, opcode
)) {
4829 case MAP(0, 0x00, 0x00): /* RBIT */
4830 case MAP(1, 0x00, 0x00):
4831 handle_rbit(s
, sf
, rn
, rd
);
4833 case MAP(0, 0x00, 0x01): /* REV16 */
4834 case MAP(1, 0x00, 0x01):
4835 handle_rev16(s
, sf
, rn
, rd
);
4837 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4838 case MAP(1, 0x00, 0x02):
4839 handle_rev32(s
, sf
, rn
, rd
);
4841 case MAP(1, 0x00, 0x03): /* REV64 */
4842 handle_rev64(s
, sf
, rn
, rd
);
4844 case MAP(0, 0x00, 0x04): /* CLZ */
4845 case MAP(1, 0x00, 0x04):
4846 handle_clz(s
, sf
, rn
, rd
);
4848 case MAP(0, 0x00, 0x05): /* CLS */
4849 case MAP(1, 0x00, 0x05):
4850 handle_cls(s
, sf
, rn
, rd
);
4852 case MAP(1, 0x01, 0x00): /* PACIA */
4853 if (s
->pauth_active
) {
4854 tcg_rd
= cpu_reg(s
, rd
);
4855 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4856 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4857 goto do_unallocated
;
4860 case MAP(1, 0x01, 0x01): /* PACIB */
4861 if (s
->pauth_active
) {
4862 tcg_rd
= cpu_reg(s
, rd
);
4863 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4864 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4865 goto do_unallocated
;
4868 case MAP(1, 0x01, 0x02): /* PACDA */
4869 if (s
->pauth_active
) {
4870 tcg_rd
= cpu_reg(s
, rd
);
4871 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4872 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4873 goto do_unallocated
;
4876 case MAP(1, 0x01, 0x03): /* PACDB */
4877 if (s
->pauth_active
) {
4878 tcg_rd
= cpu_reg(s
, rd
);
4879 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4880 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4881 goto do_unallocated
;
4884 case MAP(1, 0x01, 0x04): /* AUTIA */
4885 if (s
->pauth_active
) {
4886 tcg_rd
= cpu_reg(s
, rd
);
4887 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4888 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4889 goto do_unallocated
;
4892 case MAP(1, 0x01, 0x05): /* AUTIB */
4893 if (s
->pauth_active
) {
4894 tcg_rd
= cpu_reg(s
, rd
);
4895 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4896 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4897 goto do_unallocated
;
4900 case MAP(1, 0x01, 0x06): /* AUTDA */
4901 if (s
->pauth_active
) {
4902 tcg_rd
= cpu_reg(s
, rd
);
4903 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4904 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4905 goto do_unallocated
;
4908 case MAP(1, 0x01, 0x07): /* AUTDB */
4909 if (s
->pauth_active
) {
4910 tcg_rd
= cpu_reg(s
, rd
);
4911 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4912 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4913 goto do_unallocated
;
4916 case MAP(1, 0x01, 0x08): /* PACIZA */
4917 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4918 goto do_unallocated
;
4919 } else if (s
->pauth_active
) {
4920 tcg_rd
= cpu_reg(s
, rd
);
4921 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4924 case MAP(1, 0x01, 0x09): /* PACIZB */
4925 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4926 goto do_unallocated
;
4927 } else if (s
->pauth_active
) {
4928 tcg_rd
= cpu_reg(s
, rd
);
4929 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4932 case MAP(1, 0x01, 0x0a): /* PACDZA */
4933 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4934 goto do_unallocated
;
4935 } else if (s
->pauth_active
) {
4936 tcg_rd
= cpu_reg(s
, rd
);
4937 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4940 case MAP(1, 0x01, 0x0b): /* PACDZB */
4941 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4942 goto do_unallocated
;
4943 } else if (s
->pauth_active
) {
4944 tcg_rd
= cpu_reg(s
, rd
);
4945 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4948 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4949 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4950 goto do_unallocated
;
4951 } else if (s
->pauth_active
) {
4952 tcg_rd
= cpu_reg(s
, rd
);
4953 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4956 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4957 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4958 goto do_unallocated
;
4959 } else if (s
->pauth_active
) {
4960 tcg_rd
= cpu_reg(s
, rd
);
4961 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4964 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4965 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4966 goto do_unallocated
;
4967 } else if (s
->pauth_active
) {
4968 tcg_rd
= cpu_reg(s
, rd
);
4969 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4972 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4973 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4974 goto do_unallocated
;
4975 } else if (s
->pauth_active
) {
4976 tcg_rd
= cpu_reg(s
, rd
);
4977 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4980 case MAP(1, 0x01, 0x10): /* XPACI */
4981 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4982 goto do_unallocated
;
4983 } else if (s
->pauth_active
) {
4984 tcg_rd
= cpu_reg(s
, rd
);
4985 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
4988 case MAP(1, 0x01, 0x11): /* XPACD */
4989 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4990 goto do_unallocated
;
4991 } else if (s
->pauth_active
) {
4992 tcg_rd
= cpu_reg(s
, rd
);
4993 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
4998 unallocated_encoding(s
);
5005 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5006 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5008 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5009 tcg_rd
= cpu_reg(s
, rd
);
5011 if (!sf
&& is_signed
) {
5012 tcg_n
= new_tmp_a64(s
);
5013 tcg_m
= new_tmp_a64(s
);
5014 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5015 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5017 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5018 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5022 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5024 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5027 if (!sf
) { /* zero extend final result */
5028 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5032 /* LSLV, LSRV, ASRV, RORV */
5033 static void handle_shift_reg(DisasContext
*s
,
5034 enum a64_shift_type shift_type
, unsigned int sf
,
5035 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5037 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5038 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5039 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5041 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5042 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5043 tcg_temp_free_i64(tcg_shift
);
5046 /* CRC32[BHWX], CRC32C[BHWX] */
5047 static void handle_crc32(DisasContext
*s
,
5048 unsigned int sf
, unsigned int sz
, bool crc32c
,
5049 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5051 TCGv_i64 tcg_acc
, tcg_val
;
5054 if (!dc_isar_feature(aa64_crc32
, s
)
5055 || (sf
== 1 && sz
!= 3)
5056 || (sf
== 0 && sz
== 3)) {
5057 unallocated_encoding(s
);
5062 tcg_val
= cpu_reg(s
, rm
);
5076 g_assert_not_reached();
5078 tcg_val
= new_tmp_a64(s
);
5079 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5082 tcg_acc
= cpu_reg(s
, rn
);
5083 tcg_bytes
= tcg_const_i32(1 << sz
);
5086 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5088 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5091 tcg_temp_free_i32(tcg_bytes
);
5094 /* Data-processing (2 source)
5095 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5096 * +----+---+---+-----------------+------+--------+------+------+
5097 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5098 * +----+---+---+-----------------+------+--------+------+------+
5100 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5102 unsigned int sf
, rm
, opcode
, rn
, rd
;
5103 sf
= extract32(insn
, 31, 1);
5104 rm
= extract32(insn
, 16, 5);
5105 opcode
= extract32(insn
, 10, 6);
5106 rn
= extract32(insn
, 5, 5);
5107 rd
= extract32(insn
, 0, 5);
5109 if (extract32(insn
, 29, 1)) {
5110 unallocated_encoding(s
);
5116 handle_div(s
, false, sf
, rm
, rn
, rd
);
5119 handle_div(s
, true, sf
, rm
, rn
, rd
);
5122 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5125 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5128 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5131 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5133 case 12: /* PACGA */
5134 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5135 goto do_unallocated
;
5137 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5138 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5147 case 23: /* CRC32 */
5149 int sz
= extract32(opcode
, 0, 2);
5150 bool crc32c
= extract32(opcode
, 2, 1);
5151 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5156 unallocated_encoding(s
);
5162 * Data processing - register
5163 * 31 30 29 28 25 21 20 16 10 0
5164 * +--+---+--+---+-------+-----+-------+-------+---------+
5165 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5166 * +--+---+--+---+-------+-----+-------+-------+---------+
5168 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5170 int op0
= extract32(insn
, 30, 1);
5171 int op1
= extract32(insn
, 28, 1);
5172 int op2
= extract32(insn
, 21, 4);
5173 int op3
= extract32(insn
, 10, 6);
5178 /* Add/sub (extended register) */
5179 disas_add_sub_ext_reg(s
, insn
);
5181 /* Add/sub (shifted register) */
5182 disas_add_sub_reg(s
, insn
);
5185 /* Logical (shifted register) */
5186 disas_logic_reg(s
, insn
);
5194 case 0x00: /* Add/subtract (with carry) */
5195 disas_adc_sbc(s
, insn
);
5199 goto do_unallocated
;
5203 case 0x2: /* Conditional compare */
5204 disas_cc(s
, insn
); /* both imm and reg forms */
5207 case 0x4: /* Conditional select */
5208 disas_cond_select(s
, insn
);
5211 case 0x6: /* Data-processing */
5212 if (op0
) { /* (1 source) */
5213 disas_data_proc_1src(s
, insn
);
5214 } else { /* (2 source) */
5215 disas_data_proc_2src(s
, insn
);
5218 case 0x8 ... 0xf: /* (3 source) */
5219 disas_data_proc_3src(s
, insn
);
5224 unallocated_encoding(s
);
5229 static void handle_fp_compare(DisasContext
*s
, int size
,
5230 unsigned int rn
, unsigned int rm
,
5231 bool cmp_with_zero
, bool signal_all_nans
)
5233 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5234 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5236 if (size
== MO_64
) {
5237 TCGv_i64 tcg_vn
, tcg_vm
;
5239 tcg_vn
= read_fp_dreg(s
, rn
);
5240 if (cmp_with_zero
) {
5241 tcg_vm
= tcg_const_i64(0);
5243 tcg_vm
= read_fp_dreg(s
, rm
);
5245 if (signal_all_nans
) {
5246 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5248 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5250 tcg_temp_free_i64(tcg_vn
);
5251 tcg_temp_free_i64(tcg_vm
);
5253 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5254 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5256 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5257 if (cmp_with_zero
) {
5258 tcg_gen_movi_i32(tcg_vm
, 0);
5260 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5265 if (signal_all_nans
) {
5266 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5268 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5272 if (signal_all_nans
) {
5273 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5275 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5279 g_assert_not_reached();
5282 tcg_temp_free_i32(tcg_vn
);
5283 tcg_temp_free_i32(tcg_vm
);
5286 tcg_temp_free_ptr(fpst
);
5288 gen_set_nzcv(tcg_flags
);
5290 tcg_temp_free_i64(tcg_flags
);
5293 /* Floating point compare
5294 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5295 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5296 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5297 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5299 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5301 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5304 mos
= extract32(insn
, 29, 3);
5305 type
= extract32(insn
, 22, 2);
5306 rm
= extract32(insn
, 16, 5);
5307 op
= extract32(insn
, 14, 2);
5308 rn
= extract32(insn
, 5, 5);
5309 opc
= extract32(insn
, 3, 2);
5310 op2r
= extract32(insn
, 0, 3);
5312 if (mos
|| op
|| op2r
) {
5313 unallocated_encoding(s
);
5326 if (dc_isar_feature(aa64_fp16
, s
)) {
5331 unallocated_encoding(s
);
5335 if (!fp_access_check(s
)) {
5339 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5342 /* Floating point conditional compare
5343 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5344 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5345 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5346 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5348 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5350 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5352 TCGLabel
*label_continue
= NULL
;
5355 mos
= extract32(insn
, 29, 3);
5356 type
= extract32(insn
, 22, 2);
5357 rm
= extract32(insn
, 16, 5);
5358 cond
= extract32(insn
, 12, 4);
5359 rn
= extract32(insn
, 5, 5);
5360 op
= extract32(insn
, 4, 1);
5361 nzcv
= extract32(insn
, 0, 4);
5364 unallocated_encoding(s
);
5377 if (dc_isar_feature(aa64_fp16
, s
)) {
5382 unallocated_encoding(s
);
5386 if (!fp_access_check(s
)) {
5390 if (cond
< 0x0e) { /* not always */
5391 TCGLabel
*label_match
= gen_new_label();
5392 label_continue
= gen_new_label();
5393 arm_gen_test_cc(cond
, label_match
);
5395 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5396 gen_set_nzcv(tcg_flags
);
5397 tcg_temp_free_i64(tcg_flags
);
5398 tcg_gen_br(label_continue
);
5399 gen_set_label(label_match
);
5402 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5405 gen_set_label(label_continue
);
5409 /* Floating point conditional select
5410 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5411 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5412 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5413 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5415 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5417 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5418 TCGv_i64 t_true
, t_false
, t_zero
;
5422 mos
= extract32(insn
, 29, 3);
5423 type
= extract32(insn
, 22, 2);
5424 rm
= extract32(insn
, 16, 5);
5425 cond
= extract32(insn
, 12, 4);
5426 rn
= extract32(insn
, 5, 5);
5427 rd
= extract32(insn
, 0, 5);
5430 unallocated_encoding(s
);
5443 if (dc_isar_feature(aa64_fp16
, s
)) {
5448 unallocated_encoding(s
);
5452 if (!fp_access_check(s
)) {
5456 /* Zero extend sreg & hreg inputs to 64 bits now. */
5457 t_true
= tcg_temp_new_i64();
5458 t_false
= tcg_temp_new_i64();
5459 read_vec_element(s
, t_true
, rn
, 0, sz
);
5460 read_vec_element(s
, t_false
, rm
, 0, sz
);
5462 a64_test_cc(&c
, cond
);
5463 t_zero
= tcg_const_i64(0);
5464 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5465 tcg_temp_free_i64(t_zero
);
5466 tcg_temp_free_i64(t_false
);
5469 /* Note that sregs & hregs write back zeros to the high bits,
5470 and we've already done the zero-extension. */
5471 write_fp_dreg(s
, rd
, t_true
);
5472 tcg_temp_free_i64(t_true
);
5475 /* Floating-point data-processing (1 source) - half precision */
5476 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5478 TCGv_ptr fpst
= NULL
;
5479 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5480 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5483 case 0x0: /* FMOV */
5484 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5486 case 0x1: /* FABS */
5487 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5489 case 0x2: /* FNEG */
5490 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5492 case 0x3: /* FSQRT */
5493 fpst
= get_fpstatus_ptr(true);
5494 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5496 case 0x8: /* FRINTN */
5497 case 0x9: /* FRINTP */
5498 case 0xa: /* FRINTM */
5499 case 0xb: /* FRINTZ */
5500 case 0xc: /* FRINTA */
5502 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5503 fpst
= get_fpstatus_ptr(true);
5505 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5506 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5508 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5509 tcg_temp_free_i32(tcg_rmode
);
5512 case 0xe: /* FRINTX */
5513 fpst
= get_fpstatus_ptr(true);
5514 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5516 case 0xf: /* FRINTI */
5517 fpst
= get_fpstatus_ptr(true);
5518 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5524 write_fp_sreg(s
, rd
, tcg_res
);
5527 tcg_temp_free_ptr(fpst
);
5529 tcg_temp_free_i32(tcg_op
);
5530 tcg_temp_free_i32(tcg_res
);
5533 /* Floating-point data-processing (1 source) - single precision */
5534 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5540 fpst
= get_fpstatus_ptr(false);
5541 tcg_op
= read_fp_sreg(s
, rn
);
5542 tcg_res
= tcg_temp_new_i32();
5545 case 0x0: /* FMOV */
5546 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5548 case 0x1: /* FABS */
5549 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5551 case 0x2: /* FNEG */
5552 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5554 case 0x3: /* FSQRT */
5555 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5557 case 0x8: /* FRINTN */
5558 case 0x9: /* FRINTP */
5559 case 0xa: /* FRINTM */
5560 case 0xb: /* FRINTZ */
5561 case 0xc: /* FRINTA */
5563 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5565 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5566 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5568 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5569 tcg_temp_free_i32(tcg_rmode
);
5572 case 0xe: /* FRINTX */
5573 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5575 case 0xf: /* FRINTI */
5576 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5582 write_fp_sreg(s
, rd
, tcg_res
);
5584 tcg_temp_free_ptr(fpst
);
5585 tcg_temp_free_i32(tcg_op
);
5586 tcg_temp_free_i32(tcg_res
);
5589 /* Floating-point data-processing (1 source) - double precision */
5590 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5597 case 0x0: /* FMOV */
5598 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5602 fpst
= get_fpstatus_ptr(false);
5603 tcg_op
= read_fp_dreg(s
, rn
);
5604 tcg_res
= tcg_temp_new_i64();
5607 case 0x1: /* FABS */
5608 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5610 case 0x2: /* FNEG */
5611 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5613 case 0x3: /* FSQRT */
5614 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5616 case 0x8: /* FRINTN */
5617 case 0x9: /* FRINTP */
5618 case 0xa: /* FRINTM */
5619 case 0xb: /* FRINTZ */
5620 case 0xc: /* FRINTA */
5622 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5624 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5625 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5627 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5628 tcg_temp_free_i32(tcg_rmode
);
5631 case 0xe: /* FRINTX */
5632 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5634 case 0xf: /* FRINTI */
5635 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5641 write_fp_dreg(s
, rd
, tcg_res
);
5643 tcg_temp_free_ptr(fpst
);
5644 tcg_temp_free_i64(tcg_op
);
5645 tcg_temp_free_i64(tcg_res
);
5648 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5649 int rd
, int rn
, int dtype
, int ntype
)
5654 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5656 /* Single to double */
5657 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5658 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5659 write_fp_dreg(s
, rd
, tcg_rd
);
5660 tcg_temp_free_i64(tcg_rd
);
5662 /* Single to half */
5663 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5664 TCGv_i32 ahp
= get_ahp_flag();
5665 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5667 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5668 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5669 write_fp_sreg(s
, rd
, tcg_rd
);
5670 tcg_temp_free_i32(tcg_rd
);
5671 tcg_temp_free_i32(ahp
);
5672 tcg_temp_free_ptr(fpst
);
5674 tcg_temp_free_i32(tcg_rn
);
5679 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5680 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5682 /* Double to single */
5683 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5685 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5686 TCGv_i32 ahp
= get_ahp_flag();
5687 /* Double to half */
5688 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5689 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5690 tcg_temp_free_ptr(fpst
);
5691 tcg_temp_free_i32(ahp
);
5693 write_fp_sreg(s
, rd
, tcg_rd
);
5694 tcg_temp_free_i32(tcg_rd
);
5695 tcg_temp_free_i64(tcg_rn
);
5700 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5701 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5702 TCGv_i32 tcg_ahp
= get_ahp_flag();
5703 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5705 /* Half to single */
5706 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5707 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5708 write_fp_sreg(s
, rd
, tcg_rd
);
5709 tcg_temp_free_ptr(tcg_fpst
);
5710 tcg_temp_free_i32(tcg_ahp
);
5711 tcg_temp_free_i32(tcg_rd
);
5713 /* Half to double */
5714 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5715 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5716 write_fp_dreg(s
, rd
, tcg_rd
);
5717 tcg_temp_free_i64(tcg_rd
);
5719 tcg_temp_free_i32(tcg_rn
);
5727 /* Floating point data-processing (1 source)
5728 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5729 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5730 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5731 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5733 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5735 int mos
= extract32(insn
, 29, 3);
5736 int type
= extract32(insn
, 22, 2);
5737 int opcode
= extract32(insn
, 15, 6);
5738 int rn
= extract32(insn
, 5, 5);
5739 int rd
= extract32(insn
, 0, 5);
5742 unallocated_encoding(s
);
5747 case 0x4: case 0x5: case 0x7:
5749 /* FCVT between half, single and double precision */
5750 int dtype
= extract32(opcode
, 0, 2);
5751 if (type
== 2 || dtype
== type
) {
5752 unallocated_encoding(s
);
5755 if (!fp_access_check(s
)) {
5759 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5765 /* 32-to-32 and 64-to-64 ops */
5768 if (!fp_access_check(s
)) {
5772 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5775 if (!fp_access_check(s
)) {
5779 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5782 if (!dc_isar_feature(aa64_fp16
, s
)) {
5783 unallocated_encoding(s
);
5787 if (!fp_access_check(s
)) {
5791 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5794 unallocated_encoding(s
);
5798 unallocated_encoding(s
);
5803 /* Floating-point data-processing (2 source) - single precision */
5804 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5805 int rd
, int rn
, int rm
)
5812 tcg_res
= tcg_temp_new_i32();
5813 fpst
= get_fpstatus_ptr(false);
5814 tcg_op1
= read_fp_sreg(s
, rn
);
5815 tcg_op2
= read_fp_sreg(s
, rm
);
5818 case 0x0: /* FMUL */
5819 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5821 case 0x1: /* FDIV */
5822 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5824 case 0x2: /* FADD */
5825 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5827 case 0x3: /* FSUB */
5828 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5830 case 0x4: /* FMAX */
5831 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5833 case 0x5: /* FMIN */
5834 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5836 case 0x6: /* FMAXNM */
5837 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5839 case 0x7: /* FMINNM */
5840 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5842 case 0x8: /* FNMUL */
5843 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5844 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5848 write_fp_sreg(s
, rd
, tcg_res
);
5850 tcg_temp_free_ptr(fpst
);
5851 tcg_temp_free_i32(tcg_op1
);
5852 tcg_temp_free_i32(tcg_op2
);
5853 tcg_temp_free_i32(tcg_res
);
5856 /* Floating-point data-processing (2 source) - double precision */
5857 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5858 int rd
, int rn
, int rm
)
5865 tcg_res
= tcg_temp_new_i64();
5866 fpst
= get_fpstatus_ptr(false);
5867 tcg_op1
= read_fp_dreg(s
, rn
);
5868 tcg_op2
= read_fp_dreg(s
, rm
);
5871 case 0x0: /* FMUL */
5872 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5874 case 0x1: /* FDIV */
5875 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5877 case 0x2: /* FADD */
5878 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5880 case 0x3: /* FSUB */
5881 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5883 case 0x4: /* FMAX */
5884 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5886 case 0x5: /* FMIN */
5887 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5889 case 0x6: /* FMAXNM */
5890 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5892 case 0x7: /* FMINNM */
5893 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5895 case 0x8: /* FNMUL */
5896 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5897 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5901 write_fp_dreg(s
, rd
, tcg_res
);
5903 tcg_temp_free_ptr(fpst
);
5904 tcg_temp_free_i64(tcg_op1
);
5905 tcg_temp_free_i64(tcg_op2
);
5906 tcg_temp_free_i64(tcg_res
);
5909 /* Floating-point data-processing (2 source) - half precision */
5910 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5911 int rd
, int rn
, int rm
)
5918 tcg_res
= tcg_temp_new_i32();
5919 fpst
= get_fpstatus_ptr(true);
5920 tcg_op1
= read_fp_hreg(s
, rn
);
5921 tcg_op2
= read_fp_hreg(s
, rm
);
5924 case 0x0: /* FMUL */
5925 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5927 case 0x1: /* FDIV */
5928 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5930 case 0x2: /* FADD */
5931 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5933 case 0x3: /* FSUB */
5934 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5936 case 0x4: /* FMAX */
5937 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5939 case 0x5: /* FMIN */
5940 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5942 case 0x6: /* FMAXNM */
5943 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5945 case 0x7: /* FMINNM */
5946 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5948 case 0x8: /* FNMUL */
5949 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5950 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5953 g_assert_not_reached();
5956 write_fp_sreg(s
, rd
, tcg_res
);
5958 tcg_temp_free_ptr(fpst
);
5959 tcg_temp_free_i32(tcg_op1
);
5960 tcg_temp_free_i32(tcg_op2
);
5961 tcg_temp_free_i32(tcg_res
);
5964 /* Floating point data-processing (2 source)
5965 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5966 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5967 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5968 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5970 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5972 int mos
= extract32(insn
, 29, 3);
5973 int type
= extract32(insn
, 22, 2);
5974 int rd
= extract32(insn
, 0, 5);
5975 int rn
= extract32(insn
, 5, 5);
5976 int rm
= extract32(insn
, 16, 5);
5977 int opcode
= extract32(insn
, 12, 4);
5979 if (opcode
> 8 || mos
) {
5980 unallocated_encoding(s
);
5986 if (!fp_access_check(s
)) {
5989 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5992 if (!fp_access_check(s
)) {
5995 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5998 if (!dc_isar_feature(aa64_fp16
, s
)) {
5999 unallocated_encoding(s
);
6002 if (!fp_access_check(s
)) {
6005 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6008 unallocated_encoding(s
);
6012 /* Floating-point data-processing (3 source) - single precision */
6013 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6014 int rd
, int rn
, int rm
, int ra
)
6016 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6017 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6018 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6020 tcg_op1
= read_fp_sreg(s
, rn
);
6021 tcg_op2
= read_fp_sreg(s
, rm
);
6022 tcg_op3
= read_fp_sreg(s
, ra
);
6024 /* These are fused multiply-add, and must be done as one
6025 * floating point operation with no rounding between the
6026 * multiplication and addition steps.
6027 * NB that doing the negations here as separate steps is
6028 * correct : an input NaN should come out with its sign bit
6029 * flipped if it is a negated-input.
6032 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6036 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6039 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6041 write_fp_sreg(s
, rd
, tcg_res
);
6043 tcg_temp_free_ptr(fpst
);
6044 tcg_temp_free_i32(tcg_op1
);
6045 tcg_temp_free_i32(tcg_op2
);
6046 tcg_temp_free_i32(tcg_op3
);
6047 tcg_temp_free_i32(tcg_res
);
6050 /* Floating-point data-processing (3 source) - double precision */
6051 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6052 int rd
, int rn
, int rm
, int ra
)
6054 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6055 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6056 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6058 tcg_op1
= read_fp_dreg(s
, rn
);
6059 tcg_op2
= read_fp_dreg(s
, rm
);
6060 tcg_op3
= read_fp_dreg(s
, ra
);
6062 /* These are fused multiply-add, and must be done as one
6063 * floating point operation with no rounding between the
6064 * multiplication and addition steps.
6065 * NB that doing the negations here as separate steps is
6066 * correct : an input NaN should come out with its sign bit
6067 * flipped if it is a negated-input.
6070 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6074 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6077 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6079 write_fp_dreg(s
, rd
, tcg_res
);
6081 tcg_temp_free_ptr(fpst
);
6082 tcg_temp_free_i64(tcg_op1
);
6083 tcg_temp_free_i64(tcg_op2
);
6084 tcg_temp_free_i64(tcg_op3
);
6085 tcg_temp_free_i64(tcg_res
);
6088 /* Floating-point data-processing (3 source) - half precision */
6089 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6090 int rd
, int rn
, int rm
, int ra
)
6092 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6093 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6094 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6096 tcg_op1
= read_fp_hreg(s
, rn
);
6097 tcg_op2
= read_fp_hreg(s
, rm
);
6098 tcg_op3
= read_fp_hreg(s
, ra
);
6100 /* These are fused multiply-add, and must be done as one
6101 * floating point operation with no rounding between the
6102 * multiplication and addition steps.
6103 * NB that doing the negations here as separate steps is
6104 * correct : an input NaN should come out with its sign bit
6105 * flipped if it is a negated-input.
6108 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6112 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6115 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6117 write_fp_sreg(s
, rd
, tcg_res
);
6119 tcg_temp_free_ptr(fpst
);
6120 tcg_temp_free_i32(tcg_op1
);
6121 tcg_temp_free_i32(tcg_op2
);
6122 tcg_temp_free_i32(tcg_op3
);
6123 tcg_temp_free_i32(tcg_res
);
6126 /* Floating point data-processing (3 source)
6127 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6128 * +---+---+---+-----------+------+----+------+----+------+------+------+
6129 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6130 * +---+---+---+-----------+------+----+------+----+------+------+------+
6132 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6134 int mos
= extract32(insn
, 29, 3);
6135 int type
= extract32(insn
, 22, 2);
6136 int rd
= extract32(insn
, 0, 5);
6137 int rn
= extract32(insn
, 5, 5);
6138 int ra
= extract32(insn
, 10, 5);
6139 int rm
= extract32(insn
, 16, 5);
6140 bool o0
= extract32(insn
, 15, 1);
6141 bool o1
= extract32(insn
, 21, 1);
6144 unallocated_encoding(s
);
6150 if (!fp_access_check(s
)) {
6153 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6156 if (!fp_access_check(s
)) {
6159 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6162 if (!dc_isar_feature(aa64_fp16
, s
)) {
6163 unallocated_encoding(s
);
6166 if (!fp_access_check(s
)) {
6169 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6172 unallocated_encoding(s
);
6176 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6177 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6178 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6180 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6186 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6187 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6188 extract32(imm8
, 0, 6);
6192 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6193 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6194 (extract32(imm8
, 0, 6) << 3);
6198 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6199 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6200 (extract32(imm8
, 0, 6) << 6);
6203 g_assert_not_reached();
6208 /* Floating point immediate
6209 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6210 * +---+---+---+-----------+------+---+------------+-------+------+------+
6211 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6212 * +---+---+---+-----------+------+---+------------+-------+------+------+
6214 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6216 int rd
= extract32(insn
, 0, 5);
6217 int imm5
= extract32(insn
, 5, 5);
6218 int imm8
= extract32(insn
, 13, 8);
6219 int type
= extract32(insn
, 22, 2);
6220 int mos
= extract32(insn
, 29, 3);
6226 unallocated_encoding(s
);
6239 if (dc_isar_feature(aa64_fp16
, s
)) {
6244 unallocated_encoding(s
);
6248 if (!fp_access_check(s
)) {
6252 imm
= vfp_expand_imm(sz
, imm8
);
6254 tcg_res
= tcg_const_i64(imm
);
6255 write_fp_dreg(s
, rd
, tcg_res
);
6256 tcg_temp_free_i64(tcg_res
);
6259 /* Handle floating point <=> fixed point conversions. Note that we can
6260 * also deal with fp <=> integer conversions as a special case (scale == 64)
6261 * OPTME: consider handling that special case specially or at least skipping
6262 * the call to scalbn in the helpers for zero shifts.
6264 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6265 bool itof
, int rmode
, int scale
, int sf
, int type
)
6267 bool is_signed
= !(opcode
& 1);
6268 TCGv_ptr tcg_fpstatus
;
6269 TCGv_i32 tcg_shift
, tcg_single
;
6270 TCGv_i64 tcg_double
;
6272 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6274 tcg_shift
= tcg_const_i32(64 - scale
);
6277 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6279 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6282 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6284 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6287 tcg_int
= tcg_extend
;
6291 case 1: /* float64 */
6292 tcg_double
= tcg_temp_new_i64();
6294 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6295 tcg_shift
, tcg_fpstatus
);
6297 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6298 tcg_shift
, tcg_fpstatus
);
6300 write_fp_dreg(s
, rd
, tcg_double
);
6301 tcg_temp_free_i64(tcg_double
);
6304 case 0: /* float32 */
6305 tcg_single
= tcg_temp_new_i32();
6307 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6308 tcg_shift
, tcg_fpstatus
);
6310 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6311 tcg_shift
, tcg_fpstatus
);
6313 write_fp_sreg(s
, rd
, tcg_single
);
6314 tcg_temp_free_i32(tcg_single
);
6317 case 3: /* float16 */
6318 tcg_single
= tcg_temp_new_i32();
6320 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6321 tcg_shift
, tcg_fpstatus
);
6323 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6324 tcg_shift
, tcg_fpstatus
);
6326 write_fp_sreg(s
, rd
, tcg_single
);
6327 tcg_temp_free_i32(tcg_single
);
6331 g_assert_not_reached();
6334 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6337 if (extract32(opcode
, 2, 1)) {
6338 /* There are too many rounding modes to all fit into rmode,
6339 * so FCVTA[US] is a special case.
6341 rmode
= FPROUNDING_TIEAWAY
;
6344 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6346 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6349 case 1: /* float64 */
6350 tcg_double
= read_fp_dreg(s
, rn
);
6353 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6354 tcg_shift
, tcg_fpstatus
);
6356 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6357 tcg_shift
, tcg_fpstatus
);
6361 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6362 tcg_shift
, tcg_fpstatus
);
6364 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6365 tcg_shift
, tcg_fpstatus
);
6369 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6371 tcg_temp_free_i64(tcg_double
);
6374 case 0: /* float32 */
6375 tcg_single
= read_fp_sreg(s
, rn
);
6378 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6379 tcg_shift
, tcg_fpstatus
);
6381 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6382 tcg_shift
, tcg_fpstatus
);
6385 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6387 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6388 tcg_shift
, tcg_fpstatus
);
6390 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6391 tcg_shift
, tcg_fpstatus
);
6393 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6394 tcg_temp_free_i32(tcg_dest
);
6396 tcg_temp_free_i32(tcg_single
);
6399 case 3: /* float16 */
6400 tcg_single
= read_fp_sreg(s
, rn
);
6403 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6404 tcg_shift
, tcg_fpstatus
);
6406 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6407 tcg_shift
, tcg_fpstatus
);
6410 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6412 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6413 tcg_shift
, tcg_fpstatus
);
6415 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6416 tcg_shift
, tcg_fpstatus
);
6418 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6419 tcg_temp_free_i32(tcg_dest
);
6421 tcg_temp_free_i32(tcg_single
);
6425 g_assert_not_reached();
6428 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6429 tcg_temp_free_i32(tcg_rmode
);
6432 tcg_temp_free_ptr(tcg_fpstatus
);
6433 tcg_temp_free_i32(tcg_shift
);
6436 /* Floating point <-> fixed point conversions
6437 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6438 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6439 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6440 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6442 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6444 int rd
= extract32(insn
, 0, 5);
6445 int rn
= extract32(insn
, 5, 5);
6446 int scale
= extract32(insn
, 10, 6);
6447 int opcode
= extract32(insn
, 16, 3);
6448 int rmode
= extract32(insn
, 19, 2);
6449 int type
= extract32(insn
, 22, 2);
6450 bool sbit
= extract32(insn
, 29, 1);
6451 bool sf
= extract32(insn
, 31, 1);
6454 if (sbit
|| (!sf
&& scale
< 32)) {
6455 unallocated_encoding(s
);
6460 case 0: /* float32 */
6461 case 1: /* float64 */
6463 case 3: /* float16 */
6464 if (dc_isar_feature(aa64_fp16
, s
)) {
6469 unallocated_encoding(s
);
6473 switch ((rmode
<< 3) | opcode
) {
6474 case 0x2: /* SCVTF */
6475 case 0x3: /* UCVTF */
6478 case 0x18: /* FCVTZS */
6479 case 0x19: /* FCVTZU */
6483 unallocated_encoding(s
);
6487 if (!fp_access_check(s
)) {
6491 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6494 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6496 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6497 * without conversion.
6501 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6507 tmp
= tcg_temp_new_i64();
6508 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6509 write_fp_dreg(s
, rd
, tmp
);
6510 tcg_temp_free_i64(tmp
);
6514 write_fp_dreg(s
, rd
, tcg_rn
);
6517 /* 64 bit to top half. */
6518 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6519 clear_vec_high(s
, true, rd
);
6523 tmp
= tcg_temp_new_i64();
6524 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6525 write_fp_dreg(s
, rd
, tmp
);
6526 tcg_temp_free_i64(tmp
);
6529 g_assert_not_reached();
6532 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6537 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6541 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6544 /* 64 bits from top half */
6545 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6549 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6552 g_assert_not_reached();
6557 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6559 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6560 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6562 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6564 tcg_temp_free_ptr(fpstatus
);
6566 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6567 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6568 tcg_gen_movi_i32(cpu_CF
, 0);
6569 tcg_gen_movi_i32(cpu_NF
, 0);
6570 tcg_gen_movi_i32(cpu_VF
, 0);
6572 tcg_temp_free_i64(t
);
6575 /* Floating point <-> integer conversions
6576 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6577 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6578 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6579 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6581 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6583 int rd
= extract32(insn
, 0, 5);
6584 int rn
= extract32(insn
, 5, 5);
6585 int opcode
= extract32(insn
, 16, 3);
6586 int rmode
= extract32(insn
, 19, 2);
6587 int type
= extract32(insn
, 22, 2);
6588 bool sbit
= extract32(insn
, 29, 1);
6589 bool sf
= extract32(insn
, 31, 1);
6593 goto do_unallocated
;
6601 case 4: /* FCVTAS */
6602 case 5: /* FCVTAU */
6604 goto do_unallocated
;
6607 case 0: /* FCVT[NPMZ]S */
6608 case 1: /* FCVT[NPMZ]U */
6610 case 0: /* float32 */
6611 case 1: /* float64 */
6613 case 3: /* float16 */
6614 if (!dc_isar_feature(aa64_fp16
, s
)) {
6615 goto do_unallocated
;
6619 goto do_unallocated
;
6621 if (!fp_access_check(s
)) {
6624 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6628 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6629 case 0b01100110: /* FMOV half <-> 32-bit int */
6631 case 0b11100110: /* FMOV half <-> 64-bit int */
6633 if (!dc_isar_feature(aa64_fp16
, s
)) {
6634 goto do_unallocated
;
6637 case 0b00000110: /* FMOV 32-bit */
6639 case 0b10100110: /* FMOV 64-bit */
6641 case 0b11001110: /* FMOV top half of 128-bit */
6643 if (!fp_access_check(s
)) {
6647 handle_fmov(s
, rd
, rn
, type
, itof
);
6650 case 0b00111110: /* FJCVTZS */
6651 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6652 goto do_unallocated
;
6653 } else if (fp_access_check(s
)) {
6654 handle_fjcvtzs(s
, rd
, rn
);
6660 unallocated_encoding(s
);
6667 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6668 * 31 30 29 28 25 24 0
6669 * +---+---+---+---------+-----------------------------+
6670 * | | 0 | | 1 1 1 1 | |
6671 * +---+---+---+---------+-----------------------------+
6673 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6675 if (extract32(insn
, 24, 1)) {
6676 /* Floating point data-processing (3 source) */
6677 disas_fp_3src(s
, insn
);
6678 } else if (extract32(insn
, 21, 1) == 0) {
6679 /* Floating point to fixed point conversions */
6680 disas_fp_fixed_conv(s
, insn
);
6682 switch (extract32(insn
, 10, 2)) {
6684 /* Floating point conditional compare */
6685 disas_fp_ccomp(s
, insn
);
6688 /* Floating point data-processing (2 source) */
6689 disas_fp_2src(s
, insn
);
6692 /* Floating point conditional select */
6693 disas_fp_csel(s
, insn
);
6696 switch (ctz32(extract32(insn
, 12, 4))) {
6697 case 0: /* [15:12] == xxx1 */
6698 /* Floating point immediate */
6699 disas_fp_imm(s
, insn
);
6701 case 1: /* [15:12] == xx10 */
6702 /* Floating point compare */
6703 disas_fp_compare(s
, insn
);
6705 case 2: /* [15:12] == x100 */
6706 /* Floating point data-processing (1 source) */
6707 disas_fp_1src(s
, insn
);
6709 case 3: /* [15:12] == 1000 */
6710 unallocated_encoding(s
);
6712 default: /* [15:12] == 0000 */
6713 /* Floating point <-> integer conversions */
6714 disas_fp_int_conv(s
, insn
);
6722 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6725 /* Extract 64 bits from the middle of two concatenated 64 bit
6726 * vector register slices left:right. The extracted bits start
6727 * at 'pos' bits into the right (least significant) side.
6728 * We return the result in tcg_right, and guarantee not to
6731 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6732 assert(pos
> 0 && pos
< 64);
6734 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6735 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6736 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6738 tcg_temp_free_i64(tcg_tmp
);
6742 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6743 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6744 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6745 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6747 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6749 int is_q
= extract32(insn
, 30, 1);
6750 int op2
= extract32(insn
, 22, 2);
6751 int imm4
= extract32(insn
, 11, 4);
6752 int rm
= extract32(insn
, 16, 5);
6753 int rn
= extract32(insn
, 5, 5);
6754 int rd
= extract32(insn
, 0, 5);
6755 int pos
= imm4
<< 3;
6756 TCGv_i64 tcg_resl
, tcg_resh
;
6758 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6759 unallocated_encoding(s
);
6763 if (!fp_access_check(s
)) {
6767 tcg_resh
= tcg_temp_new_i64();
6768 tcg_resl
= tcg_temp_new_i64();
6770 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6771 * either extracting 128 bits from a 128:128 concatenation, or
6772 * extracting 64 bits from a 64:64 concatenation.
6775 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6777 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6778 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6780 tcg_gen_movi_i64(tcg_resh
, 0);
6787 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6788 EltPosns
*elt
= eltposns
;
6795 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6797 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6800 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6801 tcg_hh
= tcg_temp_new_i64();
6802 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6803 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6804 tcg_temp_free_i64(tcg_hh
);
6808 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6809 tcg_temp_free_i64(tcg_resl
);
6810 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6811 tcg_temp_free_i64(tcg_resh
);
6815 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6816 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6817 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6818 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6820 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6822 int op2
= extract32(insn
, 22, 2);
6823 int is_q
= extract32(insn
, 30, 1);
6824 int rm
= extract32(insn
, 16, 5);
6825 int rn
= extract32(insn
, 5, 5);
6826 int rd
= extract32(insn
, 0, 5);
6827 int is_tblx
= extract32(insn
, 12, 1);
6828 int len
= extract32(insn
, 13, 2);
6829 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6830 TCGv_i32 tcg_regno
, tcg_numregs
;
6833 unallocated_encoding(s
);
6837 if (!fp_access_check(s
)) {
6841 /* This does a table lookup: for every byte element in the input
6842 * we index into a table formed from up to four vector registers,
6843 * and then the output is the result of the lookups. Our helper
6844 * function does the lookup operation for a single 64 bit part of
6847 tcg_resl
= tcg_temp_new_i64();
6848 tcg_resh
= tcg_temp_new_i64();
6851 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6853 tcg_gen_movi_i64(tcg_resl
, 0);
6855 if (is_tblx
&& is_q
) {
6856 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6858 tcg_gen_movi_i64(tcg_resh
, 0);
6861 tcg_idx
= tcg_temp_new_i64();
6862 tcg_regno
= tcg_const_i32(rn
);
6863 tcg_numregs
= tcg_const_i32(len
+ 1);
6864 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6865 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6866 tcg_regno
, tcg_numregs
);
6868 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6869 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6870 tcg_regno
, tcg_numregs
);
6872 tcg_temp_free_i64(tcg_idx
);
6873 tcg_temp_free_i32(tcg_regno
);
6874 tcg_temp_free_i32(tcg_numregs
);
6876 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6877 tcg_temp_free_i64(tcg_resl
);
6878 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6879 tcg_temp_free_i64(tcg_resh
);
6883 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6884 * +---+---+-------------+------+---+------+---+------------------+------+
6885 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6886 * +---+---+-------------+------+---+------+---+------------------+------+
6888 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6890 int rd
= extract32(insn
, 0, 5);
6891 int rn
= extract32(insn
, 5, 5);
6892 int rm
= extract32(insn
, 16, 5);
6893 int size
= extract32(insn
, 22, 2);
6894 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6895 * bit 2 indicates 1 vs 2 variant of the insn.
6897 int opcode
= extract32(insn
, 12, 2);
6898 bool part
= extract32(insn
, 14, 1);
6899 bool is_q
= extract32(insn
, 30, 1);
6900 int esize
= 8 << size
;
6902 int datasize
= is_q
? 128 : 64;
6903 int elements
= datasize
/ esize
;
6904 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6906 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6907 unallocated_encoding(s
);
6911 if (!fp_access_check(s
)) {
6915 tcg_resl
= tcg_const_i64(0);
6916 tcg_resh
= tcg_const_i64(0);
6917 tcg_res
= tcg_temp_new_i64();
6919 for (i
= 0; i
< elements
; i
++) {
6921 case 1: /* UZP1/2 */
6923 int midpoint
= elements
/ 2;
6925 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6927 read_vec_element(s
, tcg_res
, rm
,
6928 2 * (i
- midpoint
) + part
, size
);
6932 case 2: /* TRN1/2 */
6934 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6936 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6939 case 3: /* ZIP1/2 */
6941 int base
= part
* elements
/ 2;
6943 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6945 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6950 g_assert_not_reached();
6955 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6956 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6958 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6959 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6963 tcg_temp_free_i64(tcg_res
);
6965 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6966 tcg_temp_free_i64(tcg_resl
);
6967 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6968 tcg_temp_free_i64(tcg_resh
);
6972 * do_reduction_op helper
6974 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6975 * important for correct NaN propagation that we do these
6976 * operations in exactly the order specified by the pseudocode.
6978 * This is a recursive function, TCG temps should be freed by the
6979 * calling function once it is done with the values.
6981 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6982 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6984 if (esize
== size
) {
6986 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6989 /* We should have one register left here */
6990 assert(ctpop8(vmap
) == 1);
6991 element
= ctz32(vmap
);
6992 assert(element
< 8);
6994 tcg_elem
= tcg_temp_new_i32();
6995 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6998 int bits
= size
/ 2;
6999 int shift
= ctpop8(vmap
) / 2;
7000 int vmap_lo
= (vmap
>> shift
) & vmap
;
7001 int vmap_hi
= (vmap
& ~vmap_lo
);
7002 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7004 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7005 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7006 tcg_res
= tcg_temp_new_i32();
7009 case 0x0c: /* fmaxnmv half-precision */
7010 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7012 case 0x0f: /* fmaxv half-precision */
7013 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7015 case 0x1c: /* fminnmv half-precision */
7016 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7018 case 0x1f: /* fminv half-precision */
7019 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7021 case 0x2c: /* fmaxnmv */
7022 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7024 case 0x2f: /* fmaxv */
7025 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7027 case 0x3c: /* fminnmv */
7028 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7030 case 0x3f: /* fminv */
7031 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7034 g_assert_not_reached();
7037 tcg_temp_free_i32(tcg_hi
);
7038 tcg_temp_free_i32(tcg_lo
);
7043 /* AdvSIMD across lanes
7044 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7045 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7046 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7047 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7049 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7051 int rd
= extract32(insn
, 0, 5);
7052 int rn
= extract32(insn
, 5, 5);
7053 int size
= extract32(insn
, 22, 2);
7054 int opcode
= extract32(insn
, 12, 5);
7055 bool is_q
= extract32(insn
, 30, 1);
7056 bool is_u
= extract32(insn
, 29, 1);
7058 bool is_min
= false;
7062 TCGv_i64 tcg_res
, tcg_elt
;
7065 case 0x1b: /* ADDV */
7067 unallocated_encoding(s
);
7071 case 0x3: /* SADDLV, UADDLV */
7072 case 0xa: /* SMAXV, UMAXV */
7073 case 0x1a: /* SMINV, UMINV */
7074 if (size
== 3 || (size
== 2 && !is_q
)) {
7075 unallocated_encoding(s
);
7079 case 0xc: /* FMAXNMV, FMINNMV */
7080 case 0xf: /* FMAXV, FMINV */
7081 /* Bit 1 of size field encodes min vs max and the actual size
7082 * depends on the encoding of the U bit. If not set (and FP16
7083 * enabled) then we do half-precision float instead of single
7086 is_min
= extract32(size
, 1, 1);
7088 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7090 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7091 unallocated_encoding(s
);
7098 unallocated_encoding(s
);
7102 if (!fp_access_check(s
)) {
7107 elements
= (is_q
? 128 : 64) / esize
;
7109 tcg_res
= tcg_temp_new_i64();
7110 tcg_elt
= tcg_temp_new_i64();
7112 /* These instructions operate across all lanes of a vector
7113 * to produce a single result. We can guarantee that a 64
7114 * bit intermediate is sufficient:
7115 * + for [US]ADDLV the maximum element size is 32 bits, and
7116 * the result type is 64 bits
7117 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7118 * same as the element size, which is 32 bits at most
7119 * For the integer operations we can choose to work at 64
7120 * or 32 bits and truncate at the end; for simplicity
7121 * we use 64 bits always. The floating point
7122 * ops do require 32 bit intermediates, though.
7125 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7127 for (i
= 1; i
< elements
; i
++) {
7128 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7131 case 0x03: /* SADDLV / UADDLV */
7132 case 0x1b: /* ADDV */
7133 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7135 case 0x0a: /* SMAXV / UMAXV */
7137 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7139 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7142 case 0x1a: /* SMINV / UMINV */
7144 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7146 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7150 g_assert_not_reached();
7155 /* Floating point vector reduction ops which work across 32
7156 * bit (single) or 16 bit (half-precision) intermediates.
7157 * Note that correct NaN propagation requires that we do these
7158 * operations in exactly the order specified by the pseudocode.
7160 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7161 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7162 int vmap
= (1 << elements
) - 1;
7163 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7164 (is_q
? 128 : 64), vmap
, fpst
);
7165 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7166 tcg_temp_free_i32(tcg_res32
);
7167 tcg_temp_free_ptr(fpst
);
7170 tcg_temp_free_i64(tcg_elt
);
7172 /* Now truncate the result to the width required for the final output */
7173 if (opcode
== 0x03) {
7174 /* SADDLV, UADDLV: result is 2*esize */
7180 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7183 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7186 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7191 g_assert_not_reached();
7194 write_fp_dreg(s
, rd
, tcg_res
);
7195 tcg_temp_free_i64(tcg_res
);
7198 /* DUP (Element, Vector)
7200 * 31 30 29 21 20 16 15 10 9 5 4 0
7201 * +---+---+-------------------+--------+-------------+------+------+
7202 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7203 * +---+---+-------------------+--------+-------------+------+------+
7205 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7207 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7210 int size
= ctz32(imm5
);
7211 int index
= imm5
>> (size
+ 1);
7213 if (size
> 3 || (size
== 3 && !is_q
)) {
7214 unallocated_encoding(s
);
7218 if (!fp_access_check(s
)) {
7222 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7223 vec_reg_offset(s
, rn
, index
, size
),
7224 is_q
? 16 : 8, vec_full_reg_size(s
));
7227 /* DUP (element, scalar)
7228 * 31 21 20 16 15 10 9 5 4 0
7229 * +-----------------------+--------+-------------+------+------+
7230 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7231 * +-----------------------+--------+-------------+------+------+
7233 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7236 int size
= ctz32(imm5
);
7241 unallocated_encoding(s
);
7245 if (!fp_access_check(s
)) {
7249 index
= imm5
>> (size
+ 1);
7251 /* This instruction just extracts the specified element and
7252 * zero-extends it into the bottom of the destination register.
7254 tmp
= tcg_temp_new_i64();
7255 read_vec_element(s
, tmp
, rn
, index
, size
);
7256 write_fp_dreg(s
, rd
, tmp
);
7257 tcg_temp_free_i64(tmp
);
7262 * 31 30 29 21 20 16 15 10 9 5 4 0
7263 * +---+---+-------------------+--------+-------------+------+------+
7264 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7265 * +---+---+-------------------+--------+-------------+------+------+
7267 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7269 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7272 int size
= ctz32(imm5
);
7273 uint32_t dofs
, oprsz
, maxsz
;
7275 if (size
> 3 || ((size
== 3) && !is_q
)) {
7276 unallocated_encoding(s
);
7280 if (!fp_access_check(s
)) {
7284 dofs
= vec_full_reg_offset(s
, rd
);
7285 oprsz
= is_q
? 16 : 8;
7286 maxsz
= vec_full_reg_size(s
);
7288 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7293 * 31 21 20 16 15 14 11 10 9 5 4 0
7294 * +-----------------------+--------+------------+---+------+------+
7295 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7296 * +-----------------------+--------+------------+---+------+------+
7298 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7299 * index: encoded in imm5<4:size+1>
7301 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7304 int size
= ctz32(imm5
);
7305 int src_index
, dst_index
;
7309 unallocated_encoding(s
);
7313 if (!fp_access_check(s
)) {
7317 dst_index
= extract32(imm5
, 1+size
, 5);
7318 src_index
= extract32(imm4
, size
, 4);
7320 tmp
= tcg_temp_new_i64();
7322 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7323 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7325 tcg_temp_free_i64(tmp
);
7331 * 31 21 20 16 15 10 9 5 4 0
7332 * +-----------------------+--------+-------------+------+------+
7333 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7334 * +-----------------------+--------+-------------+------+------+
7336 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7337 * index: encoded in imm5<4:size+1>
7339 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7341 int size
= ctz32(imm5
);
7345 unallocated_encoding(s
);
7349 if (!fp_access_check(s
)) {
7353 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7354 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7361 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7362 * +---+---+-------------------+--------+-------------+------+------+
7363 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7364 * +---+---+-------------------+--------+-------------+------+------+
7366 * U: unsigned when set
7367 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7369 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7370 int rn
, int rd
, int imm5
)
7372 int size
= ctz32(imm5
);
7376 /* Check for UnallocatedEncodings */
7378 if (size
> 2 || (size
== 2 && !is_q
)) {
7379 unallocated_encoding(s
);
7384 || (size
< 3 && is_q
)
7385 || (size
== 3 && !is_q
)) {
7386 unallocated_encoding(s
);
7391 if (!fp_access_check(s
)) {
7395 element
= extract32(imm5
, 1+size
, 4);
7397 tcg_rd
= cpu_reg(s
, rd
);
7398 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7399 if (is_signed
&& !is_q
) {
7400 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7405 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7406 * +---+---+----+-----------------+------+---+------+---+------+------+
7407 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7408 * +---+---+----+-----------------+------+---+------+---+------+------+
7410 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7412 int rd
= extract32(insn
, 0, 5);
7413 int rn
= extract32(insn
, 5, 5);
7414 int imm4
= extract32(insn
, 11, 4);
7415 int op
= extract32(insn
, 29, 1);
7416 int is_q
= extract32(insn
, 30, 1);
7417 int imm5
= extract32(insn
, 16, 5);
7422 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7424 unallocated_encoding(s
);
7429 /* DUP (element - vector) */
7430 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7434 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7439 handle_simd_insg(s
, rd
, rn
, imm5
);
7441 unallocated_encoding(s
);
7446 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7447 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7450 unallocated_encoding(s
);
7456 /* AdvSIMD modified immediate
7457 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7458 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7459 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7460 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7462 * There are a number of operations that can be carried out here:
7463 * MOVI - move (shifted) imm into register
7464 * MVNI - move inverted (shifted) imm into register
7465 * ORR - bitwise OR of (shifted) imm with register
7466 * BIC - bitwise clear of (shifted) imm with register
7467 * With ARMv8.2 we also have:
7468 * FMOV half-precision
7470 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7472 int rd
= extract32(insn
, 0, 5);
7473 int cmode
= extract32(insn
, 12, 4);
7474 int cmode_3_1
= extract32(cmode
, 1, 3);
7475 int cmode_0
= extract32(cmode
, 0, 1);
7476 int o2
= extract32(insn
, 11, 1);
7477 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7478 bool is_neg
= extract32(insn
, 29, 1);
7479 bool is_q
= extract32(insn
, 30, 1);
7482 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7483 /* Check for FMOV (vector, immediate) - half-precision */
7484 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7485 unallocated_encoding(s
);
7490 if (!fp_access_check(s
)) {
7494 /* See AdvSIMDExpandImm() in ARM ARM */
7495 switch (cmode_3_1
) {
7496 case 0: /* Replicate(Zeros(24):imm8, 2) */
7497 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7498 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7499 case 3: /* Replicate(imm8:Zeros(24), 2) */
7501 int shift
= cmode_3_1
* 8;
7502 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7505 case 4: /* Replicate(Zeros(8):imm8, 4) */
7506 case 5: /* Replicate(imm8:Zeros(8), 4) */
7508 int shift
= (cmode_3_1
& 0x1) * 8;
7509 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7514 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7515 imm
= (abcdefgh
<< 16) | 0xffff;
7517 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7518 imm
= (abcdefgh
<< 8) | 0xff;
7520 imm
= bitfield_replicate(imm
, 32);
7523 if (!cmode_0
&& !is_neg
) {
7524 imm
= bitfield_replicate(abcdefgh
, 8);
7525 } else if (!cmode_0
&& is_neg
) {
7528 for (i
= 0; i
< 8; i
++) {
7529 if ((abcdefgh
) & (1 << i
)) {
7530 imm
|= 0xffULL
<< (i
* 8);
7533 } else if (cmode_0
) {
7535 imm
= (abcdefgh
& 0x3f) << 48;
7536 if (abcdefgh
& 0x80) {
7537 imm
|= 0x8000000000000000ULL
;
7539 if (abcdefgh
& 0x40) {
7540 imm
|= 0x3fc0000000000000ULL
;
7542 imm
|= 0x4000000000000000ULL
;
7546 /* FMOV (vector, immediate) - half-precision */
7547 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7548 /* now duplicate across the lanes */
7549 imm
= bitfield_replicate(imm
, 16);
7551 imm
= (abcdefgh
& 0x3f) << 19;
7552 if (abcdefgh
& 0x80) {
7555 if (abcdefgh
& 0x40) {
7566 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7567 g_assert_not_reached();
7570 if (cmode_3_1
!= 7 && is_neg
) {
7574 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7575 /* MOVI or MVNI, with MVNI negation handled above. */
7576 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7577 vec_full_reg_size(s
), imm
);
7579 /* ORR or BIC, with BIC negation to AND handled above. */
7581 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7583 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7588 /* AdvSIMD scalar copy
7589 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7590 * +-----+----+-----------------+------+---+------+---+------+------+
7591 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7592 * +-----+----+-----------------+------+---+------+---+------+------+
7594 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7596 int rd
= extract32(insn
, 0, 5);
7597 int rn
= extract32(insn
, 5, 5);
7598 int imm4
= extract32(insn
, 11, 4);
7599 int imm5
= extract32(insn
, 16, 5);
7600 int op
= extract32(insn
, 29, 1);
7602 if (op
!= 0 || imm4
!= 0) {
7603 unallocated_encoding(s
);
7607 /* DUP (element, scalar) */
7608 handle_simd_dupes(s
, rd
, rn
, imm5
);
7611 /* AdvSIMD scalar pairwise
7612 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7613 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7614 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7615 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7617 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7619 int u
= extract32(insn
, 29, 1);
7620 int size
= extract32(insn
, 22, 2);
7621 int opcode
= extract32(insn
, 12, 5);
7622 int rn
= extract32(insn
, 5, 5);
7623 int rd
= extract32(insn
, 0, 5);
7626 /* For some ops (the FP ones), size[1] is part of the encoding.
7627 * For ADDP strictly it is not but size[1] is always 1 for valid
7630 opcode
|= (extract32(size
, 1, 1) << 5);
7633 case 0x3b: /* ADDP */
7634 if (u
|| size
!= 3) {
7635 unallocated_encoding(s
);
7638 if (!fp_access_check(s
)) {
7644 case 0xc: /* FMAXNMP */
7645 case 0xd: /* FADDP */
7646 case 0xf: /* FMAXP */
7647 case 0x2c: /* FMINNMP */
7648 case 0x2f: /* FMINP */
7649 /* FP op, size[0] is 32 or 64 bit*/
7651 if (!dc_isar_feature(aa64_fp16
, s
)) {
7652 unallocated_encoding(s
);
7658 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7661 if (!fp_access_check(s
)) {
7665 fpst
= get_fpstatus_ptr(size
== MO_16
);
7668 unallocated_encoding(s
);
7672 if (size
== MO_64
) {
7673 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7674 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7675 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7677 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7678 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7681 case 0x3b: /* ADDP */
7682 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7684 case 0xc: /* FMAXNMP */
7685 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7687 case 0xd: /* FADDP */
7688 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7690 case 0xf: /* FMAXP */
7691 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7693 case 0x2c: /* FMINNMP */
7694 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7696 case 0x2f: /* FMINP */
7697 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7700 g_assert_not_reached();
7703 write_fp_dreg(s
, rd
, tcg_res
);
7705 tcg_temp_free_i64(tcg_op1
);
7706 tcg_temp_free_i64(tcg_op2
);
7707 tcg_temp_free_i64(tcg_res
);
7709 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7710 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7711 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7713 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7714 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7716 if (size
== MO_16
) {
7718 case 0xc: /* FMAXNMP */
7719 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7721 case 0xd: /* FADDP */
7722 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7724 case 0xf: /* FMAXP */
7725 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7727 case 0x2c: /* FMINNMP */
7728 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7730 case 0x2f: /* FMINP */
7731 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7734 g_assert_not_reached();
7738 case 0xc: /* FMAXNMP */
7739 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7741 case 0xd: /* FADDP */
7742 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7744 case 0xf: /* FMAXP */
7745 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7747 case 0x2c: /* FMINNMP */
7748 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7750 case 0x2f: /* FMINP */
7751 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7754 g_assert_not_reached();
7758 write_fp_sreg(s
, rd
, tcg_res
);
7760 tcg_temp_free_i32(tcg_op1
);
7761 tcg_temp_free_i32(tcg_op2
);
7762 tcg_temp_free_i32(tcg_res
);
7766 tcg_temp_free_ptr(fpst
);
7771 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7773 * This code is handles the common shifting code and is used by both
7774 * the vector and scalar code.
7776 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7777 TCGv_i64 tcg_rnd
, bool accumulate
,
7778 bool is_u
, int size
, int shift
)
7780 bool extended_result
= false;
7781 bool round
= tcg_rnd
!= NULL
;
7783 TCGv_i64 tcg_src_hi
;
7785 if (round
&& size
== 3) {
7786 extended_result
= true;
7787 ext_lshift
= 64 - shift
;
7788 tcg_src_hi
= tcg_temp_new_i64();
7789 } else if (shift
== 64) {
7790 if (!accumulate
&& is_u
) {
7791 /* result is zero */
7792 tcg_gen_movi_i64(tcg_res
, 0);
7797 /* Deal with the rounding step */
7799 if (extended_result
) {
7800 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7802 /* take care of sign extending tcg_res */
7803 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7804 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7805 tcg_src
, tcg_src_hi
,
7808 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7812 tcg_temp_free_i64(tcg_zero
);
7814 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7818 /* Now do the shift right */
7819 if (round
&& extended_result
) {
7820 /* extended case, >64 bit precision required */
7821 if (ext_lshift
== 0) {
7822 /* special case, only high bits matter */
7823 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7825 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7826 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7827 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7832 /* essentially shifting in 64 zeros */
7833 tcg_gen_movi_i64(tcg_src
, 0);
7835 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7839 /* effectively extending the sign-bit */
7840 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7842 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7848 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7850 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7853 if (extended_result
) {
7854 tcg_temp_free_i64(tcg_src_hi
);
7858 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7859 static void handle_scalar_simd_shri(DisasContext
*s
,
7860 bool is_u
, int immh
, int immb
,
7861 int opcode
, int rn
, int rd
)
7864 int immhb
= immh
<< 3 | immb
;
7865 int shift
= 2 * (8 << size
) - immhb
;
7866 bool accumulate
= false;
7868 bool insert
= false;
7873 if (!extract32(immh
, 3, 1)) {
7874 unallocated_encoding(s
);
7878 if (!fp_access_check(s
)) {
7883 case 0x02: /* SSRA / USRA (accumulate) */
7886 case 0x04: /* SRSHR / URSHR (rounding) */
7889 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7890 accumulate
= round
= true;
7892 case 0x08: /* SRI */
7898 uint64_t round_const
= 1ULL << (shift
- 1);
7899 tcg_round
= tcg_const_i64(round_const
);
7904 tcg_rn
= read_fp_dreg(s
, rn
);
7905 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7908 /* shift count same as element size is valid but does nothing;
7909 * special case to avoid potential shift by 64.
7911 int esize
= 8 << size
;
7912 if (shift
!= esize
) {
7913 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7914 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7917 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7918 accumulate
, is_u
, size
, shift
);
7921 write_fp_dreg(s
, rd
, tcg_rd
);
7923 tcg_temp_free_i64(tcg_rn
);
7924 tcg_temp_free_i64(tcg_rd
);
7926 tcg_temp_free_i64(tcg_round
);
7930 /* SHL/SLI - Scalar shift left */
7931 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7932 int immh
, int immb
, int opcode
,
7935 int size
= 32 - clz32(immh
) - 1;
7936 int immhb
= immh
<< 3 | immb
;
7937 int shift
= immhb
- (8 << size
);
7938 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7939 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7941 if (!extract32(immh
, 3, 1)) {
7942 unallocated_encoding(s
);
7946 if (!fp_access_check(s
)) {
7950 tcg_rn
= read_fp_dreg(s
, rn
);
7951 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7954 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7956 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7959 write_fp_dreg(s
, rd
, tcg_rd
);
7961 tcg_temp_free_i64(tcg_rn
);
7962 tcg_temp_free_i64(tcg_rd
);
7965 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7966 * (signed/unsigned) narrowing */
7967 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7968 bool is_u_shift
, bool is_u_narrow
,
7969 int immh
, int immb
, int opcode
,
7972 int immhb
= immh
<< 3 | immb
;
7973 int size
= 32 - clz32(immh
) - 1;
7974 int esize
= 8 << size
;
7975 int shift
= (2 * esize
) - immhb
;
7976 int elements
= is_scalar
? 1 : (64 / esize
);
7977 bool round
= extract32(opcode
, 0, 1);
7978 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7979 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7980 TCGv_i32 tcg_rd_narrowed
;
7983 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7984 { gen_helper_neon_narrow_sat_s8
,
7985 gen_helper_neon_unarrow_sat8
},
7986 { gen_helper_neon_narrow_sat_s16
,
7987 gen_helper_neon_unarrow_sat16
},
7988 { gen_helper_neon_narrow_sat_s32
,
7989 gen_helper_neon_unarrow_sat32
},
7992 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7993 gen_helper_neon_narrow_sat_u8
,
7994 gen_helper_neon_narrow_sat_u16
,
7995 gen_helper_neon_narrow_sat_u32
,
7998 NeonGenNarrowEnvFn
*narrowfn
;
8004 if (extract32(immh
, 3, 1)) {
8005 unallocated_encoding(s
);
8009 if (!fp_access_check(s
)) {
8014 narrowfn
= unsigned_narrow_fns
[size
];
8016 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8019 tcg_rn
= tcg_temp_new_i64();
8020 tcg_rd
= tcg_temp_new_i64();
8021 tcg_rd_narrowed
= tcg_temp_new_i32();
8022 tcg_final
= tcg_const_i64(0);
8025 uint64_t round_const
= 1ULL << (shift
- 1);
8026 tcg_round
= tcg_const_i64(round_const
);
8031 for (i
= 0; i
< elements
; i
++) {
8032 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8033 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8034 false, is_u_shift
, size
+1, shift
);
8035 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8036 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8037 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8041 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8043 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8047 tcg_temp_free_i64(tcg_round
);
8049 tcg_temp_free_i64(tcg_rn
);
8050 tcg_temp_free_i64(tcg_rd
);
8051 tcg_temp_free_i32(tcg_rd_narrowed
);
8052 tcg_temp_free_i64(tcg_final
);
8054 clear_vec_high(s
, is_q
, rd
);
8057 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8058 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8059 bool src_unsigned
, bool dst_unsigned
,
8060 int immh
, int immb
, int rn
, int rd
)
8062 int immhb
= immh
<< 3 | immb
;
8063 int size
= 32 - clz32(immh
) - 1;
8064 int shift
= immhb
- (8 << size
);
8068 assert(!(scalar
&& is_q
));
8071 if (!is_q
&& extract32(immh
, 3, 1)) {
8072 unallocated_encoding(s
);
8076 /* Since we use the variable-shift helpers we must
8077 * replicate the shift count into each element of
8078 * the tcg_shift value.
8082 shift
|= shift
<< 8;
8085 shift
|= shift
<< 16;
8091 g_assert_not_reached();
8095 if (!fp_access_check(s
)) {
8100 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8101 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8102 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8103 { NULL
, gen_helper_neon_qshl_u64
},
8105 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8106 int maxpass
= is_q
? 2 : 1;
8108 for (pass
= 0; pass
< maxpass
; pass
++) {
8109 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8111 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8112 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8113 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8115 tcg_temp_free_i64(tcg_op
);
8117 tcg_temp_free_i64(tcg_shift
);
8118 clear_vec_high(s
, is_q
, rd
);
8120 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8121 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8123 { gen_helper_neon_qshl_s8
,
8124 gen_helper_neon_qshl_s16
,
8125 gen_helper_neon_qshl_s32
},
8126 { gen_helper_neon_qshlu_s8
,
8127 gen_helper_neon_qshlu_s16
,
8128 gen_helper_neon_qshlu_s32
}
8130 { NULL
, NULL
, NULL
},
8131 { gen_helper_neon_qshl_u8
,
8132 gen_helper_neon_qshl_u16
,
8133 gen_helper_neon_qshl_u32
}
8136 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8137 TCGMemOp memop
= scalar
? size
: MO_32
;
8138 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8140 for (pass
= 0; pass
< maxpass
; pass
++) {
8141 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8143 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8144 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8148 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8151 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8156 g_assert_not_reached();
8158 write_fp_sreg(s
, rd
, tcg_op
);
8160 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8163 tcg_temp_free_i32(tcg_op
);
8165 tcg_temp_free_i32(tcg_shift
);
8168 clear_vec_high(s
, is_q
, rd
);
8173 /* Common vector code for handling integer to FP conversion */
8174 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8175 int elements
, int is_signed
,
8176 int fracbits
, int size
)
8178 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8179 TCGv_i32 tcg_shift
= NULL
;
8181 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8184 if (fracbits
|| size
== MO_64
) {
8185 tcg_shift
= tcg_const_i32(fracbits
);
8188 if (size
== MO_64
) {
8189 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8190 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8192 for (pass
= 0; pass
< elements
; pass
++) {
8193 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8196 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8197 tcg_shift
, tcg_fpst
);
8199 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8200 tcg_shift
, tcg_fpst
);
8202 if (elements
== 1) {
8203 write_fp_dreg(s
, rd
, tcg_double
);
8205 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8209 tcg_temp_free_i64(tcg_int64
);
8210 tcg_temp_free_i64(tcg_double
);
8213 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8214 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8216 for (pass
= 0; pass
< elements
; pass
++) {
8217 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8223 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8224 tcg_shift
, tcg_fpst
);
8226 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8227 tcg_shift
, tcg_fpst
);
8231 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8233 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8240 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8241 tcg_shift
, tcg_fpst
);
8243 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8244 tcg_shift
, tcg_fpst
);
8248 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8250 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8255 g_assert_not_reached();
8258 if (elements
== 1) {
8259 write_fp_sreg(s
, rd
, tcg_float
);
8261 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8265 tcg_temp_free_i32(tcg_int32
);
8266 tcg_temp_free_i32(tcg_float
);
8269 tcg_temp_free_ptr(tcg_fpst
);
8271 tcg_temp_free_i32(tcg_shift
);
8274 clear_vec_high(s
, elements
<< size
== 16, rd
);
8277 /* UCVTF/SCVTF - Integer to FP conversion */
8278 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8279 bool is_q
, bool is_u
,
8280 int immh
, int immb
, int opcode
,
8283 int size
, elements
, fracbits
;
8284 int immhb
= immh
<< 3 | immb
;
8288 if (!is_scalar
&& !is_q
) {
8289 unallocated_encoding(s
);
8292 } else if (immh
& 4) {
8294 } else if (immh
& 2) {
8296 if (!dc_isar_feature(aa64_fp16
, s
)) {
8297 unallocated_encoding(s
);
8301 /* immh == 0 would be a failure of the decode logic */
8302 g_assert(immh
== 1);
8303 unallocated_encoding(s
);
8310 elements
= (8 << is_q
) >> size
;
8312 fracbits
= (16 << size
) - immhb
;
8314 if (!fp_access_check(s
)) {
8318 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8321 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8322 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8323 bool is_q
, bool is_u
,
8324 int immh
, int immb
, int rn
, int rd
)
8326 int immhb
= immh
<< 3 | immb
;
8327 int pass
, size
, fracbits
;
8328 TCGv_ptr tcg_fpstatus
;
8329 TCGv_i32 tcg_rmode
, tcg_shift
;
8333 if (!is_scalar
&& !is_q
) {
8334 unallocated_encoding(s
);
8337 } else if (immh
& 0x4) {
8339 } else if (immh
& 0x2) {
8341 if (!dc_isar_feature(aa64_fp16
, s
)) {
8342 unallocated_encoding(s
);
8346 /* Should have split out AdvSIMD modified immediate earlier. */
8348 unallocated_encoding(s
);
8352 if (!fp_access_check(s
)) {
8356 assert(!(is_scalar
&& is_q
));
8358 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8359 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8360 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8361 fracbits
= (16 << size
) - immhb
;
8362 tcg_shift
= tcg_const_i32(fracbits
);
8364 if (size
== MO_64
) {
8365 int maxpass
= is_scalar
? 1 : 2;
8367 for (pass
= 0; pass
< maxpass
; pass
++) {
8368 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8370 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8372 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8374 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8376 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8377 tcg_temp_free_i64(tcg_op
);
8379 clear_vec_high(s
, is_q
, rd
);
8381 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8382 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8387 fn
= gen_helper_vfp_touhh
;
8389 fn
= gen_helper_vfp_toshh
;
8394 fn
= gen_helper_vfp_touls
;
8396 fn
= gen_helper_vfp_tosls
;
8400 g_assert_not_reached();
8403 for (pass
= 0; pass
< maxpass
; pass
++) {
8404 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8406 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8407 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8409 write_fp_sreg(s
, rd
, tcg_op
);
8411 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8413 tcg_temp_free_i32(tcg_op
);
8416 clear_vec_high(s
, is_q
, rd
);
8420 tcg_temp_free_ptr(tcg_fpstatus
);
8421 tcg_temp_free_i32(tcg_shift
);
8422 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8423 tcg_temp_free_i32(tcg_rmode
);
8426 /* AdvSIMD scalar shift by immediate
8427 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8428 * +-----+---+-------------+------+------+--------+---+------+------+
8429 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8430 * +-----+---+-------------+------+------+--------+---+------+------+
8432 * This is the scalar version so it works on a fixed sized registers
8434 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8436 int rd
= extract32(insn
, 0, 5);
8437 int rn
= extract32(insn
, 5, 5);
8438 int opcode
= extract32(insn
, 11, 5);
8439 int immb
= extract32(insn
, 16, 3);
8440 int immh
= extract32(insn
, 19, 4);
8441 bool is_u
= extract32(insn
, 29, 1);
8444 unallocated_encoding(s
);
8449 case 0x08: /* SRI */
8451 unallocated_encoding(s
);
8455 case 0x00: /* SSHR / USHR */
8456 case 0x02: /* SSRA / USRA */
8457 case 0x04: /* SRSHR / URSHR */
8458 case 0x06: /* SRSRA / URSRA */
8459 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8461 case 0x0a: /* SHL / SLI */
8462 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8464 case 0x1c: /* SCVTF, UCVTF */
8465 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8468 case 0x10: /* SQSHRUN, SQSHRUN2 */
8469 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8471 unallocated_encoding(s
);
8474 handle_vec_simd_sqshrn(s
, true, false, false, true,
8475 immh
, immb
, opcode
, rn
, rd
);
8477 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8478 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8479 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8480 immh
, immb
, opcode
, rn
, rd
);
8482 case 0xc: /* SQSHLU */
8484 unallocated_encoding(s
);
8487 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8489 case 0xe: /* SQSHL, UQSHL */
8490 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8492 case 0x1f: /* FCVTZS, FCVTZU */
8493 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8496 unallocated_encoding(s
);
8501 /* AdvSIMD scalar three different
8502 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8503 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8504 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8505 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8507 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8509 bool is_u
= extract32(insn
, 29, 1);
8510 int size
= extract32(insn
, 22, 2);
8511 int opcode
= extract32(insn
, 12, 4);
8512 int rm
= extract32(insn
, 16, 5);
8513 int rn
= extract32(insn
, 5, 5);
8514 int rd
= extract32(insn
, 0, 5);
8517 unallocated_encoding(s
);
8522 case 0x9: /* SQDMLAL, SQDMLAL2 */
8523 case 0xb: /* SQDMLSL, SQDMLSL2 */
8524 case 0xd: /* SQDMULL, SQDMULL2 */
8525 if (size
== 0 || size
== 3) {
8526 unallocated_encoding(s
);
8531 unallocated_encoding(s
);
8535 if (!fp_access_check(s
)) {
8540 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8541 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8542 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8544 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8545 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8547 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8548 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8551 case 0xd: /* SQDMULL, SQDMULL2 */
8553 case 0xb: /* SQDMLSL, SQDMLSL2 */
8554 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8556 case 0x9: /* SQDMLAL, SQDMLAL2 */
8557 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8558 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8562 g_assert_not_reached();
8565 write_fp_dreg(s
, rd
, tcg_res
);
8567 tcg_temp_free_i64(tcg_op1
);
8568 tcg_temp_free_i64(tcg_op2
);
8569 tcg_temp_free_i64(tcg_res
);
8571 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8572 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8573 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8575 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8576 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8579 case 0xd: /* SQDMULL, SQDMULL2 */
8581 case 0xb: /* SQDMLSL, SQDMLSL2 */
8582 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8584 case 0x9: /* SQDMLAL, SQDMLAL2 */
8586 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8587 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8588 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8590 tcg_temp_free_i64(tcg_op3
);
8594 g_assert_not_reached();
8597 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8598 write_fp_dreg(s
, rd
, tcg_res
);
8600 tcg_temp_free_i32(tcg_op1
);
8601 tcg_temp_free_i32(tcg_op2
);
8602 tcg_temp_free_i64(tcg_res
);
8606 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8607 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8609 /* Handle 64x64->64 opcodes which are shared between the scalar
8610 * and vector 3-same groups. We cover every opcode where size == 3
8611 * is valid in either the three-reg-same (integer, not pairwise)
8612 * or scalar-three-reg-same groups.
8617 case 0x1: /* SQADD */
8619 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8621 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8624 case 0x5: /* SQSUB */
8626 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8628 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8631 case 0x6: /* CMGT, CMHI */
8632 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8633 * We implement this using setcond (test) and then negating.
8635 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8637 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8638 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8640 case 0x7: /* CMGE, CMHS */
8641 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8643 case 0x11: /* CMTST, CMEQ */
8648 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8650 case 0x8: /* SSHL, USHL */
8652 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8654 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8657 case 0x9: /* SQSHL, UQSHL */
8659 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8661 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8664 case 0xa: /* SRSHL, URSHL */
8666 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8668 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8671 case 0xb: /* SQRSHL, UQRSHL */
8673 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8675 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8678 case 0x10: /* ADD, SUB */
8680 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8682 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8686 g_assert_not_reached();
8690 /* Handle the 3-same-operands float operations; shared by the scalar
8691 * and vector encodings. The caller must filter out any encodings
8692 * not allocated for the encoding it is dealing with.
8694 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8695 int fpopcode
, int rd
, int rn
, int rm
)
8698 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8700 for (pass
= 0; pass
< elements
; pass
++) {
8703 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8704 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8705 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8707 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8708 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8711 case 0x39: /* FMLS */
8712 /* As usual for ARM, separate negation for fused multiply-add */
8713 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8715 case 0x19: /* FMLA */
8716 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8717 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8720 case 0x18: /* FMAXNM */
8721 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8723 case 0x1a: /* FADD */
8724 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8726 case 0x1b: /* FMULX */
8727 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8729 case 0x1c: /* FCMEQ */
8730 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8732 case 0x1e: /* FMAX */
8733 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8735 case 0x1f: /* FRECPS */
8736 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8738 case 0x38: /* FMINNM */
8739 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8741 case 0x3a: /* FSUB */
8742 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8744 case 0x3e: /* FMIN */
8745 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8747 case 0x3f: /* FRSQRTS */
8748 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8750 case 0x5b: /* FMUL */
8751 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8753 case 0x5c: /* FCMGE */
8754 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8756 case 0x5d: /* FACGE */
8757 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8759 case 0x5f: /* FDIV */
8760 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8762 case 0x7a: /* FABD */
8763 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8764 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8766 case 0x7c: /* FCMGT */
8767 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8769 case 0x7d: /* FACGT */
8770 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8773 g_assert_not_reached();
8776 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8778 tcg_temp_free_i64(tcg_res
);
8779 tcg_temp_free_i64(tcg_op1
);
8780 tcg_temp_free_i64(tcg_op2
);
8783 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8784 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8785 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8787 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8788 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8791 case 0x39: /* FMLS */
8792 /* As usual for ARM, separate negation for fused multiply-add */
8793 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8795 case 0x19: /* FMLA */
8796 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8797 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8800 case 0x1a: /* FADD */
8801 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8803 case 0x1b: /* FMULX */
8804 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8806 case 0x1c: /* FCMEQ */
8807 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8809 case 0x1e: /* FMAX */
8810 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8812 case 0x1f: /* FRECPS */
8813 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8815 case 0x18: /* FMAXNM */
8816 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8818 case 0x38: /* FMINNM */
8819 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8821 case 0x3a: /* FSUB */
8822 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8824 case 0x3e: /* FMIN */
8825 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8827 case 0x3f: /* FRSQRTS */
8828 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8830 case 0x5b: /* FMUL */
8831 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8833 case 0x5c: /* FCMGE */
8834 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8836 case 0x5d: /* FACGE */
8837 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8839 case 0x5f: /* FDIV */
8840 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8842 case 0x7a: /* FABD */
8843 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8844 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8846 case 0x7c: /* FCMGT */
8847 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8849 case 0x7d: /* FACGT */
8850 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8853 g_assert_not_reached();
8856 if (elements
== 1) {
8857 /* scalar single so clear high part */
8858 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8860 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8861 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8862 tcg_temp_free_i64(tcg_tmp
);
8864 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8867 tcg_temp_free_i32(tcg_res
);
8868 tcg_temp_free_i32(tcg_op1
);
8869 tcg_temp_free_i32(tcg_op2
);
8873 tcg_temp_free_ptr(fpst
);
8875 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8878 /* AdvSIMD scalar three same
8879 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8880 * +-----+---+-----------+------+---+------+--------+---+------+------+
8881 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8882 * +-----+---+-----------+------+---+------+--------+---+------+------+
8884 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8886 int rd
= extract32(insn
, 0, 5);
8887 int rn
= extract32(insn
, 5, 5);
8888 int opcode
= extract32(insn
, 11, 5);
8889 int rm
= extract32(insn
, 16, 5);
8890 int size
= extract32(insn
, 22, 2);
8891 bool u
= extract32(insn
, 29, 1);
8894 if (opcode
>= 0x18) {
8895 /* Floating point: U, size[1] and opcode indicate operation */
8896 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8898 case 0x1b: /* FMULX */
8899 case 0x1f: /* FRECPS */
8900 case 0x3f: /* FRSQRTS */
8901 case 0x5d: /* FACGE */
8902 case 0x7d: /* FACGT */
8903 case 0x1c: /* FCMEQ */
8904 case 0x5c: /* FCMGE */
8905 case 0x7c: /* FCMGT */
8906 case 0x7a: /* FABD */
8909 unallocated_encoding(s
);
8913 if (!fp_access_check(s
)) {
8917 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8922 case 0x1: /* SQADD, UQADD */
8923 case 0x5: /* SQSUB, UQSUB */
8924 case 0x9: /* SQSHL, UQSHL */
8925 case 0xb: /* SQRSHL, UQRSHL */
8927 case 0x8: /* SSHL, USHL */
8928 case 0xa: /* SRSHL, URSHL */
8929 case 0x6: /* CMGT, CMHI */
8930 case 0x7: /* CMGE, CMHS */
8931 case 0x11: /* CMTST, CMEQ */
8932 case 0x10: /* ADD, SUB (vector) */
8934 unallocated_encoding(s
);
8938 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8939 if (size
!= 1 && size
!= 2) {
8940 unallocated_encoding(s
);
8945 unallocated_encoding(s
);
8949 if (!fp_access_check(s
)) {
8953 tcg_rd
= tcg_temp_new_i64();
8956 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8957 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8959 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8960 tcg_temp_free_i64(tcg_rn
);
8961 tcg_temp_free_i64(tcg_rm
);
8963 /* Do a single operation on the lowest element in the vector.
8964 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8965 * no side effects for all these operations.
8966 * OPTME: special-purpose helpers would avoid doing some
8967 * unnecessary work in the helper for the 8 and 16 bit cases.
8969 NeonGenTwoOpEnvFn
*genenvfn
;
8970 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8971 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8972 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8974 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8975 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8978 case 0x1: /* SQADD, UQADD */
8980 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8981 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8982 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8983 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8985 genenvfn
= fns
[size
][u
];
8988 case 0x5: /* SQSUB, UQSUB */
8990 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8991 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8992 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8993 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8995 genenvfn
= fns
[size
][u
];
8998 case 0x9: /* SQSHL, UQSHL */
9000 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9001 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9002 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9003 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9005 genenvfn
= fns
[size
][u
];
9008 case 0xb: /* SQRSHL, UQRSHL */
9010 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9011 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9012 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9013 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9015 genenvfn
= fns
[size
][u
];
9018 case 0x16: /* SQDMULH, SQRDMULH */
9020 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9021 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9022 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9024 assert(size
== 1 || size
== 2);
9025 genenvfn
= fns
[size
- 1][u
];
9029 g_assert_not_reached();
9032 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9033 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9034 tcg_temp_free_i32(tcg_rd32
);
9035 tcg_temp_free_i32(tcg_rn
);
9036 tcg_temp_free_i32(tcg_rm
);
9039 write_fp_dreg(s
, rd
, tcg_rd
);
9041 tcg_temp_free_i64(tcg_rd
);
9044 /* AdvSIMD scalar three same FP16
9045 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9046 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9047 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9048 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9049 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9050 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9052 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9055 int rd
= extract32(insn
, 0, 5);
9056 int rn
= extract32(insn
, 5, 5);
9057 int opcode
= extract32(insn
, 11, 3);
9058 int rm
= extract32(insn
, 16, 5);
9059 bool u
= extract32(insn
, 29, 1);
9060 bool a
= extract32(insn
, 23, 1);
9061 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9068 case 0x03: /* FMULX */
9069 case 0x04: /* FCMEQ (reg) */
9070 case 0x07: /* FRECPS */
9071 case 0x0f: /* FRSQRTS */
9072 case 0x14: /* FCMGE (reg) */
9073 case 0x15: /* FACGE */
9074 case 0x1a: /* FABD */
9075 case 0x1c: /* FCMGT (reg) */
9076 case 0x1d: /* FACGT */
9079 unallocated_encoding(s
);
9083 if (!dc_isar_feature(aa64_fp16
, s
)) {
9084 unallocated_encoding(s
);
9087 if (!fp_access_check(s
)) {
9091 fpst
= get_fpstatus_ptr(true);
9093 tcg_op1
= read_fp_hreg(s
, rn
);
9094 tcg_op2
= read_fp_hreg(s
, rm
);
9095 tcg_res
= tcg_temp_new_i32();
9098 case 0x03: /* FMULX */
9099 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9101 case 0x04: /* FCMEQ (reg) */
9102 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9104 case 0x07: /* FRECPS */
9105 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9107 case 0x0f: /* FRSQRTS */
9108 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9110 case 0x14: /* FCMGE (reg) */
9111 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9113 case 0x15: /* FACGE */
9114 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9116 case 0x1a: /* FABD */
9117 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9118 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9120 case 0x1c: /* FCMGT (reg) */
9121 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9123 case 0x1d: /* FACGT */
9124 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9127 g_assert_not_reached();
9130 write_fp_sreg(s
, rd
, tcg_res
);
9133 tcg_temp_free_i32(tcg_res
);
9134 tcg_temp_free_i32(tcg_op1
);
9135 tcg_temp_free_i32(tcg_op2
);
9136 tcg_temp_free_ptr(fpst
);
9139 /* AdvSIMD scalar three same extra
9140 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9141 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9142 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9143 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9145 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9148 int rd
= extract32(insn
, 0, 5);
9149 int rn
= extract32(insn
, 5, 5);
9150 int opcode
= extract32(insn
, 11, 4);
9151 int rm
= extract32(insn
, 16, 5);
9152 int size
= extract32(insn
, 22, 2);
9153 bool u
= extract32(insn
, 29, 1);
9154 TCGv_i32 ele1
, ele2
, ele3
;
9158 switch (u
* 16 + opcode
) {
9159 case 0x10: /* SQRDMLAH (vector) */
9160 case 0x11: /* SQRDMLSH (vector) */
9161 if (size
!= 1 && size
!= 2) {
9162 unallocated_encoding(s
);
9165 feature
= dc_isar_feature(aa64_rdm
, s
);
9168 unallocated_encoding(s
);
9172 unallocated_encoding(s
);
9175 if (!fp_access_check(s
)) {
9179 /* Do a single operation on the lowest element in the vector.
9180 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9181 * with no side effects for all these operations.
9182 * OPTME: special-purpose helpers would avoid doing some
9183 * unnecessary work in the helper for the 16 bit cases.
9185 ele1
= tcg_temp_new_i32();
9186 ele2
= tcg_temp_new_i32();
9187 ele3
= tcg_temp_new_i32();
9189 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9190 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9191 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9194 case 0x0: /* SQRDMLAH */
9196 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9198 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9201 case 0x1: /* SQRDMLSH */
9203 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9205 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9209 g_assert_not_reached();
9211 tcg_temp_free_i32(ele1
);
9212 tcg_temp_free_i32(ele2
);
9214 res
= tcg_temp_new_i64();
9215 tcg_gen_extu_i32_i64(res
, ele3
);
9216 tcg_temp_free_i32(ele3
);
9218 write_fp_dreg(s
, rd
, res
);
9219 tcg_temp_free_i64(res
);
9222 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9223 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9224 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9226 /* Handle 64->64 opcodes which are shared between the scalar and
9227 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9228 * is valid in either group and also the double-precision fp ops.
9229 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9235 case 0x4: /* CLS, CLZ */
9237 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9239 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9243 /* This opcode is shared with CNT and RBIT but we have earlier
9244 * enforced that size == 3 if and only if this is the NOT insn.
9246 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9248 case 0x7: /* SQABS, SQNEG */
9250 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9252 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9255 case 0xa: /* CMLT */
9256 /* 64 bit integer comparison against zero, result is
9257 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9262 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9263 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9265 case 0x8: /* CMGT, CMGE */
9266 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9268 case 0x9: /* CMEQ, CMLE */
9269 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9271 case 0xb: /* ABS, NEG */
9273 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9275 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9276 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9277 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
9279 tcg_temp_free_i64(tcg_zero
);
9282 case 0x2f: /* FABS */
9283 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9285 case 0x6f: /* FNEG */
9286 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9288 case 0x7f: /* FSQRT */
9289 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9291 case 0x1a: /* FCVTNS */
9292 case 0x1b: /* FCVTMS */
9293 case 0x1c: /* FCVTAS */
9294 case 0x3a: /* FCVTPS */
9295 case 0x3b: /* FCVTZS */
9297 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9298 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9299 tcg_temp_free_i32(tcg_shift
);
9302 case 0x5a: /* FCVTNU */
9303 case 0x5b: /* FCVTMU */
9304 case 0x5c: /* FCVTAU */
9305 case 0x7a: /* FCVTPU */
9306 case 0x7b: /* FCVTZU */
9308 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9309 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9310 tcg_temp_free_i32(tcg_shift
);
9313 case 0x18: /* FRINTN */
9314 case 0x19: /* FRINTM */
9315 case 0x38: /* FRINTP */
9316 case 0x39: /* FRINTZ */
9317 case 0x58: /* FRINTA */
9318 case 0x79: /* FRINTI */
9319 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9321 case 0x59: /* FRINTX */
9322 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9325 g_assert_not_reached();
9329 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9330 bool is_scalar
, bool is_u
, bool is_q
,
9331 int size
, int rn
, int rd
)
9333 bool is_double
= (size
== MO_64
);
9336 if (!fp_access_check(s
)) {
9340 fpst
= get_fpstatus_ptr(size
== MO_16
);
9343 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9344 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9345 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9346 NeonGenTwoDoubleOPFn
*genfn
;
9351 case 0x2e: /* FCMLT (zero) */
9354 case 0x2c: /* FCMGT (zero) */
9355 genfn
= gen_helper_neon_cgt_f64
;
9357 case 0x2d: /* FCMEQ (zero) */
9358 genfn
= gen_helper_neon_ceq_f64
;
9360 case 0x6d: /* FCMLE (zero) */
9363 case 0x6c: /* FCMGE (zero) */
9364 genfn
= gen_helper_neon_cge_f64
;
9367 g_assert_not_reached();
9370 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9371 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9373 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9375 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9377 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9379 tcg_temp_free_i64(tcg_res
);
9380 tcg_temp_free_i64(tcg_zero
);
9381 tcg_temp_free_i64(tcg_op
);
9383 clear_vec_high(s
, !is_scalar
, rd
);
9385 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9386 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9387 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9388 NeonGenTwoSingleOPFn
*genfn
;
9390 int pass
, maxpasses
;
9392 if (size
== MO_16
) {
9394 case 0x2e: /* FCMLT (zero) */
9397 case 0x2c: /* FCMGT (zero) */
9398 genfn
= gen_helper_advsimd_cgt_f16
;
9400 case 0x2d: /* FCMEQ (zero) */
9401 genfn
= gen_helper_advsimd_ceq_f16
;
9403 case 0x6d: /* FCMLE (zero) */
9406 case 0x6c: /* FCMGE (zero) */
9407 genfn
= gen_helper_advsimd_cge_f16
;
9410 g_assert_not_reached();
9414 case 0x2e: /* FCMLT (zero) */
9417 case 0x2c: /* FCMGT (zero) */
9418 genfn
= gen_helper_neon_cgt_f32
;
9420 case 0x2d: /* FCMEQ (zero) */
9421 genfn
= gen_helper_neon_ceq_f32
;
9423 case 0x6d: /* FCMLE (zero) */
9426 case 0x6c: /* FCMGE (zero) */
9427 genfn
= gen_helper_neon_cge_f32
;
9430 g_assert_not_reached();
9437 int vector_size
= 8 << is_q
;
9438 maxpasses
= vector_size
>> size
;
9441 for (pass
= 0; pass
< maxpasses
; pass
++) {
9442 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9444 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9446 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9449 write_fp_sreg(s
, rd
, tcg_res
);
9451 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9454 tcg_temp_free_i32(tcg_res
);
9455 tcg_temp_free_i32(tcg_zero
);
9456 tcg_temp_free_i32(tcg_op
);
9458 clear_vec_high(s
, is_q
, rd
);
9462 tcg_temp_free_ptr(fpst
);
9465 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9466 bool is_scalar
, bool is_u
, bool is_q
,
9467 int size
, int rn
, int rd
)
9469 bool is_double
= (size
== 3);
9470 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9473 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9474 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9477 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9478 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9480 case 0x3d: /* FRECPE */
9481 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9483 case 0x3f: /* FRECPX */
9484 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9486 case 0x7d: /* FRSQRTE */
9487 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9490 g_assert_not_reached();
9492 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9494 tcg_temp_free_i64(tcg_res
);
9495 tcg_temp_free_i64(tcg_op
);
9496 clear_vec_high(s
, !is_scalar
, rd
);
9498 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9499 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9500 int pass
, maxpasses
;
9505 maxpasses
= is_q
? 4 : 2;
9508 for (pass
= 0; pass
< maxpasses
; pass
++) {
9509 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9512 case 0x3c: /* URECPE */
9513 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9515 case 0x3d: /* FRECPE */
9516 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9518 case 0x3f: /* FRECPX */
9519 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9521 case 0x7d: /* FRSQRTE */
9522 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9525 g_assert_not_reached();
9529 write_fp_sreg(s
, rd
, tcg_res
);
9531 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9534 tcg_temp_free_i32(tcg_res
);
9535 tcg_temp_free_i32(tcg_op
);
9537 clear_vec_high(s
, is_q
, rd
);
9540 tcg_temp_free_ptr(fpst
);
9543 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9544 int opcode
, bool u
, bool is_q
,
9545 int size
, int rn
, int rd
)
9547 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9548 * in the source becomes a size element in the destination).
9551 TCGv_i32 tcg_res
[2];
9552 int destelt
= is_q
? 2 : 0;
9553 int passes
= scalar
? 1 : 2;
9556 tcg_res
[1] = tcg_const_i32(0);
9559 for (pass
= 0; pass
< passes
; pass
++) {
9560 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9561 NeonGenNarrowFn
*genfn
= NULL
;
9562 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9565 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9567 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9569 tcg_res
[pass
] = tcg_temp_new_i32();
9572 case 0x12: /* XTN, SQXTUN */
9574 static NeonGenNarrowFn
* const xtnfns
[3] = {
9575 gen_helper_neon_narrow_u8
,
9576 gen_helper_neon_narrow_u16
,
9577 tcg_gen_extrl_i64_i32
,
9579 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9580 gen_helper_neon_unarrow_sat8
,
9581 gen_helper_neon_unarrow_sat16
,
9582 gen_helper_neon_unarrow_sat32
,
9585 genenvfn
= sqxtunfns
[size
];
9587 genfn
= xtnfns
[size
];
9591 case 0x14: /* SQXTN, UQXTN */
9593 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9594 { gen_helper_neon_narrow_sat_s8
,
9595 gen_helper_neon_narrow_sat_u8
},
9596 { gen_helper_neon_narrow_sat_s16
,
9597 gen_helper_neon_narrow_sat_u16
},
9598 { gen_helper_neon_narrow_sat_s32
,
9599 gen_helper_neon_narrow_sat_u32
},
9601 genenvfn
= fns
[size
][u
];
9604 case 0x16: /* FCVTN, FCVTN2 */
9605 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9607 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9609 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9610 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9611 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9612 TCGv_i32 ahp
= get_ahp_flag();
9614 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9615 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9616 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9617 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9618 tcg_temp_free_i32(tcg_lo
);
9619 tcg_temp_free_i32(tcg_hi
);
9620 tcg_temp_free_ptr(fpst
);
9621 tcg_temp_free_i32(ahp
);
9624 case 0x56: /* FCVTXN, FCVTXN2 */
9625 /* 64 bit to 32 bit float conversion
9626 * with von Neumann rounding (round to odd)
9629 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9632 g_assert_not_reached();
9636 genfn(tcg_res
[pass
], tcg_op
);
9637 } else if (genenvfn
) {
9638 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9641 tcg_temp_free_i64(tcg_op
);
9644 for (pass
= 0; pass
< 2; pass
++) {
9645 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9646 tcg_temp_free_i32(tcg_res
[pass
]);
9648 clear_vec_high(s
, is_q
, rd
);
9651 /* Remaining saturating accumulating ops */
9652 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9653 bool is_q
, int size
, int rn
, int rd
)
9655 bool is_double
= (size
== 3);
9658 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9659 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9662 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9663 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9664 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9666 if (is_u
) { /* USQADD */
9667 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9668 } else { /* SUQADD */
9669 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9671 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9673 tcg_temp_free_i64(tcg_rd
);
9674 tcg_temp_free_i64(tcg_rn
);
9675 clear_vec_high(s
, !is_scalar
, rd
);
9677 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9678 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9679 int pass
, maxpasses
;
9684 maxpasses
= is_q
? 4 : 2;
9687 for (pass
= 0; pass
< maxpasses
; pass
++) {
9689 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9690 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9692 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9693 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9696 if (is_u
) { /* USQADD */
9699 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9702 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9705 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9708 g_assert_not_reached();
9710 } else { /* SUQADD */
9713 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9716 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9719 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9722 g_assert_not_reached();
9727 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9728 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9729 tcg_temp_free_i64(tcg_zero
);
9731 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9733 tcg_temp_free_i32(tcg_rd
);
9734 tcg_temp_free_i32(tcg_rn
);
9735 clear_vec_high(s
, is_q
, rd
);
9739 /* AdvSIMD scalar two reg misc
9740 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9741 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9742 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9743 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9745 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9747 int rd
= extract32(insn
, 0, 5);
9748 int rn
= extract32(insn
, 5, 5);
9749 int opcode
= extract32(insn
, 12, 5);
9750 int size
= extract32(insn
, 22, 2);
9751 bool u
= extract32(insn
, 29, 1);
9752 bool is_fcvt
= false;
9755 TCGv_ptr tcg_fpstatus
;
9758 case 0x3: /* USQADD / SUQADD*/
9759 if (!fp_access_check(s
)) {
9762 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9764 case 0x7: /* SQABS / SQNEG */
9766 case 0xa: /* CMLT */
9768 unallocated_encoding(s
);
9772 case 0x8: /* CMGT, CMGE */
9773 case 0x9: /* CMEQ, CMLE */
9774 case 0xb: /* ABS, NEG */
9776 unallocated_encoding(s
);
9780 case 0x12: /* SQXTUN */
9782 unallocated_encoding(s
);
9786 case 0x14: /* SQXTN, UQXTN */
9788 unallocated_encoding(s
);
9791 if (!fp_access_check(s
)) {
9794 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9799 /* Floating point: U, size[1] and opcode indicate operation;
9800 * size[0] indicates single or double precision.
9802 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9803 size
= extract32(size
, 0, 1) ? 3 : 2;
9805 case 0x2c: /* FCMGT (zero) */
9806 case 0x2d: /* FCMEQ (zero) */
9807 case 0x2e: /* FCMLT (zero) */
9808 case 0x6c: /* FCMGE (zero) */
9809 case 0x6d: /* FCMLE (zero) */
9810 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9812 case 0x1d: /* SCVTF */
9813 case 0x5d: /* UCVTF */
9815 bool is_signed
= (opcode
== 0x1d);
9816 if (!fp_access_check(s
)) {
9819 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9822 case 0x3d: /* FRECPE */
9823 case 0x3f: /* FRECPX */
9824 case 0x7d: /* FRSQRTE */
9825 if (!fp_access_check(s
)) {
9828 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9830 case 0x1a: /* FCVTNS */
9831 case 0x1b: /* FCVTMS */
9832 case 0x3a: /* FCVTPS */
9833 case 0x3b: /* FCVTZS */
9834 case 0x5a: /* FCVTNU */
9835 case 0x5b: /* FCVTMU */
9836 case 0x7a: /* FCVTPU */
9837 case 0x7b: /* FCVTZU */
9839 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9841 case 0x1c: /* FCVTAS */
9842 case 0x5c: /* FCVTAU */
9843 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9845 rmode
= FPROUNDING_TIEAWAY
;
9847 case 0x56: /* FCVTXN, FCVTXN2 */
9849 unallocated_encoding(s
);
9852 if (!fp_access_check(s
)) {
9855 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9858 unallocated_encoding(s
);
9863 unallocated_encoding(s
);
9867 if (!fp_access_check(s
)) {
9872 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9873 tcg_fpstatus
= get_fpstatus_ptr(false);
9874 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9877 tcg_fpstatus
= NULL
;
9881 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9882 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9884 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9885 write_fp_dreg(s
, rd
, tcg_rd
);
9886 tcg_temp_free_i64(tcg_rd
);
9887 tcg_temp_free_i64(tcg_rn
);
9889 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9890 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9892 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9895 case 0x7: /* SQABS, SQNEG */
9897 NeonGenOneOpEnvFn
*genfn
;
9898 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9899 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9900 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9901 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9903 genfn
= fns
[size
][u
];
9904 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9907 case 0x1a: /* FCVTNS */
9908 case 0x1b: /* FCVTMS */
9909 case 0x1c: /* FCVTAS */
9910 case 0x3a: /* FCVTPS */
9911 case 0x3b: /* FCVTZS */
9913 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9914 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9915 tcg_temp_free_i32(tcg_shift
);
9918 case 0x5a: /* FCVTNU */
9919 case 0x5b: /* FCVTMU */
9920 case 0x5c: /* FCVTAU */
9921 case 0x7a: /* FCVTPU */
9922 case 0x7b: /* FCVTZU */
9924 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9925 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9926 tcg_temp_free_i32(tcg_shift
);
9930 g_assert_not_reached();
9933 write_fp_sreg(s
, rd
, tcg_rd
);
9934 tcg_temp_free_i32(tcg_rd
);
9935 tcg_temp_free_i32(tcg_rn
);
9939 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9940 tcg_temp_free_i32(tcg_rmode
);
9941 tcg_temp_free_ptr(tcg_fpstatus
);
9945 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9946 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9947 int immh
, int immb
, int opcode
, int rn
, int rd
)
9949 int size
= 32 - clz32(immh
) - 1;
9950 int immhb
= immh
<< 3 | immb
;
9951 int shift
= 2 * (8 << size
) - immhb
;
9952 bool accumulate
= false;
9953 int dsize
= is_q
? 128 : 64;
9954 int esize
= 8 << size
;
9955 int elements
= dsize
/esize
;
9956 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9957 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9958 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9960 uint64_t round_const
;
9963 if (extract32(immh
, 3, 1) && !is_q
) {
9964 unallocated_encoding(s
);
9967 tcg_debug_assert(size
<= 3);
9969 if (!fp_access_check(s
)) {
9974 case 0x02: /* SSRA / USRA (accumulate) */
9976 /* Shift count same as element size produces zero to add. */
9977 if (shift
== 8 << size
) {
9980 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9982 /* Shift count same as element size produces all sign to add. */
9983 if (shift
== 8 << size
) {
9986 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9989 case 0x08: /* SRI */
9990 /* Shift count same as element size is valid but does nothing. */
9991 if (shift
== 8 << size
) {
9994 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9997 case 0x00: /* SSHR / USHR */
9999 if (shift
== 8 << size
) {
10000 /* Shift count the same size as element size produces zero. */
10001 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10002 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10004 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10007 /* Shift count the same size as element size produces all sign. */
10008 if (shift
== 8 << size
) {
10011 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10015 case 0x04: /* SRSHR / URSHR (rounding) */
10017 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10021 g_assert_not_reached();
10024 round_const
= 1ULL << (shift
- 1);
10025 tcg_round
= tcg_const_i64(round_const
);
10027 for (i
= 0; i
< elements
; i
++) {
10028 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10030 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10033 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10034 accumulate
, is_u
, size
, shift
);
10036 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10038 tcg_temp_free_i64(tcg_round
);
10041 clear_vec_high(s
, is_q
, rd
);
10044 /* SHL/SLI - Vector shift left */
10045 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10046 int immh
, int immb
, int opcode
, int rn
, int rd
)
10048 int size
= 32 - clz32(immh
) - 1;
10049 int immhb
= immh
<< 3 | immb
;
10050 int shift
= immhb
- (8 << size
);
10052 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10053 assert(size
>= 0 && size
<= 3);
10055 if (extract32(immh
, 3, 1) && !is_q
) {
10056 unallocated_encoding(s
);
10060 if (!fp_access_check(s
)) {
10065 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10067 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10071 /* USHLL/SHLL - Vector shift left with widening */
10072 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10073 int immh
, int immb
, int opcode
, int rn
, int rd
)
10075 int size
= 32 - clz32(immh
) - 1;
10076 int immhb
= immh
<< 3 | immb
;
10077 int shift
= immhb
- (8 << size
);
10079 int esize
= 8 << size
;
10080 int elements
= dsize
/esize
;
10081 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10082 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10086 unallocated_encoding(s
);
10090 if (!fp_access_check(s
)) {
10094 /* For the LL variants the store is larger than the load,
10095 * so if rd == rn we would overwrite parts of our input.
10096 * So load everything right now and use shifts in the main loop.
10098 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10100 for (i
= 0; i
< elements
; i
++) {
10101 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10102 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10103 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10104 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10108 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10109 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10110 int immh
, int immb
, int opcode
, int rn
, int rd
)
10112 int immhb
= immh
<< 3 | immb
;
10113 int size
= 32 - clz32(immh
) - 1;
10115 int esize
= 8 << size
;
10116 int elements
= dsize
/esize
;
10117 int shift
= (2 * esize
) - immhb
;
10118 bool round
= extract32(opcode
, 0, 1);
10119 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10120 TCGv_i64 tcg_round
;
10123 if (extract32(immh
, 3, 1)) {
10124 unallocated_encoding(s
);
10128 if (!fp_access_check(s
)) {
10132 tcg_rn
= tcg_temp_new_i64();
10133 tcg_rd
= tcg_temp_new_i64();
10134 tcg_final
= tcg_temp_new_i64();
10135 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10138 uint64_t round_const
= 1ULL << (shift
- 1);
10139 tcg_round
= tcg_const_i64(round_const
);
10144 for (i
= 0; i
< elements
; i
++) {
10145 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10146 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10147 false, true, size
+1, shift
);
10149 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10153 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10155 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10158 tcg_temp_free_i64(tcg_round
);
10160 tcg_temp_free_i64(tcg_rn
);
10161 tcg_temp_free_i64(tcg_rd
);
10162 tcg_temp_free_i64(tcg_final
);
10164 clear_vec_high(s
, is_q
, rd
);
10168 /* AdvSIMD shift by immediate
10169 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10170 * +---+---+---+-------------+------+------+--------+---+------+------+
10171 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10172 * +---+---+---+-------------+------+------+--------+---+------+------+
10174 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10176 int rd
= extract32(insn
, 0, 5);
10177 int rn
= extract32(insn
, 5, 5);
10178 int opcode
= extract32(insn
, 11, 5);
10179 int immb
= extract32(insn
, 16, 3);
10180 int immh
= extract32(insn
, 19, 4);
10181 bool is_u
= extract32(insn
, 29, 1);
10182 bool is_q
= extract32(insn
, 30, 1);
10185 case 0x08: /* SRI */
10187 unallocated_encoding(s
);
10191 case 0x00: /* SSHR / USHR */
10192 case 0x02: /* SSRA / USRA (accumulate) */
10193 case 0x04: /* SRSHR / URSHR (rounding) */
10194 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10195 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10197 case 0x0a: /* SHL / SLI */
10198 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10200 case 0x10: /* SHRN */
10201 case 0x11: /* RSHRN / SQRSHRUN */
10203 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10206 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10209 case 0x12: /* SQSHRN / UQSHRN */
10210 case 0x13: /* SQRSHRN / UQRSHRN */
10211 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10214 case 0x14: /* SSHLL / USHLL */
10215 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10217 case 0x1c: /* SCVTF / UCVTF */
10218 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10221 case 0xc: /* SQSHLU */
10223 unallocated_encoding(s
);
10226 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10228 case 0xe: /* SQSHL, UQSHL */
10229 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10231 case 0x1f: /* FCVTZS/ FCVTZU */
10232 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10235 unallocated_encoding(s
);
10240 /* Generate code to do a "long" addition or subtraction, ie one done in
10241 * TCGv_i64 on vector lanes twice the width specified by size.
10243 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10244 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10246 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10247 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10248 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10249 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10251 NeonGenTwo64OpFn
*genfn
;
10254 genfn
= fns
[size
][is_sub
];
10255 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10258 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10259 int opcode
, int rd
, int rn
, int rm
)
10261 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10262 TCGv_i64 tcg_res
[2];
10265 tcg_res
[0] = tcg_temp_new_i64();
10266 tcg_res
[1] = tcg_temp_new_i64();
10268 /* Does this op do an adding accumulate, a subtracting accumulate,
10269 * or no accumulate at all?
10287 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10288 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10291 /* size == 2 means two 32x32->64 operations; this is worth special
10292 * casing because we can generally handle it inline.
10295 for (pass
= 0; pass
< 2; pass
++) {
10296 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10297 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10298 TCGv_i64 tcg_passres
;
10299 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10301 int elt
= pass
+ is_q
* 2;
10303 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10304 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10307 tcg_passres
= tcg_res
[pass
];
10309 tcg_passres
= tcg_temp_new_i64();
10313 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10314 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10316 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10317 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10319 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10320 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10322 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10323 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10325 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10326 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10327 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10329 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10330 tcg_temp_free_i64(tcg_tmp1
);
10331 tcg_temp_free_i64(tcg_tmp2
);
10334 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10335 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10336 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10337 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10339 case 9: /* SQDMLAL, SQDMLAL2 */
10340 case 11: /* SQDMLSL, SQDMLSL2 */
10341 case 13: /* SQDMULL, SQDMULL2 */
10342 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10343 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10344 tcg_passres
, tcg_passres
);
10347 g_assert_not_reached();
10350 if (opcode
== 9 || opcode
== 11) {
10351 /* saturating accumulate ops */
10353 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10355 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10356 tcg_res
[pass
], tcg_passres
);
10357 } else if (accop
> 0) {
10358 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10359 } else if (accop
< 0) {
10360 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10364 tcg_temp_free_i64(tcg_passres
);
10367 tcg_temp_free_i64(tcg_op1
);
10368 tcg_temp_free_i64(tcg_op2
);
10371 /* size 0 or 1, generally helper functions */
10372 for (pass
= 0; pass
< 2; pass
++) {
10373 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10374 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10375 TCGv_i64 tcg_passres
;
10376 int elt
= pass
+ is_q
* 2;
10378 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10379 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10382 tcg_passres
= tcg_res
[pass
];
10384 tcg_passres
= tcg_temp_new_i64();
10388 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10389 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10391 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10392 static NeonGenWidenFn
* const widenfns
[2][2] = {
10393 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10394 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10396 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10398 widenfn(tcg_op2_64
, tcg_op2
);
10399 widenfn(tcg_passres
, tcg_op1
);
10400 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10401 tcg_passres
, tcg_op2_64
);
10402 tcg_temp_free_i64(tcg_op2_64
);
10405 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10406 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10409 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10411 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10415 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10417 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10421 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10422 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10423 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10426 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10428 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10432 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10434 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10438 case 9: /* SQDMLAL, SQDMLAL2 */
10439 case 11: /* SQDMLSL, SQDMLSL2 */
10440 case 13: /* SQDMULL, SQDMULL2 */
10442 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10443 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10444 tcg_passres
, tcg_passres
);
10446 case 14: /* PMULL */
10448 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10451 g_assert_not_reached();
10453 tcg_temp_free_i32(tcg_op1
);
10454 tcg_temp_free_i32(tcg_op2
);
10457 if (opcode
== 9 || opcode
== 11) {
10458 /* saturating accumulate ops */
10460 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10462 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10466 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10467 tcg_res
[pass
], tcg_passres
);
10469 tcg_temp_free_i64(tcg_passres
);
10474 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10475 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10476 tcg_temp_free_i64(tcg_res
[0]);
10477 tcg_temp_free_i64(tcg_res
[1]);
10480 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10481 int opcode
, int rd
, int rn
, int rm
)
10483 TCGv_i64 tcg_res
[2];
10484 int part
= is_q
? 2 : 0;
10487 for (pass
= 0; pass
< 2; pass
++) {
10488 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10489 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10490 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10491 static NeonGenWidenFn
* const widenfns
[3][2] = {
10492 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10493 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10494 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10496 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10498 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10499 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10500 widenfn(tcg_op2_wide
, tcg_op2
);
10501 tcg_temp_free_i32(tcg_op2
);
10502 tcg_res
[pass
] = tcg_temp_new_i64();
10503 gen_neon_addl(size
, (opcode
== 3),
10504 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10505 tcg_temp_free_i64(tcg_op1
);
10506 tcg_temp_free_i64(tcg_op2_wide
);
10509 for (pass
= 0; pass
< 2; pass
++) {
10510 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10511 tcg_temp_free_i64(tcg_res
[pass
]);
10515 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10517 tcg_gen_addi_i64(in
, in
, 1U << 31);
10518 tcg_gen_extrh_i64_i32(res
, in
);
10521 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10522 int opcode
, int rd
, int rn
, int rm
)
10524 TCGv_i32 tcg_res
[2];
10525 int part
= is_q
? 2 : 0;
10528 for (pass
= 0; pass
< 2; pass
++) {
10529 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10530 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10531 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10532 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10533 { gen_helper_neon_narrow_high_u8
,
10534 gen_helper_neon_narrow_round_high_u8
},
10535 { gen_helper_neon_narrow_high_u16
,
10536 gen_helper_neon_narrow_round_high_u16
},
10537 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10539 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10541 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10542 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10544 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10546 tcg_temp_free_i64(tcg_op1
);
10547 tcg_temp_free_i64(tcg_op2
);
10549 tcg_res
[pass
] = tcg_temp_new_i32();
10550 gennarrow(tcg_res
[pass
], tcg_wideres
);
10551 tcg_temp_free_i64(tcg_wideres
);
10554 for (pass
= 0; pass
< 2; pass
++) {
10555 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10556 tcg_temp_free_i32(tcg_res
[pass
]);
10558 clear_vec_high(s
, is_q
, rd
);
10561 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10563 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10564 * is the only three-reg-diff instruction which produces a
10565 * 128-bit wide result from a single operation. However since
10566 * it's possible to calculate the two halves more or less
10567 * separately we just use two helper calls.
10569 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10570 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10571 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10573 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10574 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10575 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10576 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10577 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10578 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10580 tcg_temp_free_i64(tcg_op1
);
10581 tcg_temp_free_i64(tcg_op2
);
10582 tcg_temp_free_i64(tcg_res
);
10585 /* AdvSIMD three different
10586 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10587 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10588 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10589 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10591 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10593 /* Instructions in this group fall into three basic classes
10594 * (in each case with the operation working on each element in
10595 * the input vectors):
10596 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10598 * (2) wide 64 x 128 -> 128
10599 * (3) narrowing 128 x 128 -> 64
10600 * Here we do initial decode, catch unallocated cases and
10601 * dispatch to separate functions for each class.
10603 int is_q
= extract32(insn
, 30, 1);
10604 int is_u
= extract32(insn
, 29, 1);
10605 int size
= extract32(insn
, 22, 2);
10606 int opcode
= extract32(insn
, 12, 4);
10607 int rm
= extract32(insn
, 16, 5);
10608 int rn
= extract32(insn
, 5, 5);
10609 int rd
= extract32(insn
, 0, 5);
10612 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10613 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10614 /* 64 x 128 -> 128 */
10616 unallocated_encoding(s
);
10619 if (!fp_access_check(s
)) {
10622 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10624 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10625 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10626 /* 128 x 128 -> 64 */
10628 unallocated_encoding(s
);
10631 if (!fp_access_check(s
)) {
10634 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10636 case 14: /* PMULL, PMULL2 */
10637 if (is_u
|| size
== 1 || size
== 2) {
10638 unallocated_encoding(s
);
10642 if (!dc_isar_feature(aa64_pmull
, s
)) {
10643 unallocated_encoding(s
);
10646 if (!fp_access_check(s
)) {
10649 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10653 case 9: /* SQDMLAL, SQDMLAL2 */
10654 case 11: /* SQDMLSL, SQDMLSL2 */
10655 case 13: /* SQDMULL, SQDMULL2 */
10656 if (is_u
|| size
== 0) {
10657 unallocated_encoding(s
);
10661 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10662 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10663 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10664 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10665 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10666 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10667 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10668 /* 64 x 64 -> 128 */
10670 unallocated_encoding(s
);
10674 if (!fp_access_check(s
)) {
10678 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10681 /* opcode 15 not allocated */
10682 unallocated_encoding(s
);
10687 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10688 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10690 int rd
= extract32(insn
, 0, 5);
10691 int rn
= extract32(insn
, 5, 5);
10692 int rm
= extract32(insn
, 16, 5);
10693 int size
= extract32(insn
, 22, 2);
10694 bool is_u
= extract32(insn
, 29, 1);
10695 bool is_q
= extract32(insn
, 30, 1);
10697 if (!fp_access_check(s
)) {
10701 switch (size
+ 4 * is_u
) {
10703 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10706 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10709 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10712 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10715 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10718 case 5: /* BSL bitwise select */
10719 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10721 case 6: /* BIT, bitwise insert if true */
10722 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10724 case 7: /* BIF, bitwise insert if false */
10725 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10729 g_assert_not_reached();
10733 /* Pairwise op subgroup of C3.6.16.
10735 * This is called directly or via the handle_3same_float for float pairwise
10736 * operations where the opcode and size are calculated differently.
10738 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10739 int size
, int rn
, int rm
, int rd
)
10744 /* Floating point operations need fpst */
10745 if (opcode
>= 0x58) {
10746 fpst
= get_fpstatus_ptr(false);
10751 if (!fp_access_check(s
)) {
10755 /* These operations work on the concatenated rm:rn, with each pair of
10756 * adjacent elements being operated on to produce an element in the result.
10759 TCGv_i64 tcg_res
[2];
10761 for (pass
= 0; pass
< 2; pass
++) {
10762 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10763 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10764 int passreg
= (pass
== 0) ? rn
: rm
;
10766 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10767 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10768 tcg_res
[pass
] = tcg_temp_new_i64();
10771 case 0x17: /* ADDP */
10772 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10774 case 0x58: /* FMAXNMP */
10775 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10777 case 0x5a: /* FADDP */
10778 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10780 case 0x5e: /* FMAXP */
10781 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10783 case 0x78: /* FMINNMP */
10784 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10786 case 0x7e: /* FMINP */
10787 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10790 g_assert_not_reached();
10793 tcg_temp_free_i64(tcg_op1
);
10794 tcg_temp_free_i64(tcg_op2
);
10797 for (pass
= 0; pass
< 2; pass
++) {
10798 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10799 tcg_temp_free_i64(tcg_res
[pass
]);
10802 int maxpass
= is_q
? 4 : 2;
10803 TCGv_i32 tcg_res
[4];
10805 for (pass
= 0; pass
< maxpass
; pass
++) {
10806 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10807 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10808 NeonGenTwoOpFn
*genfn
= NULL
;
10809 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10810 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10812 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10813 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10814 tcg_res
[pass
] = tcg_temp_new_i32();
10817 case 0x17: /* ADDP */
10819 static NeonGenTwoOpFn
* const fns
[3] = {
10820 gen_helper_neon_padd_u8
,
10821 gen_helper_neon_padd_u16
,
10827 case 0x14: /* SMAXP, UMAXP */
10829 static NeonGenTwoOpFn
* const fns
[3][2] = {
10830 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10831 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10832 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10834 genfn
= fns
[size
][u
];
10837 case 0x15: /* SMINP, UMINP */
10839 static NeonGenTwoOpFn
* const fns
[3][2] = {
10840 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10841 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10842 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10844 genfn
= fns
[size
][u
];
10847 /* The FP operations are all on single floats (32 bit) */
10848 case 0x58: /* FMAXNMP */
10849 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10851 case 0x5a: /* FADDP */
10852 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10854 case 0x5e: /* FMAXP */
10855 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10857 case 0x78: /* FMINNMP */
10858 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10860 case 0x7e: /* FMINP */
10861 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10864 g_assert_not_reached();
10867 /* FP ops called directly, otherwise call now */
10869 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10872 tcg_temp_free_i32(tcg_op1
);
10873 tcg_temp_free_i32(tcg_op2
);
10876 for (pass
= 0; pass
< maxpass
; pass
++) {
10877 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10878 tcg_temp_free_i32(tcg_res
[pass
]);
10880 clear_vec_high(s
, is_q
, rd
);
10884 tcg_temp_free_ptr(fpst
);
10888 /* Floating point op subgroup of C3.6.16. */
10889 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10891 /* For floating point ops, the U, size[1] and opcode bits
10892 * together indicate the operation. size[0] indicates single
10895 int fpopcode
= extract32(insn
, 11, 5)
10896 | (extract32(insn
, 23, 1) << 5)
10897 | (extract32(insn
, 29, 1) << 6);
10898 int is_q
= extract32(insn
, 30, 1);
10899 int size
= extract32(insn
, 22, 1);
10900 int rm
= extract32(insn
, 16, 5);
10901 int rn
= extract32(insn
, 5, 5);
10902 int rd
= extract32(insn
, 0, 5);
10904 int datasize
= is_q
? 128 : 64;
10905 int esize
= 32 << size
;
10906 int elements
= datasize
/ esize
;
10908 if (size
== 1 && !is_q
) {
10909 unallocated_encoding(s
);
10913 switch (fpopcode
) {
10914 case 0x58: /* FMAXNMP */
10915 case 0x5a: /* FADDP */
10916 case 0x5e: /* FMAXP */
10917 case 0x78: /* FMINNMP */
10918 case 0x7e: /* FMINP */
10919 if (size
&& !is_q
) {
10920 unallocated_encoding(s
);
10923 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10926 case 0x1b: /* FMULX */
10927 case 0x1f: /* FRECPS */
10928 case 0x3f: /* FRSQRTS */
10929 case 0x5d: /* FACGE */
10930 case 0x7d: /* FACGT */
10931 case 0x19: /* FMLA */
10932 case 0x39: /* FMLS */
10933 case 0x18: /* FMAXNM */
10934 case 0x1a: /* FADD */
10935 case 0x1c: /* FCMEQ */
10936 case 0x1e: /* FMAX */
10937 case 0x38: /* FMINNM */
10938 case 0x3a: /* FSUB */
10939 case 0x3e: /* FMIN */
10940 case 0x5b: /* FMUL */
10941 case 0x5c: /* FCMGE */
10942 case 0x5f: /* FDIV */
10943 case 0x7a: /* FABD */
10944 case 0x7c: /* FCMGT */
10945 if (!fp_access_check(s
)) {
10948 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10951 case 0x1d: /* FMLAL */
10952 case 0x3d: /* FMLSL */
10953 case 0x59: /* FMLAL2 */
10954 case 0x79: /* FMLSL2 */
10955 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
10956 unallocated_encoding(s
);
10959 if (fp_access_check(s
)) {
10960 int is_s
= extract32(insn
, 23, 1);
10961 int is_2
= extract32(insn
, 29, 1);
10962 int data
= (is_2
<< 1) | is_s
;
10963 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
10964 vec_full_reg_offset(s
, rn
),
10965 vec_full_reg_offset(s
, rm
), cpu_env
,
10966 is_q
? 16 : 8, vec_full_reg_size(s
),
10967 data
, gen_helper_gvec_fmlal_a64
);
10972 unallocated_encoding(s
);
10977 /* Integer op subgroup of C3.6.16. */
10978 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10980 int is_q
= extract32(insn
, 30, 1);
10981 int u
= extract32(insn
, 29, 1);
10982 int size
= extract32(insn
, 22, 2);
10983 int opcode
= extract32(insn
, 11, 5);
10984 int rm
= extract32(insn
, 16, 5);
10985 int rn
= extract32(insn
, 5, 5);
10986 int rd
= extract32(insn
, 0, 5);
10991 case 0x13: /* MUL, PMUL */
10992 if (u
&& size
!= 0) {
10993 unallocated_encoding(s
);
10997 case 0x0: /* SHADD, UHADD */
10998 case 0x2: /* SRHADD, URHADD */
10999 case 0x4: /* SHSUB, UHSUB */
11000 case 0xc: /* SMAX, UMAX */
11001 case 0xd: /* SMIN, UMIN */
11002 case 0xe: /* SABD, UABD */
11003 case 0xf: /* SABA, UABA */
11004 case 0x12: /* MLA, MLS */
11006 unallocated_encoding(s
);
11010 case 0x16: /* SQDMULH, SQRDMULH */
11011 if (size
== 0 || size
== 3) {
11012 unallocated_encoding(s
);
11017 if (size
== 3 && !is_q
) {
11018 unallocated_encoding(s
);
11024 if (!fp_access_check(s
)) {
11029 case 0x01: /* SQADD, UQADD */
11030 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11031 offsetof(CPUARMState
, vfp
.qc
),
11032 vec_full_reg_offset(s
, rn
),
11033 vec_full_reg_offset(s
, rm
),
11034 is_q
? 16 : 8, vec_full_reg_size(s
),
11035 (u
? uqadd_op
: sqadd_op
) + size
);
11037 case 0x05: /* SQSUB, UQSUB */
11038 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11039 offsetof(CPUARMState
, vfp
.qc
),
11040 vec_full_reg_offset(s
, rn
),
11041 vec_full_reg_offset(s
, rm
),
11042 is_q
? 16 : 8, vec_full_reg_size(s
),
11043 (u
? uqsub_op
: sqsub_op
) + size
);
11045 case 0x0c: /* SMAX, UMAX */
11047 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11049 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11052 case 0x0d: /* SMIN, UMIN */
11054 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11056 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11059 case 0x10: /* ADD, SUB */
11061 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11063 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11066 case 0x13: /* MUL, PMUL */
11067 if (!u
) { /* MUL */
11068 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11072 case 0x12: /* MLA, MLS */
11074 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11076 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11080 if (!u
) { /* CMTST */
11081 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11085 cond
= TCG_COND_EQ
;
11087 case 0x06: /* CMGT, CMHI */
11088 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11090 case 0x07: /* CMGE, CMHS */
11091 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11093 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11094 vec_full_reg_offset(s
, rn
),
11095 vec_full_reg_offset(s
, rm
),
11096 is_q
? 16 : 8, vec_full_reg_size(s
));
11102 for (pass
= 0; pass
< 2; pass
++) {
11103 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11104 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11105 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11107 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11108 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11110 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11112 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11114 tcg_temp_free_i64(tcg_res
);
11115 tcg_temp_free_i64(tcg_op1
);
11116 tcg_temp_free_i64(tcg_op2
);
11119 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11120 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11121 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11122 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11123 NeonGenTwoOpFn
*genfn
= NULL
;
11124 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11126 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11127 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11130 case 0x0: /* SHADD, UHADD */
11132 static NeonGenTwoOpFn
* const fns
[3][2] = {
11133 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11134 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11135 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11137 genfn
= fns
[size
][u
];
11140 case 0x2: /* SRHADD, URHADD */
11142 static NeonGenTwoOpFn
* const fns
[3][2] = {
11143 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11144 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11145 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11147 genfn
= fns
[size
][u
];
11150 case 0x4: /* SHSUB, UHSUB */
11152 static NeonGenTwoOpFn
* const fns
[3][2] = {
11153 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11154 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11155 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11157 genfn
= fns
[size
][u
];
11160 case 0x8: /* SSHL, USHL */
11162 static NeonGenTwoOpFn
* const fns
[3][2] = {
11163 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11164 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11165 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11167 genfn
= fns
[size
][u
];
11170 case 0x9: /* SQSHL, UQSHL */
11172 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11173 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11174 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11175 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11177 genenvfn
= fns
[size
][u
];
11180 case 0xa: /* SRSHL, URSHL */
11182 static NeonGenTwoOpFn
* const fns
[3][2] = {
11183 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11184 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11185 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11187 genfn
= fns
[size
][u
];
11190 case 0xb: /* SQRSHL, UQRSHL */
11192 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11193 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11194 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11195 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11197 genenvfn
= fns
[size
][u
];
11200 case 0xe: /* SABD, UABD */
11201 case 0xf: /* SABA, UABA */
11203 static NeonGenTwoOpFn
* const fns
[3][2] = {
11204 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11205 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11206 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11208 genfn
= fns
[size
][u
];
11211 case 0x13: /* MUL, PMUL */
11212 assert(u
); /* PMUL */
11214 genfn
= gen_helper_neon_mul_p8
;
11216 case 0x16: /* SQDMULH, SQRDMULH */
11218 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11219 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11220 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11222 assert(size
== 1 || size
== 2);
11223 genenvfn
= fns
[size
- 1][u
];
11227 g_assert_not_reached();
11231 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11233 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11236 if (opcode
== 0xf) {
11237 /* SABA, UABA: accumulating ops */
11238 static NeonGenTwoOpFn
* const fns
[3] = {
11239 gen_helper_neon_add_u8
,
11240 gen_helper_neon_add_u16
,
11244 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11245 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11248 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11250 tcg_temp_free_i32(tcg_res
);
11251 tcg_temp_free_i32(tcg_op1
);
11252 tcg_temp_free_i32(tcg_op2
);
11255 clear_vec_high(s
, is_q
, rd
);
11258 /* AdvSIMD three same
11259 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11260 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11261 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11262 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11264 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11266 int opcode
= extract32(insn
, 11, 5);
11269 case 0x3: /* logic ops */
11270 disas_simd_3same_logic(s
, insn
);
11272 case 0x17: /* ADDP */
11273 case 0x14: /* SMAXP, UMAXP */
11274 case 0x15: /* SMINP, UMINP */
11276 /* Pairwise operations */
11277 int is_q
= extract32(insn
, 30, 1);
11278 int u
= extract32(insn
, 29, 1);
11279 int size
= extract32(insn
, 22, 2);
11280 int rm
= extract32(insn
, 16, 5);
11281 int rn
= extract32(insn
, 5, 5);
11282 int rd
= extract32(insn
, 0, 5);
11283 if (opcode
== 0x17) {
11284 if (u
|| (size
== 3 && !is_q
)) {
11285 unallocated_encoding(s
);
11290 unallocated_encoding(s
);
11294 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11297 case 0x18 ... 0x31:
11298 /* floating point ops, sz[1] and U are part of opcode */
11299 disas_simd_3same_float(s
, insn
);
11302 disas_simd_3same_int(s
, insn
);
11308 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11310 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11311 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11312 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11313 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11315 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11316 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11319 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11321 int opcode
, fpopcode
;
11322 int is_q
, u
, a
, rm
, rn
, rd
;
11323 int datasize
, elements
;
11326 bool pairwise
= false;
11328 if (!dc_isar_feature(aa64_fp16
, s
)) {
11329 unallocated_encoding(s
);
11333 if (!fp_access_check(s
)) {
11337 /* For these floating point ops, the U, a and opcode bits
11338 * together indicate the operation.
11340 opcode
= extract32(insn
, 11, 3);
11341 u
= extract32(insn
, 29, 1);
11342 a
= extract32(insn
, 23, 1);
11343 is_q
= extract32(insn
, 30, 1);
11344 rm
= extract32(insn
, 16, 5);
11345 rn
= extract32(insn
, 5, 5);
11346 rd
= extract32(insn
, 0, 5);
11348 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11349 datasize
= is_q
? 128 : 64;
11350 elements
= datasize
/ 16;
11352 switch (fpopcode
) {
11353 case 0x10: /* FMAXNMP */
11354 case 0x12: /* FADDP */
11355 case 0x16: /* FMAXP */
11356 case 0x18: /* FMINNMP */
11357 case 0x1e: /* FMINP */
11362 fpst
= get_fpstatus_ptr(true);
11365 int maxpass
= is_q
? 8 : 4;
11366 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11367 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11368 TCGv_i32 tcg_res
[8];
11370 for (pass
= 0; pass
< maxpass
; pass
++) {
11371 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11372 int passelt
= (pass
<< 1) & (maxpass
- 1);
11374 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11375 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11376 tcg_res
[pass
] = tcg_temp_new_i32();
11378 switch (fpopcode
) {
11379 case 0x10: /* FMAXNMP */
11380 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11383 case 0x12: /* FADDP */
11384 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11386 case 0x16: /* FMAXP */
11387 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11389 case 0x18: /* FMINNMP */
11390 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11393 case 0x1e: /* FMINP */
11394 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11397 g_assert_not_reached();
11401 for (pass
= 0; pass
< maxpass
; pass
++) {
11402 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11403 tcg_temp_free_i32(tcg_res
[pass
]);
11406 tcg_temp_free_i32(tcg_op1
);
11407 tcg_temp_free_i32(tcg_op2
);
11410 for (pass
= 0; pass
< elements
; pass
++) {
11411 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11412 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11413 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11415 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11416 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11418 switch (fpopcode
) {
11419 case 0x0: /* FMAXNM */
11420 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11422 case 0x1: /* FMLA */
11423 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11424 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11427 case 0x2: /* FADD */
11428 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11430 case 0x3: /* FMULX */
11431 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11433 case 0x4: /* FCMEQ */
11434 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11436 case 0x6: /* FMAX */
11437 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11439 case 0x7: /* FRECPS */
11440 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11442 case 0x8: /* FMINNM */
11443 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11445 case 0x9: /* FMLS */
11446 /* As usual for ARM, separate negation for fused multiply-add */
11447 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11448 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11449 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11452 case 0xa: /* FSUB */
11453 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11455 case 0xe: /* FMIN */
11456 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11458 case 0xf: /* FRSQRTS */
11459 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11461 case 0x13: /* FMUL */
11462 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11464 case 0x14: /* FCMGE */
11465 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11467 case 0x15: /* FACGE */
11468 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11470 case 0x17: /* FDIV */
11471 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11473 case 0x1a: /* FABD */
11474 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11475 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11477 case 0x1c: /* FCMGT */
11478 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11480 case 0x1d: /* FACGT */
11481 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11484 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11485 __func__
, insn
, fpopcode
, s
->pc
);
11486 g_assert_not_reached();
11489 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11490 tcg_temp_free_i32(tcg_res
);
11491 tcg_temp_free_i32(tcg_op1
);
11492 tcg_temp_free_i32(tcg_op2
);
11496 tcg_temp_free_ptr(fpst
);
11498 clear_vec_high(s
, is_q
, rd
);
11501 /* AdvSIMD three same extra
11502 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11503 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11504 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11505 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11507 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11509 int rd
= extract32(insn
, 0, 5);
11510 int rn
= extract32(insn
, 5, 5);
11511 int opcode
= extract32(insn
, 11, 4);
11512 int rm
= extract32(insn
, 16, 5);
11513 int size
= extract32(insn
, 22, 2);
11514 bool u
= extract32(insn
, 29, 1);
11515 bool is_q
= extract32(insn
, 30, 1);
11519 switch (u
* 16 + opcode
) {
11520 case 0x10: /* SQRDMLAH (vector) */
11521 case 0x11: /* SQRDMLSH (vector) */
11522 if (size
!= 1 && size
!= 2) {
11523 unallocated_encoding(s
);
11526 feature
= dc_isar_feature(aa64_rdm
, s
);
11528 case 0x02: /* SDOT (vector) */
11529 case 0x12: /* UDOT (vector) */
11530 if (size
!= MO_32
) {
11531 unallocated_encoding(s
);
11534 feature
= dc_isar_feature(aa64_dp
, s
);
11536 case 0x18: /* FCMLA, #0 */
11537 case 0x19: /* FCMLA, #90 */
11538 case 0x1a: /* FCMLA, #180 */
11539 case 0x1b: /* FCMLA, #270 */
11540 case 0x1c: /* FCADD, #90 */
11541 case 0x1e: /* FCADD, #270 */
11543 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11544 || (size
== 3 && !is_q
)) {
11545 unallocated_encoding(s
);
11548 feature
= dc_isar_feature(aa64_fcma
, s
);
11551 unallocated_encoding(s
);
11555 unallocated_encoding(s
);
11558 if (!fp_access_check(s
)) {
11563 case 0x0: /* SQRDMLAH (vector) */
11566 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11569 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11572 g_assert_not_reached();
11576 case 0x1: /* SQRDMLSH (vector) */
11579 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11582 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11585 g_assert_not_reached();
11589 case 0x2: /* SDOT / UDOT */
11590 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11591 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11594 case 0x8: /* FCMLA, #0 */
11595 case 0x9: /* FCMLA, #90 */
11596 case 0xa: /* FCMLA, #180 */
11597 case 0xb: /* FCMLA, #270 */
11598 rot
= extract32(opcode
, 0, 2);
11601 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11602 gen_helper_gvec_fcmlah
);
11605 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11606 gen_helper_gvec_fcmlas
);
11609 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11610 gen_helper_gvec_fcmlad
);
11613 g_assert_not_reached();
11617 case 0xc: /* FCADD, #90 */
11618 case 0xe: /* FCADD, #270 */
11619 rot
= extract32(opcode
, 1, 1);
11622 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11623 gen_helper_gvec_fcaddh
);
11626 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11627 gen_helper_gvec_fcadds
);
11630 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11631 gen_helper_gvec_fcaddd
);
11634 g_assert_not_reached();
11639 g_assert_not_reached();
11643 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11644 int size
, int rn
, int rd
)
11646 /* Handle 2-reg-misc ops which are widening (so each size element
11647 * in the source becomes a 2*size element in the destination.
11648 * The only instruction like this is FCVTL.
11653 /* 32 -> 64 bit fp conversion */
11654 TCGv_i64 tcg_res
[2];
11655 int srcelt
= is_q
? 2 : 0;
11657 for (pass
= 0; pass
< 2; pass
++) {
11658 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11659 tcg_res
[pass
] = tcg_temp_new_i64();
11661 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11662 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11663 tcg_temp_free_i32(tcg_op
);
11665 for (pass
= 0; pass
< 2; pass
++) {
11666 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11667 tcg_temp_free_i64(tcg_res
[pass
]);
11670 /* 16 -> 32 bit fp conversion */
11671 int srcelt
= is_q
? 4 : 0;
11672 TCGv_i32 tcg_res
[4];
11673 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11674 TCGv_i32 ahp
= get_ahp_flag();
11676 for (pass
= 0; pass
< 4; pass
++) {
11677 tcg_res
[pass
] = tcg_temp_new_i32();
11679 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11680 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11683 for (pass
= 0; pass
< 4; pass
++) {
11684 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11685 tcg_temp_free_i32(tcg_res
[pass
]);
11688 tcg_temp_free_ptr(fpst
);
11689 tcg_temp_free_i32(ahp
);
11693 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11694 bool is_q
, int size
, int rn
, int rd
)
11696 int op
= (opcode
<< 1) | u
;
11697 int opsz
= op
+ size
;
11698 int grp_size
= 3 - opsz
;
11699 int dsize
= is_q
? 128 : 64;
11703 unallocated_encoding(s
);
11707 if (!fp_access_check(s
)) {
11712 /* Special case bytes, use bswap op on each group of elements */
11713 int groups
= dsize
/ (8 << grp_size
);
11715 for (i
= 0; i
< groups
; i
++) {
11716 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11718 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11719 switch (grp_size
) {
11721 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11724 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11727 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11730 g_assert_not_reached();
11732 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11733 tcg_temp_free_i64(tcg_tmp
);
11735 clear_vec_high(s
, is_q
, rd
);
11737 int revmask
= (1 << grp_size
) - 1;
11738 int esize
= 8 << size
;
11739 int elements
= dsize
/ esize
;
11740 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11741 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11742 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11744 for (i
= 0; i
< elements
; i
++) {
11745 int e_rev
= (i
& 0xf) ^ revmask
;
11746 int off
= e_rev
* esize
;
11747 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11749 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11750 tcg_rn
, off
- 64, esize
);
11752 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11755 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11756 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11758 tcg_temp_free_i64(tcg_rd_hi
);
11759 tcg_temp_free_i64(tcg_rd
);
11760 tcg_temp_free_i64(tcg_rn
);
11764 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11765 bool is_q
, int size
, int rn
, int rd
)
11767 /* Implement the pairwise operations from 2-misc:
11768 * SADDLP, UADDLP, SADALP, UADALP.
11769 * These all add pairs of elements in the input to produce a
11770 * double-width result element in the output (possibly accumulating).
11772 bool accum
= (opcode
== 0x6);
11773 int maxpass
= is_q
? 2 : 1;
11775 TCGv_i64 tcg_res
[2];
11778 /* 32 + 32 -> 64 op */
11779 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11781 for (pass
= 0; pass
< maxpass
; pass
++) {
11782 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11783 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11785 tcg_res
[pass
] = tcg_temp_new_i64();
11787 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11788 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11789 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11791 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11792 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11795 tcg_temp_free_i64(tcg_op1
);
11796 tcg_temp_free_i64(tcg_op2
);
11799 for (pass
= 0; pass
< maxpass
; pass
++) {
11800 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11801 NeonGenOneOpFn
*genfn
;
11802 static NeonGenOneOpFn
* const fns
[2][2] = {
11803 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11804 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11807 genfn
= fns
[size
][u
];
11809 tcg_res
[pass
] = tcg_temp_new_i64();
11811 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11812 genfn(tcg_res
[pass
], tcg_op
);
11815 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11817 gen_helper_neon_addl_u16(tcg_res
[pass
],
11818 tcg_res
[pass
], tcg_op
);
11820 gen_helper_neon_addl_u32(tcg_res
[pass
],
11821 tcg_res
[pass
], tcg_op
);
11824 tcg_temp_free_i64(tcg_op
);
11828 tcg_res
[1] = tcg_const_i64(0);
11830 for (pass
= 0; pass
< 2; pass
++) {
11831 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11832 tcg_temp_free_i64(tcg_res
[pass
]);
11836 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11838 /* Implement SHLL and SHLL2 */
11840 int part
= is_q
? 2 : 0;
11841 TCGv_i64 tcg_res
[2];
11843 for (pass
= 0; pass
< 2; pass
++) {
11844 static NeonGenWidenFn
* const widenfns
[3] = {
11845 gen_helper_neon_widen_u8
,
11846 gen_helper_neon_widen_u16
,
11847 tcg_gen_extu_i32_i64
,
11849 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11850 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11852 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11853 tcg_res
[pass
] = tcg_temp_new_i64();
11854 widenfn(tcg_res
[pass
], tcg_op
);
11855 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11857 tcg_temp_free_i32(tcg_op
);
11860 for (pass
= 0; pass
< 2; pass
++) {
11861 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11862 tcg_temp_free_i64(tcg_res
[pass
]);
11866 /* AdvSIMD two reg misc
11867 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11868 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11869 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11870 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11872 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11874 int size
= extract32(insn
, 22, 2);
11875 int opcode
= extract32(insn
, 12, 5);
11876 bool u
= extract32(insn
, 29, 1);
11877 bool is_q
= extract32(insn
, 30, 1);
11878 int rn
= extract32(insn
, 5, 5);
11879 int rd
= extract32(insn
, 0, 5);
11880 bool need_fpstatus
= false;
11881 bool need_rmode
= false;
11883 TCGv_i32 tcg_rmode
;
11884 TCGv_ptr tcg_fpstatus
;
11887 case 0x0: /* REV64, REV32 */
11888 case 0x1: /* REV16 */
11889 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11891 case 0x5: /* CNT, NOT, RBIT */
11892 if (u
&& size
== 0) {
11895 } else if (u
&& size
== 1) {
11898 } else if (!u
&& size
== 0) {
11902 unallocated_encoding(s
);
11904 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11905 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11907 unallocated_encoding(s
);
11910 if (!fp_access_check(s
)) {
11914 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11916 case 0x4: /* CLS, CLZ */
11918 unallocated_encoding(s
);
11922 case 0x2: /* SADDLP, UADDLP */
11923 case 0x6: /* SADALP, UADALP */
11925 unallocated_encoding(s
);
11928 if (!fp_access_check(s
)) {
11931 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11933 case 0x13: /* SHLL, SHLL2 */
11934 if (u
== 0 || size
== 3) {
11935 unallocated_encoding(s
);
11938 if (!fp_access_check(s
)) {
11941 handle_shll(s
, is_q
, size
, rn
, rd
);
11943 case 0xa: /* CMLT */
11945 unallocated_encoding(s
);
11949 case 0x8: /* CMGT, CMGE */
11950 case 0x9: /* CMEQ, CMLE */
11951 case 0xb: /* ABS, NEG */
11952 if (size
== 3 && !is_q
) {
11953 unallocated_encoding(s
);
11957 case 0x3: /* SUQADD, USQADD */
11958 if (size
== 3 && !is_q
) {
11959 unallocated_encoding(s
);
11962 if (!fp_access_check(s
)) {
11965 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11967 case 0x7: /* SQABS, SQNEG */
11968 if (size
== 3 && !is_q
) {
11969 unallocated_encoding(s
);
11974 case 0x16 ... 0x1d:
11977 /* Floating point: U, size[1] and opcode indicate operation;
11978 * size[0] indicates single or double precision.
11980 int is_double
= extract32(size
, 0, 1);
11981 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11982 size
= is_double
? 3 : 2;
11984 case 0x2f: /* FABS */
11985 case 0x6f: /* FNEG */
11986 if (size
== 3 && !is_q
) {
11987 unallocated_encoding(s
);
11991 case 0x1d: /* SCVTF */
11992 case 0x5d: /* UCVTF */
11994 bool is_signed
= (opcode
== 0x1d) ? true : false;
11995 int elements
= is_double
? 2 : is_q
? 4 : 2;
11996 if (is_double
&& !is_q
) {
11997 unallocated_encoding(s
);
12000 if (!fp_access_check(s
)) {
12003 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12006 case 0x2c: /* FCMGT (zero) */
12007 case 0x2d: /* FCMEQ (zero) */
12008 case 0x2e: /* FCMLT (zero) */
12009 case 0x6c: /* FCMGE (zero) */
12010 case 0x6d: /* FCMLE (zero) */
12011 if (size
== 3 && !is_q
) {
12012 unallocated_encoding(s
);
12015 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12017 case 0x7f: /* FSQRT */
12018 if (size
== 3 && !is_q
) {
12019 unallocated_encoding(s
);
12023 case 0x1a: /* FCVTNS */
12024 case 0x1b: /* FCVTMS */
12025 case 0x3a: /* FCVTPS */
12026 case 0x3b: /* FCVTZS */
12027 case 0x5a: /* FCVTNU */
12028 case 0x5b: /* FCVTMU */
12029 case 0x7a: /* FCVTPU */
12030 case 0x7b: /* FCVTZU */
12031 need_fpstatus
= true;
12033 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12034 if (size
== 3 && !is_q
) {
12035 unallocated_encoding(s
);
12039 case 0x5c: /* FCVTAU */
12040 case 0x1c: /* FCVTAS */
12041 need_fpstatus
= true;
12043 rmode
= FPROUNDING_TIEAWAY
;
12044 if (size
== 3 && !is_q
) {
12045 unallocated_encoding(s
);
12049 case 0x3c: /* URECPE */
12051 unallocated_encoding(s
);
12055 case 0x3d: /* FRECPE */
12056 case 0x7d: /* FRSQRTE */
12057 if (size
== 3 && !is_q
) {
12058 unallocated_encoding(s
);
12061 if (!fp_access_check(s
)) {
12064 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12066 case 0x56: /* FCVTXN, FCVTXN2 */
12068 unallocated_encoding(s
);
12072 case 0x16: /* FCVTN, FCVTN2 */
12073 /* handle_2misc_narrow does a 2*size -> size operation, but these
12074 * instructions encode the source size rather than dest size.
12076 if (!fp_access_check(s
)) {
12079 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12081 case 0x17: /* FCVTL, FCVTL2 */
12082 if (!fp_access_check(s
)) {
12085 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12087 case 0x18: /* FRINTN */
12088 case 0x19: /* FRINTM */
12089 case 0x38: /* FRINTP */
12090 case 0x39: /* FRINTZ */
12092 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12094 case 0x59: /* FRINTX */
12095 case 0x79: /* FRINTI */
12096 need_fpstatus
= true;
12097 if (size
== 3 && !is_q
) {
12098 unallocated_encoding(s
);
12102 case 0x58: /* FRINTA */
12104 rmode
= FPROUNDING_TIEAWAY
;
12105 need_fpstatus
= true;
12106 if (size
== 3 && !is_q
) {
12107 unallocated_encoding(s
);
12111 case 0x7c: /* URSQRTE */
12113 unallocated_encoding(s
);
12116 need_fpstatus
= true;
12119 unallocated_encoding(s
);
12125 unallocated_encoding(s
);
12129 if (!fp_access_check(s
)) {
12133 if (need_fpstatus
|| need_rmode
) {
12134 tcg_fpstatus
= get_fpstatus_ptr(false);
12136 tcg_fpstatus
= NULL
;
12139 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12140 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12147 if (u
&& size
== 0) { /* NOT */
12148 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12154 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12161 /* All 64-bit element operations can be shared with scalar 2misc */
12164 /* Coverity claims (size == 3 && !is_q) has been eliminated
12165 * from all paths leading to here.
12167 tcg_debug_assert(is_q
);
12168 for (pass
= 0; pass
< 2; pass
++) {
12169 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12170 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12172 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12174 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12175 tcg_rmode
, tcg_fpstatus
);
12177 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12179 tcg_temp_free_i64(tcg_res
);
12180 tcg_temp_free_i64(tcg_op
);
12185 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12186 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12187 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12190 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12193 /* Special cases for 32 bit elements */
12195 case 0xa: /* CMLT */
12196 /* 32 bit integer comparison against zero, result is
12197 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12200 cond
= TCG_COND_LT
;
12202 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12203 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12205 case 0x8: /* CMGT, CMGE */
12206 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12208 case 0x9: /* CMEQ, CMLE */
12209 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12211 case 0x4: /* CLS */
12213 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12215 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12218 case 0x7: /* SQABS, SQNEG */
12220 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12222 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12225 case 0xb: /* ABS, NEG */
12227 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12229 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12230 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12231 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12232 tcg_zero
, tcg_op
, tcg_res
);
12233 tcg_temp_free_i32(tcg_zero
);
12236 case 0x2f: /* FABS */
12237 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12239 case 0x6f: /* FNEG */
12240 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12242 case 0x7f: /* FSQRT */
12243 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12245 case 0x1a: /* FCVTNS */
12246 case 0x1b: /* FCVTMS */
12247 case 0x1c: /* FCVTAS */
12248 case 0x3a: /* FCVTPS */
12249 case 0x3b: /* FCVTZS */
12251 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12252 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12253 tcg_shift
, tcg_fpstatus
);
12254 tcg_temp_free_i32(tcg_shift
);
12257 case 0x5a: /* FCVTNU */
12258 case 0x5b: /* FCVTMU */
12259 case 0x5c: /* FCVTAU */
12260 case 0x7a: /* FCVTPU */
12261 case 0x7b: /* FCVTZU */
12263 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12264 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12265 tcg_shift
, tcg_fpstatus
);
12266 tcg_temp_free_i32(tcg_shift
);
12269 case 0x18: /* FRINTN */
12270 case 0x19: /* FRINTM */
12271 case 0x38: /* FRINTP */
12272 case 0x39: /* FRINTZ */
12273 case 0x58: /* FRINTA */
12274 case 0x79: /* FRINTI */
12275 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12277 case 0x59: /* FRINTX */
12278 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12280 case 0x7c: /* URSQRTE */
12281 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12284 g_assert_not_reached();
12287 /* Use helpers for 8 and 16 bit elements */
12289 case 0x5: /* CNT, RBIT */
12290 /* For these two insns size is part of the opcode specifier
12291 * (handled earlier); they always operate on byte elements.
12294 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12296 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12299 case 0x7: /* SQABS, SQNEG */
12301 NeonGenOneOpEnvFn
*genfn
;
12302 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12303 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12304 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12306 genfn
= fns
[size
][u
];
12307 genfn(tcg_res
, cpu_env
, tcg_op
);
12310 case 0x8: /* CMGT, CMGE */
12311 case 0x9: /* CMEQ, CMLE */
12312 case 0xa: /* CMLT */
12314 static NeonGenTwoOpFn
* const fns
[3][2] = {
12315 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12316 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12317 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12319 NeonGenTwoOpFn
*genfn
;
12322 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12324 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12325 comp
= (opcode
- 0x8) * 2 + u
;
12326 /* ...but LE, LT are implemented as reverse GE, GT */
12327 reverse
= (comp
> 2);
12331 genfn
= fns
[comp
][size
];
12333 genfn(tcg_res
, tcg_zero
, tcg_op
);
12335 genfn(tcg_res
, tcg_op
, tcg_zero
);
12337 tcg_temp_free_i32(tcg_zero
);
12340 case 0xb: /* ABS, NEG */
12342 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12344 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12346 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12348 tcg_temp_free_i32(tcg_zero
);
12351 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12353 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12357 case 0x4: /* CLS, CLZ */
12360 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12362 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12366 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12368 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12373 g_assert_not_reached();
12377 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12379 tcg_temp_free_i32(tcg_res
);
12380 tcg_temp_free_i32(tcg_op
);
12383 clear_vec_high(s
, is_q
, rd
);
12386 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12387 tcg_temp_free_i32(tcg_rmode
);
12389 if (need_fpstatus
) {
12390 tcg_temp_free_ptr(tcg_fpstatus
);
12394 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12396 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12397 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12398 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12399 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12400 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12401 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12403 * This actually covers two groups where scalar access is governed by
12404 * bit 28. A bunch of the instructions (float to integral) only exist
12405 * in the vector form and are un-allocated for the scalar decode. Also
12406 * in the scalar decode Q is always 1.
12408 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12410 int fpop
, opcode
, a
, u
;
12414 bool only_in_vector
= false;
12417 TCGv_i32 tcg_rmode
= NULL
;
12418 TCGv_ptr tcg_fpstatus
= NULL
;
12419 bool need_rmode
= false;
12420 bool need_fpst
= true;
12423 if (!dc_isar_feature(aa64_fp16
, s
)) {
12424 unallocated_encoding(s
);
12428 rd
= extract32(insn
, 0, 5);
12429 rn
= extract32(insn
, 5, 5);
12431 a
= extract32(insn
, 23, 1);
12432 u
= extract32(insn
, 29, 1);
12433 is_scalar
= extract32(insn
, 28, 1);
12434 is_q
= extract32(insn
, 30, 1);
12436 opcode
= extract32(insn
, 12, 5);
12437 fpop
= deposit32(opcode
, 5, 1, a
);
12438 fpop
= deposit32(fpop
, 6, 1, u
);
12440 rd
= extract32(insn
, 0, 5);
12441 rn
= extract32(insn
, 5, 5);
12444 case 0x1d: /* SCVTF */
12445 case 0x5d: /* UCVTF */
12452 elements
= (is_q
? 8 : 4);
12455 if (!fp_access_check(s
)) {
12458 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12462 case 0x2c: /* FCMGT (zero) */
12463 case 0x2d: /* FCMEQ (zero) */
12464 case 0x2e: /* FCMLT (zero) */
12465 case 0x6c: /* FCMGE (zero) */
12466 case 0x6d: /* FCMLE (zero) */
12467 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12469 case 0x3d: /* FRECPE */
12470 case 0x3f: /* FRECPX */
12472 case 0x18: /* FRINTN */
12474 only_in_vector
= true;
12475 rmode
= FPROUNDING_TIEEVEN
;
12477 case 0x19: /* FRINTM */
12479 only_in_vector
= true;
12480 rmode
= FPROUNDING_NEGINF
;
12482 case 0x38: /* FRINTP */
12484 only_in_vector
= true;
12485 rmode
= FPROUNDING_POSINF
;
12487 case 0x39: /* FRINTZ */
12489 only_in_vector
= true;
12490 rmode
= FPROUNDING_ZERO
;
12492 case 0x58: /* FRINTA */
12494 only_in_vector
= true;
12495 rmode
= FPROUNDING_TIEAWAY
;
12497 case 0x59: /* FRINTX */
12498 case 0x79: /* FRINTI */
12499 only_in_vector
= true;
12500 /* current rounding mode */
12502 case 0x1a: /* FCVTNS */
12504 rmode
= FPROUNDING_TIEEVEN
;
12506 case 0x1b: /* FCVTMS */
12508 rmode
= FPROUNDING_NEGINF
;
12510 case 0x1c: /* FCVTAS */
12512 rmode
= FPROUNDING_TIEAWAY
;
12514 case 0x3a: /* FCVTPS */
12516 rmode
= FPROUNDING_POSINF
;
12518 case 0x3b: /* FCVTZS */
12520 rmode
= FPROUNDING_ZERO
;
12522 case 0x5a: /* FCVTNU */
12524 rmode
= FPROUNDING_TIEEVEN
;
12526 case 0x5b: /* FCVTMU */
12528 rmode
= FPROUNDING_NEGINF
;
12530 case 0x5c: /* FCVTAU */
12532 rmode
= FPROUNDING_TIEAWAY
;
12534 case 0x7a: /* FCVTPU */
12536 rmode
= FPROUNDING_POSINF
;
12538 case 0x7b: /* FCVTZU */
12540 rmode
= FPROUNDING_ZERO
;
12542 case 0x2f: /* FABS */
12543 case 0x6f: /* FNEG */
12546 case 0x7d: /* FRSQRTE */
12547 case 0x7f: /* FSQRT (vector) */
12550 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12551 g_assert_not_reached();
12555 /* Check additional constraints for the scalar encoding */
12558 unallocated_encoding(s
);
12561 /* FRINTxx is only in the vector form */
12562 if (only_in_vector
) {
12563 unallocated_encoding(s
);
12568 if (!fp_access_check(s
)) {
12572 if (need_rmode
|| need_fpst
) {
12573 tcg_fpstatus
= get_fpstatus_ptr(true);
12577 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12578 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12582 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12583 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12586 case 0x1a: /* FCVTNS */
12587 case 0x1b: /* FCVTMS */
12588 case 0x1c: /* FCVTAS */
12589 case 0x3a: /* FCVTPS */
12590 case 0x3b: /* FCVTZS */
12591 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12593 case 0x3d: /* FRECPE */
12594 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12596 case 0x3f: /* FRECPX */
12597 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12599 case 0x5a: /* FCVTNU */
12600 case 0x5b: /* FCVTMU */
12601 case 0x5c: /* FCVTAU */
12602 case 0x7a: /* FCVTPU */
12603 case 0x7b: /* FCVTZU */
12604 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12606 case 0x6f: /* FNEG */
12607 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12609 case 0x7d: /* FRSQRTE */
12610 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12613 g_assert_not_reached();
12616 /* limit any sign extension going on */
12617 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12618 write_fp_sreg(s
, rd
, tcg_res
);
12620 tcg_temp_free_i32(tcg_res
);
12621 tcg_temp_free_i32(tcg_op
);
12623 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12624 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12625 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12627 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12630 case 0x1a: /* FCVTNS */
12631 case 0x1b: /* FCVTMS */
12632 case 0x1c: /* FCVTAS */
12633 case 0x3a: /* FCVTPS */
12634 case 0x3b: /* FCVTZS */
12635 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12637 case 0x3d: /* FRECPE */
12638 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12640 case 0x5a: /* FCVTNU */
12641 case 0x5b: /* FCVTMU */
12642 case 0x5c: /* FCVTAU */
12643 case 0x7a: /* FCVTPU */
12644 case 0x7b: /* FCVTZU */
12645 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12647 case 0x18: /* FRINTN */
12648 case 0x19: /* FRINTM */
12649 case 0x38: /* FRINTP */
12650 case 0x39: /* FRINTZ */
12651 case 0x58: /* FRINTA */
12652 case 0x79: /* FRINTI */
12653 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12655 case 0x59: /* FRINTX */
12656 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12658 case 0x2f: /* FABS */
12659 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12661 case 0x6f: /* FNEG */
12662 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12664 case 0x7d: /* FRSQRTE */
12665 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12667 case 0x7f: /* FSQRT */
12668 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12671 g_assert_not_reached();
12674 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12676 tcg_temp_free_i32(tcg_res
);
12677 tcg_temp_free_i32(tcg_op
);
12680 clear_vec_high(s
, is_q
, rd
);
12684 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12685 tcg_temp_free_i32(tcg_rmode
);
12688 if (tcg_fpstatus
) {
12689 tcg_temp_free_ptr(tcg_fpstatus
);
12693 /* AdvSIMD scalar x indexed element
12694 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12695 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12696 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12697 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12698 * AdvSIMD vector x indexed element
12699 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12700 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12701 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12702 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12704 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12706 /* This encoding has two kinds of instruction:
12707 * normal, where we perform elt x idxelt => elt for each
12708 * element in the vector
12709 * long, where we perform elt x idxelt and generate a result of
12710 * double the width of the input element
12711 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12713 bool is_scalar
= extract32(insn
, 28, 1);
12714 bool is_q
= extract32(insn
, 30, 1);
12715 bool u
= extract32(insn
, 29, 1);
12716 int size
= extract32(insn
, 22, 2);
12717 int l
= extract32(insn
, 21, 1);
12718 int m
= extract32(insn
, 20, 1);
12719 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12720 int rm
= extract32(insn
, 16, 4);
12721 int opcode
= extract32(insn
, 12, 4);
12722 int h
= extract32(insn
, 11, 1);
12723 int rn
= extract32(insn
, 5, 5);
12724 int rd
= extract32(insn
, 0, 5);
12725 bool is_long
= false;
12727 bool is_fp16
= false;
12731 switch (16 * u
+ opcode
) {
12732 case 0x08: /* MUL */
12733 case 0x10: /* MLA */
12734 case 0x14: /* MLS */
12736 unallocated_encoding(s
);
12740 case 0x02: /* SMLAL, SMLAL2 */
12741 case 0x12: /* UMLAL, UMLAL2 */
12742 case 0x06: /* SMLSL, SMLSL2 */
12743 case 0x16: /* UMLSL, UMLSL2 */
12744 case 0x0a: /* SMULL, SMULL2 */
12745 case 0x1a: /* UMULL, UMULL2 */
12747 unallocated_encoding(s
);
12752 case 0x03: /* SQDMLAL, SQDMLAL2 */
12753 case 0x07: /* SQDMLSL, SQDMLSL2 */
12754 case 0x0b: /* SQDMULL, SQDMULL2 */
12757 case 0x0c: /* SQDMULH */
12758 case 0x0d: /* SQRDMULH */
12760 case 0x01: /* FMLA */
12761 case 0x05: /* FMLS */
12762 case 0x09: /* FMUL */
12763 case 0x19: /* FMULX */
12766 case 0x1d: /* SQRDMLAH */
12767 case 0x1f: /* SQRDMLSH */
12768 if (!dc_isar_feature(aa64_rdm
, s
)) {
12769 unallocated_encoding(s
);
12773 case 0x0e: /* SDOT */
12774 case 0x1e: /* UDOT */
12775 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12776 unallocated_encoding(s
);
12780 case 0x11: /* FCMLA #0 */
12781 case 0x13: /* FCMLA #90 */
12782 case 0x15: /* FCMLA #180 */
12783 case 0x17: /* FCMLA #270 */
12784 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12785 unallocated_encoding(s
);
12790 case 0x00: /* FMLAL */
12791 case 0x04: /* FMLSL */
12792 case 0x18: /* FMLAL2 */
12793 case 0x1c: /* FMLSL2 */
12794 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12795 unallocated_encoding(s
);
12799 /* is_fp, but we pass cpu_env not fp_status. */
12802 unallocated_encoding(s
);
12807 case 1: /* normal fp */
12808 /* convert insn encoded size to TCGMemOp size */
12810 case 0: /* half-precision */
12814 case MO_32
: /* single precision */
12815 case MO_64
: /* double precision */
12818 unallocated_encoding(s
);
12823 case 2: /* complex fp */
12824 /* Each indexable element is a complex pair. */
12829 unallocated_encoding(s
);
12837 unallocated_encoding(s
);
12842 default: /* integer */
12846 unallocated_encoding(s
);
12851 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12852 unallocated_encoding(s
);
12856 /* Given TCGMemOp size, adjust register and indexing. */
12859 index
= h
<< 2 | l
<< 1 | m
;
12862 index
= h
<< 1 | l
;
12867 unallocated_encoding(s
);
12874 g_assert_not_reached();
12877 if (!fp_access_check(s
)) {
12882 fpst
= get_fpstatus_ptr(is_fp16
);
12887 switch (16 * u
+ opcode
) {
12888 case 0x0e: /* SDOT */
12889 case 0x1e: /* UDOT */
12890 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12891 u
? gen_helper_gvec_udot_idx_b
12892 : gen_helper_gvec_sdot_idx_b
);
12894 case 0x11: /* FCMLA #0 */
12895 case 0x13: /* FCMLA #90 */
12896 case 0x15: /* FCMLA #180 */
12897 case 0x17: /* FCMLA #270 */
12899 int rot
= extract32(insn
, 13, 2);
12900 int data
= (index
<< 2) | rot
;
12901 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12902 vec_full_reg_offset(s
, rn
),
12903 vec_full_reg_offset(s
, rm
), fpst
,
12904 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12906 ? gen_helper_gvec_fcmlas_idx
12907 : gen_helper_gvec_fcmlah_idx
);
12908 tcg_temp_free_ptr(fpst
);
12912 case 0x00: /* FMLAL */
12913 case 0x04: /* FMLSL */
12914 case 0x18: /* FMLAL2 */
12915 case 0x1c: /* FMLSL2 */
12917 int is_s
= extract32(opcode
, 2, 1);
12919 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
12920 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12921 vec_full_reg_offset(s
, rn
),
12922 vec_full_reg_offset(s
, rm
), cpu_env
,
12923 is_q
? 16 : 8, vec_full_reg_size(s
),
12924 data
, gen_helper_gvec_fmlal_idx_a64
);
12930 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12933 assert(is_fp
&& is_q
&& !is_long
);
12935 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12937 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12938 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12939 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12941 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12943 switch (16 * u
+ opcode
) {
12944 case 0x05: /* FMLS */
12945 /* As usual for ARM, separate negation for fused multiply-add */
12946 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12948 case 0x01: /* FMLA */
12949 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12950 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12952 case 0x09: /* FMUL */
12953 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12955 case 0x19: /* FMULX */
12956 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12959 g_assert_not_reached();
12962 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12963 tcg_temp_free_i64(tcg_op
);
12964 tcg_temp_free_i64(tcg_res
);
12967 tcg_temp_free_i64(tcg_idx
);
12968 clear_vec_high(s
, !is_scalar
, rd
);
12969 } else if (!is_long
) {
12970 /* 32 bit floating point, or 16 or 32 bit integer.
12971 * For the 16 bit scalar case we use the usual Neon helpers and
12972 * rely on the fact that 0 op 0 == 0 with no side effects.
12974 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12975 int pass
, maxpasses
;
12980 maxpasses
= is_q
? 4 : 2;
12983 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12985 if (size
== 1 && !is_scalar
) {
12986 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12987 * the index into both halves of the 32 bit tcg_idx and then use
12988 * the usual Neon helpers.
12990 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12993 for (pass
= 0; pass
< maxpasses
; pass
++) {
12994 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12995 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12997 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12999 switch (16 * u
+ opcode
) {
13000 case 0x08: /* MUL */
13001 case 0x10: /* MLA */
13002 case 0x14: /* MLS */
13004 static NeonGenTwoOpFn
* const fns
[2][2] = {
13005 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13006 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13008 NeonGenTwoOpFn
*genfn
;
13009 bool is_sub
= opcode
== 0x4;
13012 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13014 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13016 if (opcode
== 0x8) {
13019 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13020 genfn
= fns
[size
- 1][is_sub
];
13021 genfn(tcg_res
, tcg_op
, tcg_res
);
13024 case 0x05: /* FMLS */
13025 case 0x01: /* FMLA */
13026 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13027 is_scalar
? size
: MO_32
);
13030 if (opcode
== 0x5) {
13031 /* As usual for ARM, separate negation for fused
13033 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13036 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13039 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13044 if (opcode
== 0x5) {
13045 /* As usual for ARM, separate negation for
13046 * fused multiply-add */
13047 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13049 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13053 g_assert_not_reached();
13056 case 0x09: /* FMUL */
13060 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13063 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13068 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13071 g_assert_not_reached();
13074 case 0x19: /* FMULX */
13078 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13081 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13086 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13089 g_assert_not_reached();
13092 case 0x0c: /* SQDMULH */
13094 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13097 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13101 case 0x0d: /* SQRDMULH */
13103 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13106 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13110 case 0x1d: /* SQRDMLAH */
13111 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13112 is_scalar
? size
: MO_32
);
13114 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13115 tcg_op
, tcg_idx
, tcg_res
);
13117 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13118 tcg_op
, tcg_idx
, tcg_res
);
13121 case 0x1f: /* SQRDMLSH */
13122 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13123 is_scalar
? size
: MO_32
);
13125 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13126 tcg_op
, tcg_idx
, tcg_res
);
13128 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13129 tcg_op
, tcg_idx
, tcg_res
);
13133 g_assert_not_reached();
13137 write_fp_sreg(s
, rd
, tcg_res
);
13139 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13142 tcg_temp_free_i32(tcg_op
);
13143 tcg_temp_free_i32(tcg_res
);
13146 tcg_temp_free_i32(tcg_idx
);
13147 clear_vec_high(s
, is_q
, rd
);
13149 /* long ops: 16x16->32 or 32x32->64 */
13150 TCGv_i64 tcg_res
[2];
13152 bool satop
= extract32(opcode
, 0, 1);
13153 TCGMemOp memop
= MO_32
;
13160 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13162 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13164 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13165 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13166 TCGv_i64 tcg_passres
;
13172 passelt
= pass
+ (is_q
* 2);
13175 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13177 tcg_res
[pass
] = tcg_temp_new_i64();
13179 if (opcode
== 0xa || opcode
== 0xb) {
13180 /* Non-accumulating ops */
13181 tcg_passres
= tcg_res
[pass
];
13183 tcg_passres
= tcg_temp_new_i64();
13186 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13187 tcg_temp_free_i64(tcg_op
);
13190 /* saturating, doubling */
13191 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13192 tcg_passres
, tcg_passres
);
13195 if (opcode
== 0xa || opcode
== 0xb) {
13199 /* Accumulating op: handle accumulate step */
13200 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13203 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13204 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13206 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13207 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13209 case 0x7: /* SQDMLSL, SQDMLSL2 */
13210 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13212 case 0x3: /* SQDMLAL, SQDMLAL2 */
13213 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13218 g_assert_not_reached();
13220 tcg_temp_free_i64(tcg_passres
);
13222 tcg_temp_free_i64(tcg_idx
);
13224 clear_vec_high(s
, !is_scalar
, rd
);
13226 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13229 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13232 /* The simplest way to handle the 16x16 indexed ops is to
13233 * duplicate the index into both halves of the 32 bit tcg_idx
13234 * and then use the usual Neon helpers.
13236 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13239 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13240 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13241 TCGv_i64 tcg_passres
;
13244 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13246 read_vec_element_i32(s
, tcg_op
, rn
,
13247 pass
+ (is_q
* 2), MO_32
);
13250 tcg_res
[pass
] = tcg_temp_new_i64();
13252 if (opcode
== 0xa || opcode
== 0xb) {
13253 /* Non-accumulating ops */
13254 tcg_passres
= tcg_res
[pass
];
13256 tcg_passres
= tcg_temp_new_i64();
13259 if (memop
& MO_SIGN
) {
13260 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13262 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13265 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13266 tcg_passres
, tcg_passres
);
13268 tcg_temp_free_i32(tcg_op
);
13270 if (opcode
== 0xa || opcode
== 0xb) {
13274 /* Accumulating op: handle accumulate step */
13275 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13278 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13279 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13282 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13283 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13286 case 0x7: /* SQDMLSL, SQDMLSL2 */
13287 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13289 case 0x3: /* SQDMLAL, SQDMLAL2 */
13290 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13295 g_assert_not_reached();
13297 tcg_temp_free_i64(tcg_passres
);
13299 tcg_temp_free_i32(tcg_idx
);
13302 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13307 tcg_res
[1] = tcg_const_i64(0);
13310 for (pass
= 0; pass
< 2; pass
++) {
13311 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13312 tcg_temp_free_i64(tcg_res
[pass
]);
13317 tcg_temp_free_ptr(fpst
);
13322 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13323 * +-----------------+------+-----------+--------+-----+------+------+
13324 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13325 * +-----------------+------+-----------+--------+-----+------+------+
13327 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13329 int size
= extract32(insn
, 22, 2);
13330 int opcode
= extract32(insn
, 12, 5);
13331 int rn
= extract32(insn
, 5, 5);
13332 int rd
= extract32(insn
, 0, 5);
13334 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13335 TCGv_i32 tcg_decrypt
;
13336 CryptoThreeOpIntFn
*genfn
;
13338 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13339 unallocated_encoding(s
);
13344 case 0x4: /* AESE */
13346 genfn
= gen_helper_crypto_aese
;
13348 case 0x6: /* AESMC */
13350 genfn
= gen_helper_crypto_aesmc
;
13352 case 0x5: /* AESD */
13354 genfn
= gen_helper_crypto_aese
;
13356 case 0x7: /* AESIMC */
13358 genfn
= gen_helper_crypto_aesmc
;
13361 unallocated_encoding(s
);
13365 if (!fp_access_check(s
)) {
13369 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13370 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13371 tcg_decrypt
= tcg_const_i32(decrypt
);
13373 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13375 tcg_temp_free_ptr(tcg_rd_ptr
);
13376 tcg_temp_free_ptr(tcg_rn_ptr
);
13377 tcg_temp_free_i32(tcg_decrypt
);
13380 /* Crypto three-reg SHA
13381 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13382 * +-----------------+------+---+------+---+--------+-----+------+------+
13383 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13384 * +-----------------+------+---+------+---+--------+-----+------+------+
13386 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13388 int size
= extract32(insn
, 22, 2);
13389 int opcode
= extract32(insn
, 12, 3);
13390 int rm
= extract32(insn
, 16, 5);
13391 int rn
= extract32(insn
, 5, 5);
13392 int rd
= extract32(insn
, 0, 5);
13393 CryptoThreeOpFn
*genfn
;
13394 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13398 unallocated_encoding(s
);
13403 case 0: /* SHA1C */
13404 case 1: /* SHA1P */
13405 case 2: /* SHA1M */
13406 case 3: /* SHA1SU0 */
13408 feature
= dc_isar_feature(aa64_sha1
, s
);
13410 case 4: /* SHA256H */
13411 genfn
= gen_helper_crypto_sha256h
;
13412 feature
= dc_isar_feature(aa64_sha256
, s
);
13414 case 5: /* SHA256H2 */
13415 genfn
= gen_helper_crypto_sha256h2
;
13416 feature
= dc_isar_feature(aa64_sha256
, s
);
13418 case 6: /* SHA256SU1 */
13419 genfn
= gen_helper_crypto_sha256su1
;
13420 feature
= dc_isar_feature(aa64_sha256
, s
);
13423 unallocated_encoding(s
);
13428 unallocated_encoding(s
);
13432 if (!fp_access_check(s
)) {
13436 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13437 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13438 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13441 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13443 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13445 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13446 tcg_rm_ptr
, tcg_opcode
);
13447 tcg_temp_free_i32(tcg_opcode
);
13450 tcg_temp_free_ptr(tcg_rd_ptr
);
13451 tcg_temp_free_ptr(tcg_rn_ptr
);
13452 tcg_temp_free_ptr(tcg_rm_ptr
);
13455 /* Crypto two-reg SHA
13456 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13457 * +-----------------+------+-----------+--------+-----+------+------+
13458 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13459 * +-----------------+------+-----------+--------+-----+------+------+
13461 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13463 int size
= extract32(insn
, 22, 2);
13464 int opcode
= extract32(insn
, 12, 5);
13465 int rn
= extract32(insn
, 5, 5);
13466 int rd
= extract32(insn
, 0, 5);
13467 CryptoTwoOpFn
*genfn
;
13469 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13472 unallocated_encoding(s
);
13477 case 0: /* SHA1H */
13478 feature
= dc_isar_feature(aa64_sha1
, s
);
13479 genfn
= gen_helper_crypto_sha1h
;
13481 case 1: /* SHA1SU1 */
13482 feature
= dc_isar_feature(aa64_sha1
, s
);
13483 genfn
= gen_helper_crypto_sha1su1
;
13485 case 2: /* SHA256SU0 */
13486 feature
= dc_isar_feature(aa64_sha256
, s
);
13487 genfn
= gen_helper_crypto_sha256su0
;
13490 unallocated_encoding(s
);
13495 unallocated_encoding(s
);
13499 if (!fp_access_check(s
)) {
13503 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13504 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13506 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13508 tcg_temp_free_ptr(tcg_rd_ptr
);
13509 tcg_temp_free_ptr(tcg_rn_ptr
);
13512 /* Crypto three-reg SHA512
13513 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13514 * +-----------------------+------+---+---+-----+--------+------+------+
13515 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13516 * +-----------------------+------+---+---+-----+--------+------+------+
13518 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13520 int opcode
= extract32(insn
, 10, 2);
13521 int o
= extract32(insn
, 14, 1);
13522 int rm
= extract32(insn
, 16, 5);
13523 int rn
= extract32(insn
, 5, 5);
13524 int rd
= extract32(insn
, 0, 5);
13526 CryptoThreeOpFn
*genfn
;
13530 case 0: /* SHA512H */
13531 feature
= dc_isar_feature(aa64_sha512
, s
);
13532 genfn
= gen_helper_crypto_sha512h
;
13534 case 1: /* SHA512H2 */
13535 feature
= dc_isar_feature(aa64_sha512
, s
);
13536 genfn
= gen_helper_crypto_sha512h2
;
13538 case 2: /* SHA512SU1 */
13539 feature
= dc_isar_feature(aa64_sha512
, s
);
13540 genfn
= gen_helper_crypto_sha512su1
;
13543 feature
= dc_isar_feature(aa64_sha3
, s
);
13549 case 0: /* SM3PARTW1 */
13550 feature
= dc_isar_feature(aa64_sm3
, s
);
13551 genfn
= gen_helper_crypto_sm3partw1
;
13553 case 1: /* SM3PARTW2 */
13554 feature
= dc_isar_feature(aa64_sm3
, s
);
13555 genfn
= gen_helper_crypto_sm3partw2
;
13557 case 2: /* SM4EKEY */
13558 feature
= dc_isar_feature(aa64_sm4
, s
);
13559 genfn
= gen_helper_crypto_sm4ekey
;
13562 unallocated_encoding(s
);
13568 unallocated_encoding(s
);
13572 if (!fp_access_check(s
)) {
13577 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13579 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13580 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13581 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13583 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13585 tcg_temp_free_ptr(tcg_rd_ptr
);
13586 tcg_temp_free_ptr(tcg_rn_ptr
);
13587 tcg_temp_free_ptr(tcg_rm_ptr
);
13589 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13592 tcg_op1
= tcg_temp_new_i64();
13593 tcg_op2
= tcg_temp_new_i64();
13594 tcg_res
[0] = tcg_temp_new_i64();
13595 tcg_res
[1] = tcg_temp_new_i64();
13597 for (pass
= 0; pass
< 2; pass
++) {
13598 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13599 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13601 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13602 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13604 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13605 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13607 tcg_temp_free_i64(tcg_op1
);
13608 tcg_temp_free_i64(tcg_op2
);
13609 tcg_temp_free_i64(tcg_res
[0]);
13610 tcg_temp_free_i64(tcg_res
[1]);
13614 /* Crypto two-reg SHA512
13615 * 31 12 11 10 9 5 4 0
13616 * +-----------------------------------------+--------+------+------+
13617 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13618 * +-----------------------------------------+--------+------+------+
13620 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13622 int opcode
= extract32(insn
, 10, 2);
13623 int rn
= extract32(insn
, 5, 5);
13624 int rd
= extract32(insn
, 0, 5);
13625 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13627 CryptoTwoOpFn
*genfn
;
13630 case 0: /* SHA512SU0 */
13631 feature
= dc_isar_feature(aa64_sha512
, s
);
13632 genfn
= gen_helper_crypto_sha512su0
;
13635 feature
= dc_isar_feature(aa64_sm4
, s
);
13636 genfn
= gen_helper_crypto_sm4e
;
13639 unallocated_encoding(s
);
13644 unallocated_encoding(s
);
13648 if (!fp_access_check(s
)) {
13652 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13653 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13655 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13657 tcg_temp_free_ptr(tcg_rd_ptr
);
13658 tcg_temp_free_ptr(tcg_rn_ptr
);
13661 /* Crypto four-register
13662 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13663 * +-------------------+-----+------+---+------+------+------+
13664 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13665 * +-------------------+-----+------+---+------+------+------+
13667 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13669 int op0
= extract32(insn
, 21, 2);
13670 int rm
= extract32(insn
, 16, 5);
13671 int ra
= extract32(insn
, 10, 5);
13672 int rn
= extract32(insn
, 5, 5);
13673 int rd
= extract32(insn
, 0, 5);
13679 feature
= dc_isar_feature(aa64_sha3
, s
);
13681 case 2: /* SM3SS1 */
13682 feature
= dc_isar_feature(aa64_sm3
, s
);
13685 unallocated_encoding(s
);
13690 unallocated_encoding(s
);
13694 if (!fp_access_check(s
)) {
13699 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13702 tcg_op1
= tcg_temp_new_i64();
13703 tcg_op2
= tcg_temp_new_i64();
13704 tcg_op3
= tcg_temp_new_i64();
13705 tcg_res
[0] = tcg_temp_new_i64();
13706 tcg_res
[1] = tcg_temp_new_i64();
13708 for (pass
= 0; pass
< 2; pass
++) {
13709 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13710 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13711 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13715 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13718 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13720 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13722 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13723 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13725 tcg_temp_free_i64(tcg_op1
);
13726 tcg_temp_free_i64(tcg_op2
);
13727 tcg_temp_free_i64(tcg_op3
);
13728 tcg_temp_free_i64(tcg_res
[0]);
13729 tcg_temp_free_i64(tcg_res
[1]);
13731 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13733 tcg_op1
= tcg_temp_new_i32();
13734 tcg_op2
= tcg_temp_new_i32();
13735 tcg_op3
= tcg_temp_new_i32();
13736 tcg_res
= tcg_temp_new_i32();
13737 tcg_zero
= tcg_const_i32(0);
13739 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13740 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13741 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13743 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13744 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13745 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13746 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13748 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13749 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13750 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13751 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13753 tcg_temp_free_i32(tcg_op1
);
13754 tcg_temp_free_i32(tcg_op2
);
13755 tcg_temp_free_i32(tcg_op3
);
13756 tcg_temp_free_i32(tcg_res
);
13757 tcg_temp_free_i32(tcg_zero
);
13762 * 31 21 20 16 15 10 9 5 4 0
13763 * +-----------------------+------+--------+------+------+
13764 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13765 * +-----------------------+------+--------+------+------+
13767 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13769 int rm
= extract32(insn
, 16, 5);
13770 int imm6
= extract32(insn
, 10, 6);
13771 int rn
= extract32(insn
, 5, 5);
13772 int rd
= extract32(insn
, 0, 5);
13773 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13776 if (!dc_isar_feature(aa64_sha3
, s
)) {
13777 unallocated_encoding(s
);
13781 if (!fp_access_check(s
)) {
13785 tcg_op1
= tcg_temp_new_i64();
13786 tcg_op2
= tcg_temp_new_i64();
13787 tcg_res
[0] = tcg_temp_new_i64();
13788 tcg_res
[1] = tcg_temp_new_i64();
13790 for (pass
= 0; pass
< 2; pass
++) {
13791 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13792 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13794 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13795 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13797 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13798 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13800 tcg_temp_free_i64(tcg_op1
);
13801 tcg_temp_free_i64(tcg_op2
);
13802 tcg_temp_free_i64(tcg_res
[0]);
13803 tcg_temp_free_i64(tcg_res
[1]);
13806 /* Crypto three-reg imm2
13807 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13808 * +-----------------------+------+-----+------+--------+------+------+
13809 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13810 * +-----------------------+------+-----+------+--------+------+------+
13812 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13814 int opcode
= extract32(insn
, 10, 2);
13815 int imm2
= extract32(insn
, 12, 2);
13816 int rm
= extract32(insn
, 16, 5);
13817 int rn
= extract32(insn
, 5, 5);
13818 int rd
= extract32(insn
, 0, 5);
13819 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13820 TCGv_i32 tcg_imm2
, tcg_opcode
;
13822 if (!dc_isar_feature(aa64_sm3
, s
)) {
13823 unallocated_encoding(s
);
13827 if (!fp_access_check(s
)) {
13831 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13832 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13833 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13834 tcg_imm2
= tcg_const_i32(imm2
);
13835 tcg_opcode
= tcg_const_i32(opcode
);
13837 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13840 tcg_temp_free_ptr(tcg_rd_ptr
);
13841 tcg_temp_free_ptr(tcg_rn_ptr
);
13842 tcg_temp_free_ptr(tcg_rm_ptr
);
13843 tcg_temp_free_i32(tcg_imm2
);
13844 tcg_temp_free_i32(tcg_opcode
);
13847 /* C3.6 Data processing - SIMD, inc Crypto
13849 * As the decode gets a little complex we are using a table based
13850 * approach for this part of the decode.
13852 static const AArch64DecodeTable data_proc_simd
[] = {
13853 /* pattern , mask , fn */
13854 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13855 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13856 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13857 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13858 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13859 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13860 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13861 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13862 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13863 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13864 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13865 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13866 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13867 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13868 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13869 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13870 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13871 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13872 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13873 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13874 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13875 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13876 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13877 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13878 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13879 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13880 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13881 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13882 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13883 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13884 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13885 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13886 { 0x00000000, 0x00000000, NULL
}
13889 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13891 /* Note that this is called with all non-FP cases from
13892 * table C3-6 so it must UNDEF for entries not specifically
13893 * allocated to instructions in that table.
13895 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13899 unallocated_encoding(s
);
13903 /* C3.6 Data processing - SIMD and floating point */
13904 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13906 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13907 disas_data_proc_fp(s
, insn
);
13909 /* SIMD, including crypto */
13910 disas_data_proc_simd(s
, insn
);
13916 * @env: The cpu environment
13917 * @s: The DisasContext
13919 * Return true if the page is guarded.
13921 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13923 #ifdef CONFIG_USER_ONLY
13924 return false; /* FIXME */
13926 uint64_t addr
= s
->base
.pc_first
;
13927 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13928 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13929 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13932 * We test this immediately after reading an insn, which means
13933 * that any normal page must be in the TLB. The only exception
13934 * would be for executing from flash or device memory, which
13935 * does not retain the TLB entry.
13937 * FIXME: Assume false for those, for now. We could use
13938 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13939 * table entry even for that case.
13941 return (tlb_hit(entry
->addr_code
, addr
) &&
13942 env
->iotlb
[mmu_idx
][index
].attrs
.target_tlb_bit0
);
13947 * btype_destination_ok:
13948 * @insn: The instruction at the branch destination
13949 * @bt: SCTLR_ELx.BT
13950 * @btype: PSTATE.BTYPE, and is non-zero
13952 * On a guarded page, there are a limited number of insns
13953 * that may be present at the branch target:
13954 * - branch target identifiers,
13955 * - paciasp, pacibsp,
13958 * Anything else causes a Branch Target Exception.
13960 * Return true if the branch is compatible, false to raise BTITRAP.
13962 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
13964 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
13966 switch (extract32(insn
, 5, 7)) {
13967 case 0b011001: /* PACIASP */
13968 case 0b011011: /* PACIBSP */
13970 * If SCTLR_ELx.BT, then PACI*SP are not compatible
13971 * with btype == 3. Otherwise all btype are ok.
13973 return !bt
|| btype
!= 3;
13974 case 0b100000: /* BTI */
13975 /* Not compatible with any btype. */
13977 case 0b100010: /* BTI c */
13978 /* Not compatible with btype == 3 */
13980 case 0b100100: /* BTI j */
13981 /* Not compatible with btype == 2 */
13983 case 0b100110: /* BTI jc */
13984 /* Compatible with any btype. */
13988 switch (insn
& 0xffe0001fu
) {
13989 case 0xd4200000u
: /* BRK */
13990 case 0xd4400000u
: /* HLT */
13991 /* Give priority to the breakpoint exception. */
13998 /* C3.1 A64 instruction index by encoding */
13999 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14003 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
14007 s
->fp_access_checked
= false;
14009 if (dc_isar_feature(aa64_bti
, s
)) {
14010 if (s
->base
.num_insns
== 1) {
14012 * At the first insn of the TB, compute s->guarded_page.
14013 * We delayed computing this until successfully reading
14014 * the first insn of the TB, above. This (mostly) ensures
14015 * that the softmmu tlb entry has been populated, and the
14016 * page table GP bit is available.
14018 * Note that we need to compute this even if btype == 0,
14019 * because this value is used for BR instructions later
14020 * where ENV is not available.
14022 s
->guarded_page
= is_guarded_page(env
, s
);
14024 /* First insn can have btype set to non-zero. */
14025 tcg_debug_assert(s
->btype
>= 0);
14028 * Note that the Branch Target Exception has fairly high
14029 * priority -- below debugging exceptions but above most
14030 * everything else. This allows us to handle this now
14031 * instead of waiting until the insn is otherwise decoded.
14035 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14036 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
14037 default_exception_el(s
));
14041 /* Not the first insn: btype must be 0. */
14042 tcg_debug_assert(s
->btype
== 0);
14046 switch (extract32(insn
, 25, 4)) {
14047 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14048 unallocated_encoding(s
);
14051 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14052 unallocated_encoding(s
);
14055 case 0x8: case 0x9: /* Data processing - immediate */
14056 disas_data_proc_imm(s
, insn
);
14058 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14059 disas_b_exc_sys(s
, insn
);
14064 case 0xe: /* Loads and stores */
14065 disas_ldst(s
, insn
);
14068 case 0xd: /* Data processing - register */
14069 disas_data_proc_reg(s
, insn
);
14072 case 0xf: /* Data processing - SIMD and floating point */
14073 disas_data_proc_simd_fp(s
, insn
);
14076 assert(FALSE
); /* all 15 cases should be handled above */
14080 /* if we allocated any temporaries, free them here */
14084 * After execution of most insns, btype is reset to 0.
14085 * Note that we set btype == -1 when the insn sets btype.
14087 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14092 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14095 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14096 CPUARMState
*env
= cpu
->env_ptr
;
14097 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
14098 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14099 int bound
, core_mmu_idx
;
14101 dc
->isar
= &arm_cpu
->isar
;
14102 dc
->pc
= dc
->base
.pc_first
;
14106 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14107 * there is no secure EL1, so we route exceptions to EL3.
14109 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14110 !arm_el_is_aa64(env
, 3);
14113 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14114 dc
->condexec_mask
= 0;
14115 dc
->condexec_cond
= 0;
14116 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14117 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14118 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14119 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14120 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14121 #if !defined(CONFIG_USER_ONLY)
14122 dc
->user
= (dc
->current_el
== 0);
14124 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14125 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14126 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14127 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14128 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14129 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14131 dc
->vec_stride
= 0;
14132 dc
->cp_regs
= arm_cpu
->cp_regs
;
14133 dc
->features
= env
->features
;
14135 /* Single step state. The code-generation logic here is:
14137 * generate code with no special handling for single-stepping (except
14138 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14139 * this happens anyway because those changes are all system register or
14141 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14142 * emit code for one insn
14143 * emit code to clear PSTATE.SS
14144 * emit code to generate software step exception for completed step
14145 * end TB (as usual for having generated an exception)
14146 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14147 * emit code to generate a software step exception
14150 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14151 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14152 dc
->is_ldex
= false;
14153 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14155 /* Bound the number of insns to execute to those left on the page. */
14156 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14158 /* If architectural single step active, limit to 1. */
14159 if (dc
->ss_active
) {
14162 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14164 init_tmp_a64_array(dc
);
14167 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14171 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14173 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14175 tcg_gen_insn_start(dc
->pc
, 0, 0);
14176 dc
->insn_start
= tcg_last_op();
14179 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14180 const CPUBreakpoint
*bp
)
14182 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14184 if (bp
->flags
& BP_CPU
) {
14185 gen_a64_set_pc_im(dc
->pc
);
14186 gen_helper_check_breakpoints(cpu_env
);
14187 /* End the TB early; it likely won't be executed */
14188 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14190 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14191 /* The address covered by the breakpoint must be
14192 included in [tb->pc, tb->pc + tb->size) in order
14193 to for it to be properly cleared -- thus we
14194 increment the PC here so that the logic setting
14195 tb->size below does the right thing. */
14197 dc
->base
.is_jmp
= DISAS_NORETURN
;
14203 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14205 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14206 CPUARMState
*env
= cpu
->env_ptr
;
14208 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14209 /* Singlestep state is Active-pending.
14210 * If we're in this state at the start of a TB then either
14211 * a) we just took an exception to an EL which is being debugged
14212 * and this is the first insn in the exception handler
14213 * b) debug exceptions were masked and we just unmasked them
14214 * without changing EL (eg by clearing PSTATE.D)
14215 * In either case we're going to take a swstep exception in the
14216 * "did not step an insn" case, and so the syndrome ISV and EX
14217 * bits should be zero.
14219 assert(dc
->base
.num_insns
== 1);
14220 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14221 default_exception_el(dc
));
14222 dc
->base
.is_jmp
= DISAS_NORETURN
;
14224 disas_a64_insn(env
, dc
);
14227 dc
->base
.pc_next
= dc
->pc
;
14228 translator_loop_temp_check(&dc
->base
);
14231 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14233 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14235 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14236 /* Note that this means single stepping WFI doesn't halt the CPU.
14237 * For conditional branch insns this is harmless unreachable code as
14238 * gen_goto_tb() has already handled emitting the debug exception
14239 * (and thus a tb-jump is not possible when singlestepping).
14241 switch (dc
->base
.is_jmp
) {
14243 gen_a64_set_pc_im(dc
->pc
);
14247 if (dc
->base
.singlestep_enabled
) {
14248 gen_exception_internal(EXCP_DEBUG
);
14250 gen_step_complete_exception(dc
);
14253 case DISAS_NORETURN
:
14257 switch (dc
->base
.is_jmp
) {
14259 case DISAS_TOO_MANY
:
14260 gen_goto_tb(dc
, 1, dc
->pc
);
14264 gen_a64_set_pc_im(dc
->pc
);
14267 tcg_gen_exit_tb(NULL
, 0);
14270 tcg_gen_lookup_and_goto_ptr();
14272 case DISAS_NORETURN
:
14276 gen_a64_set_pc_im(dc
->pc
);
14277 gen_helper_wfe(cpu_env
);
14280 gen_a64_set_pc_im(dc
->pc
);
14281 gen_helper_yield(cpu_env
);
14285 /* This is a special case because we don't want to just halt the CPU
14286 * if trying to debug across a WFI.
14288 TCGv_i32 tmp
= tcg_const_i32(4);
14290 gen_a64_set_pc_im(dc
->pc
);
14291 gen_helper_wfi(cpu_env
, tmp
);
14292 tcg_temp_free_i32(tmp
);
14293 /* The helper doesn't necessarily throw an exception, but we
14294 * must go back to the main loop to check for interrupts anyway.
14296 tcg_gen_exit_tb(NULL
, 0);
14302 /* Functions above can change dc->pc, so re-align db->pc_next */
14303 dc
->base
.pc_next
= dc
->pc
;
14306 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14309 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14311 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14312 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14315 const TranslatorOps aarch64_translator_ops
= {
14316 .init_disas_context
= aarch64_tr_init_disas_context
,
14317 .tb_start
= aarch64_tr_tb_start
,
14318 .insn_start
= aarch64_tr_insn_start
,
14319 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14320 .translate_insn
= aarch64_tr_translate_insn
,
14321 .tb_stop
= aarch64_tr_tb_stop
,
14322 .disas_log
= aarch64_tr_disas_log
,