2 * S/390 virtual CPU header
4 * For details on the s390x architecture and used definitions (e.g.,
5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
8 * Copyright (c) 2009 Ulrich Hecht
9 * Copyright IBM Corp. 2012, 2018
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
29 #include "cpu_models.h"
30 #include "exec/cpu-defs.h"
31 #include "qemu/cpu-float.h"
32 #include "tcg/tcg_s390x.h"
33 #include "qapi/qapi-types-machine-common.h"
35 #define ELF_MACHINE_UNAME "S390X"
37 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */
38 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
40 #define TARGET_HAS_PRECISE_SMC
42 #define TARGET_INSN_START_EXTRA_WORDS 2
44 #define MMU_USER_IDX 0
46 #define S390_MAX_CPUS 248
49 #define S390_ADAPTER_SUPPRESSIBLE 0x01
51 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
60 uint64_t regs
[16]; /* GP registers */
62 * The floating point registers are part of the vector registers.
63 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
65 uint64_t vregs
[32][2] QEMU_ALIGNED(16); /* vector registers */
66 uint32_t aregs
[16]; /* access registers */
67 uint64_t gscb
[4]; /* guarded storage control */
68 uint64_t etoken
; /* etoken */
69 uint64_t etoken_extension
; /* etoken extension */
71 uint64_t diag318_info
;
73 /* Fields up to this point are not cleared by initial CPU reset */
74 struct {} start_initial_reset_fields
;
76 uint32_t fpc
; /* floating-point control register */
78 bool bpbc
; /* branch prediction blocking */
80 float_status fpu_status
; /* passed to softfloat lib */
84 S390CrashReason crash_reason
;
96 uint32_t int_pgm_code
;
97 uint32_t int_pgm_ilen
;
99 uint32_t int_svc_code
;
100 uint32_t int_svc_ilen
;
102 uint64_t per_address
;
103 uint16_t per_perc_atmid
;
105 uint64_t cregs
[16]; /* control registers */
111 uint64_t pfault_token
;
112 uint64_t pfault_compare
;
113 uint64_t pfault_select
;
118 /* Fields up to this point are not cleared by normal CPU reset */
119 struct {} start_normal_reset_fields
;
120 uint8_t riccb
[64]; /* runtime instrumentation control */
123 uint16_t external_call_addr
;
124 DECLARE_BITMAP(emergency_signals
, S390_MAX_CPUS
);
126 #if !defined(CONFIG_USER_ONLY)
127 uint64_t tlb_fill_tec
; /* translation exception code during tlb_fill */
128 int tlb_fill_exc
; /* exception number seen during tlb_fill */
131 /* Fields up to this point are cleared by a CPU reset */
132 struct {} end_reset_fields
;
134 #if !defined(CONFIG_USER_ONLY)
135 uint32_t core_id
; /* PoP "CPU address", same as cpu_index */
140 CpuS390Entitlement entitlement
; /* Used only for vertical polarization */
144 QEMUTimer
*tod_timer
;
146 QEMUTimer
*cpu_timer
;
149 * The cpu state represents the logical state of a cpu. In contrast to other
150 * architectures, there is a difference between a halt and a stop on s390.
151 * If all cpus are either stopped (including check stop) or in the disabled
152 * wait state, the vm can be shut down.
153 * The acceptable cpu_state values are defined in the CpuInfoS390State
158 /* currently processed sigp order */
163 static inline uint64_t *get_freg(CPUS390XState
*cs
, int nr
)
165 return &cs
->vregs
[nr
][0];
170 * @env: #CPUS390XState.
181 /* needed for live migration */
183 uint32_t irqstate_saved_size
;
187 #ifndef CONFIG_USER_ONLY
188 extern const VMStateDescription vmstate_s390_cpu
;
191 /* distinguish between 24 bit and 31 bit addressing */
192 #define HIGH_ORDER_BIT 0x80000000
194 /* Interrupt Codes */
195 /* Program Interrupts */
196 #define PGM_OPERATION 0x0001
197 #define PGM_PRIVILEGED 0x0002
198 #define PGM_EXECUTE 0x0003
199 #define PGM_PROTECTION 0x0004
200 #define PGM_ADDRESSING 0x0005
201 #define PGM_SPECIFICATION 0x0006
202 #define PGM_DATA 0x0007
203 #define PGM_FIXPT_OVERFLOW 0x0008
204 #define PGM_FIXPT_DIVIDE 0x0009
205 #define PGM_DEC_OVERFLOW 0x000a
206 #define PGM_DEC_DIVIDE 0x000b
207 #define PGM_HFP_EXP_OVERFLOW 0x000c
208 #define PGM_HFP_EXP_UNDERFLOW 0x000d
209 #define PGM_HFP_SIGNIFICANCE 0x000e
210 #define PGM_HFP_DIVIDE 0x000f
211 #define PGM_SEGMENT_TRANS 0x0010
212 #define PGM_PAGE_TRANS 0x0011
213 #define PGM_TRANS_SPEC 0x0012
214 #define PGM_SPECIAL_OP 0x0013
215 #define PGM_OPERAND 0x0015
216 #define PGM_TRACE_TABLE 0x0016
217 #define PGM_VECTOR_PROCESSING 0x001b
218 #define PGM_SPACE_SWITCH 0x001c
219 #define PGM_HFP_SQRT 0x001d
220 #define PGM_PC_TRANS_SPEC 0x001f
221 #define PGM_AFX_TRANS 0x0020
222 #define PGM_ASX_TRANS 0x0021
223 #define PGM_LX_TRANS 0x0022
224 #define PGM_EX_TRANS 0x0023
225 #define PGM_PRIM_AUTH 0x0024
226 #define PGM_SEC_AUTH 0x0025
227 #define PGM_ALET_SPEC 0x0028
228 #define PGM_ALEN_SPEC 0x0029
229 #define PGM_ALE_SEQ 0x002a
230 #define PGM_ASTE_VALID 0x002b
231 #define PGM_ASTE_SEQ 0x002c
232 #define PGM_EXT_AUTH 0x002d
233 #define PGM_STACK_FULL 0x0030
234 #define PGM_STACK_EMPTY 0x0031
235 #define PGM_STACK_SPEC 0x0032
236 #define PGM_STACK_TYPE 0x0033
237 #define PGM_STACK_OP 0x0034
238 #define PGM_ASCE_TYPE 0x0038
239 #define PGM_REG_FIRST_TRANS 0x0039
240 #define PGM_REG_SEC_TRANS 0x003a
241 #define PGM_REG_THIRD_TRANS 0x003b
242 #define PGM_MONITOR 0x0040
243 #define PGM_PER 0x0080
244 #define PGM_CRYPTO 0x0119
246 /* External Interrupts */
247 #define EXT_INTERRUPT_KEY 0x0040
248 #define EXT_CLOCK_COMP 0x1004
249 #define EXT_CPU_TIMER 0x1005
250 #define EXT_MALFUNCTION 0x1200
251 #define EXT_EMERGENCY 0x1201
252 #define EXT_EXTERNAL_CALL 0x1202
253 #define EXT_ETR 0x1406
254 #define EXT_SERVICE 0x2401
255 #define EXT_VIRTIO 0x2603
259 #undef PSW_MASK_UNUSED_2
260 #undef PSW_MASK_UNUSED_3
266 #undef PSW_MASK_MCHECK
268 #undef PSW_MASK_PSTATE
274 #undef PSW_SHIFT_MASK_PM
277 #undef PSW_MASK_ESA_ADDR
279 #define PSW_MASK_PER 0x4000000000000000ULL
280 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
281 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL
282 #define PSW_MASK_DAT 0x0400000000000000ULL
283 #define PSW_MASK_IO 0x0200000000000000ULL
284 #define PSW_MASK_EXT 0x0100000000000000ULL
285 #define PSW_MASK_KEY 0x00F0000000000000ULL
286 #define PSW_SHIFT_KEY 52
287 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
288 #define PSW_MASK_MCHECK 0x0004000000000000ULL
289 #define PSW_MASK_WAIT 0x0002000000000000ULL
290 #define PSW_MASK_PSTATE 0x0001000000000000ULL
291 #define PSW_MASK_ASC 0x0000C00000000000ULL
292 #define PSW_SHIFT_ASC 46
293 #define PSW_MASK_CC 0x0000300000000000ULL
294 #define PSW_MASK_PM 0x00000F0000000000ULL
295 #define PSW_SHIFT_MASK_PM 40
296 #define PSW_MASK_RI 0x0000008000000000ULL
297 #define PSW_MASK_64 0x0000000100000000ULL
298 #define PSW_MASK_32 0x0000000080000000ULL
299 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
300 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
301 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL
303 #undef PSW_ASC_PRIMARY
304 #undef PSW_ASC_ACCREG
305 #undef PSW_ASC_SECONDARY
308 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
309 #define PSW_ASC_ACCREG 0x0000400000000000ULL
310 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
311 #define PSW_ASC_HOME 0x0000C00000000000ULL
313 /* the address space values shifted */
316 #define AS_SECONDARY 2
321 #define FLAG_MASK_PSW_SHIFT 31
322 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
323 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
324 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
325 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
326 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
327 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
328 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
329 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
331 /* we'll use some unused PSW positions to store CR flags in tb flags */
332 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
333 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
335 /* Control register 0 bits */
336 #define CR0_LOWPROT 0x0000000010000000ULL
337 #define CR0_SECONDARY 0x0000000004000000ULL
338 #define CR0_EDAT 0x0000000000800000ULL
339 #define CR0_AFP 0x0000000000040000ULL
340 #define CR0_VECTOR 0x0000000000020000ULL
341 #define CR0_IEP 0x0000000000100000ULL
342 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
343 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
344 #define CR0_CKC_SC 0x0000000000000800ULL
345 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
346 #define CR0_SERVICE_SC 0x0000000000000200ULL
348 /* Control register 14 bits */
349 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
352 #define MMU_PRIMARY_IDX 0
353 #define MMU_SECONDARY_IDX 1
354 #define MMU_HOME_IDX 2
355 #define MMU_REAL_IDX 3
357 static inline int cpu_mmu_index(CPUS390XState
*env
, bool ifetch
)
359 #ifdef CONFIG_USER_ONLY
362 if (!(env
->psw
.mask
& PSW_MASK_DAT
)) {
367 if ((env
->psw
.mask
& PSW_MASK_ASC
) == PSW_ASC_HOME
) {
370 return MMU_PRIMARY_IDX
;
373 switch (env
->psw
.mask
& PSW_MASK_ASC
) {
374 case PSW_ASC_PRIMARY
:
375 return MMU_PRIMARY_IDX
;
376 case PSW_ASC_SECONDARY
:
377 return MMU_SECONDARY_IDX
;
381 /* Fallthrough: access register mode is not yet supported */
388 static inline void cpu_get_tb_cpu_state(CPUS390XState
*env
, vaddr
*pc
,
389 uint64_t *cs_base
, uint32_t *flags
)
391 if (env
->psw
.addr
& 1) {
393 * Instructions must be at even addresses.
394 * This needs to be checked before address translation.
396 env
->int_pgm_ilen
= 2; /* see s390_cpu_tlb_fill() */
397 tcg_s390_program_interrupt(env
, PGM_SPECIFICATION
, 0);
400 *cs_base
= env
->ex_value
;
401 *flags
= (env
->psw
.mask
>> FLAG_MASK_PSW_SHIFT
) & FLAG_MASK_PSW
;
402 if (env
->cregs
[0] & CR0_AFP
) {
403 *flags
|= FLAG_MASK_AFP
;
405 if (env
->cregs
[0] & CR0_VECTOR
) {
406 *flags
|= FLAG_MASK_VECTOR
;
410 /* PER bits from control register 9 */
411 #define PER_CR9_EVENT_BRANCH 0x80000000
412 #define PER_CR9_EVENT_IFETCH 0x40000000
413 #define PER_CR9_EVENT_STORE 0x20000000
414 #define PER_CR9_EVENT_STORE_REAL 0x08000000
415 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
416 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
417 #define PER_CR9_CONTROL_ALTERATION 0x00200000
419 /* PER bits from the PER CODE/ATMID/AI in lowcore */
420 #define PER_CODE_EVENT_BRANCH 0x8000
421 #define PER_CODE_EVENT_IFETCH 0x4000
422 #define PER_CODE_EVENT_STORE 0x2000
423 #define PER_CODE_EVENT_STORE_REAL 0x0800
424 #define PER_CODE_EVENT_NULLIFICATION 0x0100
426 #define EXCP_EXT 1 /* external interrupt */
427 #define EXCP_SVC 2 /* supervisor call (syscall) */
428 #define EXCP_PGM 3 /* program interruption */
429 #define EXCP_RESTART 4 /* restart interrupt */
430 #define EXCP_STOP 5 /* stop interrupt */
431 #define EXCP_IO 7 /* I/O interrupt */
432 #define EXCP_MCHK 8 /* machine check */
434 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
435 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
436 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
437 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
438 #define INTERRUPT_RESTART (1 << 7)
439 #define INTERRUPT_STOP (1 << 8)
441 /* Program Status Word. */
442 #define S390_PSWM_REGNUM 0
443 #define S390_PSWA_REGNUM 1
444 /* General Purpose Registers. */
445 #define S390_R0_REGNUM 2
446 #define S390_R1_REGNUM 3
447 #define S390_R2_REGNUM 4
448 #define S390_R3_REGNUM 5
449 #define S390_R4_REGNUM 6
450 #define S390_R5_REGNUM 7
451 #define S390_R6_REGNUM 8
452 #define S390_R7_REGNUM 9
453 #define S390_R8_REGNUM 10
454 #define S390_R9_REGNUM 11
455 #define S390_R10_REGNUM 12
456 #define S390_R11_REGNUM 13
457 #define S390_R12_REGNUM 14
458 #define S390_R13_REGNUM 15
459 #define S390_R14_REGNUM 16
460 #define S390_R15_REGNUM 17
461 /* Total Core Registers. */
462 #define S390_NUM_CORE_REGS 18
464 static inline void setcc(S390CPU
*cpu
, uint64_t cc
)
466 CPUS390XState
*env
= &cpu
->env
;
468 env
->psw
.mask
&= ~(3ull << 44);
469 env
->psw
.mask
|= (cc
& 3) << 44;
474 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
475 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
476 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
477 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
478 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
479 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
480 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
481 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
482 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
484 /* Basic Machine Configuration */
485 typedef struct SysIB_111
{
491 uint8_t sequence
[16];
495 QEMU_BUILD_BUG_ON(sizeof(SysIB_111
) != 4096);
497 /* Basic Machine CPU */
498 typedef struct SysIB_121
{
500 uint8_t sequence
[16];
506 QEMU_BUILD_BUG_ON(sizeof(SysIB_121
) != 4096);
508 /* Basic Machine CPUs */
509 typedef struct SysIB_122
{
514 uint16_t standby_cpus
;
515 uint16_t reserved_cpus
;
516 uint16_t adjustments
[2026];
518 QEMU_BUILD_BUG_ON(sizeof(SysIB_122
) != 4096);
521 typedef struct SysIB_221
{
523 uint8_t sequence
[16];
529 QEMU_BUILD_BUG_ON(sizeof(SysIB_221
) != 4096);
532 typedef struct SysIB_222
{
539 uint16_t standby_cpus
;
540 uint16_t reserved_cpus
;
544 uint16_t dedicated_cpus
;
545 uint16_t shared_cpus
;
548 QEMU_BUILD_BUG_ON(sizeof(SysIB_222
) != 4096);
551 typedef struct SysIB_322
{
558 uint16_t standby_cpus
;
559 uint16_t reserved_cpus
;
564 uint8_t ext_name_encoding
;
569 uint8_t ext_names
[8][256];
571 QEMU_BUILD_BUG_ON(sizeof(SysIB_322
) != 4096);
574 * Topology Magnitude fields (MAG) indicates the maximum number of
575 * topology list entries (TLE) at the corresponding nesting level.
577 #define S390_TOPOLOGY_MAG 6
578 #define S390_TOPOLOGY_MAG6 0
579 #define S390_TOPOLOGY_MAG5 1
580 #define S390_TOPOLOGY_MAG4 2
581 #define S390_TOPOLOGY_MAG3 3
582 #define S390_TOPOLOGY_MAG2 4
583 #define S390_TOPOLOGY_MAG1 5
584 /* Configuration topology */
585 typedef struct SysIB_151x
{
586 uint8_t reserved0
[2];
588 uint8_t mag
[S390_TOPOLOGY_MAG
];
594 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x
) != 16);
596 typedef union SysIB
{
603 SysIB_151x sysib_151x
;
605 QEMU_BUILD_BUG_ON(sizeof(SysIB
) != 4096);
608 * CPU Topology List provided by STSI with fc=15 provides a list
609 * of two different Topology List Entries (TLE) types to specify
610 * the topology hierarchy.
612 * - Container Topology List Entry
613 * Defines a container to contain other Topology List Entries
614 * of any type, nested containers or CPU.
615 * - CPU Topology List Entry
616 * Specifies the CPUs position, type, entitlement and polarization
617 * of the CPUs contained in the last container TLE.
619 * There can be theoretically up to five levels of containers, QEMU
620 * uses only three levels, the drawer's, book's and socket's level.
622 * A container with a nesting level (NL) greater than 1 can only
623 * contain another container of nesting level NL-1.
625 * A container of nesting level 1 (socket), contains as many CPU TLE
626 * as needed to describe the position and qualities of all CPUs inside
628 * The qualities of a CPU are polarization, entitlement and type.
630 * The CPU TLE defines the position of the CPUs of identical qualities
631 * using a 64bits mask which first bit has its offset defined by
632 * the CPU address origin field of the CPU TLE like in:
633 * CPU address = origin * 64 + bit position within the mask
635 /* Container type Topology List Entry */
636 typedef struct SYSIBContainerListEntry
{
640 } SYSIBContainerListEntry
;
641 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry
) != 8);
643 /* CPU type Topology List Entry */
644 typedef struct SysIBCPUListEntry
{
646 uint8_t reserved0
[3];
647 #define SYSIB_TLE_POLARITY_MASK 0x03
648 #define SYSIB_TLE_DEDICATED 0x04
654 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry
) != 16);
656 void insert_stsi_15_1_x(S390CPU
*cpu
, int sel2
, uint64_t addr
, uint8_t ar
, uintptr_t ra
);
657 void s390_cpu_topology_set_changed(bool changed
);
660 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
661 #define ASCE_SUBSPACE 0x200 /* subspace group control */
662 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
663 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
664 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
665 #define ASCE_REAL_SPACE 0x20 /* real space control */
666 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
667 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
668 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
669 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
670 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
671 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
673 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
674 #define REGION_ENTRY_P 0x0000000000000200ULL
675 #define REGION_ENTRY_TF 0x00000000000000c0ULL
676 #define REGION_ENTRY_I 0x0000000000000020ULL
677 #define REGION_ENTRY_TT 0x000000000000000cULL
678 #define REGION_ENTRY_TL 0x0000000000000003ULL
680 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
681 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
682 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
684 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
685 #define REGION3_ENTRY_AV 0x0000000000010000ULL
686 #define REGION3_ENTRY_ACC 0x000000000000f000ULL
687 #define REGION3_ENTRY_F 0x0000000000000800ULL
688 #define REGION3_ENTRY_FC 0x0000000000000400ULL
689 #define REGION3_ENTRY_IEP 0x0000000000000100ULL
690 #define REGION3_ENTRY_CR 0x0000000000000010ULL
692 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
693 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
694 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL
695 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
696 #define SEGMENT_ENTRY_F 0x0000000000000800ULL
697 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL
698 #define SEGMENT_ENTRY_P 0x0000000000000200ULL
699 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
700 #define SEGMENT_ENTRY_I 0x0000000000000020ULL
701 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL
702 #define SEGMENT_ENTRY_TT 0x000000000000000cULL
704 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
706 #define PAGE_ENTRY_0 0x0000000000000800ULL
707 #define PAGE_ENTRY_I 0x0000000000000400ULL
708 #define PAGE_ENTRY_P 0x0000000000000200ULL
709 #define PAGE_ENTRY_IEP 0x0000000000000100ULL
711 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
712 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
713 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
714 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
715 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
717 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
718 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
719 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
720 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
721 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
723 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
724 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
725 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
726 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
728 #define SK_C (0x1 << 1)
729 #define SK_R (0x1 << 2)
730 #define SK_F (0x1 << 3)
731 #define SK_ACC_MASK (0xf << 4)
733 /* SIGP order codes */
734 #define SIGP_SENSE 0x01
735 #define SIGP_EXTERNAL_CALL 0x02
736 #define SIGP_EMERGENCY 0x03
737 #define SIGP_START 0x04
738 #define SIGP_STOP 0x05
739 #define SIGP_RESTART 0x06
740 #define SIGP_STOP_STORE_STATUS 0x09
741 #define SIGP_INITIAL_CPU_RESET 0x0b
742 #define SIGP_CPU_RESET 0x0c
743 #define SIGP_SET_PREFIX 0x0d
744 #define SIGP_STORE_STATUS_ADDR 0x0e
745 #define SIGP_SET_ARCH 0x12
746 #define SIGP_COND_EMERGENCY 0x13
747 #define SIGP_SENSE_RUNNING 0x15
748 #define SIGP_STORE_ADTL_STATUS 0x17
750 /* SIGP condition codes */
751 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
752 #define SIGP_CC_STATUS_STORED 1
753 #define SIGP_CC_BUSY 2
754 #define SIGP_CC_NOT_OPERATIONAL 3
756 /* SIGP status bits */
757 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
758 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
759 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
760 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
761 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
762 #define SIGP_STAT_STOPPED 0x00000040UL
763 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
764 #define SIGP_STAT_CHECK_STOP 0x00000010UL
765 #define SIGP_STAT_INOPERATIVE 0x00000004UL
766 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
767 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
769 /* SIGP order code mask corresponding to bit positions 56-63 */
770 #define SIGP_ORDER_MASK 0x000000ff
772 /* machine check interruption code */
775 #define MCIC_SC_SD 0x8000000000000000ULL
776 #define MCIC_SC_PD 0x4000000000000000ULL
777 #define MCIC_SC_SR 0x2000000000000000ULL
778 #define MCIC_SC_CD 0x0800000000000000ULL
779 #define MCIC_SC_ED 0x0400000000000000ULL
780 #define MCIC_SC_DG 0x0100000000000000ULL
781 #define MCIC_SC_W 0x0080000000000000ULL
782 #define MCIC_SC_CP 0x0040000000000000ULL
783 #define MCIC_SC_SP 0x0020000000000000ULL
784 #define MCIC_SC_CK 0x0010000000000000ULL
786 /* subclass modifiers */
787 #define MCIC_SCM_B 0x0002000000000000ULL
788 #define MCIC_SCM_DA 0x0000000020000000ULL
789 #define MCIC_SCM_AP 0x0000000000080000ULL
792 #define MCIC_SE_SE 0x0000800000000000ULL
793 #define MCIC_SE_SC 0x0000400000000000ULL
794 #define MCIC_SE_KE 0x0000200000000000ULL
795 #define MCIC_SE_DS 0x0000100000000000ULL
796 #define MCIC_SE_IE 0x0000000080000000ULL
799 #define MCIC_VB_WP 0x0000080000000000ULL
800 #define MCIC_VB_MS 0x0000040000000000ULL
801 #define MCIC_VB_PM 0x0000020000000000ULL
802 #define MCIC_VB_IA 0x0000010000000000ULL
803 #define MCIC_VB_FA 0x0000008000000000ULL
804 #define MCIC_VB_VR 0x0000004000000000ULL
805 #define MCIC_VB_EC 0x0000002000000000ULL
806 #define MCIC_VB_FP 0x0000001000000000ULL
807 #define MCIC_VB_GR 0x0000000800000000ULL
808 #define MCIC_VB_CR 0x0000000400000000ULL
809 #define MCIC_VB_ST 0x0000000100000000ULL
810 #define MCIC_VB_AR 0x0000000040000000ULL
811 #define MCIC_VB_GS 0x0000000008000000ULL
812 #define MCIC_VB_PR 0x0000000000200000ULL
813 #define MCIC_VB_FC 0x0000000000100000ULL
814 #define MCIC_VB_CT 0x0000000000020000ULL
815 #define MCIC_VB_CC 0x0000000000010000ULL
817 static inline uint64_t s390_build_validity_mcic(void)
822 * Indicate all validity bits (no damage) only. Other bits have to be
823 * added by the caller. (storage errors, subclasses and subclass modifiers)
825 mcic
= MCIC_VB_WP
| MCIC_VB_MS
| MCIC_VB_PM
| MCIC_VB_IA
| MCIC_VB_FP
|
826 MCIC_VB_GR
| MCIC_VB_CR
| MCIC_VB_ST
| MCIC_VB_AR
| MCIC_VB_PR
|
827 MCIC_VB_FC
| MCIC_VB_CT
| MCIC_VB_CC
;
828 if (s390_has_feat(S390_FEAT_VECTOR
)) {
831 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE
)) {
837 static inline void s390_do_cpu_full_reset(CPUState
*cs
, run_on_cpu_data arg
)
842 static inline void s390_do_cpu_reset(CPUState
*cs
, run_on_cpu_data arg
)
844 S390CPUClass
*scc
= S390_CPU_GET_CLASS(cs
);
846 scc
->reset(cs
, S390_CPU_RESET_NORMAL
);
849 static inline void s390_do_cpu_initial_reset(CPUState
*cs
, run_on_cpu_data arg
)
851 S390CPUClass
*scc
= S390_CPU_GET_CLASS(cs
);
853 scc
->reset(cs
, S390_CPU_RESET_INITIAL
);
856 static inline void s390_do_cpu_load_normal(CPUState
*cs
, run_on_cpu_data arg
)
858 S390CPUClass
*scc
= S390_CPU_GET_CLASS(cs
);
860 scc
->load_normal(cs
);
865 void s390_crypto_reset(void);
866 int s390_set_memory_limit(uint64_t new_limit
, uint64_t *hw_limit
);
867 void s390_set_max_pagesize(uint64_t pagesize
, Error
**errp
);
868 void s390_cmma_reset(void);
869 void s390_enable_css_support(S390CPU
*cpu
);
870 void s390_do_cpu_set_diag318(CPUState
*cs
, run_on_cpu_data arg
);
871 int s390_assign_subch_ioeventfd(EventNotifier
*notifier
, uint32_t sch_id
,
872 int vq
, bool assign
);
873 #ifndef CONFIG_USER_ONLY
874 unsigned int s390_cpu_set_state(uint8_t cpu_state
, S390CPU
*cpu
);
876 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state
, S390CPU
*cpu
)
880 #endif /* CONFIG_USER_ONLY */
881 static inline uint8_t s390_cpu_get_state(S390CPU
*cpu
)
883 return cpu
->env
.cpu_state
;
888 void s390_cpu_list(void);
889 #define cpu_list s390_cpu_list
890 void s390_set_qemu_cpu_model(uint16_t type
, uint8_t gen
, uint8_t ec_ga
,
891 const S390FeatInit feat_init
);
895 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
896 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
897 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
901 void s390_program_interrupt(CPUS390XState
*env
, uint32_t code
, uintptr_t ra
);
902 /* service interrupts are floating therefore we must not pass an cpustate */
903 void s390_sclp_extint(uint32_t parm
);
906 int s390_cpu_virt_mem_rw(S390CPU
*cpu
, vaddr laddr
, uint8_t ar
, void *hostbuf
,
907 int len
, bool is_write
);
908 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
909 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
910 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
911 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
912 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
913 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
914 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
915 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
916 void s390_cpu_virt_mem_handle_exc(S390CPU
*cpu
, uintptr_t ra
);
917 int s390_cpu_pv_mem_rw(S390CPU
*cpu
, unsigned int offset
, void *hostbuf
,
918 int len
, bool is_write
);
919 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \
920 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
921 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \
922 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
925 int s390_cpu_restart(S390CPU
*cpu
);
926 void s390_init_sigp(void);
929 void s390_cpu_set_psw(CPUS390XState
*env
, uint64_t mask
, uint64_t addr
);
930 uint64_t s390_cpu_get_psw_mask(CPUS390XState
*env
);
932 /* outside of target/s390x/ */
933 S390CPU
*s390_cpu_addr2state(uint16_t cpu_addr
);
935 #include "exec/cpu-all.h"