hw/display/vga-isa-mm.c

   1 /*
   2  * QEMU ISA MM VGA Emulator.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "ui/console.h"
  26 #include "hw/i386/pc.h"
  27 #include "vga_int.h"
  28 #include "ui/pixel_ops.h"
  29 #include "qemu/timer.h"
  30
  31 #define VGA_RAM_SIZE (8192 * 1024)
  32
  33 typedef struct ISAVGAMMState {
  34     VGACommonState vga;
  35     int it_shift;
  36 } ISAVGAMMState;
  37
  38 /* Memory mapped interface */
  39 static uint32_t vga_mm_readb (void *opaque, hwaddr addr)
  40 {
  41     ISAVGAMMState *s = opaque;
  42
  43     return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
  44 }
  45
  46 static void vga_mm_writeb (void *opaque,
  47                            hwaddr addr, uint32_t value)
  48 {
  49     ISAVGAMMState *s = opaque;
  50
  51     vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
  52 }
  53
  54 static uint32_t vga_mm_readw (void *opaque, hwaddr addr)
  55 {
  56     ISAVGAMMState *s = opaque;
  57
  58     return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
  59 }
  60
  61 static void vga_mm_writew (void *opaque,
  62                            hwaddr addr, uint32_t value)
  63 {
  64     ISAVGAMMState *s = opaque;
  65
  66     vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
  67 }
  68
  69 static uint32_t vga_mm_readl (void *opaque, hwaddr addr)
  70 {
  71     ISAVGAMMState *s = opaque;
  72
  73     return vga_ioport_read(&s->vga, addr >> s->it_shift);
  74 }
  75
  76 static void vga_mm_writel (void *opaque,
  77                            hwaddr addr, uint32_t value)
  78 {
  79     ISAVGAMMState *s = opaque;
  80
  81     vga_ioport_write(&s->vga, addr >> s->it_shift, value);
  82 }
  83
  84 static const MemoryRegionOps vga_mm_ctrl_ops = {
  85     .old_mmio = {
  86         .read = {
  87             vga_mm_readb,
  88             vga_mm_readw,
  89             vga_mm_readl,
  90         },
  91         .write = {
  92             vga_mm_writeb,
  93             vga_mm_writew,
  94             vga_mm_writel,
  95         },
  96     },
  97     .endianness = DEVICE_NATIVE_ENDIAN,
  98 };
  99
 100 static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base,
 101                         hwaddr ctrl_base, int it_shift,
 102                         MemoryRegion *address_space)
 103 {
 104     MemoryRegion *s_ioport_ctrl, *vga_io_memory;
 105
 106     s->it_shift = it_shift;
 107     s_ioport_ctrl = g_malloc(sizeof(*s_ioport_ctrl));
 108     memory_region_init_io(s_ioport_ctrl, NULL, &vga_mm_ctrl_ops, s,
 109                           "vga-mm-ctrl", 0x100000);
 110     memory_region_set_flush_coalesced(s_ioport_ctrl);
 111
 112     vga_io_memory = g_malloc(sizeof(*vga_io_memory));
 113     /* XXX: endianness? */
 114     memory_region_init_io(vga_io_memory, NULL, &vga_mem_ops, &s->vga,
 115                           "vga-mem", 0x20000);
 116
 117     vmstate_register(NULL, 0, &vmstate_vga_common, s);
 118
 119     memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl);
 120     s->vga.bank_offset = 0;
 121     memory_region_add_subregion(address_space,
 122                                 vram_base + 0x000a0000, vga_io_memory);
 123     memory_region_set_coalescing(vga_io_memory);
 124 }
 125
 126 int isa_vga_mm_init(hwaddr vram_base,
 127                     hwaddr ctrl_base, int it_shift,
 128                     MemoryRegion *address_space)
 129 {
 130     ISAVGAMMState *s;
 131
 132     s = g_malloc0(sizeof(*s));
 133
 134     s->vga.vram_size_mb = VGA_RAM_SIZE >> 20;
 135     vga_common_init(&s->vga, NULL, true);
 136     vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
 137
 138     s->vga.con = graphic_console_init(NULL, 0, s->vga.hw_ops, s);
 139
 140     vga_init_vbe(&s->vga, NULL, address_space);
 141     return 0;
 142 }