?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
qxl: handle no updates in interface_update_area_complete
[qemu/ar7.git] / hw / i386 / acpi-build.c
blobfbba461a8720e64a9c88afee5befc1ecbf4bba2e
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
48
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/intel_iommu.h"
56 #include "hw/timer/hpet.h"
57
58 #include "hw/acpi/aml-build.h"
59
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62
63 #include "hw/acpi/ipmi.h"
64
65 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
66 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
67 * a little bit, there should be plenty of free space since the DSDT
68 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
69 */
70 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
71 #define ACPI_BUILD_ALIGN_SIZE 0x1000
72
73 #define ACPI_BUILD_TABLE_SIZE 0x20000
74
75 /* #define DEBUG_ACPI_BUILD */
76 #ifdef DEBUG_ACPI_BUILD
77 #define ACPI_BUILD_DPRINTF(fmt, ...) \
78 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
79 #else
80 #define ACPI_BUILD_DPRINTF(fmt, ...)
81 #endif
82
83 typedef struct AcpiMcfgInfo {
84 uint64_t mcfg_base;
85 uint32_t mcfg_size;
86 } AcpiMcfgInfo;
87
88 typedef struct AcpiPmInfo {
89 bool s3_disabled;
90 bool s4_disabled;
91 bool pcihp_bridge_en;
92 uint8_t s4_val;
93 uint16_t sci_int;
94 uint8_t acpi_enable_cmd;
95 uint8_t acpi_disable_cmd;
96 uint32_t gpe0_blk;
97 uint32_t gpe0_blk_len;
98 uint32_t io_base;
99 uint16_t cpu_hp_io_base;
100 uint16_t mem_hp_io_base;
101 uint16_t mem_hp_io_len;
102 uint16_t pcihp_io_base;
103 uint16_t pcihp_io_len;
104 } AcpiPmInfo;
105
106 typedef struct AcpiMiscInfo {
107 bool is_piix4;
108 bool has_hpet;
109 TPMVersion tpm_version;
110 const unsigned char *dsdt_code;
111 unsigned dsdt_size;
112 uint16_t pvpanic_port;
113 uint16_t applesmc_io_base;
114 } AcpiMiscInfo;
115
116 typedef struct AcpiBuildPciBusHotplugState {
117 GArray *device_table;
118 GArray *notify_table;
119 struct AcpiBuildPciBusHotplugState *parent;
120 bool pcihp_bridge_en;
121 } AcpiBuildPciBusHotplugState;
122
123 static void acpi_get_pm_info(AcpiPmInfo *pm)
124 {
125 Object *piix = piix4_pm_find();
126 Object *lpc = ich9_lpc_find();
127 Object *obj = NULL;
128 QObject *o;
129
130 pm->cpu_hp_io_base = 0;
131 pm->pcihp_io_base = 0;
132 pm->pcihp_io_len = 0;
133 if (piix) {
134 obj = piix;
135 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
136 pm->pcihp_io_base =
137 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
138 pm->pcihp_io_len =
139 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
140 }
141 if (lpc) {
142 obj = lpc;
143 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
144 }
145 assert(obj);
146
147 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
148 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
149
150 /* Fill in optional s3/s4 related properties */
151 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
152 if (o) {
153 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
154 } else {
155 pm->s3_disabled = false;
156 }
157 qobject_decref(o);
158 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
159 if (o) {
160 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
161 } else {
162 pm->s4_disabled = false;
163 }
164 qobject_decref(o);
165 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
166 if (o) {
167 pm->s4_val = qint_get_int(qobject_to_qint(o));
168 } else {
169 pm->s4_val = false;
170 }
171 qobject_decref(o);
172
173 /* Fill in mandatory properties */
174 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
175
176 pm->acpi_enable_cmd = object_property_get_int(obj,
177 ACPI_PM_PROP_ACPI_ENABLE_CMD,
178 NULL);
179 pm->acpi_disable_cmd = object_property_get_int(obj,
180 ACPI_PM_PROP_ACPI_DISABLE_CMD,
181 NULL);
182 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
183 NULL);
184 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
185 NULL);
186 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
187 NULL);
188 pm->pcihp_bridge_en =
189 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
190 NULL);
191 }
192
193 static void acpi_get_misc_info(AcpiMiscInfo *info)
194 {
195 Object *piix = piix4_pm_find();
196 Object *lpc = ich9_lpc_find();
197 assert(!!piix != !!lpc);
198
199 if (piix) {
200 info->is_piix4 = true;
201 }
202 if (lpc) {
203 info->is_piix4 = false;
204 }
205
206 info->has_hpet = hpet_find();
207 info->tpm_version = tpm_get_version();
208 info->pvpanic_port = pvpanic_port();
209 info->applesmc_io_base = applesmc_port();
210 }
211
212 /*
213 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
214 * On i386 arch we only have two pci hosts, so we can look only for them.
215 */
216 static Object *acpi_get_i386_pci_host(void)
217 {
218 PCIHostState *host;
219
220 host = OBJECT_CHECK(PCIHostState,
221 object_resolve_path("/machine/i440fx", NULL),
222 TYPE_PCI_HOST_BRIDGE);
223 if (!host) {
224 host = OBJECT_CHECK(PCIHostState,
225 object_resolve_path("/machine/q35", NULL),
226 TYPE_PCI_HOST_BRIDGE);
227 }
228
229 return OBJECT(host);
230 }
231
232 static void acpi_get_pci_holes(Range *hole, Range *hole64)
233 {
234 Object *pci_host;
235
236 pci_host = acpi_get_i386_pci_host();
237 g_assert(pci_host);
238
239 range_set_bounds1(hole,
240 object_property_get_int(pci_host,
241 PCI_HOST_PROP_PCI_HOLE_START,
242 NULL),
243 object_property_get_int(pci_host,
244 PCI_HOST_PROP_PCI_HOLE_END,
245 NULL));
246 range_set_bounds1(hole64,
247 object_property_get_int(pci_host,
248 PCI_HOST_PROP_PCI_HOLE64_START,
249 NULL),
250 object_property_get_int(pci_host,
251 PCI_HOST_PROP_PCI_HOLE64_END,
252 NULL));
253 }
254
255 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
256
257 static void acpi_align_size(GArray *blob, unsigned align)
258 {
259 /* Align size to multiple of given size. This reduces the chance
260 * we need to change size in the future (breaking cross version migration).
261 */
262 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
263 }
264
265 /* FACS */
266 static void
267 build_facs(GArray *table_data, BIOSLinker *linker)
268 {
269 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
270 memcpy(&facs->signature, "FACS", 4);
271 facs->length = cpu_to_le32(sizeof(*facs));
272 }
273
274 /* Load chipset information in FADT */
275 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
276 {
277 fadt->model = 1;
278 fadt->reserved1 = 0;
279 fadt->sci_int = cpu_to_le16(pm->sci_int);
280 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
281 fadt->acpi_enable = pm->acpi_enable_cmd;
282 fadt->acpi_disable = pm->acpi_disable_cmd;
283 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
284 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
285 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
286 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
287 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
288 /* EVT, CNT, TMR length matches hw/acpi/core.c */
289 fadt->pm1_evt_len = 4;
290 fadt->pm1_cnt_len = 2;
291 fadt->pm_tmr_len = 4;
292 fadt->gpe0_blk_len = pm->gpe0_blk_len;
293 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
294 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
295 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
296 (1 << ACPI_FADT_F_PROC_C1) |
297 (1 << ACPI_FADT_F_SLP_BUTTON) |
298 (1 << ACPI_FADT_F_RTC_S4));
299 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
300 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
301 * For more than 8 CPUs, "Clustered Logical" mode has to be used
302 */
303 if (max_cpus > 8) {
304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
305 }
306 fadt->century = RTC_CENTURY;
307 }
308
309
310 /* FADT */
311 static void
312 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
313 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
314 const char *oem_id, const char *oem_table_id)
315 {
316 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
317 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
318 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
319
320 /* FACS address to be filled by Guest linker */
321 bios_linker_loader_add_pointer(linker,
322 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
323 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
324
325 /* DSDT address to be filled by Guest linker */
326 fadt_setup(fadt, pm);
327 bios_linker_loader_add_pointer(linker,
328 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
329 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
330
331 build_header(linker, table_data,
332 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
333 }
334
335 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
336 CPUArchIdList *apic_ids, GArray *entry)
337 {
338 int apic_id;
339 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
340
341 apic_id = apic_ids->cpus[uid].arch_id;
342 apic->type = ACPI_APIC_PROCESSOR;
343 apic->length = sizeof(*apic);
344 apic->processor_id = uid;
345 apic->local_apic_id = apic_id;
346 if (apic_ids->cpus[uid].cpu != NULL) {
347 apic->flags = cpu_to_le32(1);
348 } else {
349 /* ACPI spec says that LAPIC entry for non present
350 * CPU may be omitted from MADT or it must be marked
351 * as disabled. However omitting non present CPU from
352 * MADT breaks hotplug on linux. So possible CPUs
353 * should be put in MADT but kept disabled.
354 */
355 apic->flags = cpu_to_le32(0);
356 }
357 }
358
359 static void
360 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
361 {
362 MachineClass *mc = MACHINE_GET_CLASS(pcms);
363 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
364 int madt_start = table_data->len;
365 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
366 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
367
368 AcpiMultipleApicTable *madt;
369 AcpiMadtIoApic *io_apic;
370 AcpiMadtIntsrcovr *intsrcovr;
371 AcpiMadtLocalNmi *local_nmi;
372 int i;
373
374 madt = acpi_data_push(table_data, sizeof *madt);
375 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
376 madt->flags = cpu_to_le32(1);
377
378 for (i = 0; i < apic_ids->len; i++) {
379 adevc->madt_cpu(adev, i, apic_ids, table_data);
380 }
381 g_free(apic_ids);
382
383 io_apic = acpi_data_push(table_data, sizeof *io_apic);
384 io_apic->type = ACPI_APIC_IO;
385 io_apic->length = sizeof(*io_apic);
386 #define ACPI_BUILD_IOAPIC_ID 0x0
387 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
388 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
389 io_apic->interrupt = cpu_to_le32(0);
390
391 if (pcms->apic_xrupt_override) {
392 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
393 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
394 intsrcovr->length = sizeof(*intsrcovr);
395 intsrcovr->source = 0;
396 intsrcovr->gsi = cpu_to_le32(2);
397 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
398 }
399 for (i = 1; i < 16; i++) {
400 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
401 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
402 /* No need for a INT source override structure. */
403 continue;
404 }
405 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
406 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
407 intsrcovr->length = sizeof(*intsrcovr);
408 intsrcovr->source = i;
409 intsrcovr->gsi = cpu_to_le32(i);
410 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
411 }
412
413 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
414 local_nmi->type = ACPI_APIC_LOCAL_NMI;
415 local_nmi->length = sizeof(*local_nmi);
416 local_nmi->processor_id = 0xff; /* all processors */
417 local_nmi->flags = cpu_to_le16(0);
418 local_nmi->lint = 1; /* ACPI_LINT1 */
419
420 build_header(linker, table_data,
421 (void *)(table_data->data + madt_start), "APIC",
422 table_data->len - madt_start, 1, NULL, NULL);
423 }
424
425 /* Assign BSEL property to all buses. In the future, this can be changed
426 * to only assign to buses that support hotplug.
427 */
428 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
429 {
430 unsigned *bsel_alloc = opaque;
431 unsigned *bus_bsel;
432
433 if (qbus_is_hotpluggable(BUS(bus))) {
434 bus_bsel = g_malloc(sizeof *bus_bsel);
435
436 *bus_bsel = (*bsel_alloc)++;
437 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
438 bus_bsel, NULL);
439 }
440
441 return bsel_alloc;
442 }
443
444 static void acpi_set_pci_info(void)
445 {
446 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
447 unsigned bsel_alloc = 0;
448
449 if (bus) {
450 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
451 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
452 }
453 }
454
455 static void build_append_pcihp_notify_entry(Aml *method, int slot)
456 {
457 Aml *if_ctx;
458 int32_t devfn = PCI_DEVFN(slot, 0);
459
460 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
461 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
462 aml_append(method, if_ctx);
463 }
464
465 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
466 bool pcihp_bridge_en)
467 {
468 Aml *dev, *notify_method, *method;
469 QObject *bsel;
470 PCIBus *sec;
471 int i;
472
473 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
474 if (bsel) {
475 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
476
477 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
478 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
479 }
480
481 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
482 DeviceClass *dc;
483 PCIDeviceClass *pc;
484 PCIDevice *pdev = bus->devices[i];
485 int slot = PCI_SLOT(i);
486 bool hotplug_enabled_dev;
487 bool bridge_in_acpi;
488
489 if (!pdev) {
490 if (bsel) { /* add hotplug slots for non present devices */
491 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
492 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
493 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
494 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
495 aml_append(method,
496 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
497 );
498 aml_append(dev, method);
499 aml_append(parent_scope, dev);
500
501 build_append_pcihp_notify_entry(notify_method, slot);
502 }
503 continue;
504 }
505
506 pc = PCI_DEVICE_GET_CLASS(pdev);
507 dc = DEVICE_GET_CLASS(pdev);
508
509 /* When hotplug for bridges is enabled, bridges are
510 * described in ACPI separately (see build_pci_bus_end).
511 * In this case they aren't themselves hot-pluggable.
512 * Hotplugged bridges *are* hot-pluggable.
513 */
514 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
515 !DEVICE(pdev)->hotplugged;
516
517 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
518
519 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
520 continue;
521 }
522
523 /* start to compose PCI slot descriptor */
524 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
525 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
526
527 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
528 /* add VGA specific AML methods */
529 int s3d;
530
531 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
532 s3d = 3;
533 } else {
534 s3d = 0;
535 }
536
537 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
538 aml_append(method, aml_return(aml_int(0)));
539 aml_append(dev, method);
540
541 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
542 aml_append(method, aml_return(aml_int(0)));
543 aml_append(dev, method);
544
545 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
546 aml_append(method, aml_return(aml_int(s3d)));
547 aml_append(dev, method);
548 } else if (hotplug_enabled_dev) {
549 /* add _SUN/_EJ0 to make slot hotpluggable */
550 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
551
552 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
553 aml_append(method,
554 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
555 );
556 aml_append(dev, method);
557
558 if (bsel) {
559 build_append_pcihp_notify_entry(notify_method, slot);
560 }
561 } else if (bridge_in_acpi) {
562 /*
563 * device is coldplugged bridge,
564 * add child device descriptions into its scope
565 */
566 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
567
568 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
569 }
570 /* slot descriptor has been composed, add it into parent context */
571 aml_append(parent_scope, dev);
572 }
573
574 if (bsel) {
575 aml_append(parent_scope, notify_method);
576 }
577
578 /* Append PCNT method to notify about events on local and child buses.
579 * Add unconditionally for root since DSDT expects it.
580 */
581 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
582
583 /* If bus supports hotplug select it and notify about local events */
584 if (bsel) {
585 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
586 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
587 aml_append(method,
588 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
589 );
590 aml_append(method,
591 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
592 );
593 }
594
595 /* Notify about child bus events in any case */
596 if (pcihp_bridge_en) {
597 QLIST_FOREACH(sec, &bus->child, sibling) {
598 int32_t devfn = sec->parent_dev->devfn;
599
600 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
601 }
602 }
603 aml_append(parent_scope, method);
604 qobject_decref(bsel);
605 }
606
607 /**
608 * build_prt_entry:
609 * @link_name: link name for PCI route entry
610 *
611 * build AML package containing a PCI route entry for @link_name
612 */
613 static Aml *build_prt_entry(const char *link_name)
614 {
615 Aml *a_zero = aml_int(0);
616 Aml *pkg = aml_package(4);
617 aml_append(pkg, a_zero);
618 aml_append(pkg, a_zero);
619 aml_append(pkg, aml_name("%s", link_name));
620 aml_append(pkg, a_zero);
621 return pkg;
622 }
623
624 /*
625 * initialize_route - Initialize the interrupt routing rule
626 * through a specific LINK:
627 * if (lnk_idx == idx)
628 * route using link 'link_name'
629 */
630 static Aml *initialize_route(Aml *route, const char *link_name,
631 Aml *lnk_idx, int idx)
632 {
633 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
634 Aml *pkg = build_prt_entry(link_name);
635
636 aml_append(if_ctx, aml_store(pkg, route));
637
638 return if_ctx;
639 }
640
641 /*
642 * build_prt - Define interrupt rounting rules
643 *
644 * Returns an array of 128 routes, one for each device,
645 * based on device location.
646 * The main goal is to equaly distribute the interrupts
647 * over the 4 existing ACPI links (works only for i440fx).
648 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
649 *
650 */
651 static Aml *build_prt(bool is_pci0_prt)
652 {
653 Aml *method, *while_ctx, *pin, *res;
654
655 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
656 res = aml_local(0);
657 pin = aml_local(1);
658 aml_append(method, aml_store(aml_package(128), res));
659 aml_append(method, aml_store(aml_int(0), pin));
660
661 /* while (pin < 128) */
662 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
663 {
664 Aml *slot = aml_local(2);
665 Aml *lnk_idx = aml_local(3);
666 Aml *route = aml_local(4);
667
668 /* slot = pin >> 2 */
669 aml_append(while_ctx,
670 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
671 /* lnk_idx = (slot + pin) & 3 */
672 aml_append(while_ctx,
673 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
674 lnk_idx));
675
676 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
677 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
678 if (is_pci0_prt) {
679 Aml *if_device_1, *if_pin_4, *else_pin_4;
680
681 /* device 1 is the power-management device, needs SCI */
682 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
683 {
684 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
685 {
686 aml_append(if_pin_4,
687 aml_store(build_prt_entry("LNKS"), route));
688 }
689 aml_append(if_device_1, if_pin_4);
690 else_pin_4 = aml_else();
691 {
692 aml_append(else_pin_4,
693 aml_store(build_prt_entry("LNKA"), route));
694 }
695 aml_append(if_device_1, else_pin_4);
696 }
697 aml_append(while_ctx, if_device_1);
698 } else {
699 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
700 }
701 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
702 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
703
704 /* route[0] = 0x[slot]FFFF */
705 aml_append(while_ctx,
706 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
707 NULL),
708 aml_index(route, aml_int(0))));
709 /* route[1] = pin & 3 */
710 aml_append(while_ctx,
711 aml_store(aml_and(pin, aml_int(3), NULL),
712 aml_index(route, aml_int(1))));
713 /* res[pin] = route */
714 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
715 /* pin++ */
716 aml_append(while_ctx, aml_increment(pin));
717 }
718 aml_append(method, while_ctx);
719 /* return res*/
720 aml_append(method, aml_return(res));
721
722 return method;
723 }
724
725 typedef struct CrsRangeEntry {
726 uint64_t base;
727 uint64_t limit;
728 } CrsRangeEntry;
729
730 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
731 {
732 CrsRangeEntry *entry;
733
734 entry = g_malloc(sizeof(*entry));
735 entry->base = base;
736 entry->limit = limit;
737
738 g_ptr_array_add(ranges, entry);
739 }
740
741 static void crs_range_free(gpointer data)
742 {
743 CrsRangeEntry *entry = (CrsRangeEntry *)data;
744 g_free(entry);
745 }
746
747 static gint crs_range_compare(gconstpointer a, gconstpointer b)
748 {
749 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
750 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
751
752 return (int64_t)entry_a->base - (int64_t)entry_b->base;
753 }
754
755 /*
756 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
757 * interval, computes the 'free' ranges from the same interval.
758 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
759 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
760 */
761 static void crs_replace_with_free_ranges(GPtrArray *ranges,
762 uint64_t start, uint64_t end)
763 {
764 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
765 uint64_t free_base = start;
766 int i;
767
768 g_ptr_array_sort(ranges, crs_range_compare);
769 for (i = 0; i < ranges->len; i++) {
770 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
771
772 if (free_base < used->base) {
773 crs_range_insert(free_ranges, free_base, used->base - 1);
774 }
775
776 free_base = used->limit + 1;
777 }
778
779 if (free_base < end) {
780 crs_range_insert(free_ranges, free_base, end);
781 }
782
783 g_ptr_array_set_size(ranges, 0);
784 for (i = 0; i < free_ranges->len; i++) {
785 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
786 }
787
788 g_ptr_array_free(free_ranges, false);
789 }
790
791 /*
792 * crs_range_merge - merges adjacent ranges in the given array.
793 * Array elements are deleted and replaced with the merged ranges.
794 */
795 static void crs_range_merge(GPtrArray *range)
796 {
797 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
798 CrsRangeEntry *entry;
799 uint64_t range_base, range_limit;
800 int i;
801
802 if (!range->len) {
803 return;
804 }
805
806 g_ptr_array_sort(range, crs_range_compare);
807
808 entry = g_ptr_array_index(range, 0);
809 range_base = entry->base;
810 range_limit = entry->limit;
811 for (i = 1; i < range->len; i++) {
812 entry = g_ptr_array_index(range, i);
813 if (entry->base - 1 == range_limit) {
814 range_limit = entry->limit;
815 } else {
816 crs_range_insert(tmp, range_base, range_limit);
817 range_base = entry->base;
818 range_limit = entry->limit;
819 }
820 }
821 crs_range_insert(tmp, range_base, range_limit);
822
823 g_ptr_array_set_size(range, 0);
824 for (i = 0; i < tmp->len; i++) {
825 entry = g_ptr_array_index(tmp, i);
826 crs_range_insert(range, entry->base, entry->limit);
827 }
828 g_ptr_array_free(tmp, true);
829 }
830
831 static Aml *build_crs(PCIHostState *host,
832 GPtrArray *io_ranges, GPtrArray *mem_ranges)
833 {
834 Aml *crs = aml_resource_template();
835 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
836 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
837 CrsRangeEntry *entry;
838 uint8_t max_bus = pci_bus_num(host->bus);
839 uint8_t type;
840 int devfn;
841 int i;
842
843 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
844 uint64_t range_base, range_limit;
845 PCIDevice *dev = host->bus->devices[devfn];
846
847 if (!dev) {
848 continue;
849 }
850
851 for (i = 0; i < PCI_NUM_REGIONS; i++) {
852 PCIIORegion *r = &dev->io_regions[i];
853
854 range_base = r->addr;
855 range_limit = r->addr + r->size - 1;
856
857 /*
858 * Work-around for old bioses
859 * that do not support multiple root buses
860 */
861 if (!range_base || range_base > range_limit) {
862 continue;
863 }
864
865 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
866 crs_range_insert(host_io_ranges, range_base, range_limit);
867 } else { /* "memory" */
868 crs_range_insert(host_mem_ranges, range_base, range_limit);
869 }
870 }
871
872 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
873 if (type == PCI_HEADER_TYPE_BRIDGE) {
874 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
875 if (subordinate > max_bus) {
876 max_bus = subordinate;
877 }
878
879 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
880 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
881
882 /*
883 * Work-around for old bioses
884 * that do not support multiple root buses
885 */
886 if (range_base && range_base <= range_limit) {
887 crs_range_insert(host_io_ranges, range_base, range_limit);
888 }
889
890 range_base =
891 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
892 range_limit =
893 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
894
895 /*
896 * Work-around for old bioses
897 * that do not support multiple root buses
898 */
899 if (range_base && range_base <= range_limit) {
900 crs_range_insert(host_mem_ranges, range_base, range_limit);
901 }
902
903 range_base =
904 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
905 range_limit =
906 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
907
908 /*
909 * Work-around for old bioses
910 * that do not support multiple root buses
911 */
912 if (range_base && range_base <= range_limit) {
913 crs_range_insert(host_mem_ranges, range_base, range_limit);
914 }
915 }
916 }
917
918 crs_range_merge(host_io_ranges);
919 for (i = 0; i < host_io_ranges->len; i++) {
920 entry = g_ptr_array_index(host_io_ranges, i);
921 aml_append(crs,
922 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
923 AML_POS_DECODE, AML_ENTIRE_RANGE,
924 0, entry->base, entry->limit, 0,
925 entry->limit - entry->base + 1));
926 crs_range_insert(io_ranges, entry->base, entry->limit);
927 }
928 g_ptr_array_free(host_io_ranges, true);
929
930 crs_range_merge(host_mem_ranges);
931 for (i = 0; i < host_mem_ranges->len; i++) {
932 entry = g_ptr_array_index(host_mem_ranges, i);
933 aml_append(crs,
934 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
935 AML_MAX_FIXED, AML_NON_CACHEABLE,
936 AML_READ_WRITE,
937 0, entry->base, entry->limit, 0,
938 entry->limit - entry->base + 1));
939 crs_range_insert(mem_ranges, entry->base, entry->limit);
940 }
941 g_ptr_array_free(host_mem_ranges, true);
942
943 aml_append(crs,
944 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
945 0,
946 pci_bus_num(host->bus),
947 max_bus,
948 0,
949 max_bus - pci_bus_num(host->bus) + 1));
950
951 return crs;
952 }
953
954 static void build_memory_devices(Aml *sb_scope, int nr_mem,
955 uint16_t io_base, uint16_t io_len)
956 {
957 int i;
958 Aml *scope;
959 Aml *crs;
960 Aml *field;
961 Aml *dev;
962 Aml *method;
963 Aml *ifctx;
964
965 /* build memory devices */
966 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
967 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
968 aml_append(scope,
969 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
970 );
971
972 crs = aml_resource_template();
973 aml_append(crs,
974 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
975 );
976 aml_append(scope, aml_name_decl("_CRS", crs));
977
978 aml_append(scope, aml_operation_region(
979 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
980 aml_int(io_base), io_len)
981 );
982
983 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
984 AML_NOLOCK, AML_PRESERVE);
985 aml_append(field, /* read only */
986 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
987 aml_append(field, /* read only */
988 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
989 aml_append(field, /* read only */
990 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
991 aml_append(field, /* read only */
992 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
993 aml_append(field, /* read only */
994 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
995 aml_append(scope, field);
996
997 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
998 AML_NOLOCK, AML_WRITE_AS_ZEROS);
999 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1000 aml_append(field, /* 1 if enabled, read only */
1001 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1002 aml_append(field,
1003 /*(read) 1 if has a insert event. (write) 1 to clear event */
1004 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1005 aml_append(field,
1006 /* (read) 1 if has a remove event. (write) 1 to clear event */
1007 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1008 aml_append(field,
1009 /* initiates device eject, write only */
1010 aml_named_field(MEMORY_SLOT_EJECT, 1));
1011 aml_append(scope, field);
1012
1013 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1014 AML_NOLOCK, AML_PRESERVE);
1015 aml_append(field, /* DIMM selector, write only */
1016 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1017 aml_append(field, /* _OST event code, write only */
1018 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1019 aml_append(field, /* _OST status code, write only */
1020 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1021 aml_append(scope, field);
1022 aml_append(sb_scope, scope);
1023
1024 for (i = 0; i < nr_mem; i++) {
1025 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1026 const char *s;
1027
1028 dev = aml_device("MP%02X", i);
1029 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1030 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1031
1032 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1033 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1034 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1035 aml_append(dev, method);
1036
1037 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1038 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1039 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1040 aml_append(dev, method);
1041
1042 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1043 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1044 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1045 aml_append(dev, method);
1046
1047 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1048 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1049
1050 aml_append(method, aml_return(aml_call4(
1051 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1052 )));
1053 aml_append(dev, method);
1054
1055 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1056 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1057 aml_append(method, aml_return(aml_call2(
1058 s, aml_name("_UID"), aml_arg(0))));
1059 aml_append(dev, method);
1060
1061 aml_append(sb_scope, dev);
1062 }
1063
1064 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1065 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1066 */
1067 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1068 for (i = 0; i < nr_mem; i++) {
1069 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1070 aml_append(ifctx,
1071 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1072 );
1073 aml_append(method, ifctx);
1074 }
1075 aml_append(sb_scope, method);
1076 }
1077
1078 static void build_hpet_aml(Aml *table)
1079 {
1080 Aml *crs;
1081 Aml *field;
1082 Aml *method;
1083 Aml *if_ctx;
1084 Aml *scope = aml_scope("_SB");
1085 Aml *dev = aml_device("HPET");
1086 Aml *zero = aml_int(0);
1087 Aml *id = aml_local(0);
1088 Aml *period = aml_local(1);
1089
1090 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1091 aml_append(dev, aml_name_decl("_UID", zero));
1092
1093 aml_append(dev,
1094 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1095 HPET_LEN));
1096 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1097 aml_append(field, aml_named_field("VEND", 32));
1098 aml_append(field, aml_named_field("PRD", 32));
1099 aml_append(dev, field);
1100
1101 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1102 aml_append(method, aml_store(aml_name("VEND"), id));
1103 aml_append(method, aml_store(aml_name("PRD"), period));
1104 aml_append(method, aml_shiftright(id, aml_int(16), id));
1105 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1106 aml_equal(id, aml_int(0xffff))));
1107 {
1108 aml_append(if_ctx, aml_return(zero));
1109 }
1110 aml_append(method, if_ctx);
1111
1112 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1113 aml_lgreater(period, aml_int(100000000))));
1114 {
1115 aml_append(if_ctx, aml_return(zero));
1116 }
1117 aml_append(method, if_ctx);
1118
1119 aml_append(method, aml_return(aml_int(0x0F)));
1120 aml_append(dev, method);
1121
1122 crs = aml_resource_template();
1123 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1124 aml_append(dev, aml_name_decl("_CRS", crs));
1125
1126 aml_append(scope, dev);
1127 aml_append(table, scope);
1128 }
1129
1130 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1131 {
1132 Aml *dev, *fdi;
1133 uint8_t maxc, maxh, maxs;
1134
1135 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1136
1137 dev = aml_device("FLP%c", 'A' + idx);
1138
1139 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1140
1141 fdi = aml_package(16);
1142 aml_append(fdi, aml_int(idx)); /* Drive Number */
1143 aml_append(fdi,
1144 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1145 /*
1146 * the values below are the limits of the drive, and are thus independent
1147 * of the inserted media
1148 */
1149 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1150 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1151 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1152 /*
1153 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1154 * the drive type, so shall we
1155 */
1156 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1157 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1158 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1159 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1160 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1161 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1162 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1163 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1164 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1165 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1166 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1167
1168 aml_append(dev, aml_name_decl("_FDI", fdi));
1169 return dev;
1170 }
1171
1172 static Aml *build_fdc_device_aml(ISADevice *fdc)
1173 {
1174 int i;
1175 Aml *dev;
1176 Aml *crs;
1177
1178 #define ACPI_FDE_MAX_FD 4
1179 uint32_t fde_buf[5] = {
1180 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1181 cpu_to_le32(2) /* tape presence (2 == never present) */
1182 };
1183
1184 dev = aml_device("FDC0");
1185 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1186
1187 crs = aml_resource_template();
1188 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1189 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1190 aml_append(crs, aml_irq_no_flags(6));
1191 aml_append(crs,
1192 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1193 aml_append(dev, aml_name_decl("_CRS", crs));
1194
1195 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1196 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1197
1198 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1199 fde_buf[i] = cpu_to_le32(1); /* drive present */
1200 aml_append(dev, build_fdinfo_aml(i, type));
1201 }
1202 }
1203 aml_append(dev, aml_name_decl("_FDE",
1204 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1205
1206 return dev;
1207 }
1208
1209 static Aml *build_rtc_device_aml(void)
1210 {
1211 Aml *dev;
1212 Aml *crs;
1213
1214 dev = aml_device("RTC");
1215 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1216 crs = aml_resource_template();
1217 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1218 aml_append(crs, aml_irq_no_flags(8));
1219 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1220 aml_append(dev, aml_name_decl("_CRS", crs));
1221
1222 return dev;
1223 }
1224
1225 static Aml *build_kbd_device_aml(void)
1226 {
1227 Aml *dev;
1228 Aml *crs;
1229 Aml *method;
1230
1231 dev = aml_device("KBD");
1232 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1233
1234 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1235 aml_append(method, aml_return(aml_int(0x0f)));
1236 aml_append(dev, method);
1237
1238 crs = aml_resource_template();
1239 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1240 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1241 aml_append(crs, aml_irq_no_flags(1));
1242 aml_append(dev, aml_name_decl("_CRS", crs));
1243
1244 return dev;
1245 }
1246
1247 static Aml *build_mouse_device_aml(void)
1248 {
1249 Aml *dev;
1250 Aml *crs;
1251 Aml *method;
1252
1253 dev = aml_device("MOU");
1254 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1255
1256 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1257 aml_append(method, aml_return(aml_int(0x0f)));
1258 aml_append(dev, method);
1259
1260 crs = aml_resource_template();
1261 aml_append(crs, aml_irq_no_flags(12));
1262 aml_append(dev, aml_name_decl("_CRS", crs));
1263
1264 return dev;
1265 }
1266
1267 static Aml *build_lpt_device_aml(void)
1268 {
1269 Aml *dev;
1270 Aml *crs;
1271 Aml *method;
1272 Aml *if_ctx;
1273 Aml *else_ctx;
1274 Aml *zero = aml_int(0);
1275 Aml *is_present = aml_local(0);
1276
1277 dev = aml_device("LPT");
1278 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1279
1280 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1281 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1282 if_ctx = aml_if(aml_equal(is_present, zero));
1283 {
1284 aml_append(if_ctx, aml_return(aml_int(0x00)));
1285 }
1286 aml_append(method, if_ctx);
1287 else_ctx = aml_else();
1288 {
1289 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1290 }
1291 aml_append(method, else_ctx);
1292 aml_append(dev, method);
1293
1294 crs = aml_resource_template();
1295 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1296 aml_append(crs, aml_irq_no_flags(7));
1297 aml_append(dev, aml_name_decl("_CRS", crs));
1298
1299 return dev;
1300 }
1301
1302 static Aml *build_com_device_aml(uint8_t uid)
1303 {
1304 Aml *dev;
1305 Aml *crs;
1306 Aml *method;
1307 Aml *if_ctx;
1308 Aml *else_ctx;
1309 Aml *zero = aml_int(0);
1310 Aml *is_present = aml_local(0);
1311 const char *enabled_field = "CAEN";
1312 uint8_t irq = 4;
1313 uint16_t io_port = 0x03F8;
1314
1315 assert(uid == 1 || uid == 2);
1316 if (uid == 2) {
1317 enabled_field = "CBEN";
1318 irq = 3;
1319 io_port = 0x02F8;
1320 }
1321
1322 dev = aml_device("COM%d", uid);
1323 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1324 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1325
1326 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1327 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1328 if_ctx = aml_if(aml_equal(is_present, zero));
1329 {
1330 aml_append(if_ctx, aml_return(aml_int(0x00)));
1331 }
1332 aml_append(method, if_ctx);
1333 else_ctx = aml_else();
1334 {
1335 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1336 }
1337 aml_append(method, else_ctx);
1338 aml_append(dev, method);
1339
1340 crs = aml_resource_template();
1341 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1342 aml_append(crs, aml_irq_no_flags(irq));
1343 aml_append(dev, aml_name_decl("_CRS", crs));
1344
1345 return dev;
1346 }
1347
1348 static void build_isa_devices_aml(Aml *table)
1349 {
1350 ISADevice *fdc = pc_find_fdc0();
1351 bool ambiguous;
1352
1353 Aml *scope = aml_scope("_SB.PCI0.ISA");
1354 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1355
1356 aml_append(scope, build_rtc_device_aml());
1357 aml_append(scope, build_kbd_device_aml());
1358 aml_append(scope, build_mouse_device_aml());
1359 if (fdc) {
1360 aml_append(scope, build_fdc_device_aml(fdc));
1361 }
1362 aml_append(scope, build_lpt_device_aml());
1363 aml_append(scope, build_com_device_aml(1));
1364 aml_append(scope, build_com_device_aml(2));
1365
1366 if (ambiguous) {
1367 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1368 } else if (!obj) {
1369 error_report("No ISA bus, unable to define IPMI ACPI data");
1370 } else {
1371 build_acpi_ipmi_devices(scope, BUS(obj));
1372 }
1373
1374 aml_append(table, scope);
1375 }
1376
1377 static void build_dbg_aml(Aml *table)
1378 {
1379 Aml *field;
1380 Aml *method;
1381 Aml *while_ctx;
1382 Aml *scope = aml_scope("\\");
1383 Aml *buf = aml_local(0);
1384 Aml *len = aml_local(1);
1385 Aml *idx = aml_local(2);
1386
1387 aml_append(scope,
1388 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1389 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1390 aml_append(field, aml_named_field("DBGB", 8));
1391 aml_append(scope, field);
1392
1393 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1394
1395 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1396 aml_append(method, aml_to_buffer(buf, buf));
1397 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1398 aml_append(method, aml_store(aml_int(0), idx));
1399
1400 while_ctx = aml_while(aml_lless(idx, len));
1401 aml_append(while_ctx,
1402 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1403 aml_append(while_ctx, aml_increment(idx));
1404 aml_append(method, while_ctx);
1405
1406 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1407 aml_append(scope, method);
1408
1409 aml_append(table, scope);
1410 }
1411
1412 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1413 {
1414 Aml *dev;
1415 Aml *crs;
1416 Aml *method;
1417 uint32_t irqs[] = {5, 10, 11};
1418
1419 dev = aml_device("%s", name);
1420 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1421 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1422
1423 crs = aml_resource_template();
1424 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1425 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1426 aml_append(dev, aml_name_decl("_PRS", crs));
1427
1428 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1429 aml_append(method, aml_return(aml_call1("IQST", reg)));
1430 aml_append(dev, method);
1431
1432 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1433 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1434 aml_append(dev, method);
1435
1436 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1437 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1438 aml_append(dev, method);
1439
1440 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1441 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1442 aml_append(method, aml_store(aml_name("PRRI"), reg));
1443 aml_append(dev, method);
1444
1445 return dev;
1446 }
1447
1448 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1449 {
1450 Aml *dev;
1451 Aml *crs;
1452 Aml *method;
1453 uint32_t irqs;
1454
1455 dev = aml_device("%s", name);
1456 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1457 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1458
1459 crs = aml_resource_template();
1460 irqs = gsi;
1461 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1462 AML_SHARED, &irqs, 1));
1463 aml_append(dev, aml_name_decl("_PRS", crs));
1464
1465 aml_append(dev, aml_name_decl("_CRS", crs));
1466
1467 /*
1468 * _DIS can be no-op because the interrupt cannot be disabled.
1469 */
1470 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1471 aml_append(dev, method);
1472
1473 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1474 aml_append(dev, method);
1475
1476 return dev;
1477 }
1478
1479 /* _CRS method - get current settings */
1480 static Aml *build_iqcr_method(bool is_piix4)
1481 {
1482 Aml *if_ctx;
1483 uint32_t irqs;
1484 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1485 Aml *crs = aml_resource_template();
1486
1487 irqs = 0;
1488 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1489 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1490 aml_append(method, aml_name_decl("PRR0", crs));
1491
1492 aml_append(method,
1493 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1494
1495 if (is_piix4) {
1496 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1497 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1498 aml_append(method, if_ctx);
1499 } else {
1500 aml_append(method,
1501 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1502 aml_name("PRRI")));
1503 }
1504
1505 aml_append(method, aml_return(aml_name("PRR0")));
1506 return method;
1507 }
1508
1509 /* _STA method - get status */
1510 static Aml *build_irq_status_method(void)
1511 {
1512 Aml *if_ctx;
1513 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1514
1515 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1516 aml_append(if_ctx, aml_return(aml_int(0x09)));
1517 aml_append(method, if_ctx);
1518 aml_append(method, aml_return(aml_int(0x0B)));
1519 return method;
1520 }
1521
1522 static void build_piix4_pci0_int(Aml *table)
1523 {
1524 Aml *dev;
1525 Aml *crs;
1526 Aml *field;
1527 Aml *method;
1528 uint32_t irqs;
1529 Aml *sb_scope = aml_scope("_SB");
1530 Aml *pci0_scope = aml_scope("PCI0");
1531
1532 aml_append(pci0_scope, build_prt(true));
1533 aml_append(sb_scope, pci0_scope);
1534
1535 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1536 aml_append(field, aml_named_field("PRQ0", 8));
1537 aml_append(field, aml_named_field("PRQ1", 8));
1538 aml_append(field, aml_named_field("PRQ2", 8));
1539 aml_append(field, aml_named_field("PRQ3", 8));
1540 aml_append(sb_scope, field);
1541
1542 aml_append(sb_scope, build_irq_status_method());
1543 aml_append(sb_scope, build_iqcr_method(true));
1544
1545 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1546 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1547 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1548 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1549
1550 dev = aml_device("LNKS");
1551 {
1552 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1553 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1554
1555 crs = aml_resource_template();
1556 irqs = 9;
1557 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1558 AML_ACTIVE_HIGH, AML_SHARED,
1559 &irqs, 1));
1560 aml_append(dev, aml_name_decl("_PRS", crs));
1561
1562 /* The SCI cannot be disabled and is always attached to GSI 9,
1563 * so these are no-ops. We only need this link to override the
1564 * polarity to active high and match the content of the MADT.
1565 */
1566 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1567 aml_append(method, aml_return(aml_int(0x0b)));
1568 aml_append(dev, method);
1569
1570 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1571 aml_append(dev, method);
1572
1573 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1574 aml_append(method, aml_return(aml_name("_PRS")));
1575 aml_append(dev, method);
1576
1577 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1578 aml_append(dev, method);
1579 }
1580 aml_append(sb_scope, dev);
1581
1582 aml_append(table, sb_scope);
1583 }
1584
1585 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1586 {
1587 int i;
1588 int head;
1589 Aml *pkg;
1590 char base = name[3] < 'E' ? 'A' : 'E';
1591 char *s = g_strdup(name);
1592 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1593
1594 assert(strlen(s) == 4);
1595
1596 head = name[3] - base;
1597 for (i = 0; i < 4; i++) {
1598 if (head + i > 3) {
1599 head = i * -1;
1600 }
1601 s[3] = base + head + i;
1602 pkg = aml_package(4);
1603 aml_append(pkg, a_nr);
1604 aml_append(pkg, aml_int(i));
1605 aml_append(pkg, aml_name("%s", s));
1606 aml_append(pkg, aml_int(0));
1607 aml_append(ctx, pkg);
1608 }
1609 g_free(s);
1610 }
1611
1612 static Aml *build_q35_routing_table(const char *str)
1613 {
1614 int i;
1615 Aml *pkg;
1616 char *name = g_strdup_printf("%s ", str);
1617
1618 pkg = aml_package(128);
1619 for (i = 0; i < 0x18; i++) {
1620 name[3] = 'E' + (i & 0x3);
1621 append_q35_prt_entry(pkg, i, name);
1622 }
1623
1624 name[3] = 'E';
1625 append_q35_prt_entry(pkg, 0x18, name);
1626
1627 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1628 for (i = 0x0019; i < 0x1e; i++) {
1629 name[3] = 'A';
1630 append_q35_prt_entry(pkg, i, name);
1631 }
1632
1633 /* PCIe->PCI bridge. use PIRQ[E-H] */
1634 name[3] = 'E';
1635 append_q35_prt_entry(pkg, 0x1e, name);
1636 name[3] = 'A';
1637 append_q35_prt_entry(pkg, 0x1f, name);
1638
1639 g_free(name);
1640 return pkg;
1641 }
1642
1643 static void build_q35_pci0_int(Aml *table)
1644 {
1645 Aml *field;
1646 Aml *method;
1647 Aml *sb_scope = aml_scope("_SB");
1648 Aml *pci0_scope = aml_scope("PCI0");
1649
1650 /* Zero => PIC mode, One => APIC Mode */
1651 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1652 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1653 {
1654 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1655 }
1656 aml_append(table, method);
1657
1658 aml_append(pci0_scope,
1659 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1660 aml_append(pci0_scope,
1661 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1662
1663 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1664 {
1665 Aml *if_ctx;
1666 Aml *else_ctx;
1667
1668 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1669 section 6.2.8.1 */
1670 /* Note: we provide the same info as the PCI routing
1671 table of the Bochs BIOS */
1672 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1673 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1674 aml_append(method, if_ctx);
1675 else_ctx = aml_else();
1676 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1677 aml_append(method, else_ctx);
1678 }
1679 aml_append(pci0_scope, method);
1680 aml_append(sb_scope, pci0_scope);
1681
1682 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1683 aml_append(field, aml_named_field("PRQA", 8));
1684 aml_append(field, aml_named_field("PRQB", 8));
1685 aml_append(field, aml_named_field("PRQC", 8));
1686 aml_append(field, aml_named_field("PRQD", 8));
1687 aml_append(field, aml_reserved_field(0x20));
1688 aml_append(field, aml_named_field("PRQE", 8));
1689 aml_append(field, aml_named_field("PRQF", 8));
1690 aml_append(field, aml_named_field("PRQG", 8));
1691 aml_append(field, aml_named_field("PRQH", 8));
1692 aml_append(sb_scope, field);
1693
1694 aml_append(sb_scope, build_irq_status_method());
1695 aml_append(sb_scope, build_iqcr_method(false));
1696
1697 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1698 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1699 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1700 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1701 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1702 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1703 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1704 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1705
1706 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1707 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1708 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1709 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1710 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1711 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1712 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1713 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1714
1715 aml_append(table, sb_scope);
1716 }
1717
1718 static void build_q35_isa_bridge(Aml *table)
1719 {
1720 Aml *dev;
1721 Aml *scope;
1722 Aml *field;
1723
1724 scope = aml_scope("_SB.PCI0");
1725 dev = aml_device("ISA");
1726 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1727
1728 /* ICH9 PCI to ISA irq remapping */
1729 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1730 aml_int(0x60), 0x0C));
1731
1732 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1733 aml_int(0x80), 0x02));
1734 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1735 aml_append(field, aml_named_field("COMA", 3));
1736 aml_append(field, aml_reserved_field(1));
1737 aml_append(field, aml_named_field("COMB", 3));
1738 aml_append(field, aml_reserved_field(1));
1739 aml_append(field, aml_named_field("LPTD", 2));
1740 aml_append(dev, field);
1741
1742 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1743 aml_int(0x82), 0x02));
1744 /* enable bits */
1745 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1746 aml_append(field, aml_named_field("CAEN", 1));
1747 aml_append(field, aml_named_field("CBEN", 1));
1748 aml_append(field, aml_named_field("LPEN", 1));
1749 aml_append(dev, field);
1750
1751 aml_append(scope, dev);
1752 aml_append(table, scope);
1753 }
1754
1755 static void build_piix4_pm(Aml *table)
1756 {
1757 Aml *dev;
1758 Aml *scope;
1759
1760 scope = aml_scope("_SB.PCI0");
1761 dev = aml_device("PX13");
1762 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1763
1764 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1765 aml_int(0x00), 0xff));
1766 aml_append(scope, dev);
1767 aml_append(table, scope);
1768 }
1769
1770 static void build_piix4_isa_bridge(Aml *table)
1771 {
1772 Aml *dev;
1773 Aml *scope;
1774 Aml *field;
1775
1776 scope = aml_scope("_SB.PCI0");
1777 dev = aml_device("ISA");
1778 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1779
1780 /* PIIX PCI to ISA irq remapping */
1781 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1782 aml_int(0x60), 0x04));
1783 /* enable bits */
1784 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1785 /* Offset(0x5f),, 7, */
1786 aml_append(field, aml_reserved_field(0x2f8));
1787 aml_append(field, aml_reserved_field(7));
1788 aml_append(field, aml_named_field("LPEN", 1));
1789 /* Offset(0x67),, 3, */
1790 aml_append(field, aml_reserved_field(0x38));
1791 aml_append(field, aml_reserved_field(3));
1792 aml_append(field, aml_named_field("CAEN", 1));
1793 aml_append(field, aml_reserved_field(3));
1794 aml_append(field, aml_named_field("CBEN", 1));
1795 aml_append(dev, field);
1796
1797 aml_append(scope, dev);
1798 aml_append(table, scope);
1799 }
1800
1801 static void build_piix4_pci_hotplug(Aml *table)
1802 {
1803 Aml *scope;
1804 Aml *field;
1805 Aml *method;
1806
1807 scope = aml_scope("_SB.PCI0");
1808
1809 aml_append(scope,
1810 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1811 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1812 aml_append(field, aml_named_field("PCIU", 32));
1813 aml_append(field, aml_named_field("PCID", 32));
1814 aml_append(scope, field);
1815
1816 aml_append(scope,
1817 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1818 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1819 aml_append(field, aml_named_field("B0EJ", 32));
1820 aml_append(scope, field);
1821
1822 aml_append(scope,
1823 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1824 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1825 aml_append(field, aml_named_field("BNUM", 32));
1826 aml_append(scope, field);
1827
1828 aml_append(scope, aml_mutex("BLCK", 0));
1829
1830 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1831 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1832 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1833 aml_append(method,
1834 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1835 aml_append(method, aml_release(aml_name("BLCK")));
1836 aml_append(method, aml_return(aml_int(0)));
1837 aml_append(scope, method);
1838
1839 aml_append(table, scope);
1840 }
1841
1842 static Aml *build_q35_osc_method(void)
1843 {
1844 Aml *if_ctx;
1845 Aml *if_ctx2;
1846 Aml *else_ctx;
1847 Aml *method;
1848 Aml *a_cwd1 = aml_name("CDW1");
1849 Aml *a_ctrl = aml_name("CTRL");
1850
1851 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1852 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1853
1854 if_ctx = aml_if(aml_equal(
1855 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1856 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1857 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1858
1859 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1860 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1861
1862 /*
1863 * Always allow native PME, AER (no dependencies)
1864 * Never allow SHPC (no SHPC controller in this system)
1865 */
1866 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1867
1868 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1869 /* Unknown revision */
1870 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1871 aml_append(if_ctx, if_ctx2);
1872
1873 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1874 /* Capabilities bits were masked */
1875 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1876 aml_append(if_ctx, if_ctx2);
1877
1878 /* Update DWORD3 in the buffer */
1879 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1880 aml_append(method, if_ctx);
1881
1882 else_ctx = aml_else();
1883 /* Unrecognized UUID */
1884 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1885 aml_append(method, else_ctx);
1886
1887 aml_append(method, aml_return(aml_arg(3)));
1888 return method;
1889 }
1890
1891 static void
1892 build_dsdt(GArray *table_data, BIOSLinker *linker,
1893 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1894 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1895 {
1896 CrsRangeEntry *entry;
1897 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1898 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1899 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1900 PCMachineState *pcms = PC_MACHINE(machine);
1901 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1902 uint32_t nr_mem = machine->ram_slots;
1903 int root_bus_limit = 0xFF;
1904 PCIBus *bus = NULL;
1905 int i;
1906
1907 dsdt = init_aml_allocator();
1908
1909 /* Reserve space for header */
1910 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1911
1912 build_dbg_aml(dsdt);
1913 if (misc->is_piix4) {
1914 sb_scope = aml_scope("_SB");
1915 dev = aml_device("PCI0");
1916 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1917 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1918 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1919 aml_append(sb_scope, dev);
1920 aml_append(dsdt, sb_scope);
1921
1922 build_hpet_aml(dsdt);
1923 build_piix4_pm(dsdt);
1924 build_piix4_isa_bridge(dsdt);
1925 build_isa_devices_aml(dsdt);
1926 build_piix4_pci_hotplug(dsdt);
1927 build_piix4_pci0_int(dsdt);
1928 } else {
1929 sb_scope = aml_scope("_SB");
1930 aml_append(sb_scope,
1931 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1932 aml_append(sb_scope,
1933 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1934 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1935 aml_append(field, aml_named_field("PCIB", 8));
1936 aml_append(sb_scope, field);
1937 aml_append(dsdt, sb_scope);
1938
1939 sb_scope = aml_scope("_SB");
1940 dev = aml_device("PCI0");
1941 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1942 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1943 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1944 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1945 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1946 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1947 aml_append(dev, build_q35_osc_method());
1948 aml_append(sb_scope, dev);
1949 aml_append(dsdt, sb_scope);
1950
1951 build_hpet_aml(dsdt);
1952 build_q35_isa_bridge(dsdt);
1953 build_isa_devices_aml(dsdt);
1954 build_q35_pci0_int(dsdt);
1955 }
1956
1957 if (pcmc->legacy_cpu_hotplug) {
1958 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1959 } else {
1960 CPUHotplugFeatures opts = {
1961 .apci_1_compatible = true, .has_legacy_cphp = true
1962 };
1963 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1964 "\\_SB.PCI0", "\\_GPE._E02");
1965 }
1966 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
1967 pm->mem_hp_io_len);
1968
1969 scope = aml_scope("_GPE");
1970 {
1971 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1972
1973 if (misc->is_piix4) {
1974 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1975 aml_append(method,
1976 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1977 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1978 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1979 aml_append(scope, method);
1980 }
1981
1982 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1983 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1984 aml_append(scope, method);
1985 }
1986 aml_append(dsdt, scope);
1987
1988 bus = PC_MACHINE(machine)->bus;
1989 if (bus) {
1990 QLIST_FOREACH(bus, &bus->child, sibling) {
1991 uint8_t bus_num = pci_bus_num(bus);
1992 uint8_t numa_node = pci_bus_numa_node(bus);
1993
1994 /* look only for expander root buses */
1995 if (!pci_bus_is_root(bus)) {
1996 continue;
1997 }
1998
1999 if (bus_num < root_bus_limit) {
2000 root_bus_limit = bus_num - 1;
2001 }
2002
2003 scope = aml_scope("\\_SB");
2004 dev = aml_device("PC%.02X", bus_num);
2005 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2006 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2007 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2008
2009 if (numa_node != NUMA_NODE_UNASSIGNED) {
2010 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2011 }
2012
2013 aml_append(dev, build_prt(false));
2014 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2015 io_ranges, mem_ranges);
2016 aml_append(dev, aml_name_decl("_CRS", crs));
2017 aml_append(scope, dev);
2018 aml_append(dsdt, scope);
2019 }
2020 }
2021
2022 scope = aml_scope("\\_SB.PCI0");
2023 /* build PCI0._CRS */
2024 crs = aml_resource_template();
2025 aml_append(crs,
2026 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2027 0x0000, 0x0, root_bus_limit,
2028 0x0000, root_bus_limit + 1));
2029 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2030
2031 aml_append(crs,
2032 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2033 AML_POS_DECODE, AML_ENTIRE_RANGE,
2034 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2035
2036 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2037 for (i = 0; i < io_ranges->len; i++) {
2038 entry = g_ptr_array_index(io_ranges, i);
2039 aml_append(crs,
2040 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2041 AML_POS_DECODE, AML_ENTIRE_RANGE,
2042 0x0000, entry->base, entry->limit,
2043 0x0000, entry->limit - entry->base + 1));
2044 }
2045
2046 aml_append(crs,
2047 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2048 AML_CACHEABLE, AML_READ_WRITE,
2049 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2050
2051 crs_replace_with_free_ranges(mem_ranges,
2052 range_lob(pci_hole),
2053 range_upb(pci_hole));
2054 for (i = 0; i < mem_ranges->len; i++) {
2055 entry = g_ptr_array_index(mem_ranges, i);
2056 aml_append(crs,
2057 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2058 AML_NON_CACHEABLE, AML_READ_WRITE,
2059 0, entry->base, entry->limit,
2060 0, entry->limit - entry->base + 1));
2061 }
2062
2063 if (!range_is_empty(pci_hole64)) {
2064 aml_append(crs,
2065 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2066 AML_CACHEABLE, AML_READ_WRITE,
2067 0, range_lob(pci_hole64), range_upb(pci_hole64), 0,
2068 range_upb(pci_hole64) + 1 - range_lob(pci_hole64)));
2069 }
2070
2071 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2072 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2073 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2074 }
2075 aml_append(scope, aml_name_decl("_CRS", crs));
2076
2077 /* reserve GPE0 block resources */
2078 dev = aml_device("GPE0");
2079 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2080 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2081 /* device present, functioning, decoding, not shown in UI */
2082 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2083 crs = aml_resource_template();
2084 aml_append(crs,
2085 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2086 );
2087 aml_append(dev, aml_name_decl("_CRS", crs));
2088 aml_append(scope, dev);
2089
2090 g_ptr_array_free(io_ranges, true);
2091 g_ptr_array_free(mem_ranges, true);
2092
2093 /* reserve PCIHP resources */
2094 if (pm->pcihp_io_len) {
2095 dev = aml_device("PHPR");
2096 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2097 aml_append(dev,
2098 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2099 /* device present, functioning, decoding, not shown in UI */
2100 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2101 crs = aml_resource_template();
2102 aml_append(crs,
2103 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2104 pm->pcihp_io_len)
2105 );
2106 aml_append(dev, aml_name_decl("_CRS", crs));
2107 aml_append(scope, dev);
2108 }
2109 aml_append(dsdt, scope);
2110
2111 /* create S3_ / S4_ / S5_ packages if necessary */
2112 scope = aml_scope("\\");
2113 if (!pm->s3_disabled) {
2114 pkg = aml_package(4);
2115 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2116 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2117 aml_append(pkg, aml_int(0)); /* reserved */
2118 aml_append(pkg, aml_int(0)); /* reserved */
2119 aml_append(scope, aml_name_decl("_S3", pkg));
2120 }
2121
2122 if (!pm->s4_disabled) {
2123 pkg = aml_package(4);
2124 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2125 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2126 aml_append(pkg, aml_int(pm->s4_val));
2127 aml_append(pkg, aml_int(0)); /* reserved */
2128 aml_append(pkg, aml_int(0)); /* reserved */
2129 aml_append(scope, aml_name_decl("_S4", pkg));
2130 }
2131
2132 pkg = aml_package(4);
2133 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2134 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2135 aml_append(pkg, aml_int(0)); /* reserved */
2136 aml_append(pkg, aml_int(0)); /* reserved */
2137 aml_append(scope, aml_name_decl("_S5", pkg));
2138 aml_append(dsdt, scope);
2139
2140 /* create fw_cfg node, unconditionally */
2141 {
2142 /* when using port i/o, the 8-bit data register *always* overlaps
2143 * with half of the 16-bit control register. Hence, the total size
2144 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2145 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2146 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2147 "dma_enabled", NULL) ?
2148 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2149 FW_CFG_CTL_SIZE;
2150
2151 scope = aml_scope("\\_SB.PCI0");
2152 dev = aml_device("FWCF");
2153
2154 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2155
2156 /* device present, functioning, decoding, not shown in UI */
2157 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2158
2159 crs = aml_resource_template();
2160 aml_append(crs,
2161 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2162 );
2163 aml_append(dev, aml_name_decl("_CRS", crs));
2164
2165 aml_append(scope, dev);
2166 aml_append(dsdt, scope);
2167 }
2168
2169 if (misc->applesmc_io_base) {
2170 scope = aml_scope("\\_SB.PCI0.ISA");
2171 dev = aml_device("SMC");
2172
2173 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2174 /* device present, functioning, decoding, not shown in UI */
2175 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2176
2177 crs = aml_resource_template();
2178 aml_append(crs,
2179 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2180 0x01, APPLESMC_MAX_DATA_LENGTH)
2181 );
2182 aml_append(crs, aml_irq_no_flags(6));
2183 aml_append(dev, aml_name_decl("_CRS", crs));
2184
2185 aml_append(scope, dev);
2186 aml_append(dsdt, scope);
2187 }
2188
2189 if (misc->pvpanic_port) {
2190 scope = aml_scope("\\_SB.PCI0.ISA");
2191
2192 dev = aml_device("PEVT");
2193 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2194
2195 crs = aml_resource_template();
2196 aml_append(crs,
2197 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2198 );
2199 aml_append(dev, aml_name_decl("_CRS", crs));
2200
2201 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2202 aml_int(misc->pvpanic_port), 1));
2203 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2204 aml_append(field, aml_named_field("PEPT", 8));
2205 aml_append(dev, field);
2206
2207 /* device present, functioning, decoding, shown in UI */
2208 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2209
2210 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2211 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2212 aml_append(method, aml_return(aml_local(0)));
2213 aml_append(dev, method);
2214
2215 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2216 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2217 aml_append(dev, method);
2218
2219 aml_append(scope, dev);
2220 aml_append(dsdt, scope);
2221 }
2222
2223 sb_scope = aml_scope("\\_SB");
2224 {
2225 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2226 pm->mem_hp_io_len);
2227
2228 {
2229 Object *pci_host;
2230 PCIBus *bus = NULL;
2231
2232 pci_host = acpi_get_i386_pci_host();
2233 if (pci_host) {
2234 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2235 }
2236
2237 if (bus) {
2238 Aml *scope = aml_scope("PCI0");
2239 /* Scan all PCI buses. Generate tables to support hotplug. */
2240 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2241
2242 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2243 dev = aml_device("ISA.TPM");
2244 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2245 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2246 crs = aml_resource_template();
2247 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2248 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2249 /*
2250 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2251 Rewrite to take IRQ from TPM device model and
2252 fix default IRQ value there to use some unused IRQ
2253 */
2254 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2255 aml_append(dev, aml_name_decl("_CRS", crs));
2256 aml_append(scope, dev);
2257 }
2258
2259 aml_append(sb_scope, scope);
2260 }
2261 }
2262 aml_append(dsdt, sb_scope);
2263 }
2264
2265 /* copy AML table into ACPI tables blob and patch header there */
2266 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2267 build_header(linker, table_data,
2268 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2269 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2270 free_aml_allocator();
2271 }
2272
2273 static void
2274 build_hpet(GArray *table_data, BIOSLinker *linker)
2275 {
2276 Acpi20Hpet *hpet;
2277
2278 hpet = acpi_data_push(table_data, sizeof(*hpet));
2279 /* Note timer_block_id value must be kept in sync with value advertised by
2280 * emulated hpet
2281 */
2282 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2283 hpet->addr.address = cpu_to_le64(HPET_BASE);
2284 build_header(linker, table_data,
2285 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2286 }
2287
2288 static void
2289 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2290 {
2291 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2292 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2293 unsigned log_addr_offset =
2294 (char *)&tcpa->log_area_start_address - table_data->data;
2295
2296 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2297 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2298 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2299
2300 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2301 false /* high memory */);
2302
2303 /* log area start address to be filled by Guest linker */
2304 bios_linker_loader_add_pointer(linker,
2305 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2306 ACPI_BUILD_TPMLOG_FILE, 0);
2307
2308 build_header(linker, table_data,
2309 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2310 }
2311
2312 static void
2313 build_tpm2(GArray *table_data, BIOSLinker *linker)
2314 {
2315 Acpi20TPM2 *tpm2_ptr;
2316
2317 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2318
2319 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2320 tpm2_ptr->control_area_address = cpu_to_le64(0);
2321 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2322
2323 build_header(linker, table_data,
2324 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2325 }
2326
2327 static void
2328 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2329 {
2330 AcpiSystemResourceAffinityTable *srat;
2331 AcpiSratProcessorAffinity *core;
2332 AcpiSratMemoryAffinity *numamem;
2333
2334 int i;
2335 int srat_start, numa_start, slots;
2336 uint64_t mem_len, mem_base, next_base;
2337 MachineClass *mc = MACHINE_GET_CLASS(machine);
2338 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2339 PCMachineState *pcms = PC_MACHINE(machine);
2340 ram_addr_t hotplugabble_address_space_size =
2341 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2342 NULL);
2343
2344 srat_start = table_data->len;
2345
2346 srat = acpi_data_push(table_data, sizeof *srat);
2347 srat->reserved1 = cpu_to_le32(1);
2348
2349 for (i = 0; i < apic_ids->len; i++) {
2350 int j;
2351 int apic_id = apic_ids->cpus[i].arch_id;
2352
2353 core = acpi_data_push(table_data, sizeof *core);
2354 core->type = ACPI_SRAT_PROCESSOR_APIC;
2355 core->length = sizeof(*core);
2356 core->local_apic_id = apic_id;
2357 for (j = 0; j < nb_numa_nodes; j++) {
2358 if (test_bit(i, numa_info[j].node_cpu)) {
2359 core->proximity_lo = j;
2360 break;
2361 }
2362 }
2363 memset(core->proximity_hi, 0, 3);
2364 core->local_sapic_eid = 0;
2365 core->flags = cpu_to_le32(1);
2366 }
2367
2368
2369 /* the memory map is a bit tricky, it contains at least one hole
2370 * from 640k-1M and possibly another one from 3.5G-4G.
2371 */
2372 next_base = 0;
2373 numa_start = table_data->len;
2374
2375 numamem = acpi_data_push(table_data, sizeof *numamem);
2376 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2377 next_base = 1024 * 1024;
2378 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2379 mem_base = next_base;
2380 mem_len = pcms->node_mem[i - 1];
2381 if (i == 1) {
2382 mem_len -= 1024 * 1024;
2383 }
2384 next_base = mem_base + mem_len;
2385
2386 /* Cut out the ACPI_PCI hole */
2387 if (mem_base <= pcms->below_4g_mem_size &&
2388 next_base > pcms->below_4g_mem_size) {
2389 mem_len -= next_base - pcms->below_4g_mem_size;
2390 if (mem_len > 0) {
2391 numamem = acpi_data_push(table_data, sizeof *numamem);
2392 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2393 MEM_AFFINITY_ENABLED);
2394 }
2395 mem_base = 1ULL << 32;
2396 mem_len = next_base - pcms->below_4g_mem_size;
2397 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2398 }
2399 numamem = acpi_data_push(table_data, sizeof *numamem);
2400 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2401 MEM_AFFINITY_ENABLED);
2402 }
2403 slots = (table_data->len - numa_start) / sizeof *numamem;
2404 for (; slots < pcms->numa_nodes + 2; slots++) {
2405 numamem = acpi_data_push(table_data, sizeof *numamem);
2406 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2407 }
2408
2409 /*
2410 * Entry is required for Windows to enable memory hotplug in OS.
2411 * Memory devices may override proximity set by this entry,
2412 * providing _PXM method if necessary.
2413 */
2414 if (hotplugabble_address_space_size) {
2415 numamem = acpi_data_push(table_data, sizeof *numamem);
2416 build_srat_memory(numamem, pcms->hotplug_memory.base,
2417 hotplugabble_address_space_size, 0,
2418 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2419 }
2420
2421 build_header(linker, table_data,
2422 (void *)(table_data->data + srat_start),
2423 "SRAT",
2424 table_data->len - srat_start, 1, NULL, NULL);
2425 g_free(apic_ids);
2426 }
2427
2428 static void
2429 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2430 {
2431 AcpiTableMcfg *mcfg;
2432 const char *sig;
2433 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2434
2435 mcfg = acpi_data_push(table_data, len);
2436 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2437 /* Only a single allocation so no need to play with segments */
2438 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2439 mcfg->allocation[0].start_bus_number = 0;
2440 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2441
2442 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2443 * To avoid table size changes (which create migration issues),
2444 * always create the table even if there are no allocations,
2445 * but set the signature to a reserved value in this case.
2446 * ACPI spec requires OSPMs to ignore such tables.
2447 */
2448 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2449 /* Reserved signature: ignored by OSPM */
2450 sig = "QEMU";
2451 } else {
2452 sig = "MCFG";
2453 }
2454 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2455 }
2456
2457 static void
2458 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2459 {
2460 int dmar_start = table_data->len;
2461
2462 AcpiTableDmar *dmar;
2463 AcpiDmarHardwareUnit *drhd;
2464
2465 dmar = acpi_data_push(table_data, sizeof(*dmar));
2466 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2467 dmar->flags = 0; /* No intr_remap for now */
2468
2469 /* DMAR Remapping Hardware Unit Definition structure */
2470 drhd = acpi_data_push(table_data, sizeof(*drhd));
2471 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2472 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2473 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2474 drhd->pci_segment = cpu_to_le16(0);
2475 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2476
2477 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2478 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2479 }
2480
2481 static GArray *
2482 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2483 {
2484 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2485 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2486 unsigned rsdt_pa_offset =
2487 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2488
2489 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2490 true /* fseg memory */);
2491
2492 memcpy(&rsdp->signature, "RSD PTR ", 8);
2493 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2494 /* Address to be filled by Guest linker */
2495 bios_linker_loader_add_pointer(linker,
2496 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2497 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2498
2499 /* Checksum to be filled by Guest linker */
2500 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2501 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2502 (char *)&rsdp->checksum - rsdp_table->data);
2503
2504 return rsdp_table;
2505 }
2506
2507 typedef
2508 struct AcpiBuildState {
2509 /* Copy of table in RAM (for patching). */
2510 MemoryRegion *table_mr;
2511 /* Is table patched? */
2512 uint8_t patched;
2513 void *rsdp;
2514 MemoryRegion *rsdp_mr;
2515 MemoryRegion *linker_mr;
2516 } AcpiBuildState;
2517
2518 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2519 {
2520 Object *pci_host;
2521 QObject *o;
2522
2523 pci_host = acpi_get_i386_pci_host();
2524 g_assert(pci_host);
2525
2526 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2527 if (!o) {
2528 return false;
2529 }
2530 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2531 qobject_decref(o);
2532
2533 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2534 assert(o);
2535 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2536 qobject_decref(o);
2537 return true;
2538 }
2539
2540 static bool acpi_has_iommu(void)
2541 {
2542 bool ambiguous;
2543 Object *intel_iommu;
2544
2545 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2546 &ambiguous);
2547 return intel_iommu && !ambiguous;
2548 }
2549
2550 static
2551 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2552 {
2553 PCMachineState *pcms = PC_MACHINE(machine);
2554 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2555 GArray *table_offsets;
2556 unsigned facs, dsdt, rsdt, fadt;
2557 AcpiPmInfo pm;
2558 AcpiMiscInfo misc;
2559 AcpiMcfgInfo mcfg;
2560 Range pci_hole, pci_hole64;
2561 uint8_t *u;
2562 size_t aml_len = 0;
2563 GArray *tables_blob = tables->table_data;
2564 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2565
2566 acpi_get_pm_info(&pm);
2567 acpi_get_misc_info(&misc);
2568 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2569 acpi_get_slic_oem(&slic_oem);
2570
2571 table_offsets = g_array_new(false, true /* clear */,
2572 sizeof(uint32_t));
2573 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2574
2575 bios_linker_loader_alloc(tables->linker,
2576 ACPI_BUILD_TABLE_FILE, tables_blob,
2577 64 /* Ensure FACS is aligned */,
2578 false /* high memory */);
2579
2580 /*
2581 * FACS is pointed to by FADT.
2582 * We place it first since it's the only table that has alignment
2583 * requirements.
2584 */
2585 facs = tables_blob->len;
2586 build_facs(tables_blob, tables->linker);
2587
2588 /* DSDT is pointed to by FADT */
2589 dsdt = tables_blob->len;
2590 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2591 &pci_hole, &pci_hole64, machine);
2592
2593 /* Count the size of the DSDT and SSDT, we will need it for legacy
2594 * sizing of ACPI tables.
2595 */
2596 aml_len += tables_blob->len - dsdt;
2597
2598 /* ACPI tables pointed to by RSDT */
2599 fadt = tables_blob->len;
2600 acpi_add_table(table_offsets, tables_blob);
2601 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2602 slic_oem.id, slic_oem.table_id);
2603 aml_len += tables_blob->len - fadt;
2604
2605 acpi_add_table(table_offsets, tables_blob);
2606 build_madt(tables_blob, tables->linker, pcms);
2607
2608 if (misc.has_hpet) {
2609 acpi_add_table(table_offsets, tables_blob);
2610 build_hpet(tables_blob, tables->linker);
2611 }
2612 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2613 acpi_add_table(table_offsets, tables_blob);
2614 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2615
2616 if (misc.tpm_version == TPM_VERSION_2_0) {
2617 acpi_add_table(table_offsets, tables_blob);
2618 build_tpm2(tables_blob, tables->linker);
2619 }
2620 }
2621 if (pcms->numa_nodes) {
2622 acpi_add_table(table_offsets, tables_blob);
2623 build_srat(tables_blob, tables->linker, machine);
2624 }
2625 if (acpi_get_mcfg(&mcfg)) {
2626 acpi_add_table(table_offsets, tables_blob);
2627 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2628 }
2629 if (acpi_has_iommu()) {
2630 acpi_add_table(table_offsets, tables_blob);
2631 build_dmar_q35(tables_blob, tables->linker);
2632 }
2633 if (pcms->acpi_nvdimm_state.is_enabled) {
2634 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2635 pcms->acpi_nvdimm_state.dsm_mem);
2636 }
2637
2638 /* Add tables supplied by user (if any) */
2639 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2640 unsigned len = acpi_table_len(u);
2641
2642 acpi_add_table(table_offsets, tables_blob);
2643 g_array_append_vals(tables_blob, u, len);
2644 }
2645
2646 /* RSDT is pointed to by RSDP */
2647 rsdt = tables_blob->len;
2648 build_rsdt(tables_blob, tables->linker, table_offsets,
2649 slic_oem.id, slic_oem.table_id);
2650
2651 /* RSDP is in FSEG memory, so allocate it separately */
2652 build_rsdp(tables->rsdp, tables->linker, rsdt);
2653
2654 /* We'll expose it all to Guest so we want to reduce
2655 * chance of size changes.
2656 *
2657 * We used to align the tables to 4k, but of course this would
2658 * too simple to be enough. 4k turned out to be too small an
2659 * alignment very soon, and in fact it is almost impossible to
2660 * keep the table size stable for all (max_cpus, max_memory_slots)
2661 * combinations. So the table size is always 64k for pc-i440fx-2.1
2662 * and we give an error if the table grows beyond that limit.
2663 *
2664 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2665 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2666 * than 2.0 and we can always pad the smaller tables with zeros. We can
2667 * then use the exact size of the 2.0 tables.
2668 *
2669 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2670 */
2671 if (pcmc->legacy_acpi_table_size) {
2672 /* Subtracting aml_len gives the size of fixed tables. Then add the
2673 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2674 */
2675 int legacy_aml_len =
2676 pcmc->legacy_acpi_table_size +
2677 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2678 int legacy_table_size =
2679 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2680 ACPI_BUILD_ALIGN_SIZE);
2681 if (tables_blob->len > legacy_table_size) {
2682 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2683 error_report("Warning: migration may not work.");
2684 }
2685 g_array_set_size(tables_blob, legacy_table_size);
2686 } else {
2687 /* Make sure we have a buffer in case we need to resize the tables. */
2688 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2689 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2690 error_report("Warning: ACPI tables are larger than 64k.");
2691 error_report("Warning: migration may not work.");
2692 error_report("Warning: please remove CPUs, NUMA nodes, "
2693 "memory slots or PCI bridges.");
2694 }
2695 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2696 }
2697
2698 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2699
2700 /* Cleanup memory that's no longer used. */
2701 g_array_free(table_offsets, true);
2702 }
2703
2704 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2705 {
2706 uint32_t size = acpi_data_len(data);
2707
2708 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2709 memory_region_ram_resize(mr, size, &error_abort);
2710
2711 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2712 memory_region_set_dirty(mr, 0, size);
2713 }
2714
2715 static void acpi_build_update(void *build_opaque)
2716 {
2717 AcpiBuildState *build_state = build_opaque;
2718 AcpiBuildTables tables;
2719
2720 /* No state to update or already patched? Nothing to do. */
2721 if (!build_state || build_state->patched) {
2722 return;
2723 }
2724 build_state->patched = 1;
2725
2726 acpi_build_tables_init(&tables);
2727
2728 acpi_build(&tables, MACHINE(qdev_get_machine()));
2729
2730 acpi_ram_update(build_state->table_mr, tables.table_data);
2731
2732 if (build_state->rsdp) {
2733 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2734 } else {
2735 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2736 }
2737
2738 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2739 acpi_build_tables_cleanup(&tables, true);
2740 }
2741
2742 static void acpi_build_reset(void *build_opaque)
2743 {
2744 AcpiBuildState *build_state = build_opaque;
2745 build_state->patched = 0;
2746 }
2747
2748 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2749 GArray *blob, const char *name,
2750 uint64_t max_size)
2751 {
2752 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2753 name, acpi_build_update, build_state);
2754 }
2755
2756 static const VMStateDescription vmstate_acpi_build = {
2757 .name = "acpi_build",
2758 .version_id = 1,
2759 .minimum_version_id = 1,
2760 .fields = (VMStateField[]) {
2761 VMSTATE_UINT8(patched, AcpiBuildState),
2762 VMSTATE_END_OF_LIST()
2763 },
2764 };
2765
2766 void acpi_setup(void)
2767 {
2768 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2769 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2770 AcpiBuildTables tables;
2771 AcpiBuildState *build_state;
2772
2773 if (!pcms->fw_cfg) {
2774 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2775 return;
2776 }
2777
2778 if (!pcmc->has_acpi_build) {
2779 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2780 return;
2781 }
2782
2783 if (!acpi_enabled) {
2784 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2785 return;
2786 }
2787
2788 build_state = g_malloc0(sizeof *build_state);
2789
2790 acpi_set_pci_info();
2791
2792 acpi_build_tables_init(&tables);
2793 acpi_build(&tables, MACHINE(pcms));
2794
2795 /* Now expose it all to Guest */
2796 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2797 ACPI_BUILD_TABLE_FILE,
2798 ACPI_BUILD_TABLE_MAX_SIZE);
2799 assert(build_state->table_mr != NULL);
2800
2801 build_state->linker_mr =
2802 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2803 "etc/table-loader", 0);
2804
2805 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2806 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2807
2808 if (!pcmc->rsdp_in_ram) {
2809 /*
2810 * Keep for compatibility with old machine types.
2811 * Though RSDP is small, its contents isn't immutable, so
2812 * we'll update it along with the rest of tables on guest access.
2813 */
2814 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2815
2816 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2817 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2818 acpi_build_update, build_state,
2819 build_state->rsdp, rsdp_size);
2820 build_state->rsdp_mr = NULL;
2821 } else {
2822 build_state->rsdp = NULL;
2823 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2824 ACPI_BUILD_RSDP_FILE, 0);
2825 }
2826
2827 qemu_register_reset(acpi_build_reset, build_state);
2828 acpi_build_reset(build_state);
2829 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2830
2831 /* Cleanup tables but don't free the memory: we track it
2832 * in build_state.
2833 */
2834 acpi_build_tables_cleanup(&tables, false);
2835 }
AR7 emulation for QEMU