target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 308 {
 309     ARMCPU *cpu = arm_env_get_cpu(env);
 310
 311     raw_write(env, ri, value);
 312     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 313 }
 314
 315 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 316 {
 317     ARMCPU *cpu = arm_env_get_cpu(env);
 318
 319     if (raw_read(env, ri) != value) {
 320         /* Unlike real hardware the qemu TLB uses virtual addresses,
 321          * not modified virtual addresses, so this causes a TLB flush.
 322          */
 323         tlb_flush(CPU(cpu), 1);
 324         raw_write(env, ri, value);
 325     }
 326 }
 327
 328 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 329                              uint64_t value)
 330 {
 331     ARMCPU *cpu = arm_env_get_cpu(env);
 332
 333     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 334         && !extended_addresses_enabled(env)) {
 335         /* For VMSA (when not using the LPAE long descriptor page table
 336          * format) this register includes the ASID, so do a TLB flush.
 337          * For PMSA it is purely a process ID and no action is needed.
 338          */
 339         tlb_flush(CPU(cpu), 1);
 340     }
 341     raw_write(env, ri, value);
 342 }
 343
 344 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 345                           uint64_t value)
 346 {
 347     /* Invalidate all (TLBIALL) */
 348     ARMCPU *cpu = arm_env_get_cpu(env);
 349
 350     tlb_flush(CPU(cpu), 1);
 351 }
 352
 353 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 354                           uint64_t value)
 355 {
 356     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 357     ARMCPU *cpu = arm_env_get_cpu(env);
 358
 359     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 360 }
 361
 362 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 363                            uint64_t value)
 364 {
 365     /* Invalidate by ASID (TLBIASID) */
 366     ARMCPU *cpu = arm_env_get_cpu(env);
 367
 368     tlb_flush(CPU(cpu), value == 0);
 369 }
 370
 371 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 372                            uint64_t value)
 373 {
 374     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 375     ARMCPU *cpu = arm_env_get_cpu(env);
 376
 377     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 378 }
 379
 380 /* IS variants of TLB operations must affect all cores */
 381 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 382                              uint64_t value)
 383 {
 384     CPUState *other_cs;
 385
 386     CPU_FOREACH(other_cs) {
 387         tlb_flush(other_cs, 1);
 388     }
 389 }
 390
 391 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 392                              uint64_t value)
 393 {
 394     CPUState *other_cs;
 395
 396     CPU_FOREACH(other_cs) {
 397         tlb_flush(other_cs, value == 0);
 398     }
 399 }
 400
 401 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 402                              uint64_t value)
 403 {
 404     CPUState *other_cs;
 405
 406     CPU_FOREACH(other_cs) {
 407         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 408     }
 409 }
 410
 411 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 412                              uint64_t value)
 413 {
 414     CPUState *other_cs;
 415
 416     CPU_FOREACH(other_cs) {
 417         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 418     }
 419 }
 420
 421 static const ARMCPRegInfo cp_reginfo[] = {
 422     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 423       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 424       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 425     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 426       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 427       .access = PL1_RW,
 428       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 429       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 430     REGINFO_SENTINEL
 431 };
 432
 433 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 434     /* NB: Some of these registers exist in v8 but with more precise
 435      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 436      */
 437     /* MMU Domain access control / MPU write buffer control */
 438     { .name = "DACR", .cp = 15,
 439       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 440       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 441       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 442     /* ??? This covers not just the impdef TLB lockdown registers but also
 443      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 444      */
 445     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 446       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 447     /* Cache maintenance ops; some of this space may be overridden later. */
 448     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 449       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 450       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 451     REGINFO_SENTINEL
 452 };
 453
 454 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 455     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 456      * over-broad.
 457      */
 458     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 459       .access = PL1_W, .type = ARM_CP_WFI },
 460     REGINFO_SENTINEL
 461 };
 462
 463 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 464     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 465      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 466      */
 467     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 468       .access = PL1_W, .type = ARM_CP_WFI },
 469     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 470      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 471      * OMAPCP will override this space.
 472      */
 473     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 474       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 475       .resetvalue = 0 },
 476     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 477       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 478       .resetvalue = 0 },
 479     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 480     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 481       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 482       .resetvalue = 0 },
 483     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 484      * implementing it as RAZ means the "debug architecture version" bits
 485      * will read as a reserved value, which should cause Linux to not try
 486      * to use the debug hardware.
 487      */
 488     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 489       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 490     /* MMU TLB control. Note that the wildcarding means we cover not just
 491      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 492      */
 493     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 494       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 495       .type = ARM_CP_NO_MIGRATE },
 496     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 497       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 498       .type = ARM_CP_NO_MIGRATE },
 499     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 500       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 501       .type = ARM_CP_NO_MIGRATE },
 502     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 503       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 504       .type = ARM_CP_NO_MIGRATE },
 505     REGINFO_SENTINEL
 506 };
 507
 508 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 509                         uint64_t value)
 510 {
 511     uint32_t mask = 0;
 512
 513     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 514     if (!arm_feature(env, ARM_FEATURE_V8)) {
 515         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 516          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 517          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 518          */
 519         if (arm_feature(env, ARM_FEATURE_VFP)) {
 520             /* VFP coprocessor: cp10 & cp11 [23:20] */
 521             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 522
 523             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 524                 /* ASEDIS [31] bit is RAO/WI */
 525                 value |= (1 << 31);
 526             }
 527
 528             /* VFPv3 and upwards with NEON implement 32 double precision
 529              * registers (D0-D31).
 530              */
 531             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 532                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 533                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 534                 value |= (1 << 30);
 535             }
 536         }
 537         value &= mask;
 538     }
 539     env->cp15.c1_coproc = value;
 540 }
 541
 542 static const ARMCPRegInfo v6_cp_reginfo[] = {
 543     /* prefetch by MVA in v6, NOP in v7 */
 544     { .name = "MVA_prefetch",
 545       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 546       .access = PL1_W, .type = ARM_CP_NOP },
 547     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 548       .access = PL0_W, .type = ARM_CP_NOP },
 549     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 550       .access = PL0_W, .type = ARM_CP_NOP },
 551     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 552       .access = PL0_W, .type = ARM_CP_NOP },
 553     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 554       .access = PL1_RW,
 555       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 556       .resetvalue = 0, },
 557     /* Watchpoint Fault Address Register : should actually only be present
 558      * for 1136, 1176, 11MPCore.
 559      */
 560     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 561       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 562     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 563       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 564       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 565       .resetvalue = 0, .writefn = cpacr_write },
 566     REGINFO_SENTINEL
 567 };
 568
 569 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 570 {
 571     /* Performance monitor registers user accessibility is controlled
 572      * by PMUSERENR.
 573      */
 574     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 575         return CP_ACCESS_TRAP;
 576     }
 577     return CP_ACCESS_OK;
 578 }
 579
 580 #ifndef CONFIG_USER_ONLY
 581
 582 static inline bool arm_ccnt_enabled(CPUARMState *env)
 583 {
 584     /* This does not support checking PMCCFILTR_EL0 register */
 585
 586     if (!(env->cp15.c9_pmcr & PMCRE)) {
 587         return false;
 588     }
 589
 590     return true;
 591 }
 592
 593 void pmccntr_sync(CPUARMState *env)
 594 {
 595     uint64_t temp_ticks;
 596
 597     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 598                           get_ticks_per_sec(), 1000000);
 599
 600     if (env->cp15.c9_pmcr & PMCRD) {
 601         /* Increment once every 64 processor clock cycles */
 602         temp_ticks /= 64;
 603     }
 604
 605     if (arm_ccnt_enabled(env)) {
 606         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 607     }
 608 }
 609
 610 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 611                        uint64_t value)
 612 {
 613     pmccntr_sync(env);
 614
 615     if (value & PMCRC) {
 616         /* The counter has been reset */
 617         env->cp15.c15_ccnt = 0;
 618     }
 619
 620     /* only the DP, X, D and E bits are writable */
 621     env->cp15.c9_pmcr &= ~0x39;
 622     env->cp15.c9_pmcr |= (value & 0x39);
 623
 624     pmccntr_sync(env);
 625 }
 626
 627 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 628 {
 629     uint64_t total_ticks;
 630
 631     if (!arm_ccnt_enabled(env)) {
 632         /* Counter is disabled, do not change value */
 633         return env->cp15.c15_ccnt;
 634     }
 635
 636     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 637                            get_ticks_per_sec(), 1000000);
 638
 639     if (env->cp15.c9_pmcr & PMCRD) {
 640         /* Increment once every 64 processor clock cycles */
 641         total_ticks /= 64;
 642     }
 643     return total_ticks - env->cp15.c15_ccnt;
 644 }
 645
 646 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 647                         uint64_t value)
 648 {
 649     uint64_t total_ticks;
 650
 651     if (!arm_ccnt_enabled(env)) {
 652         /* Counter is disabled, set the absolute value */
 653         env->cp15.c15_ccnt = value;
 654         return;
 655     }
 656
 657     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 658                            get_ticks_per_sec(), 1000000);
 659
 660     if (env->cp15.c9_pmcr & PMCRD) {
 661         /* Increment once every 64 processor clock cycles */
 662         total_ticks /= 64;
 663     }
 664     env->cp15.c15_ccnt = total_ticks - value;
 665 }
 666
 667 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 668                             uint64_t value)
 669 {
 670     uint64_t cur_val = pmccntr_read(env, NULL);
 671
 672     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 673 }
 674
 675 #else /* CONFIG_USER_ONLY */
 676
 677 void pmccntr_sync(CPUARMState *env)
 678 {
 679 }
 680
 681 #endif
 682
 683 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 684                             uint64_t value)
 685 {
 686     pmccntr_sync(env);
 687     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 688     pmccntr_sync(env);
 689 }
 690
 691 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 692                             uint64_t value)
 693 {
 694     value &= (1 << 31);
 695     env->cp15.c9_pmcnten |= value;
 696 }
 697
 698 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 699                              uint64_t value)
 700 {
 701     value &= (1 << 31);
 702     env->cp15.c9_pmcnten &= ~value;
 703 }
 704
 705 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 706                          uint64_t value)
 707 {
 708     env->cp15.c9_pmovsr &= ~value;
 709 }
 710
 711 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 712                              uint64_t value)
 713 {
 714     env->cp15.c9_pmxevtyper = value & 0xff;
 715 }
 716
 717 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 718                             uint64_t value)
 719 {
 720     env->cp15.c9_pmuserenr = value & 1;
 721 }
 722
 723 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 724                              uint64_t value)
 725 {
 726     /* We have no event counters so only the C bit can be changed */
 727     value &= (1 << 31);
 728     env->cp15.c9_pminten |= value;
 729 }
 730
 731 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 732                              uint64_t value)
 733 {
 734     value &= (1 << 31);
 735     env->cp15.c9_pminten &= ~value;
 736 }
 737
 738 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 739                        uint64_t value)
 740 {
 741     /* Note that even though the AArch64 view of this register has bits
 742      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 743      * architectural requirements for bits which are RES0 only in some
 744      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 745      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 746      */
 747     raw_write(env, ri, value & ~0x1FULL);
 748 }
 749
 750 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 751 {
 752     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 753      * For bits that vary between AArch32/64, code needs to check the
 754      * current execution mode before directly using the feature bit.
 755      */
 756     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 757
 758     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 759         valid_mask &= ~SCR_HCE;
 760
 761         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 762          * supported if EL2 exists. The bit is UNK/SBZP when
 763          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 764          * when EL2 is unavailable.
 765          */
 766         if (arm_feature(env, ARM_FEATURE_V7)) {
 767             valid_mask &= ~SCR_SMD;
 768         }
 769     }
 770
 771     /* Clear all-context RES0 bits.  */
 772     value &= valid_mask;
 773     raw_write(env, ri, value);
 774 }
 775
 776 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 777 {
 778     ARMCPU *cpu = arm_env_get_cpu(env);
 779     return cpu->ccsidr[env->cp15.c0_cssel];
 780 }
 781
 782 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 783                          uint64_t value)
 784 {
 785     raw_write(env, ri, value & 0xf);
 786 }
 787
 788 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 789 {
 790     CPUState *cs = ENV_GET_CPU(env);
 791     uint64_t ret = 0;
 792
 793     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 794         ret |= CPSR_I;
 795     }
 796     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 797         ret |= CPSR_F;
 798     }
 799     /* External aborts are not possible in QEMU so A bit is always clear */
 800     return ret;
 801 }
 802
 803 static const ARMCPRegInfo v7_cp_reginfo[] = {
 804     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 805     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 806       .access = PL1_W, .type = ARM_CP_NOP },
 807     /* Performance monitors are implementation defined in v7,
 808      * but with an ARM recommended set of registers, which we
 809      * follow (although we don't actually implement any counters)
 810      *
 811      * Performance registers fall into three categories:
 812      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 813      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 814      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 815      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 816      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 817      */
 818     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 819       .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
 820       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 821       .writefn = pmcntenset_write,
 822       .accessfn = pmreg_access,
 823       .raw_writefn = raw_write },
 824     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 825       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 826       .access = PL0_RW, .accessfn = pmreg_access,
 827       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 828       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 829     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 830       .access = PL0_RW,
 831       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 832       .accessfn = pmreg_access,
 833       .writefn = pmcntenclr_write,
 834       .type = ARM_CP_NO_MIGRATE },
 835     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 836       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 837       .access = PL0_RW, .accessfn = pmreg_access,
 838       .type = ARM_CP_NO_MIGRATE,
 839       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 840       .writefn = pmcntenclr_write },
 841     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 842       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 843       .accessfn = pmreg_access,
 844       .writefn = pmovsr_write,
 845       .raw_writefn = raw_write },
 846     /* Unimplemented so WI. */
 847     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 848       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 849     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 850      * We choose to RAZ/WI.
 851      */
 852     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 853       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 854       .accessfn = pmreg_access },
 855 #ifndef CONFIG_USER_ONLY
 856     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 857       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 858       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 859       .accessfn = pmreg_access },
 860     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 861       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 862       .access = PL0_RW, .accessfn = pmreg_access,
 863       .type = ARM_CP_IO,
 864       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 865 #endif
 866     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 867       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 868       .writefn = pmccfiltr_write,
 869       .access = PL0_RW, .accessfn = pmreg_access,
 870       .type = ARM_CP_IO,
 871       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 872       .resetvalue = 0, },
 873     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 874       .access = PL0_RW,
 875       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 876       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 877       .raw_writefn = raw_write },
 878     /* Unimplemented, RAZ/WI. */
 879     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 880       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 881       .accessfn = pmreg_access },
 882     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 883       .access = PL0_R | PL1_RW,
 884       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 885       .resetvalue = 0,
 886       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 887     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 888       .access = PL1_RW,
 889       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 890       .resetvalue = 0,
 891       .writefn = pmintenset_write, .raw_writefn = raw_write },
 892     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 893       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 894       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 895       .resetvalue = 0, .writefn = pmintenclr_write, },
 896     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 897       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 898       .access = PL1_RW, .writefn = vbar_write,
 899       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
 900       .resetvalue = 0 },
 901     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 902       .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
 903       .resetvalue = 0, .writefn = scr_write },
 904     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 905       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 906       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 907     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 908       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 909       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 910       .writefn = csselr_write, .resetvalue = 0 },
 911     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 912      * just RAZ for all cores:
 913      */
 914     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 915       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 916       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 917     /* Auxiliary fault status registers: these also are IMPDEF, and we
 918      * choose to RAZ/WI for all cores.
 919      */
 920     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 921       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 922       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 923     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 924       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 925       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 926     /* MAIR can just read-as-written because we don't implement caches
 927      * and so don't need to care about memory attributes.
 928      */
 929     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 930       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 931       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 932       .resetvalue = 0 },
 933     /* For non-long-descriptor page tables these are PRRR and NMRR;
 934      * regardless they still act as reads-as-written for QEMU.
 935      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 936      * definition.
 937      */
 938     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 939       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 940       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 941       .resetfn = arm_cp_reset_ignore },
 942     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 943       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 944       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 945       .resetfn = arm_cp_reset_ignore },
 946     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 947       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 948       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 949     /* 32 bit ITLB invalidates */
 950     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
 951       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
 952     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
 953       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
 954     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
 955       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
 956     /* 32 bit DTLB invalidates */
 957     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
 958       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
 959     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
 960       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
 961     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
 962       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
 963     /* 32 bit TLB invalidates */
 964     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
 965       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
 966     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
 967       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
 968     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
 969       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
 970     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
 971       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
 972     REGINFO_SENTINEL
 973 };
 974
 975 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
 976     /* 32 bit TLB invalidates, Inner Shareable */
 977     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
 978       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_is_write },
 979     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
 980       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
 981     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
 982       .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
 983       .writefn = tlbiasid_is_write },
 984     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
 985       .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
 986       .writefn = tlbimvaa_is_write },
 987     REGINFO_SENTINEL
 988 };
 989
 990 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 991                         uint64_t value)
 992 {
 993     value &= 1;
 994     env->teecr = value;
 995 }
 996
 997 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 998 {
 999     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
1000         return CP_ACCESS_TRAP;
1001     }
1002     return CP_ACCESS_OK;
1003 }
1004
1005 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1006     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1007       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1008       .resetvalue = 0,
1009       .writefn = teecr_write },
1010     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1011       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1012       .accessfn = teehbr_access, .resetvalue = 0 },
1013     REGINFO_SENTINEL
1014 };
1015
1016 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1017     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1018       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1019       .access = PL0_RW,
1020       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
1021     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1022       .access = PL0_RW,
1023       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
1024       .resetfn = arm_cp_reset_ignore },
1025     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1026       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1027       .access = PL0_R|PL1_W,
1028       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
1029     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1030       .access = PL0_R|PL1_W,
1031       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
1032       .resetfn = arm_cp_reset_ignore },
1033     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
1034       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1035       .access = PL1_RW,
1036       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
1037     REGINFO_SENTINEL
1038 };
1039
1040 #ifndef CONFIG_USER_ONLY
1041
1042 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1043 {
1044     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1045     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1046         return CP_ACCESS_TRAP;
1047     }
1048     return CP_ACCESS_OK;
1049 }
1050
1051 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1052 {
1053     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1054     if (arm_current_pl(env) == 0 &&
1055         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1056         return CP_ACCESS_TRAP;
1057     }
1058     return CP_ACCESS_OK;
1059 }
1060
1061 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1062 {
1063     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1064      * EL0[PV]TEN is zero.
1065      */
1066     if (arm_current_pl(env) == 0 &&
1067         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1068         return CP_ACCESS_TRAP;
1069     }
1070     return CP_ACCESS_OK;
1071 }
1072
1073 static CPAccessResult gt_pct_access(CPUARMState *env,
1074                                          const ARMCPRegInfo *ri)
1075 {
1076     return gt_counter_access(env, GTIMER_PHYS);
1077 }
1078
1079 static CPAccessResult gt_vct_access(CPUARMState *env,
1080                                          const ARMCPRegInfo *ri)
1081 {
1082     return gt_counter_access(env, GTIMER_VIRT);
1083 }
1084
1085 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1086 {
1087     return gt_timer_access(env, GTIMER_PHYS);
1088 }
1089
1090 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1091 {
1092     return gt_timer_access(env, GTIMER_VIRT);
1093 }
1094
1095 static uint64_t gt_get_countervalue(CPUARMState *env)
1096 {
1097     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1098 }
1099
1100 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1101 {
1102     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1103
1104     if (gt->ctl & 1) {
1105         /* Timer enabled: calculate and set current ISTATUS, irq, and
1106          * reset timer to when ISTATUS next has to change
1107          */
1108         uint64_t count = gt_get_countervalue(&cpu->env);
1109         /* Note that this must be unsigned 64 bit arithmetic: */
1110         int istatus = count >= gt->cval;
1111         uint64_t nexttick;
1112
1113         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1114         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1115                      (istatus && !(gt->ctl & 2)));
1116         if (istatus) {
1117             /* Next transition is when count rolls back over to zero */
1118             nexttick = UINT64_MAX;
1119         } else {
1120             /* Next transition is when we hit cval */
1121             nexttick = gt->cval;
1122         }
1123         /* Note that the desired next expiry time might be beyond the
1124          * signed-64-bit range of a QEMUTimer -- in this case we just
1125          * set the timer for as far in the future as possible. When the
1126          * timer expires we will reset the timer for any remaining period.
1127          */
1128         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1129             nexttick = INT64_MAX / GTIMER_SCALE;
1130         }
1131         timer_mod(cpu->gt_timer[timeridx], nexttick);
1132     } else {
1133         /* Timer disabled: ISTATUS and timer output always clear */
1134         gt->ctl &= ~4;
1135         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1136         timer_del(cpu->gt_timer[timeridx]);
1137     }
1138 }
1139
1140 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1141 {
1142     ARMCPU *cpu = arm_env_get_cpu(env);
1143     int timeridx = ri->opc1 & 1;
1144
1145     timer_del(cpu->gt_timer[timeridx]);
1146 }
1147
1148 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1149 {
1150     return gt_get_countervalue(env);
1151 }
1152
1153 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1154                           uint64_t value)
1155 {
1156     int timeridx = ri->opc1 & 1;
1157
1158     env->cp15.c14_timer[timeridx].cval = value;
1159     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1160 }
1161
1162 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1163 {
1164     int timeridx = ri->crm & 1;
1165
1166     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1167                       gt_get_countervalue(env));
1168 }
1169
1170 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1171                           uint64_t value)
1172 {
1173     int timeridx = ri->crm & 1;
1174
1175     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1176         + sextract64(value, 0, 32);
1177     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1178 }
1179
1180 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1181                          uint64_t value)
1182 {
1183     ARMCPU *cpu = arm_env_get_cpu(env);
1184     int timeridx = ri->crm & 1;
1185     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1186
1187     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1188     if ((oldval ^ value) & 1) {
1189         /* Enable toggled */
1190         gt_recalc_timer(cpu, timeridx);
1191     } else if ((oldval ^ value) & 2) {
1192         /* IMASK toggled: don't need to recalculate,
1193          * just set the interrupt line based on ISTATUS
1194          */
1195         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1196                      (oldval & 4) && !(value & 2));
1197     }
1198 }
1199
1200 void arm_gt_ptimer_cb(void *opaque)
1201 {
1202     ARMCPU *cpu = opaque;
1203
1204     gt_recalc_timer(cpu, GTIMER_PHYS);
1205 }
1206
1207 void arm_gt_vtimer_cb(void *opaque)
1208 {
1209     ARMCPU *cpu = opaque;
1210
1211     gt_recalc_timer(cpu, GTIMER_VIRT);
1212 }
1213
1214 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1215     /* Note that CNTFRQ is purely reads-as-written for the benefit
1216      * of software; writing it doesn't actually change the timer frequency.
1217      * Our reset value matches the fixed frequency we implement the timer at.
1218      */
1219     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1220       .type = ARM_CP_NO_MIGRATE,
1221       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1222       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1223       .resetfn = arm_cp_reset_ignore,
1224     },
1225     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1226       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1227       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1228       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1229       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1230     },
1231     /* overall control: mostly access permissions */
1232     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1233       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1234       .access = PL1_RW,
1235       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1236       .resetvalue = 0,
1237     },
1238     /* per-timer control */
1239     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1240       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1241       .accessfn = gt_ptimer_access,
1242       .fieldoffset = offsetoflow32(CPUARMState,
1243                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1244       .resetfn = arm_cp_reset_ignore,
1245       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1246     },
1247     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1248       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1249       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1250       .accessfn = gt_ptimer_access,
1251       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1252       .resetvalue = 0,
1253       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1254     },
1255     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1256       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1257       .accessfn = gt_vtimer_access,
1258       .fieldoffset = offsetoflow32(CPUARMState,
1259                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1260       .resetfn = arm_cp_reset_ignore,
1261       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1262     },
1263     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1264       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1265       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1266       .accessfn = gt_vtimer_access,
1267       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1268       .resetvalue = 0,
1269       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1270     },
1271     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1272     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1273       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1274       .accessfn = gt_ptimer_access,
1275       .readfn = gt_tval_read, .writefn = gt_tval_write,
1276     },
1277     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1278       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1279       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1280       .readfn = gt_tval_read, .writefn = gt_tval_write,
1281     },
1282     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1283       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1284       .accessfn = gt_vtimer_access,
1285       .readfn = gt_tval_read, .writefn = gt_tval_write,
1286     },
1287     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1288       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1289       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1290       .readfn = gt_tval_read, .writefn = gt_tval_write,
1291     },
1292     /* The counter itself */
1293     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1294       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1295       .accessfn = gt_pct_access,
1296       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1297     },
1298     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1299       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1300       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1301       .accessfn = gt_pct_access,
1302       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1303     },
1304     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1305       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1306       .accessfn = gt_vct_access,
1307       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1308     },
1309     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1310       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1311       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1312       .accessfn = gt_vct_access,
1313       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1314     },
1315     /* Comparison value, indicating when the timer goes off */
1316     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1317       .access = PL1_RW | PL0_R,
1318       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1319       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1320       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1321       .writefn = gt_cval_write, .raw_writefn = raw_write,
1322     },
1323     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1324       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1325       .access = PL1_RW | PL0_R,
1326       .type = ARM_CP_IO,
1327       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1328       .resetvalue = 0, .accessfn = gt_vtimer_access,
1329       .writefn = gt_cval_write, .raw_writefn = raw_write,
1330     },
1331     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1332       .access = PL1_RW | PL0_R,
1333       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1334       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1335       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1336       .writefn = gt_cval_write, .raw_writefn = raw_write,
1337     },
1338     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1339       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1340       .access = PL1_RW | PL0_R,
1341       .type = ARM_CP_IO,
1342       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1343       .resetvalue = 0, .accessfn = gt_vtimer_access,
1344       .writefn = gt_cval_write, .raw_writefn = raw_write,
1345     },
1346     REGINFO_SENTINEL
1347 };
1348
1349 #else
1350 /* In user-mode none of the generic timer registers are accessible,
1351  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1352  * so instead just don't register any of them.
1353  */
1354 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1355     REGINFO_SENTINEL
1356 };
1357
1358 #endif
1359
1360 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1361 {
1362     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1363         raw_write(env, ri, value);
1364     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1365         raw_write(env, ri, value & 0xfffff6ff);
1366     } else {
1367         raw_write(env, ri, value & 0xfffff1ff);
1368     }
1369 }
1370
1371 #ifndef CONFIG_USER_ONLY
1372 /* get_phys_addr() isn't present for user-mode-only targets */
1373
1374 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1375 {
1376     if (ri->opc2 & 4) {
1377         /* Other states are only available with TrustZone; in
1378          * a non-TZ implementation these registers don't exist
1379          * at all, which is an Uncategorized trap. This underdecoding
1380          * is safe because the reginfo is NO_MIGRATE.
1381          */
1382         return CP_ACCESS_TRAP_UNCATEGORIZED;
1383     }
1384     return CP_ACCESS_OK;
1385 }
1386
1387 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1388 {
1389     hwaddr phys_addr;
1390     target_ulong page_size;
1391     int prot;
1392     int ret, is_user = ri->opc2 & 2;
1393     int access_type = ri->opc2 & 1;
1394
1395     ret = get_phys_addr(env, value, access_type, is_user,
1396                         &phys_addr, &prot, &page_size);
1397     if (extended_addresses_enabled(env)) {
1398         /* ret is a DFSR/IFSR value for the long descriptor
1399          * translation table format, but with WnR always clear.
1400          * Convert it to a 64-bit PAR.
1401          */
1402         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1403         if (ret == 0) {
1404             par64 |= phys_addr & ~0xfffULL;
1405             /* We don't set the ATTR or SH fields in the PAR. */
1406         } else {
1407             par64 |= 1; /* F */
1408             par64 |= (ret & 0x3f) << 1; /* FS */
1409             /* Note that S2WLK and FSTAGE are always zero, because we don't
1410              * implement virtualization and therefore there can't be a stage 2
1411              * fault.
1412              */
1413         }
1414         env->cp15.par_el1 = par64;
1415     } else {
1416         /* ret is a DFSR/IFSR value for the short descriptor
1417          * translation table format (with WnR always clear).
1418          * Convert it to a 32-bit PAR.
1419          */
1420         if (ret == 0) {
1421             /* We do not set any attribute bits in the PAR */
1422             if (page_size == (1 << 24)
1423                 && arm_feature(env, ARM_FEATURE_V7)) {
1424                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1425             } else {
1426                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1427             }
1428         } else {
1429             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1430                 ((ret & (1 << 12)) >> 6) |
1431                 ((ret & 0xf) << 1) | 1;
1432         }
1433     }
1434 }
1435 #endif
1436
1437 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1438     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1439       .access = PL1_RW, .resetvalue = 0,
1440       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1441       .writefn = par_write },
1442 #ifndef CONFIG_USER_ONLY
1443     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1444       .access = PL1_W, .accessfn = ats_access,
1445       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1446 #endif
1447     REGINFO_SENTINEL
1448 };
1449
1450 /* Return basic MPU access permission bits.  */
1451 static uint32_t simple_mpu_ap_bits(uint32_t val)
1452 {
1453     uint32_t ret;
1454     uint32_t mask;
1455     int i;
1456     ret = 0;
1457     mask = 3;
1458     for (i = 0; i < 16; i += 2) {
1459         ret |= (val >> i) & mask;
1460         mask <<= 2;
1461     }
1462     return ret;
1463 }
1464
1465 /* Pad basic MPU access permission bits to extended format.  */
1466 static uint32_t extended_mpu_ap_bits(uint32_t val)
1467 {
1468     uint32_t ret;
1469     uint32_t mask;
1470     int i;
1471     ret = 0;
1472     mask = 3;
1473     for (i = 0; i < 16; i += 2) {
1474         ret |= (val & mask) << i;
1475         mask <<= 2;
1476     }
1477     return ret;
1478 }
1479
1480 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1481                                  uint64_t value)
1482 {
1483     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1484 }
1485
1486 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1487 {
1488     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1489 }
1490
1491 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1492                                  uint64_t value)
1493 {
1494     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1495 }
1496
1497 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1498 {
1499     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1500 }
1501
1502 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1503     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1504       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1505       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1506       .resetvalue = 0,
1507       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1508     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1509       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1510       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1511       .resetvalue = 0,
1512       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1513     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1514       .access = PL1_RW,
1515       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1516       .resetvalue = 0, },
1517     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1518       .access = PL1_RW,
1519       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1520       .resetvalue = 0, },
1521     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1522       .access = PL1_RW,
1523       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1524     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1525       .access = PL1_RW,
1526       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1527     /* Protection region base and size registers */
1528     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1529       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1530       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1531     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1532       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1533       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1534     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1535       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1536       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1537     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1538       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1539       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1540     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1541       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1542       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1543     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1544       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1545       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1546     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1547       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1548       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1549     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1550       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1551       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1552     REGINFO_SENTINEL
1553 };
1554
1555 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1556                                  uint64_t value)
1557 {
1558     int maskshift = extract32(value, 0, 3);
1559
1560     if (!arm_feature(env, ARM_FEATURE_V8)) {
1561         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1562             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1563              * using Long-desciptor translation table format */
1564             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1565         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1566             /* In an implementation that includes the Security Extensions
1567              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1568              * Short-descriptor translation table format.
1569              */
1570             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1571         } else {
1572             value &= TTBCR_N;
1573         }
1574     }
1575
1576     /* Note that we always calculate c2_mask and c2_base_mask, but
1577      * they are only used for short-descriptor tables (ie if EAE is 0);
1578      * for long-descriptor tables the TTBCR fields are used differently
1579      * and the c2_mask and c2_base_mask values are meaningless.
1580      */
1581     raw_write(env, ri, value);
1582     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1583     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1584 }
1585
1586 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1587                              uint64_t value)
1588 {
1589     ARMCPU *cpu = arm_env_get_cpu(env);
1590
1591     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1592         /* With LPAE the TTBCR could result in a change of ASID
1593          * via the TTBCR.A1 bit, so do a TLB flush.
1594          */
1595         tlb_flush(CPU(cpu), 1);
1596     }
1597     vmsa_ttbcr_raw_write(env, ri, value);
1598 }
1599
1600 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1601 {
1602     env->cp15.c2_base_mask = 0xffffc000u;
1603     raw_write(env, ri, 0);
1604     env->cp15.c2_mask = 0;
1605 }
1606
1607 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1608                                uint64_t value)
1609 {
1610     ARMCPU *cpu = arm_env_get_cpu(env);
1611
1612     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1613     tlb_flush(CPU(cpu), 1);
1614     raw_write(env, ri, value);
1615 }
1616
1617 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1618                             uint64_t value)
1619 {
1620     /* 64 bit accesses to the TTBRs can change the ASID and so we
1621      * must flush the TLB.
1622      */
1623     if (cpreg_field_is_64bit(ri)) {
1624         ARMCPU *cpu = arm_env_get_cpu(env);
1625
1626         tlb_flush(CPU(cpu), 1);
1627     }
1628     raw_write(env, ri, value);
1629 }
1630
1631 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1632     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1633       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1634       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1635       .resetfn = arm_cp_reset_ignore, },
1636     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1637       .access = PL1_RW,
1638       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1639     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1640       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1641       .access = PL1_RW,
1642       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1643     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1644       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1645       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1646       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1647     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1648       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1649       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1650       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1651     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1652       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1653       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1654       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1655       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1656     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1657       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1658       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1659       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1660     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1661     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1662       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1663       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1664       .resetvalue = 0, },
1665     REGINFO_SENTINEL
1666 };
1667
1668 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1669                                 uint64_t value)
1670 {
1671     env->cp15.c15_ticonfig = value & 0xe7;
1672     /* The OS_TYPE bit in this register changes the reported CPUID! */
1673     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1674         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1675 }
1676
1677 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1678                                 uint64_t value)
1679 {
1680     env->cp15.c15_threadid = value & 0xffff;
1681 }
1682
1683 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1684                            uint64_t value)
1685 {
1686     /* Wait-for-interrupt (deprecated) */
1687     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1688 }
1689
1690 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1691                                   uint64_t value)
1692 {
1693     /* On OMAP there are registers indicating the max/min index of dcache lines
1694      * containing a dirty line; cache flush operations have to reset these.
1695      */
1696     env->cp15.c15_i_max = 0x000;
1697     env->cp15.c15_i_min = 0xff0;
1698 }
1699
1700 static const ARMCPRegInfo omap_cp_reginfo[] = {
1701     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1702       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1703       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1704       .resetvalue = 0, },
1705     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1706       .access = PL1_RW, .type = ARM_CP_NOP },
1707     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1708       .access = PL1_RW,
1709       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1710       .writefn = omap_ticonfig_write },
1711     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1712       .access = PL1_RW,
1713       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1714     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1715       .access = PL1_RW, .resetvalue = 0xff0,
1716       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1717     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1718       .access = PL1_RW,
1719       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1720       .writefn = omap_threadid_write },
1721     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1722       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1723       .type = ARM_CP_NO_MIGRATE,
1724       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1725     /* TODO: Peripheral port remap register:
1726      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1727      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1728      * when MMU is off.
1729      */
1730     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1731       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1732       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1733       .writefn = omap_cachemaint_write },
1734     { .name = "C9", .cp = 15, .crn = 9,
1735       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1736       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1737     REGINFO_SENTINEL
1738 };
1739
1740 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1741                               uint64_t value)
1742 {
1743     env->cp15.c15_cpar = value & 0x3fff;
1744 }
1745
1746 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1747     { .name = "XSCALE_CPAR",
1748       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1749       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1750       .writefn = xscale_cpar_write, },
1751     { .name = "XSCALE_AUXCR",
1752       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1753       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1754       .resetvalue = 0, },
1755     /* XScale specific cache-lockdown: since we have no cache we NOP these
1756      * and hope the guest does not really rely on cache behaviour.
1757      */
1758     { .name = "XSCALE_LOCK_ICACHE_LINE",
1759       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1760       .access = PL1_W, .type = ARM_CP_NOP },
1761     { .name = "XSCALE_UNLOCK_ICACHE",
1762       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1763       .access = PL1_W, .type = ARM_CP_NOP },
1764     { .name = "XSCALE_DCACHE_LOCK",
1765       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1766       .access = PL1_RW, .type = ARM_CP_NOP },
1767     { .name = "XSCALE_UNLOCK_DCACHE",
1768       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1769       .access = PL1_W, .type = ARM_CP_NOP },
1770     REGINFO_SENTINEL
1771 };
1772
1773 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1774     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1775      * implementation of this implementation-defined space.
1776      * Ideally this should eventually disappear in favour of actually
1777      * implementing the correct behaviour for all cores.
1778      */
1779     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1780       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1781       .access = PL1_RW,
1782       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1783       .resetvalue = 0 },
1784     REGINFO_SENTINEL
1785 };
1786
1787 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1788     /* Cache status: RAZ because we have no cache so it's always clean */
1789     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1790       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1791       .resetvalue = 0 },
1792     REGINFO_SENTINEL
1793 };
1794
1795 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1796     /* We never have a a block transfer operation in progress */
1797     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1798       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1799       .resetvalue = 0 },
1800     /* The cache ops themselves: these all NOP for QEMU */
1801     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1802       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1803     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1804       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1805     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1806       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1807     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1808       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1809     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1810       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1811     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1812       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1813     REGINFO_SENTINEL
1814 };
1815
1816 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1817     /* The cache test-and-clean instructions always return (1 << 30)
1818      * to indicate that there are no dirty cache lines.
1819      */
1820     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1821       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1822       .resetvalue = (1 << 30) },
1823     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1824       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1825       .resetvalue = (1 << 30) },
1826     REGINFO_SENTINEL
1827 };
1828
1829 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1830     /* Ignore ReadBuffer accesses */
1831     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1832       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1833       .access = PL1_RW, .resetvalue = 0,
1834       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1835     REGINFO_SENTINEL
1836 };
1837
1838 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1839 {
1840     CPUState *cs = CPU(arm_env_get_cpu(env));
1841     uint32_t mpidr = cs->cpu_index;
1842     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1843      * in later ARM ARM versions), or any of the higher affinity level fields,
1844      * so these bits always RAZ.
1845      */
1846     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1847         mpidr |= (1U << 31);
1848         /* Cores which are uniprocessor (non-coherent)
1849          * but still implement the MP extensions set
1850          * bit 30. (For instance, A9UP.) However we do
1851          * not currently model any of those cores.
1852          */
1853     }
1854     return mpidr;
1855 }
1856
1857 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1858     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1859       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1860       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1861     REGINFO_SENTINEL
1862 };
1863
1864 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1865     /* NOP AMAIR0/1: the override is because these clash with the rather
1866      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1867      */
1868     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1869       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1870       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1871       .resetvalue = 0 },
1872     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1873     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1874       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1875       .resetvalue = 0 },
1876     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1877       .access = PL1_RW, .type = ARM_CP_64BIT,
1878       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1879     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1880       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1881       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1882       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1883     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1884       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1885       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1886       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1887     REGINFO_SENTINEL
1888 };
1889
1890 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1891 {
1892     return vfp_get_fpcr(env);
1893 }
1894
1895 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1896                             uint64_t value)
1897 {
1898     vfp_set_fpcr(env, value);
1899 }
1900
1901 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1902 {
1903     return vfp_get_fpsr(env);
1904 }
1905
1906 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1907                             uint64_t value)
1908 {
1909     vfp_set_fpsr(env, value);
1910 }
1911
1912 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1913 {
1914     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1915         return CP_ACCESS_TRAP;
1916     }
1917     return CP_ACCESS_OK;
1918 }
1919
1920 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1921                             uint64_t value)
1922 {
1923     env->daif = value & PSTATE_DAIF;
1924 }
1925
1926 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1927                                           const ARMCPRegInfo *ri)
1928 {
1929     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1930      * SCTLR_EL1.UCI is set.
1931      */
1932     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1933         return CP_ACCESS_TRAP;
1934     }
1935     return CP_ACCESS_OK;
1936 }
1937
1938 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1939  * Page D4-1736 (DDI0487A.b)
1940  */
1941
1942 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1943                                uint64_t value)
1944 {
1945     /* Invalidate by VA (AArch64 version) */
1946     ARMCPU *cpu = arm_env_get_cpu(env);
1947     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1948
1949     tlb_flush_page(CPU(cpu), pageaddr);
1950 }
1951
1952 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1953                                 uint64_t value)
1954 {
1955     /* Invalidate by VA, all ASIDs (AArch64 version) */
1956     ARMCPU *cpu = arm_env_get_cpu(env);
1957     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1958
1959     tlb_flush_page(CPU(cpu), pageaddr);
1960 }
1961
1962 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1963                                  uint64_t value)
1964 {
1965     /* Invalidate by ASID (AArch64 version) */
1966     ARMCPU *cpu = arm_env_get_cpu(env);
1967     int asid = extract64(value, 48, 16);
1968     tlb_flush(CPU(cpu), asid == 0);
1969 }
1970
1971 static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
1972                                   uint64_t value)
1973 {
1974     CPUState *other_cs;
1975     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1976
1977     CPU_FOREACH(other_cs) {
1978         tlb_flush_page(other_cs, pageaddr);
1979     }
1980 }
1981
1982 static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
1983                                   uint64_t value)
1984 {
1985     CPUState *other_cs;
1986     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1987
1988     CPU_FOREACH(other_cs) {
1989         tlb_flush_page(other_cs, pageaddr);
1990     }
1991 }
1992
1993 static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
1994                                   uint64_t value)
1995 {
1996     CPUState *other_cs;
1997     int asid = extract64(value, 48, 16);
1998
1999     CPU_FOREACH(other_cs) {
2000         tlb_flush(other_cs, asid == 0);
2001     }
2002 }
2003
2004 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2005 {
2006     /* We don't implement EL2, so the only control on DC ZVA is the
2007      * bit in the SCTLR which can prohibit access for EL0.
2008      */
2009     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
2010         return CP_ACCESS_TRAP;
2011     }
2012     return CP_ACCESS_OK;
2013 }
2014
2015 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2016 {
2017     ARMCPU *cpu = arm_env_get_cpu(env);
2018     int dzp_bit = 1 << 4;
2019
2020     /* DZP indicates whether DC ZVA access is allowed */
2021     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
2022         dzp_bit = 0;
2023     }
2024     return cpu->dcz_blocksize | dzp_bit;
2025 }
2026
2027 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2028 {
2029     if (!(env->pstate & PSTATE_SP)) {
2030         /* Access to SP_EL0 is undefined if it's being used as
2031          * the stack pointer.
2032          */
2033         return CP_ACCESS_TRAP_UNCATEGORIZED;
2034     }
2035     return CP_ACCESS_OK;
2036 }
2037
2038 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2039 {
2040     return env->pstate & PSTATE_SP;
2041 }
2042
2043 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2044 {
2045     update_spsel(env, val);
2046 }
2047
2048 static const ARMCPRegInfo v8_cp_reginfo[] = {
2049     /* Minimal set of EL0-visible registers. This will need to be expanded
2050      * significantly for system emulation of AArch64 CPUs.
2051      */
2052     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2053       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2054       .access = PL0_RW, .type = ARM_CP_NZCV },
2055     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2056       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2057       .type = ARM_CP_NO_MIGRATE,
2058       .access = PL0_RW, .accessfn = aa64_daif_access,
2059       .fieldoffset = offsetof(CPUARMState, daif),
2060       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2061     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2062       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2063       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2064     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2065       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2066       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2067     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2068       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2069       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
2070       .readfn = aa64_dczid_read },
2071     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2072       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2073       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2074 #ifndef CONFIG_USER_ONLY
2075       /* Avoid overhead of an access check that always passes in user-mode */
2076       .accessfn = aa64_zva_access,
2077 #endif
2078     },
2079     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2080       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2081       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2082     /* Cache ops: all NOPs since we don't emulate caches */
2083     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2084       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2085       .access = PL1_W, .type = ARM_CP_NOP },
2086     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2087       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2088       .access = PL1_W, .type = ARM_CP_NOP },
2089     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2090       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2091       .access = PL0_W, .type = ARM_CP_NOP,
2092       .accessfn = aa64_cacheop_access },
2093     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2094       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2095       .access = PL1_W, .type = ARM_CP_NOP },
2096     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2097       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2098       .access = PL1_W, .type = ARM_CP_NOP },
2099     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2100       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2101       .access = PL0_W, .type = ARM_CP_NOP,
2102       .accessfn = aa64_cacheop_access },
2103     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2104       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2105       .access = PL1_W, .type = ARM_CP_NOP },
2106     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2107       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2108       .access = PL0_W, .type = ARM_CP_NOP,
2109       .accessfn = aa64_cacheop_access },
2110     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2111       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2112       .access = PL0_W, .type = ARM_CP_NOP,
2113       .accessfn = aa64_cacheop_access },
2114     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2115       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2116       .access = PL1_W, .type = ARM_CP_NOP },
2117     /* TLBI operations */
2118     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2119       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2120       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2121       .writefn = tlbiall_is_write },
2122     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2123       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2124       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2125       .writefn = tlbi_aa64_va_is_write },
2126     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2127       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2128       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2129       .writefn = tlbi_aa64_asid_is_write },
2130     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2131       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2132       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2133       .writefn = tlbi_aa64_vaa_is_write },
2134     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2135       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2136       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2137       .writefn = tlbi_aa64_va_is_write },
2138     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2139       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2140       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2141       .writefn = tlbi_aa64_vaa_is_write },
2142     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2143       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2144       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2145       .writefn = tlbiall_write },
2146     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2147       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2148       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2149       .writefn = tlbi_aa64_va_write },
2150     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2151       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2152       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2153       .writefn = tlbi_aa64_asid_write },
2154     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2155       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2156       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2157       .writefn = tlbi_aa64_vaa_write },
2158     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2159       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2160       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2161       .writefn = tlbi_aa64_va_write },
2162     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2163       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2164       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2165       .writefn = tlbi_aa64_vaa_write },
2166 #ifndef CONFIG_USER_ONLY
2167     /* 64 bit address translation operations */
2168     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2169       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2170       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2171     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2172       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2173       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2174     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2175       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2176       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2177     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2178       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2179       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2180 #endif
2181     /* TLB invalidate last level of translation table walk */
2182     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2183       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
2184     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2185       .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
2186       .writefn = tlbimvaa_is_write },
2187     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2188       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2189     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2190       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2191     /* 32 bit cache operations */
2192     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2193       .type = ARM_CP_NOP, .access = PL1_W },
2194     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2195       .type = ARM_CP_NOP, .access = PL1_W },
2196     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2197       .type = ARM_CP_NOP, .access = PL1_W },
2198     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2199       .type = ARM_CP_NOP, .access = PL1_W },
2200     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2201       .type = ARM_CP_NOP, .access = PL1_W },
2202     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2203       .type = ARM_CP_NOP, .access = PL1_W },
2204     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2205       .type = ARM_CP_NOP, .access = PL1_W },
2206     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2207       .type = ARM_CP_NOP, .access = PL1_W },
2208     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2209       .type = ARM_CP_NOP, .access = PL1_W },
2210     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2211       .type = ARM_CP_NOP, .access = PL1_W },
2212     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2213       .type = ARM_CP_NOP, .access = PL1_W },
2214     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2215       .type = ARM_CP_NOP, .access = PL1_W },
2216     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2217       .type = ARM_CP_NOP, .access = PL1_W },
2218     /* MMU Domain access control / MPU write buffer control */
2219     { .name = "DACR", .cp = 15,
2220       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2221       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2222       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2223     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2224       .type = ARM_CP_NO_MIGRATE,
2225       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2226       .access = PL1_RW,
2227       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2228     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2229       .type = ARM_CP_NO_MIGRATE,
2230       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2231       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2232     /* We rely on the access checks not allowing the guest to write to the
2233      * state field when SPSel indicates that it's being used as the stack
2234      * pointer.
2235      */
2236     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2237       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2238       .access = PL1_RW, .accessfn = sp_el0_access,
2239       .type = ARM_CP_NO_MIGRATE,
2240       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2241     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2242       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2243       .type = ARM_CP_NO_MIGRATE,
2244       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2245     REGINFO_SENTINEL
2246 };
2247
2248 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2249 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2250     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2251       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2252       .access = PL2_RW,
2253       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2254     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2255       .type = ARM_CP_NO_MIGRATE,
2256       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2257       .access = PL2_RW,
2258       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2259     REGINFO_SENTINEL
2260 };
2261
2262 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2263 {
2264     ARMCPU *cpu = arm_env_get_cpu(env);
2265     uint64_t valid_mask = HCR_MASK;
2266
2267     if (arm_feature(env, ARM_FEATURE_EL3)) {
2268         valid_mask &= ~HCR_HCD;
2269     } else {
2270         valid_mask &= ~HCR_TSC;
2271     }
2272
2273     /* Clear RES0 bits.  */
2274     value &= valid_mask;
2275
2276     /* These bits change the MMU setup:
2277      * HCR_VM enables stage 2 translation
2278      * HCR_PTW forbids certain page-table setups
2279      * HCR_DC Disables stage1 and enables stage2 translation
2280      */
2281     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
2282         tlb_flush(CPU(cpu), 1);
2283     }
2284     raw_write(env, ri, value);
2285 }
2286
2287 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2288     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2289       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2290       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
2291       .writefn = hcr_write },
2292     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2293       .type = ARM_CP_NO_MIGRATE,
2294       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2295       .access = PL2_RW,
2296       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2297     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2298       .type = ARM_CP_NO_MIGRATE,
2299       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2300       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2301     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2302       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2303       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2304     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2305       .type = ARM_CP_NO_MIGRATE,
2306       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2307       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2308     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2309       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2310       .access = PL2_RW, .writefn = vbar_write,
2311       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2312       .resetvalue = 0 },
2313     REGINFO_SENTINEL
2314 };
2315
2316 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2317     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2318       .type = ARM_CP_NO_MIGRATE,
2319       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2320       .access = PL3_RW,
2321       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2322     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2323       .type = ARM_CP_NO_MIGRATE,
2324       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2325       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2326     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2327       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2328       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2329     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2330       .type = ARM_CP_NO_MIGRATE,
2331       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2332       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2333     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2334       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2335       .access = PL3_RW, .writefn = vbar_write,
2336       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2337       .resetvalue = 0 },
2338     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
2339       .type = ARM_CP_NO_MIGRATE,
2340       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
2341       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
2342       .writefn = scr_write },
2343     REGINFO_SENTINEL
2344 };
2345
2346 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2347                         uint64_t value)
2348 {
2349     ARMCPU *cpu = arm_env_get_cpu(env);
2350
2351     if (raw_read(env, ri) == value) {
2352         /* Skip the TLB flush if nothing actually changed; Linux likes
2353          * to do a lot of pointless SCTLR writes.
2354          */
2355         return;
2356     }
2357
2358     raw_write(env, ri, value);
2359     /* ??? Lots of these bits are not implemented.  */
2360     /* This may enable/disable the MMU, so do a TLB flush.  */
2361     tlb_flush(CPU(cpu), 1);
2362 }
2363
2364 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2365 {
2366     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2367      * but the AArch32 CTR has its own reginfo struct)
2368      */
2369     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2370         return CP_ACCESS_TRAP;
2371     }
2372     return CP_ACCESS_OK;
2373 }
2374
2375 static const ARMCPRegInfo debug_cp_reginfo[] = {
2376     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2377      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2378      * unlike DBGDRAR it is never accessible from EL0.
2379      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2380      * accessor.
2381      */
2382     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2383       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2384     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2385       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2386       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2387     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2388       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2389     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2390     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2391       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2392       .access = PL1_RW,
2393       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2394       .resetvalue = 0 },
2395     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2396      * We don't implement the configurable EL0 access.
2397      */
2398     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
2399       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2400       .type = ARM_CP_NO_MIGRATE,
2401       .access = PL1_R,
2402       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2403       .resetfn = arm_cp_reset_ignore },
2404     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2405     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2406       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2407       .access = PL1_W, .type = ARM_CP_NOP },
2408     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2409     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
2410       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
2411       .access = PL1_RW, .type = ARM_CP_NOP },
2412     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2413      * implement vector catch debug events yet.
2414      */
2415     { .name = "DBGVCR",
2416       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2417       .access = PL1_RW, .type = ARM_CP_NOP },
2418     REGINFO_SENTINEL
2419 };
2420
2421 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2422     /* 64 bit access versions of the (dummy) debug registers */
2423     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2424       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2425     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2426       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2427     REGINFO_SENTINEL
2428 };
2429
2430 void hw_watchpoint_update(ARMCPU *cpu, int n)
2431 {
2432     CPUARMState *env = &cpu->env;
2433     vaddr len = 0;
2434     vaddr wvr = env->cp15.dbgwvr[n];
2435     uint64_t wcr = env->cp15.dbgwcr[n];
2436     int mask;
2437     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
2438
2439     if (env->cpu_watchpoint[n]) {
2440         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
2441         env->cpu_watchpoint[n] = NULL;
2442     }
2443
2444     if (!extract64(wcr, 0, 1)) {
2445         /* E bit clear : watchpoint disabled */
2446         return;
2447     }
2448
2449     switch (extract64(wcr, 3, 2)) {
2450     case 0:
2451         /* LSC 00 is reserved and must behave as if the wp is disabled */
2452         return;
2453     case 1:
2454         flags |= BP_MEM_READ;
2455         break;
2456     case 2:
2457         flags |= BP_MEM_WRITE;
2458         break;
2459     case 3:
2460         flags |= BP_MEM_ACCESS;
2461         break;
2462     }
2463
2464     /* Attempts to use both MASK and BAS fields simultaneously are
2465      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2466      * thus generating a watchpoint for every byte in the masked region.
2467      */
2468     mask = extract64(wcr, 24, 4);
2469     if (mask == 1 || mask == 2) {
2470         /* Reserved values of MASK; we must act as if the mask value was
2471          * some non-reserved value, or as if the watchpoint were disabled.
2472          * We choose the latter.
2473          */
2474         return;
2475     } else if (mask) {
2476         /* Watchpoint covers an aligned area up to 2GB in size */
2477         len = 1ULL << mask;
2478         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2479          * whether the watchpoint fires when the unmasked bits match; we opt
2480          * to generate the exceptions.
2481          */
2482         wvr &= ~(len - 1);
2483     } else {
2484         /* Watchpoint covers bytes defined by the byte address select bits */
2485         int bas = extract64(wcr, 5, 8);
2486         int basstart;
2487
2488         if (bas == 0) {
2489             /* This must act as if the watchpoint is disabled */
2490             return;
2491         }
2492
2493         if (extract64(wvr, 2, 1)) {
2494             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2495              * ignored, and BAS[3:0] define which bytes to watch.
2496              */
2497             bas &= 0xf;
2498         }
2499         /* The BAS bits are supposed to be programmed to indicate a contiguous
2500          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2501          * we fire for each byte in the word/doubleword addressed by the WVR.
2502          * We choose to ignore any non-zero bits after the first range of 1s.
2503          */
2504         basstart = ctz32(bas);
2505         len = cto32(bas >> basstart);
2506         wvr += basstart;
2507     }
2508
2509     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
2510                           &env->cpu_watchpoint[n]);
2511 }
2512
2513 void hw_watchpoint_update_all(ARMCPU *cpu)
2514 {
2515     int i;
2516     CPUARMState *env = &cpu->env;
2517
2518     /* Completely clear out existing QEMU watchpoints and our array, to
2519      * avoid possible stale entries following migration load.
2520      */
2521     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
2522     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
2523
2524     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
2525         hw_watchpoint_update(cpu, i);
2526     }
2527 }
2528
2529 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2530                          uint64_t value)
2531 {
2532     ARMCPU *cpu = arm_env_get_cpu(env);
2533     int i = ri->crm;
2534
2535     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2536      * register reads and behaves as if values written are sign extended.
2537      * Bits [1:0] are RES0.
2538      */
2539     value = sextract64(value, 0, 49) & ~3ULL;
2540
2541     raw_write(env, ri, value);
2542     hw_watchpoint_update(cpu, i);
2543 }
2544
2545 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2546                          uint64_t value)
2547 {
2548     ARMCPU *cpu = arm_env_get_cpu(env);
2549     int i = ri->crm;
2550
2551     raw_write(env, ri, value);
2552     hw_watchpoint_update(cpu, i);
2553 }
2554
2555 void hw_breakpoint_update(ARMCPU *cpu, int n)
2556 {
2557     CPUARMState *env = &cpu->env;
2558     uint64_t bvr = env->cp15.dbgbvr[n];
2559     uint64_t bcr = env->cp15.dbgbcr[n];
2560     vaddr addr;
2561     int bt;
2562     int flags = BP_CPU;
2563
2564     if (env->cpu_breakpoint[n]) {
2565         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
2566         env->cpu_breakpoint[n] = NULL;
2567     }
2568
2569     if (!extract64(bcr, 0, 1)) {
2570         /* E bit clear : watchpoint disabled */
2571         return;
2572     }
2573
2574     bt = extract64(bcr, 20, 4);
2575
2576     switch (bt) {
2577     case 4: /* unlinked address mismatch (reserved if AArch64) */
2578     case 5: /* linked address mismatch (reserved if AArch64) */
2579         qemu_log_mask(LOG_UNIMP,
2580                       "arm: address mismatch breakpoint types not implemented");
2581         return;
2582     case 0: /* unlinked address match */
2583     case 1: /* linked address match */
2584     {
2585         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2586          * we behave as if the register was sign extended. Bits [1:0] are
2587          * RES0. The BAS field is used to allow setting breakpoints on 16
2588          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2589          * a bp will fire if the addresses covered by the bp and the addresses
2590          * covered by the insn overlap but the insn doesn't start at the
2591          * start of the bp address range. We choose to require the insn and
2592          * the bp to have the same address. The constraints on writing to
2593          * BAS enforced in dbgbcr_write mean we have only four cases:
2594          *  0b0000  => no breakpoint
2595          *  0b0011  => breakpoint on addr
2596          *  0b1100  => breakpoint on addr + 2
2597          *  0b1111  => breakpoint on addr
2598          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2599          */
2600         int bas = extract64(bcr, 5, 4);
2601         addr = sextract64(bvr, 0, 49) & ~3ULL;
2602         if (bas == 0) {
2603             return;
2604         }
2605         if (bas == 0xc) {
2606             addr += 2;
2607         }
2608         break;
2609     }
2610     case 2: /* unlinked context ID match */
2611     case 8: /* unlinked VMID match (reserved if no EL2) */
2612     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2613         qemu_log_mask(LOG_UNIMP,
2614                       "arm: unlinked context breakpoint types not implemented");
2615         return;
2616     case 9: /* linked VMID match (reserved if no EL2) */
2617     case 11: /* linked context ID and VMID match (reserved if no EL2) */
2618     case 3: /* linked context ID match */
2619     default:
2620         /* We must generate no events for Linked context matches (unless
2621          * they are linked to by some other bp/wp, which is handled in
2622          * updates for the linking bp/wp). We choose to also generate no events
2623          * for reserved values.
2624          */
2625         return;
2626     }
2627
2628     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
2629 }
2630
2631 void hw_breakpoint_update_all(ARMCPU *cpu)
2632 {
2633     int i;
2634     CPUARMState *env = &cpu->env;
2635
2636     /* Completely clear out existing QEMU breakpoints and our array, to
2637      * avoid possible stale entries following migration load.
2638      */
2639     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
2640     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
2641
2642     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
2643         hw_breakpoint_update(cpu, i);
2644     }
2645 }
2646
2647 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2648                          uint64_t value)
2649 {
2650     ARMCPU *cpu = arm_env_get_cpu(env);
2651     int i = ri->crm;
2652
2653     raw_write(env, ri, value);
2654     hw_breakpoint_update(cpu, i);
2655 }
2656
2657 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2658                          uint64_t value)
2659 {
2660     ARMCPU *cpu = arm_env_get_cpu(env);
2661     int i = ri->crm;
2662
2663     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
2664      * copy of BAS[0].
2665      */
2666     value = deposit64(value, 6, 1, extract64(value, 5, 1));
2667     value = deposit64(value, 8, 1, extract64(value, 7, 1));
2668
2669     raw_write(env, ri, value);
2670     hw_breakpoint_update(cpu, i);
2671 }
2672
2673 static void define_debug_regs(ARMCPU *cpu)
2674 {
2675     /* Define v7 and v8 architectural debug registers.
2676      * These are just dummy implementations for now.
2677      */
2678     int i;
2679     int wrps, brps, ctx_cmps;
2680     ARMCPRegInfo dbgdidr = {
2681         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2682         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2683     };
2684
2685     /* Note that all these register fields hold "number of Xs minus 1". */
2686     brps = extract32(cpu->dbgdidr, 24, 4);
2687     wrps = extract32(cpu->dbgdidr, 28, 4);
2688     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
2689
2690     assert(ctx_cmps <= brps);
2691
2692     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2693      * of the debug registers such as number of breakpoints;
2694      * check that if they both exist then they agree.
2695      */
2696     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2697         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2698         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2699         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
2700     }
2701
2702     define_one_arm_cp_reg(cpu, &dbgdidr);
2703     define_arm_cp_regs(cpu, debug_cp_reginfo);
2704
2705     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2706         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2707     }
2708
2709     for (i = 0; i < brps + 1; i++) {
2710         ARMCPRegInfo dbgregs[] = {
2711             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2712               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2713               .access = PL1_RW,
2714               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
2715               .writefn = dbgbvr_write, .raw_writefn = raw_write
2716             },
2717             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2718               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2719               .access = PL1_RW,
2720               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
2721               .writefn = dbgbcr_write, .raw_writefn = raw_write
2722             },
2723             REGINFO_SENTINEL
2724         };
2725         define_arm_cp_regs(cpu, dbgregs);
2726     }
2727
2728     for (i = 0; i < wrps + 1; i++) {
2729         ARMCPRegInfo dbgregs[] = {
2730             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2731               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2732               .access = PL1_RW,
2733               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
2734               .writefn = dbgwvr_write, .raw_writefn = raw_write
2735             },
2736             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2737               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2738               .access = PL1_RW,
2739               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
2740               .writefn = dbgwcr_write, .raw_writefn = raw_write
2741             },
2742             REGINFO_SENTINEL
2743         };
2744         define_arm_cp_regs(cpu, dbgregs);
2745     }
2746 }
2747
2748 void register_cp_regs_for_features(ARMCPU *cpu)
2749 {
2750     /* Register all the coprocessor registers based on feature bits */
2751     CPUARMState *env = &cpu->env;
2752     if (arm_feature(env, ARM_FEATURE_M)) {
2753         /* M profile has no coprocessor registers */
2754         return;
2755     }
2756
2757     define_arm_cp_regs(cpu, cp_reginfo);
2758     if (!arm_feature(env, ARM_FEATURE_V8)) {
2759         /* Must go early as it is full of wildcards that may be
2760          * overridden by later definitions.
2761          */
2762         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2763     }
2764
2765     if (arm_feature(env, ARM_FEATURE_V6)) {
2766         /* The ID registers all have impdef reset values */
2767         ARMCPRegInfo v6_idregs[] = {
2768             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2769               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2770               .access = PL1_R, .type = ARM_CP_CONST,
2771               .resetvalue = cpu->id_pfr0 },
2772             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2773               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2774               .access = PL1_R, .type = ARM_CP_CONST,
2775               .resetvalue = cpu->id_pfr1 },
2776             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2777               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2778               .access = PL1_R, .type = ARM_CP_CONST,
2779               .resetvalue = cpu->id_dfr0 },
2780             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2781               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2782               .access = PL1_R, .type = ARM_CP_CONST,
2783               .resetvalue = cpu->id_afr0 },
2784             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2785               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2786               .access = PL1_R, .type = ARM_CP_CONST,
2787               .resetvalue = cpu->id_mmfr0 },
2788             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2789               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2790               .access = PL1_R, .type = ARM_CP_CONST,
2791               .resetvalue = cpu->id_mmfr1 },
2792             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2793               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2794               .access = PL1_R, .type = ARM_CP_CONST,
2795               .resetvalue = cpu->id_mmfr2 },
2796             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2797               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2798               .access = PL1_R, .type = ARM_CP_CONST,
2799               .resetvalue = cpu->id_mmfr3 },
2800             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2801               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2802               .access = PL1_R, .type = ARM_CP_CONST,
2803               .resetvalue = cpu->id_isar0 },
2804             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2805               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2806               .access = PL1_R, .type = ARM_CP_CONST,
2807               .resetvalue = cpu->id_isar1 },
2808             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2809               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2810               .access = PL1_R, .type = ARM_CP_CONST,
2811               .resetvalue = cpu->id_isar2 },
2812             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2813               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2814               .access = PL1_R, .type = ARM_CP_CONST,
2815               .resetvalue = cpu->id_isar3 },
2816             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2817               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2818               .access = PL1_R, .type = ARM_CP_CONST,
2819               .resetvalue = cpu->id_isar4 },
2820             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2821               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2822               .access = PL1_R, .type = ARM_CP_CONST,
2823               .resetvalue = cpu->id_isar5 },
2824             /* 6..7 are as yet unallocated and must RAZ */
2825             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2826               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2827               .resetvalue = 0 },
2828             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2829               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2830               .resetvalue = 0 },
2831             REGINFO_SENTINEL
2832         };
2833         define_arm_cp_regs(cpu, v6_idregs);
2834         define_arm_cp_regs(cpu, v6_cp_reginfo);
2835     } else {
2836         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2837     }
2838     if (arm_feature(env, ARM_FEATURE_V6K)) {
2839         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2840     }
2841     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2842         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
2843     }
2844     if (arm_feature(env, ARM_FEATURE_V7)) {
2845         /* v7 performance monitor control register: same implementor
2846          * field as main ID register, and we implement only the cycle
2847          * count register.
2848          */
2849 #ifndef CONFIG_USER_ONLY
2850         ARMCPRegInfo pmcr = {
2851             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2852             .access = PL0_RW,
2853             .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
2854             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
2855             .accessfn = pmreg_access, .writefn = pmcr_write,
2856             .raw_writefn = raw_write,
2857         };
2858         ARMCPRegInfo pmcr64 = {
2859             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
2860             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
2861             .access = PL0_RW, .accessfn = pmreg_access,
2862             .type = ARM_CP_IO,
2863             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2864             .resetvalue = cpu->midr & 0xff000000,
2865             .writefn = pmcr_write, .raw_writefn = raw_write,
2866         };
2867         define_one_arm_cp_reg(cpu, &pmcr);
2868         define_one_arm_cp_reg(cpu, &pmcr64);
2869 #endif
2870         ARMCPRegInfo clidr = {
2871             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2872             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2873             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2874         };
2875         define_one_arm_cp_reg(cpu, &clidr);
2876         define_arm_cp_regs(cpu, v7_cp_reginfo);
2877         define_debug_regs(cpu);
2878     } else {
2879         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2880     }
2881     if (arm_feature(env, ARM_FEATURE_V8)) {
2882         /* AArch64 ID registers, which all have impdef reset values */
2883         ARMCPRegInfo v8_idregs[] = {
2884             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2885               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2886               .access = PL1_R, .type = ARM_CP_CONST,
2887               .resetvalue = cpu->id_aa64pfr0 },
2888             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2889               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2890               .access = PL1_R, .type = ARM_CP_CONST,
2891               .resetvalue = cpu->id_aa64pfr1},
2892             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2893               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2894               .access = PL1_R, .type = ARM_CP_CONST,
2895               /* We mask out the PMUVer field, because we don't currently
2896                * implement the PMU. Not advertising it prevents the guest
2897                * from trying to use it and getting UNDEFs on registers we
2898                * don't implement.
2899                */
2900               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2901             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2902               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2903               .access = PL1_R, .type = ARM_CP_CONST,
2904               .resetvalue = cpu->id_aa64dfr1 },
2905             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2906               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2907               .access = PL1_R, .type = ARM_CP_CONST,
2908               .resetvalue = cpu->id_aa64afr0 },
2909             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2910               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2911               .access = PL1_R, .type = ARM_CP_CONST,
2912               .resetvalue = cpu->id_aa64afr1 },
2913             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2914               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2915               .access = PL1_R, .type = ARM_CP_CONST,
2916               .resetvalue = cpu->id_aa64isar0 },
2917             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2918               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2919               .access = PL1_R, .type = ARM_CP_CONST,
2920               .resetvalue = cpu->id_aa64isar1 },
2921             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2922               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2923               .access = PL1_R, .type = ARM_CP_CONST,
2924               .resetvalue = cpu->id_aa64mmfr0 },
2925             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2926               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2927               .access = PL1_R, .type = ARM_CP_CONST,
2928               .resetvalue = cpu->id_aa64mmfr1 },
2929             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2930               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2931               .access = PL1_R, .type = ARM_CP_CONST,
2932               .resetvalue = cpu->mvfr0 },
2933             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2934               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2935               .access = PL1_R, .type = ARM_CP_CONST,
2936               .resetvalue = cpu->mvfr1 },
2937             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2938               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2939               .access = PL1_R, .type = ARM_CP_CONST,
2940               .resetvalue = cpu->mvfr2 },
2941             REGINFO_SENTINEL
2942         };
2943         ARMCPRegInfo rvbar = {
2944             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2945             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2946             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2947         };
2948         define_one_arm_cp_reg(cpu, &rvbar);
2949         define_arm_cp_regs(cpu, v8_idregs);
2950         define_arm_cp_regs(cpu, v8_cp_reginfo);
2951     }
2952     if (arm_feature(env, ARM_FEATURE_EL2)) {
2953         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2954     } else {
2955         /* If EL2 is missing but higher ELs are enabled, we need to
2956          * register the no_el2 reginfos.
2957          */
2958         if (arm_feature(env, ARM_FEATURE_EL3)) {
2959             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2960         }
2961     }
2962     if (arm_feature(env, ARM_FEATURE_EL3)) {
2963         define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2964     }
2965     if (arm_feature(env, ARM_FEATURE_MPU)) {
2966         /* These are the MPU registers prior to PMSAv6. Any new
2967          * PMSA core later than the ARM946 will require that we
2968          * implement the PMSAv6 or PMSAv7 registers, which are
2969          * completely different.
2970          */
2971         assert(!arm_feature(env, ARM_FEATURE_V6));
2972         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2973     } else {
2974         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2975     }
2976     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2977         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2978     }
2979     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2980         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2981     }
2982     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2983         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2984     }
2985     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2986         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2987     }
2988     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2989         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2990     }
2991     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2992         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2993     }
2994     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2995         define_arm_cp_regs(cpu, omap_cp_reginfo);
2996     }
2997     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2998         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2999     }
3000     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3001         define_arm_cp_regs(cpu, xscale_cp_reginfo);
3002     }
3003     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
3004         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
3005     }
3006     if (arm_feature(env, ARM_FEATURE_LPAE)) {
3007         define_arm_cp_regs(cpu, lpae_cp_reginfo);
3008     }
3009     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3010      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3011      * be read-only (ie write causes UNDEF exception).
3012      */
3013     {
3014         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
3015             /* Pre-v8 MIDR space.
3016              * Note that the MIDR isn't a simple constant register because
3017              * of the TI925 behaviour where writes to another register can
3018              * cause the MIDR value to change.
3019              *
3020              * Unimplemented registers in the c15 0 0 0 space default to
3021              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3022              * and friends override accordingly.
3023              */
3024             { .name = "MIDR",
3025               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
3026               .access = PL1_R, .resetvalue = cpu->midr,
3027               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
3028               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
3029               .type = ARM_CP_OVERRIDE },
3030             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3031             { .name = "DUMMY",
3032               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
3033               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3034             { .name = "DUMMY",
3035               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
3036               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3037             { .name = "DUMMY",
3038               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
3039               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3040             { .name = "DUMMY",
3041               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
3042               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3043             { .name = "DUMMY",
3044               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
3045               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3046             REGINFO_SENTINEL
3047         };
3048         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
3049             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
3050              * variable-MIDR TI925 behaviour. Instead we have a single
3051              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
3052              */
3053             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
3054               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
3055               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3056             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
3057               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
3058               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3059             REGINFO_SENTINEL
3060         };
3061         ARMCPRegInfo id_cp_reginfo[] = {
3062             /* These are common to v8 and pre-v8 */
3063             { .name = "CTR",
3064               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
3065               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3066             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
3067               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
3068               .access = PL0_R, .accessfn = ctr_el0_access,
3069               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3070             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3071             { .name = "TCMTR",
3072               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
3073               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3074             { .name = "TLBTR",
3075               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
3076               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3077             REGINFO_SENTINEL
3078         };
3079         ARMCPRegInfo crn0_wi_reginfo = {
3080             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
3081             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
3082             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
3083         };
3084         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
3085             arm_feature(env, ARM_FEATURE_STRONGARM)) {
3086             ARMCPRegInfo *r;
3087             /* Register the blanket "writes ignored" value first to cover the
3088              * whole space. Then update the specific ID registers to allow write
3089              * access, so that they ignore writes rather than causing them to
3090              * UNDEF.
3091              */
3092             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
3093             for (r = id_pre_v8_midr_cp_reginfo;
3094                  r->type != ARM_CP_SENTINEL; r++) {
3095                 r->access = PL1_RW;
3096             }
3097             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
3098                 r->access = PL1_RW;
3099             }
3100         }
3101         if (arm_feature(env, ARM_FEATURE_V8)) {
3102             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
3103         } else {
3104             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
3105         }
3106         define_arm_cp_regs(cpu, id_cp_reginfo);
3107     }
3108
3109     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
3110         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
3111     }
3112
3113     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
3114         ARMCPRegInfo auxcr = {
3115             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
3116             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
3117             .access = PL1_RW, .type = ARM_CP_CONST,
3118             .resetvalue = cpu->reset_auxcr
3119         };
3120         define_one_arm_cp_reg(cpu, &auxcr);
3121     }
3122
3123     if (arm_feature(env, ARM_FEATURE_CBAR)) {
3124         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3125             /* 32 bit view is [31:18] 0...0 [43:32]. */
3126             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
3127                 | extract64(cpu->reset_cbar, 32, 12);
3128             ARMCPRegInfo cbar_reginfo[] = {
3129                 { .name = "CBAR",
3130                   .type = ARM_CP_CONST,
3131                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3132                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
3133                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
3134                   .type = ARM_CP_CONST,
3135                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
3136                   .access = PL1_R, .resetvalue = cbar32 },
3137                 REGINFO_SENTINEL
3138             };
3139             /* We don't implement a r/w 64 bit CBAR currently */
3140             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
3141             define_arm_cp_regs(cpu, cbar_reginfo);
3142         } else {
3143             ARMCPRegInfo cbar = {
3144                 .name = "CBAR",
3145                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3146                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
3147                 .fieldoffset = offsetof(CPUARMState,
3148                                         cp15.c15_config_base_address)
3149             };
3150             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
3151                 cbar.access = PL1_R;
3152                 cbar.fieldoffset = 0;
3153                 cbar.type = ARM_CP_CONST;
3154             }
3155             define_one_arm_cp_reg(cpu, &cbar);
3156         }
3157     }
3158
3159     /* Generic registers whose values depend on the implementation */
3160     {
3161         ARMCPRegInfo sctlr = {
3162             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
3163             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3164             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
3165             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
3166             .raw_writefn = raw_write,
3167         };
3168         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3169             /* Normally we would always end the TB on an SCTLR write, but Linux
3170              * arch/arm/mach-pxa/sleep.S expects two instructions following
3171              * an MMU enable to execute from cache.  Imitate this behaviour.
3172              */
3173             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
3174         }
3175         define_one_arm_cp_reg(cpu, &sctlr);
3176     }
3177 }
3178
3179 ARMCPU *cpu_arm_init(const char *cpu_model)
3180 {
3181     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
3182 }
3183
3184 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
3185 {
3186     CPUState *cs = CPU(cpu);
3187     CPUARMState *env = &cpu->env;
3188
3189     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3190         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
3191                                  aarch64_fpu_gdb_set_reg,
3192                                  34, "aarch64-fpu.xml", 0);
3193     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
3194         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3195                                  51, "arm-neon.xml", 0);
3196     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
3197         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3198                                  35, "arm-vfp3.xml", 0);
3199     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
3200         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3201                                  19, "arm-vfp.xml", 0);
3202     }
3203 }
3204
3205 /* Sort alphabetically by type name, except for "any". */
3206 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
3207 {
3208     ObjectClass *class_a = (ObjectClass *)a;
3209     ObjectClass *class_b = (ObjectClass *)b;
3210     const char *name_a, *name_b;
3211
3212     name_a = object_class_get_name(class_a);
3213     name_b = object_class_get_name(class_b);
3214     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
3215         return 1;
3216     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
3217         return -1;
3218     } else {
3219         return strcmp(name_a, name_b);
3220     }
3221 }
3222
3223 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
3224 {
3225     ObjectClass *oc = data;
3226     CPUListState *s = user_data;
3227     const char *typename;
3228     char *name;
3229
3230     typename = object_class_get_name(oc);
3231     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
3232     (*s->cpu_fprintf)(s->file, "  %s\n",
3233                       name);
3234     g_free(name);
3235 }
3236
3237 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3238 {
3239     CPUListState s = {
3240         .file = f,
3241         .cpu_fprintf = cpu_fprintf,
3242     };
3243     GSList *list;
3244
3245     list = object_class_get_list(TYPE_ARM_CPU, false);
3246     list = g_slist_sort(list, arm_cpu_list_compare);
3247     (*cpu_fprintf)(f, "Available CPUs:\n");
3248     g_slist_foreach(list, arm_cpu_list_entry, &s);
3249     g_slist_free(list);
3250 #ifdef CONFIG_KVM
3251     /* The 'host' CPU type is dynamically registered only if KVM is
3252      * enabled, so we have to special-case it here:
3253      */
3254     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
3255 #endif
3256 }
3257
3258 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
3259 {
3260     ObjectClass *oc = data;
3261     CpuDefinitionInfoList **cpu_list = user_data;
3262     CpuDefinitionInfoList *entry;
3263     CpuDefinitionInfo *info;
3264     const char *typename;
3265
3266     typename = object_class_get_name(oc);
3267     info = g_malloc0(sizeof(*info));
3268     info->name = g_strndup(typename,
3269                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
3270
3271     entry = g_malloc0(sizeof(*entry));
3272     entry->value = info;
3273     entry->next = *cpu_list;
3274     *cpu_list = entry;
3275 }
3276
3277 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
3278 {
3279     CpuDefinitionInfoList *cpu_list = NULL;
3280     GSList *list;
3281
3282     list = object_class_get_list(TYPE_ARM_CPU, false);
3283     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
3284     g_slist_free(list);
3285
3286     return cpu_list;
3287 }
3288
3289 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
3290                                    void *opaque, int state,
3291                                    int crm, int opc1, int opc2)
3292 {
3293     /* Private utility function for define_one_arm_cp_reg_with_opaque():
3294      * add a single reginfo struct to the hash table.
3295      */
3296     uint32_t *key = g_new(uint32_t, 1);
3297     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
3298     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
3299     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
3300         /* The AArch32 view of a shared register sees the lower 32 bits
3301          * of a 64 bit backing field. It is not migratable as the AArch64
3302          * view handles that. AArch64 also handles reset.
3303          * We assume it is a cp15 register if the .cp field is left unset.
3304          */
3305         if (r2->cp == 0) {
3306             r2->cp = 15;
3307         }
3308         r2->type |= ARM_CP_NO_MIGRATE;
3309         r2->resetfn = arm_cp_reset_ignore;
3310 #ifdef HOST_WORDS_BIGENDIAN
3311         if (r2->fieldoffset) {
3312             r2->fieldoffset += sizeof(uint32_t);
3313         }
3314 #endif
3315     }
3316     if (state == ARM_CP_STATE_AA64) {
3317         /* To allow abbreviation of ARMCPRegInfo
3318          * definitions, we treat cp == 0 as equivalent to
3319          * the value for "standard guest-visible sysreg".
3320          * STATE_BOTH definitions are also always "standard
3321          * sysreg" in their AArch64 view (the .cp value may
3322          * be non-zero for the benefit of the AArch32 view).
3323          */
3324         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
3325             r2->cp = CP_REG_ARM64_SYSREG_CP;
3326         }
3327         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
3328                                   r2->opc0, opc1, opc2);
3329     } else {
3330         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
3331     }
3332     if (opaque) {
3333         r2->opaque = opaque;
3334     }
3335     /* reginfo passed to helpers is correct for the actual access,
3336      * and is never ARM_CP_STATE_BOTH:
3337      */
3338     r2->state = state;
3339     /* Make sure reginfo passed to helpers for wildcarded regs
3340      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3341      */
3342     r2->crm = crm;
3343     r2->opc1 = opc1;
3344     r2->opc2 = opc2;
3345     /* By convention, for wildcarded registers only the first
3346      * entry is used for migration; the others are marked as
3347      * NO_MIGRATE so we don't try to transfer the register
3348      * multiple times. Special registers (ie NOP/WFI) are
3349      * never migratable.
3350      */
3351     if ((r->type & ARM_CP_SPECIAL) ||
3352         ((r->crm == CP_ANY) && crm != 0) ||
3353         ((r->opc1 == CP_ANY) && opc1 != 0) ||
3354         ((r->opc2 == CP_ANY) && opc2 != 0)) {
3355         r2->type |= ARM_CP_NO_MIGRATE;
3356     }
3357
3358     /* Overriding of an existing definition must be explicitly
3359      * requested.
3360      */
3361     if (!(r->type & ARM_CP_OVERRIDE)) {
3362         ARMCPRegInfo *oldreg;
3363         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
3364         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
3365             fprintf(stderr, "Register redefined: cp=%d %d bit "
3366                     "crn=%d crm=%d opc1=%d opc2=%d, "
3367                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
3368                     r2->crn, r2->crm, r2->opc1, r2->opc2,
3369                     oldreg->name, r2->name);
3370             g_assert_not_reached();
3371         }
3372     }
3373     g_hash_table_insert(cpu->cp_regs, key, r2);
3374 }
3375
3376
3377 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
3378                                        const ARMCPRegInfo *r, void *opaque)
3379 {
3380     /* Define implementations of coprocessor registers.
3381      * We store these in a hashtable because typically
3382      * there are less than 150 registers in a space which
3383      * is 16*16*16*8*8 = 262144 in size.
3384      * Wildcarding is supported for the crm, opc1 and opc2 fields.
3385      * If a register is defined twice then the second definition is
3386      * used, so this can be used to define some generic registers and
3387      * then override them with implementation specific variations.
3388      * At least one of the original and the second definition should
3389      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3390      * against accidental use.
3391      *
3392      * The state field defines whether the register is to be
3393      * visible in the AArch32 or AArch64 execution state. If the
3394      * state is set to ARM_CP_STATE_BOTH then we synthesise a
3395      * reginfo structure for the AArch32 view, which sees the lower
3396      * 32 bits of the 64 bit register.
3397      *
3398      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3399      * be wildcarded. AArch64 registers are always considered to be 64
3400      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3401      * the register, if any.
3402      */
3403     int crm, opc1, opc2, state;
3404     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
3405     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
3406     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3407     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3408     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3409     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3410     /* 64 bit registers have only CRm and Opc1 fields */
3411     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3412     /* op0 only exists in the AArch64 encodings */
3413     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3414     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3415     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3416     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3417      * encodes a minimum access level for the register. We roll this
3418      * runtime check into our general permission check code, so check
3419      * here that the reginfo's specified permissions are strict enough
3420      * to encompass the generic architectural permission check.
3421      */
3422     if (r->state != ARM_CP_STATE_AA32) {
3423         int mask = 0;
3424         switch (r->opc1) {
3425         case 0: case 1: case 2:
3426             /* min_EL EL1 */
3427             mask = PL1_RW;
3428             break;
3429         case 3:
3430             /* min_EL EL0 */
3431             mask = PL0_RW;
3432             break;
3433         case 4:
3434             /* min_EL EL2 */
3435             mask = PL2_RW;
3436             break;
3437         case 5:
3438             /* unallocated encoding, so not possible */
3439             assert(false);
3440             break;
3441         case 6:
3442             /* min_EL EL3 */
3443             mask = PL3_RW;
3444             break;
3445         case 7:
3446             /* min_EL EL1, secure mode only (we don't check the latter) */
3447             mask = PL1_RW;
3448             break;
3449         default:
3450             /* broken reginfo with out-of-range opc1 */
3451             assert(false);
3452             break;
3453         }
3454         /* assert our permissions are not too lax (stricter is fine) */
3455         assert((r->access & ~mask) == 0);
3456     }
3457
3458     /* Check that the register definition has enough info to handle
3459      * reads and writes if they are permitted.
3460      */
3461     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3462         if (r->access & PL3_R) {
3463             assert(r->fieldoffset || r->readfn);
3464         }
3465         if (r->access & PL3_W) {
3466             assert(r->fieldoffset || r->writefn);
3467         }
3468     }
3469     /* Bad type field probably means missing sentinel at end of reg list */
3470     assert(cptype_valid(r->type));
3471     for (crm = crmmin; crm <= crmmax; crm++) {
3472         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3473             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3474                 for (state = ARM_CP_STATE_AA32;
3475                      state <= ARM_CP_STATE_AA64; state++) {
3476                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3477                         continue;
3478                     }
3479                     add_cpreg_to_hashtable(cpu, r, opaque, state,
3480                                            crm, opc1, opc2);
3481                 }
3482             }
3483         }
3484     }
3485 }
3486
3487 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3488                                     const ARMCPRegInfo *regs, void *opaque)
3489 {
3490     /* Define a whole list of registers */
3491     const ARMCPRegInfo *r;
3492     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3493         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3494     }
3495 }
3496
3497 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3498 {
3499     return g_hash_table_lookup(cpregs, &encoded_cp);
3500 }
3501
3502 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3503                          uint64_t value)
3504 {
3505     /* Helper coprocessor write function for write-ignore registers */
3506 }
3507
3508 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3509 {
3510     /* Helper coprocessor write function for read-as-zero registers */
3511     return 0;
3512 }
3513
3514 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3515 {
3516     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3517 }
3518
3519 static int bad_mode_switch(CPUARMState *env, int mode)
3520 {
3521     /* Return true if it is not valid for us to switch to
3522      * this CPU mode (ie all the UNPREDICTABLE cases in
3523      * the ARM ARM CPSRWriteByInstr pseudocode).
3524      */
3525     switch (mode) {
3526     case ARM_CPU_MODE_USR:
3527     case ARM_CPU_MODE_SYS:
3528     case ARM_CPU_MODE_SVC:
3529     case ARM_CPU_MODE_ABT:
3530     case ARM_CPU_MODE_UND:
3531     case ARM_CPU_MODE_IRQ:
3532     case ARM_CPU_MODE_FIQ:
3533         return 0;
3534     default:
3535         return 1;
3536     }
3537 }
3538
3539 uint32_t cpsr_read(CPUARMState *env)
3540 {
3541     int ZF;
3542     ZF = (env->ZF == 0);
3543     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3544         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3545         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3546         | ((env->condexec_bits & 0xfc) << 8)
3547         | (env->GE << 16) | (env->daif & CPSR_AIF);
3548 }
3549
3550 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3551 {
3552     if (mask & CPSR_NZCV) {
3553         env->ZF = (~val) & CPSR_Z;
3554         env->NF = val;
3555         env->CF = (val >> 29) & 1;
3556         env->VF = (val << 3) & 0x80000000;
3557     }
3558     if (mask & CPSR_Q)
3559         env->QF = ((val & CPSR_Q) != 0);
3560     if (mask & CPSR_T)
3561         env->thumb = ((val & CPSR_T) != 0);
3562     if (mask & CPSR_IT_0_1) {
3563         env->condexec_bits &= ~3;
3564         env->condexec_bits |= (val >> 25) & 3;
3565     }
3566     if (mask & CPSR_IT_2_7) {
3567         env->condexec_bits &= 3;
3568         env->condexec_bits |= (val >> 8) & 0xfc;
3569     }
3570     if (mask & CPSR_GE) {
3571         env->GE = (val >> 16) & 0xf;
3572     }
3573
3574     env->daif &= ~(CPSR_AIF & mask);
3575     env->daif |= val & CPSR_AIF & mask;
3576
3577     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3578         if (bad_mode_switch(env, val & CPSR_M)) {
3579             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3580              * We choose to ignore the attempt and leave the CPSR M field
3581              * untouched.
3582              */
3583             mask &= ~CPSR_M;
3584         } else {
3585             switch_mode(env, val & CPSR_M);
3586         }
3587     }
3588     mask &= ~CACHED_CPSR_BITS;
3589     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3590 }
3591
3592 /* Sign/zero extend */
3593 uint32_t HELPER(sxtb16)(uint32_t x)
3594 {
3595     uint32_t res;
3596     res = (uint16_t)(int8_t)x;
3597     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3598     return res;
3599 }
3600
3601 uint32_t HELPER(uxtb16)(uint32_t x)
3602 {
3603     uint32_t res;
3604     res = (uint16_t)(uint8_t)x;
3605     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3606     return res;
3607 }
3608
3609 uint32_t HELPER(clz)(uint32_t x)
3610 {
3611     return clz32(x);
3612 }
3613
3614 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3615 {
3616     if (den == 0)
3617       return 0;
3618     if (num == INT_MIN && den == -1)
3619       return INT_MIN;
3620     return num / den;
3621 }
3622
3623 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3624 {
3625     if (den == 0)
3626       return 0;
3627     return num / den;
3628 }
3629
3630 uint32_t HELPER(rbit)(uint32_t x)
3631 {
3632     x =  ((x & 0xff000000) >> 24)
3633        | ((x & 0x00ff0000) >> 8)
3634        | ((x & 0x0000ff00) << 8)
3635        | ((x & 0x000000ff) << 24);
3636     x =  ((x & 0xf0f0f0f0) >> 4)
3637        | ((x & 0x0f0f0f0f) << 4);
3638     x =  ((x & 0x88888888) >> 3)
3639        | ((x & 0x44444444) >> 1)
3640        | ((x & 0x22222222) << 1)
3641        | ((x & 0x11111111) << 3);
3642     return x;
3643 }
3644
3645 #if defined(CONFIG_USER_ONLY)
3646
3647 void arm_cpu_do_interrupt(CPUState *cs)
3648 {
3649     cs->exception_index = -1;
3650 }
3651
3652 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3653                              int mmu_idx)
3654 {
3655     ARMCPU *cpu = ARM_CPU(cs);
3656     CPUARMState *env = &cpu->env;
3657
3658     env->exception.vaddress = address;
3659     if (rw == 2) {
3660         cs->exception_index = EXCP_PREFETCH_ABORT;
3661     } else {
3662         cs->exception_index = EXCP_DATA_ABORT;
3663     }
3664     return 1;
3665 }
3666
3667 /* These should probably raise undefined insn exceptions.  */
3668 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3669 {
3670     ARMCPU *cpu = arm_env_get_cpu(env);
3671
3672     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3673 }
3674
3675 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3676 {
3677     ARMCPU *cpu = arm_env_get_cpu(env);
3678
3679     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3680     return 0;
3681 }
3682
3683 void switch_mode(CPUARMState *env, int mode)
3684 {
3685     ARMCPU *cpu = arm_env_get_cpu(env);
3686
3687     if (mode != ARM_CPU_MODE_USR) {
3688         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3689     }
3690 }
3691
3692 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3693 {
3694     ARMCPU *cpu = arm_env_get_cpu(env);
3695
3696     cpu_abort(CPU(cpu), "banked r13 write\n");
3697 }
3698
3699 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3700 {
3701     ARMCPU *cpu = arm_env_get_cpu(env);
3702
3703     cpu_abort(CPU(cpu), "banked r13 read\n");
3704     return 0;
3705 }
3706
3707 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
3708 {
3709     return 1;
3710 }
3711
3712 #else
3713
3714 /* Map CPU modes onto saved register banks.  */
3715 int bank_number(int mode)
3716 {
3717     switch (mode) {
3718     case ARM_CPU_MODE_USR:
3719     case ARM_CPU_MODE_SYS:
3720         return 0;
3721     case ARM_CPU_MODE_SVC:
3722         return 1;
3723     case ARM_CPU_MODE_ABT:
3724         return 2;
3725     case ARM_CPU_MODE_UND:
3726         return 3;
3727     case ARM_CPU_MODE_IRQ:
3728         return 4;
3729     case ARM_CPU_MODE_FIQ:
3730         return 5;
3731     case ARM_CPU_MODE_HYP:
3732         return 6;
3733     case ARM_CPU_MODE_MON:
3734         return 7;
3735     }
3736     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3737 }
3738
3739 void switch_mode(CPUARMState *env, int mode)
3740 {
3741     int old_mode;
3742     int i;
3743
3744     old_mode = env->uncached_cpsr & CPSR_M;
3745     if (mode == old_mode)
3746         return;
3747
3748     if (old_mode == ARM_CPU_MODE_FIQ) {
3749         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3750         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3751     } else if (mode == ARM_CPU_MODE_FIQ) {
3752         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3753         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3754     }
3755
3756     i = bank_number(old_mode);
3757     env->banked_r13[i] = env->regs[13];
3758     env->banked_r14[i] = env->regs[14];
3759     env->banked_spsr[i] = env->spsr;
3760
3761     i = bank_number(mode);
3762     env->regs[13] = env->banked_r13[i];
3763     env->regs[14] = env->banked_r14[i];
3764     env->spsr = env->banked_spsr[i];
3765 }
3766
3767 /*
3768  * Determine the target EL for a given exception type.
3769  */
3770 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
3771 {
3772     ARMCPU *cpu = ARM_CPU(cs);
3773     CPUARMState *env = &cpu->env;
3774     unsigned int cur_el = arm_current_pl(env);
3775     unsigned int target_el;
3776     /* FIXME: Use actual secure state.  */
3777     bool secure = false;
3778
3779     if (!env->aarch64) {
3780         /* TODO: Add EL2 and 3 exception handling for AArch32.  */
3781         return 1;
3782     }
3783
3784     switch (excp_idx) {
3785     case EXCP_HVC:
3786     case EXCP_HYP_TRAP:
3787         target_el = 2;
3788         break;
3789     case EXCP_SMC:
3790         target_el = 3;
3791         break;
3792     case EXCP_FIQ:
3793     case EXCP_IRQ:
3794     {
3795         const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO;
3796         const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ;
3797
3798         target_el = 1;
3799         if (!secure && (env->cp15.hcr_el2 & hcr_mask)) {
3800             target_el = 2;
3801         }
3802         if (env->cp15.scr_el3 & scr_mask) {
3803             target_el = 3;
3804         }
3805         break;
3806     }
3807     case EXCP_VIRQ:
3808     case EXCP_VFIQ:
3809         target_el = 1;
3810         break;
3811     default:
3812         target_el = MAX(cur_el, 1);
3813         break;
3814     }
3815     return target_el;
3816 }
3817
3818 static void v7m_push(CPUARMState *env, uint32_t val)
3819 {
3820     CPUState *cs = CPU(arm_env_get_cpu(env));
3821
3822     env->regs[13] -= 4;
3823     stl_phys(cs->as, env->regs[13], val);
3824 }
3825
3826 static uint32_t v7m_pop(CPUARMState *env)
3827 {
3828     CPUState *cs = CPU(arm_env_get_cpu(env));
3829     uint32_t val;
3830
3831     val = ldl_phys(cs->as, env->regs[13]);
3832     env->regs[13] += 4;
3833     return val;
3834 }
3835
3836 /* Switch to V7M main or process stack pointer.  */
3837 static void switch_v7m_sp(CPUARMState *env, int process)
3838 {
3839     uint32_t tmp;
3840     if (env->v7m.current_sp != process) {
3841         tmp = env->v7m.other_sp;
3842         env->v7m.other_sp = env->regs[13];
3843         env->regs[13] = tmp;
3844         env->v7m.current_sp = process;
3845     }
3846 }
3847
3848 static void do_v7m_exception_exit(CPUARMState *env)
3849 {
3850     uint32_t type;
3851     uint32_t xpsr;
3852
3853     type = env->regs[15];
3854     if (env->v7m.exception != 0)
3855         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3856
3857     /* Switch to the target stack.  */
3858     switch_v7m_sp(env, (type & 4) != 0);
3859     /* Pop registers.  */
3860     env->regs[0] = v7m_pop(env);
3861     env->regs[1] = v7m_pop(env);
3862     env->regs[2] = v7m_pop(env);
3863     env->regs[3] = v7m_pop(env);
3864     env->regs[12] = v7m_pop(env);
3865     env->regs[14] = v7m_pop(env);
3866     env->regs[15] = v7m_pop(env);
3867     xpsr = v7m_pop(env);
3868     xpsr_write(env, xpsr, 0xfffffdff);
3869     /* Undo stack alignment.  */
3870     if (xpsr & 0x200)
3871         env->regs[13] |= 4;
3872     /* ??? The exception return type specifies Thread/Handler mode.  However
3873        this is also implied by the xPSR value. Not sure what to do
3874        if there is a mismatch.  */
3875     /* ??? Likewise for mismatches between the CONTROL register and the stack
3876        pointer.  */
3877 }
3878
3879 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3880 {
3881     ARMCPU *cpu = ARM_CPU(cs);
3882     CPUARMState *env = &cpu->env;
3883     uint32_t xpsr = xpsr_read(env);
3884     uint32_t lr;
3885     uint32_t addr;
3886
3887     arm_log_exception(cs->exception_index);
3888
3889     lr = 0xfffffff1;
3890     if (env->v7m.current_sp)
3891         lr |= 4;
3892     if (env->v7m.exception == 0)
3893         lr |= 8;
3894
3895     /* For exceptions we just mark as pending on the NVIC, and let that
3896        handle it.  */
3897     /* TODO: Need to escalate if the current priority is higher than the
3898        one we're raising.  */
3899     switch (cs->exception_index) {
3900     case EXCP_UDEF:
3901         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3902         return;
3903     case EXCP_SWI:
3904         /* The PC already points to the next instruction.  */
3905         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3906         return;
3907     case EXCP_PREFETCH_ABORT:
3908     case EXCP_DATA_ABORT:
3909         /* TODO: if we implemented the MPU registers, this is where we
3910          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3911          */
3912         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3913         return;
3914     case EXCP_BKPT:
3915         if (semihosting_enabled) {
3916             int nr;
3917             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3918             if (nr == 0xab) {
3919                 env->regs[15] += 2;
3920                 env->regs[0] = do_arm_semihosting(env);
3921                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3922                 return;
3923             }
3924         }
3925         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3926         return;
3927     case EXCP_IRQ:
3928         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3929         break;
3930     case EXCP_EXCEPTION_EXIT:
3931         do_v7m_exception_exit(env);
3932         return;
3933     default:
3934         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3935         return; /* Never happens.  Keep compiler happy.  */
3936     }
3937
3938     /* Align stack pointer.  */
3939     /* ??? Should only do this if Configuration Control Register
3940        STACKALIGN bit is set.  */
3941     if (env->regs[13] & 4) {
3942         env->regs[13] -= 4;
3943         xpsr |= 0x200;
3944     }
3945     /* Switch to the handler mode.  */
3946     v7m_push(env, xpsr);
3947     v7m_push(env, env->regs[15]);
3948     v7m_push(env, env->regs[14]);
3949     v7m_push(env, env->regs[12]);
3950     v7m_push(env, env->regs[3]);
3951     v7m_push(env, env->regs[2]);
3952     v7m_push(env, env->regs[1]);
3953     v7m_push(env, env->regs[0]);
3954     switch_v7m_sp(env, 0);
3955     /* Clear IT bits */
3956     env->condexec_bits = 0;
3957     env->regs[14] = lr;
3958     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3959     env->regs[15] = addr & 0xfffffffe;
3960     env->thumb = addr & 1;
3961 }
3962
3963 /* Handle a CPU exception.  */
3964 void arm_cpu_do_interrupt(CPUState *cs)
3965 {
3966     ARMCPU *cpu = ARM_CPU(cs);
3967     CPUARMState *env = &cpu->env;
3968     uint32_t addr;
3969     uint32_t mask;
3970     int new_mode;
3971     uint32_t offset;
3972     uint32_t moe;
3973
3974     assert(!IS_M(env));
3975
3976     arm_log_exception(cs->exception_index);
3977
3978     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
3979     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
3980     case EC_BREAKPOINT:
3981     case EC_BREAKPOINT_SAME_EL:
3982         moe = 1;
3983         break;
3984     case EC_WATCHPOINT:
3985     case EC_WATCHPOINT_SAME_EL:
3986         moe = 10;
3987         break;
3988     case EC_AA32_BKPT:
3989         moe = 3;
3990         break;
3991     case EC_VECTORCATCH:
3992         moe = 5;
3993         break;
3994     default:
3995         moe = 0;
3996         break;
3997     }
3998
3999     if (moe) {
4000         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
4001     }
4002
4003     /* TODO: Vectored interrupt controller.  */
4004     switch (cs->exception_index) {
4005     case EXCP_UDEF:
4006         new_mode = ARM_CPU_MODE_UND;
4007         addr = 0x04;
4008         mask = CPSR_I;
4009         if (env->thumb)
4010             offset = 2;
4011         else
4012             offset = 4;
4013         break;
4014     case EXCP_SWI:
4015         if (semihosting_enabled) {
4016             /* Check for semihosting interrupt.  */
4017             if (env->thumb) {
4018                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
4019                     & 0xff;
4020             } else {
4021                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
4022                     & 0xffffff;
4023             }
4024             /* Only intercept calls from privileged modes, to provide some
4025                semblance of security.  */
4026             if (((mask == 0x123456 && !env->thumb)
4027                     || (mask == 0xab && env->thumb))
4028                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4029                 env->regs[0] = do_arm_semihosting(env);
4030                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4031                 return;
4032             }
4033         }
4034         new_mode = ARM_CPU_MODE_SVC;
4035         addr = 0x08;
4036         mask = CPSR_I;
4037         /* The PC already points to the next instruction.  */
4038         offset = 0;
4039         break;
4040     case EXCP_BKPT:
4041         /* See if this is a semihosting syscall.  */
4042         if (env->thumb && semihosting_enabled) {
4043             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4044             if (mask == 0xab
4045                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4046                 env->regs[15] += 2;
4047                 env->regs[0] = do_arm_semihosting(env);
4048                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4049                 return;
4050             }
4051         }
4052         env->exception.fsr = 2;
4053         /* Fall through to prefetch abort.  */
4054     case EXCP_PREFETCH_ABORT:
4055         env->cp15.ifsr_el2 = env->exception.fsr;
4056         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
4057                                         env->exception.vaddress);
4058         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
4059                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
4060         new_mode = ARM_CPU_MODE_ABT;
4061         addr = 0x0c;
4062         mask = CPSR_A | CPSR_I;
4063         offset = 4;
4064         break;
4065     case EXCP_DATA_ABORT:
4066         env->cp15.esr_el[1] = env->exception.fsr;
4067         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
4068                                         env->exception.vaddress);
4069         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
4070                       (uint32_t)env->cp15.esr_el[1],
4071                       (uint32_t)env->exception.vaddress);
4072         new_mode = ARM_CPU_MODE_ABT;
4073         addr = 0x10;
4074         mask = CPSR_A | CPSR_I;
4075         offset = 8;
4076         break;
4077     case EXCP_IRQ:
4078         new_mode = ARM_CPU_MODE_IRQ;
4079         addr = 0x18;
4080         /* Disable IRQ and imprecise data aborts.  */
4081         mask = CPSR_A | CPSR_I;
4082         offset = 4;
4083         break;
4084     case EXCP_FIQ:
4085         new_mode = ARM_CPU_MODE_FIQ;
4086         addr = 0x1c;
4087         /* Disable FIQ, IRQ and imprecise data aborts.  */
4088         mask = CPSR_A | CPSR_I | CPSR_F;
4089         offset = 4;
4090         break;
4091     default:
4092         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4093         return; /* Never happens.  Keep compiler happy.  */
4094     }
4095     /* High vectors.  */
4096     if (env->cp15.c1_sys & SCTLR_V) {
4097         /* when enabled, base address cannot be remapped.  */
4098         addr += 0xffff0000;
4099     } else {
4100         /* ARM v7 architectures provide a vector base address register to remap
4101          * the interrupt vector table.
4102          * This register is only followed in non-monitor mode, and has a secure
4103          * and un-secure copy. Since the cpu is always in a un-secure operation
4104          * and is never in monitor mode this feature is always active.
4105          * Note: only bits 31:5 are valid.
4106          */
4107         addr += env->cp15.vbar_el[1];
4108     }
4109     switch_mode (env, new_mode);
4110     /* For exceptions taken to AArch32 we must clear the SS bit in both
4111      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4112      */
4113     env->uncached_cpsr &= ~PSTATE_SS;
4114     env->spsr = cpsr_read(env);
4115     /* Clear IT bits.  */
4116     env->condexec_bits = 0;
4117     /* Switch to the new mode, and to the correct instruction set.  */
4118     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
4119     env->daif |= mask;
4120     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4121      * and we should just guard the thumb mode on V4 */
4122     if (arm_feature(env, ARM_FEATURE_V4T)) {
4123         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
4124     }
4125     env->regs[14] = env->regs[15] + offset;
4126     env->regs[15] = addr;
4127     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
4128 }
4129
4130 /* Check section/page access permissions.
4131    Returns the page protection flags, or zero if the access is not
4132    permitted.  */
4133 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
4134                            int access_type, int is_user)
4135 {
4136   int prot_ro;
4137
4138   if (domain_prot == 3) {
4139     return PAGE_READ | PAGE_WRITE;
4140   }
4141
4142   if (access_type == 1)
4143       prot_ro = 0;
4144   else
4145       prot_ro = PAGE_READ;
4146
4147   switch (ap) {
4148   case 0:
4149       if (arm_feature(env, ARM_FEATURE_V7)) {
4150           return 0;
4151       }
4152       if (access_type == 1)
4153           return 0;
4154       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
4155       case SCTLR_S:
4156           return is_user ? 0 : PAGE_READ;
4157       case SCTLR_R:
4158           return PAGE_READ;
4159       default:
4160           return 0;
4161       }
4162   case 1:
4163       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
4164   case 2:
4165       if (is_user)
4166           return prot_ro;
4167       else
4168           return PAGE_READ | PAGE_WRITE;
4169   case 3:
4170       return PAGE_READ | PAGE_WRITE;
4171   case 4: /* Reserved.  */
4172       return 0;
4173   case 5:
4174       return is_user ? 0 : prot_ro;
4175   case 6:
4176       return prot_ro;
4177   case 7:
4178       if (!arm_feature (env, ARM_FEATURE_V6K))
4179           return 0;
4180       return prot_ro;
4181   default:
4182       abort();
4183   }
4184 }
4185
4186 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
4187                                          uint32_t address)
4188 {
4189     if (address & env->cp15.c2_mask) {
4190         if ((env->cp15.c2_control & TTBCR_PD1)) {
4191             /* Translation table walk disabled for TTBR1 */
4192             return false;
4193         }
4194         *table = env->cp15.ttbr1_el1 & 0xffffc000;
4195     } else {
4196         if ((env->cp15.c2_control & TTBCR_PD0)) {
4197             /* Translation table walk disabled for TTBR0 */
4198             return false;
4199         }
4200         *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
4201     }
4202     *table |= (address >> 18) & 0x3ffc;
4203     return true;
4204 }
4205
4206 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
4207                             int is_user, hwaddr *phys_ptr,
4208                             int *prot, target_ulong *page_size)
4209 {
4210     CPUState *cs = CPU(arm_env_get_cpu(env));
4211     int code;
4212     uint32_t table;
4213     uint32_t desc;
4214     int type;
4215     int ap;
4216     int domain = 0;
4217     int domain_prot;
4218     hwaddr phys_addr;
4219
4220     /* Pagetable walk.  */
4221     /* Lookup l1 descriptor.  */
4222     if (!get_level1_table_address(env, &table, address)) {
4223         /* Section translation fault if page walk is disabled by PD0 or PD1 */
4224         code = 5;
4225         goto do_fault;
4226     }
4227     desc = ldl_phys(cs->as, table);
4228     type = (desc & 3);
4229     domain = (desc >> 5) & 0x0f;
4230     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
4231     if (type == 0) {
4232         /* Section translation fault.  */
4233         code = 5;
4234         goto do_fault;
4235     }
4236     if (domain_prot == 0 || domain_prot == 2) {
4237         if (type == 2)
4238             code = 9; /* Section domain fault.  */
4239         else
4240             code = 11; /* Page domain fault.  */
4241         goto do_fault;
4242     }
4243     if (type == 2) {
4244         /* 1Mb section.  */
4245         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
4246         ap = (desc >> 10) & 3;
4247         code = 13;
4248         *page_size = 1024 * 1024;
4249     } else {
4250         /* Lookup l2 entry.  */
4251         if (type == 1) {
4252             /* Coarse pagetable.  */
4253             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
4254         } else {
4255             /* Fine pagetable.  */
4256             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
4257         }
4258         desc = ldl_phys(cs->as, table);
4259         switch (desc & 3) {
4260         case 0: /* Page translation fault.  */
4261             code = 7;
4262             goto do_fault;
4263         case 1: /* 64k page.  */
4264             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
4265             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
4266             *page_size = 0x10000;
4267             break;
4268         case 2: /* 4k page.  */
4269             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
4270             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
4271             *page_size = 0x1000;
4272             break;
4273         case 3: /* 1k page.  */
4274             if (type == 1) {
4275                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4276                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
4277                 } else {
4278                     /* Page translation fault.  */
4279                     code = 7;
4280                     goto do_fault;
4281                 }
4282             } else {
4283                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
4284             }
4285             ap = (desc >> 4) & 3;
4286             *page_size = 0x400;
4287             break;
4288         default:
4289             /* Never happens, but compiler isn't smart enough to tell.  */
4290             abort();
4291         }
4292         code = 15;
4293     }
4294     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
4295     if (!*prot) {
4296         /* Access permission fault.  */
4297         goto do_fault;
4298     }
4299     *prot |= PAGE_EXEC;
4300     *phys_ptr = phys_addr;
4301     return 0;
4302 do_fault:
4303     return code | (domain << 4);
4304 }
4305
4306 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
4307                             int is_user, hwaddr *phys_ptr,
4308                             int *prot, target_ulong *page_size)
4309 {
4310     CPUState *cs = CPU(arm_env_get_cpu(env));
4311     int code;
4312     uint32_t table;
4313     uint32_t desc;
4314     uint32_t xn;
4315     uint32_t pxn = 0;
4316     int type;
4317     int ap;
4318     int domain = 0;
4319     int domain_prot;
4320     hwaddr phys_addr;
4321
4322     /* Pagetable walk.  */
4323     /* Lookup l1 descriptor.  */
4324     if (!get_level1_table_address(env, &table, address)) {
4325         /* Section translation fault if page walk is disabled by PD0 or PD1 */
4326         code = 5;
4327         goto do_fault;
4328     }
4329     desc = ldl_phys(cs->as, table);
4330     type = (desc & 3);
4331     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
4332         /* Section translation fault, or attempt to use the encoding
4333          * which is Reserved on implementations without PXN.
4334          */
4335         code = 5;
4336         goto do_fault;
4337     }
4338     if ((type == 1) || !(desc & (1 << 18))) {
4339         /* Page or Section.  */
4340         domain = (desc >> 5) & 0x0f;
4341     }
4342     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
4343     if (domain_prot == 0 || domain_prot == 2) {
4344         if (type != 1) {
4345             code = 9; /* Section domain fault.  */
4346         } else {
4347             code = 11; /* Page domain fault.  */
4348         }
4349         goto do_fault;
4350     }
4351     if (type != 1) {
4352         if (desc & (1 << 18)) {
4353             /* Supersection.  */
4354             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
4355             *page_size = 0x1000000;
4356         } else {
4357             /* Section.  */
4358             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
4359             *page_size = 0x100000;
4360         }
4361         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
4362         xn = desc & (1 << 4);
4363         pxn = desc & 1;
4364         code = 13;
4365     } else {
4366         if (arm_feature(env, ARM_FEATURE_PXN)) {
4367             pxn = (desc >> 2) & 1;
4368         }
4369         /* Lookup l2 entry.  */
4370         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
4371         desc = ldl_phys(cs->as, table);
4372         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
4373         switch (desc & 3) {
4374         case 0: /* Page translation fault.  */
4375             code = 7;
4376             goto do_fault;
4377         case 1: /* 64k page.  */
4378             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
4379             xn = desc & (1 << 15);
4380             *page_size = 0x10000;
4381             break;
4382         case 2: case 3: /* 4k page.  */
4383             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
4384             xn = desc & 1;
4385             *page_size = 0x1000;
4386             break;
4387         default:
4388             /* Never happens, but compiler isn't smart enough to tell.  */
4389             abort();
4390         }
4391         code = 15;
4392     }
4393     if (domain_prot == 3) {
4394         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4395     } else {
4396         if (pxn && !is_user) {
4397             xn = 1;
4398         }
4399         if (xn && access_type == 2)
4400             goto do_fault;
4401
4402         /* The simplified model uses AP[0] as an access control bit.  */
4403         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
4404             /* Access flag fault.  */
4405             code = (code == 15) ? 6 : 3;
4406             goto do_fault;
4407         }
4408         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
4409         if (!*prot) {
4410             /* Access permission fault.  */
4411             goto do_fault;
4412         }
4413         if (!xn) {
4414             *prot |= PAGE_EXEC;
4415         }
4416     }
4417     *phys_ptr = phys_addr;
4418     return 0;
4419 do_fault:
4420     return code | (domain << 4);
4421 }
4422
4423 /* Fault type for long-descriptor MMU fault reporting; this corresponds
4424  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
4425  */
4426 typedef enum {
4427     translation_fault = 1,
4428     access_fault = 2,
4429     permission_fault = 3,
4430 } MMUFaultType;
4431
4432 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
4433                               int access_type, int is_user,
4434                               hwaddr *phys_ptr, int *prot,
4435                               target_ulong *page_size_ptr)
4436 {
4437     CPUState *cs = CPU(arm_env_get_cpu(env));
4438     /* Read an LPAE long-descriptor translation table. */
4439     MMUFaultType fault_type = translation_fault;
4440     uint32_t level = 1;
4441     uint32_t epd;
4442     int32_t tsz;
4443     uint32_t tg;
4444     uint64_t ttbr;
4445     int ttbr_select;
4446     hwaddr descaddr, descmask;
4447     uint32_t tableattrs;
4448     target_ulong page_size;
4449     uint32_t attrs;
4450     int32_t granule_sz = 9;
4451     int32_t va_size = 32;
4452     int32_t tbi = 0;
4453
4454     if (arm_el_is_aa64(env, 1)) {
4455         va_size = 64;
4456         if (extract64(address, 55, 1))
4457             tbi = extract64(env->cp15.c2_control, 38, 1);
4458         else
4459             tbi = extract64(env->cp15.c2_control, 37, 1);
4460         tbi *= 8;
4461     }
4462
4463     /* Determine whether this address is in the region controlled by
4464      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
4465      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
4466      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
4467      */
4468     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
4469     if (arm_el_is_aa64(env, 1)) {
4470         t0sz = MIN(t0sz, 39);
4471         t0sz = MAX(t0sz, 16);
4472     }
4473     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
4474     if (arm_el_is_aa64(env, 1)) {
4475         t1sz = MIN(t1sz, 39);
4476         t1sz = MAX(t1sz, 16);
4477     }
4478     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
4479         /* there is a ttbr0 region and we are in it (high bits all zero) */
4480         ttbr_select = 0;
4481     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
4482         /* there is a ttbr1 region and we are in it (high bits all one) */
4483         ttbr_select = 1;
4484     } else if (!t0sz) {
4485         /* ttbr0 region is "everything not in the ttbr1 region" */
4486         ttbr_select = 0;
4487     } else if (!t1sz) {
4488         /* ttbr1 region is "everything not in the ttbr0 region" */
4489         ttbr_select = 1;
4490     } else {
4491         /* in the gap between the two regions, this is a Translation fault */
4492         fault_type = translation_fault;
4493         goto do_fault;
4494     }
4495
4496     /* Note that QEMU ignores shareability and cacheability attributes,
4497      * so we don't need to do anything with the SH, ORGN, IRGN fields
4498      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
4499      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
4500      * implement any ASID-like capability so we can ignore it (instead
4501      * we will always flush the TLB any time the ASID is changed).
4502      */
4503     if (ttbr_select == 0) {
4504         ttbr = env->cp15.ttbr0_el1;
4505         epd = extract32(env->cp15.c2_control, 7, 1);
4506         tsz = t0sz;
4507
4508         tg = extract32(env->cp15.c2_control, 14, 2);
4509         if (tg == 1) { /* 64KB pages */
4510             granule_sz = 13;
4511         }
4512         if (tg == 2) { /* 16KB pages */
4513             granule_sz = 11;
4514         }
4515     } else {
4516         ttbr = env->cp15.ttbr1_el1;
4517         epd = extract32(env->cp15.c2_control, 23, 1);
4518         tsz = t1sz;
4519
4520         tg = extract32(env->cp15.c2_control, 30, 2);
4521         if (tg == 3)  { /* 64KB pages */
4522             granule_sz = 13;
4523         }
4524         if (tg == 1) { /* 16KB pages */
4525             granule_sz = 11;
4526         }
4527     }
4528
4529     if (epd) {
4530         /* Translation table walk disabled => Translation fault on TLB miss */
4531         goto do_fault;
4532     }
4533
4534     /* The starting level depends on the virtual address size which can be
4535      * up to 48-bits and the translation granule size.
4536      */
4537     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
4538         level = 0;
4539     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
4540         level = 1;
4541     } else {
4542         level = 2;
4543     }
4544
4545     /* Clear the vaddr bits which aren't part of the within-region address,
4546      * so that we don't have to special case things when calculating the
4547      * first descriptor address.
4548      */
4549     if (tsz) {
4550         address &= (1ULL << (va_size - tsz)) - 1;
4551     }
4552
4553     descmask = (1ULL << (granule_sz + 3)) - 1;
4554
4555     /* Now we can extract the actual base address from the TTBR */
4556     descaddr = extract64(ttbr, 0, 48);
4557     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
4558
4559     tableattrs = 0;
4560     for (;;) {
4561         uint64_t descriptor;
4562
4563         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
4564         descaddr &= ~7ULL;
4565         descriptor = ldq_phys(cs->as, descaddr);
4566         if (!(descriptor & 1) ||
4567             (!(descriptor & 2) && (level == 3))) {
4568             /* Invalid, or the Reserved level 3 encoding */
4569             goto do_fault;
4570         }
4571         descaddr = descriptor & 0xfffffff000ULL;
4572
4573         if ((descriptor & 2) && (level < 3)) {
4574             /* Table entry. The top five bits are attributes which  may
4575              * propagate down through lower levels of the table (and
4576              * which are all arranged so that 0 means "no effect", so
4577              * we can gather them up by ORing in the bits at each level).
4578              */
4579             tableattrs |= extract64(descriptor, 59, 5);
4580             level++;
4581             continue;
4582         }
4583         /* Block entry at level 1 or 2, or page entry at level 3.
4584          * These are basically the same thing, although the number
4585          * of bits we pull in from the vaddr varies.
4586          */
4587         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
4588         descaddr |= (address & (page_size - 1));
4589         /* Extract attributes from the descriptor and merge with table attrs */
4590         attrs = extract64(descriptor, 2, 10)
4591             | (extract64(descriptor, 52, 12) << 10);
4592         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
4593         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
4594         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
4595          * means "force PL1 access only", which means forcing AP[1] to 0.
4596          */
4597         if (extract32(tableattrs, 2, 1)) {
4598             attrs &= ~(1 << 4);
4599         }
4600         /* Since we're always in the Non-secure state, NSTable is ignored. */
4601         break;
4602     }
4603     /* Here descaddr is the final physical address, and attributes
4604      * are all in attrs.
4605      */
4606     fault_type = access_fault;
4607     if ((attrs & (1 << 8)) == 0) {
4608         /* Access flag */
4609         goto do_fault;
4610     }
4611     fault_type = permission_fault;
4612     if (is_user && !(attrs & (1 << 4))) {
4613         /* Unprivileged access not enabled */
4614         goto do_fault;
4615     }
4616     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4617     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4618         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4619         (!is_user && (attrs & (1 << 11)))) {
4620         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4621          * treat XN/UXN as UXN for v8.
4622          */
4623         if (access_type == 2) {
4624             goto do_fault;
4625         }
4626         *prot &= ~PAGE_EXEC;
4627     }
4628     if (attrs & (1 << 5)) {
4629         /* Write access forbidden */
4630         if (access_type == 1) {
4631             goto do_fault;
4632         }
4633         *prot &= ~PAGE_WRITE;
4634     }
4635
4636     *phys_ptr = descaddr;
4637     *page_size_ptr = page_size;
4638     return 0;
4639
4640 do_fault:
4641     /* Long-descriptor format IFSR/DFSR value */
4642     return (1 << 9) | (fault_type << 2) | level;
4643 }
4644
4645 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4646                              int access_type, int is_user,
4647                              hwaddr *phys_ptr, int *prot)
4648 {
4649     int n;
4650     uint32_t mask;
4651     uint32_t base;
4652
4653     *phys_ptr = address;
4654     for (n = 7; n >= 0; n--) {
4655         base = env->cp15.c6_region[n];
4656         if ((base & 1) == 0)
4657             continue;
4658         mask = 1 << ((base >> 1) & 0x1f);
4659         /* Keep this shift separate from the above to avoid an
4660            (undefined) << 32.  */
4661         mask = (mask << 1) - 1;
4662         if (((base ^ address) & ~mask) == 0)
4663             break;
4664     }
4665     if (n < 0)
4666         return 2;
4667
4668     if (access_type == 2) {
4669         mask = env->cp15.pmsav5_insn_ap;
4670     } else {
4671         mask = env->cp15.pmsav5_data_ap;
4672     }
4673     mask = (mask >> (n * 4)) & 0xf;
4674     switch (mask) {
4675     case 0:
4676         return 1;
4677     case 1:
4678         if (is_user)
4679           return 1;
4680         *prot = PAGE_READ | PAGE_WRITE;
4681         break;
4682     case 2:
4683         *prot = PAGE_READ;
4684         if (!is_user)
4685             *prot |= PAGE_WRITE;
4686         break;
4687     case 3:
4688         *prot = PAGE_READ | PAGE_WRITE;
4689         break;
4690     case 5:
4691         if (is_user)
4692             return 1;
4693         *prot = PAGE_READ;
4694         break;
4695     case 6:
4696         *prot = PAGE_READ;
4697         break;
4698     default:
4699         /* Bad permission.  */
4700         return 1;
4701     }
4702     *prot |= PAGE_EXEC;
4703     return 0;
4704 }
4705
4706 /* get_phys_addr - get the physical address for this virtual address
4707  *
4708  * Find the physical address corresponding to the given virtual address,
4709  * by doing a translation table walk on MMU based systems or using the
4710  * MPU state on MPU based systems.
4711  *
4712  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4713  * prot and page_size are not filled in, and the return value provides
4714  * information on why the translation aborted, in the format of a
4715  * DFSR/IFSR fault register, with the following caveats:
4716  *  * we honour the short vs long DFSR format differences.
4717  *  * the WnR bit is never set (the caller must do this).
4718  *  * for MPU based systems we don't bother to return a full FSR format
4719  *    value.
4720  *
4721  * @env: CPUARMState
4722  * @address: virtual address to get physical address for
4723  * @access_type: 0 for read, 1 for write, 2 for execute
4724  * @is_user: 0 for privileged access, 1 for user
4725  * @phys_ptr: set to the physical address corresponding to the virtual address
4726  * @prot: set to the permissions for the page containing phys_ptr
4727  * @page_size: set to the size of the page containing phys_ptr
4728  */
4729 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4730                                 int access_type, int is_user,
4731                                 hwaddr *phys_ptr, int *prot,
4732                                 target_ulong *page_size)
4733 {
4734     /* Fast Context Switch Extension.  */
4735     if (address < 0x02000000)
4736         address += env->cp15.c13_fcse;
4737
4738     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4739         /* MMU/MPU disabled.  */
4740         *phys_ptr = address;
4741         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4742         *page_size = TARGET_PAGE_SIZE;
4743         return 0;
4744     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4745         *page_size = TARGET_PAGE_SIZE;
4746         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4747                                  prot);
4748     } else if (extended_addresses_enabled(env)) {
4749         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4750                                   prot, page_size);
4751     } else if (env->cp15.c1_sys & SCTLR_XP) {
4752         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4753                                 prot, page_size);
4754     } else {
4755         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4756                                 prot, page_size);
4757     }
4758 }
4759
4760 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4761                              int access_type, int mmu_idx)
4762 {
4763     ARMCPU *cpu = ARM_CPU(cs);
4764     CPUARMState *env = &cpu->env;
4765     hwaddr phys_addr;
4766     target_ulong page_size;
4767     int prot;
4768     int ret, is_user;
4769     uint32_t syn;
4770     bool same_el = (arm_current_pl(env) != 0);
4771
4772     is_user = mmu_idx == MMU_USER_IDX;
4773     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4774                         &page_size);
4775     if (ret == 0) {
4776         /* Map a single [sub]page.  */
4777         phys_addr &= TARGET_PAGE_MASK;
4778         address &= TARGET_PAGE_MASK;
4779         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4780         return 0;
4781     }
4782
4783     /* AArch64 syndrome does not have an LPAE bit */
4784     syn = ret & ~(1 << 9);
4785
4786     /* For insn and data aborts we assume there is no instruction syndrome
4787      * information; this is always true for exceptions reported to EL1.
4788      */
4789     if (access_type == 2) {
4790         syn = syn_insn_abort(same_el, 0, 0, syn);
4791         cs->exception_index = EXCP_PREFETCH_ABORT;
4792     } else {
4793         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4794         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4795             ret |= (1 << 11);
4796         }
4797         cs->exception_index = EXCP_DATA_ABORT;
4798     }
4799
4800     env->exception.syndrome = syn;
4801     env->exception.vaddress = address;
4802     env->exception.fsr = ret;
4803     return 1;
4804 }
4805
4806 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4807 {
4808     ARMCPU *cpu = ARM_CPU(cs);
4809     hwaddr phys_addr;
4810     target_ulong page_size;
4811     int prot;
4812     int ret;
4813
4814     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4815
4816     if (ret != 0) {
4817         return -1;
4818     }
4819
4820     return phys_addr;
4821 }
4822
4823 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4824 {
4825     if ((env->uncached_cpsr & CPSR_M) == mode) {
4826         env->regs[13] = val;
4827     } else {
4828         env->banked_r13[bank_number(mode)] = val;
4829     }
4830 }
4831
4832 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4833 {
4834     if ((env->uncached_cpsr & CPSR_M) == mode) {
4835         return env->regs[13];
4836     } else {
4837         return env->banked_r13[bank_number(mode)];
4838     }
4839 }
4840
4841 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4842 {
4843     ARMCPU *cpu = arm_env_get_cpu(env);
4844
4845     switch (reg) {
4846     case 0: /* APSR */
4847         return xpsr_read(env) & 0xf8000000;
4848     case 1: /* IAPSR */
4849         return xpsr_read(env) & 0xf80001ff;
4850     case 2: /* EAPSR */
4851         return xpsr_read(env) & 0xff00fc00;
4852     case 3: /* xPSR */
4853         return xpsr_read(env) & 0xff00fdff;
4854     case 5: /* IPSR */
4855         return xpsr_read(env) & 0x000001ff;
4856     case 6: /* EPSR */
4857         return xpsr_read(env) & 0x0700fc00;
4858     case 7: /* IEPSR */
4859         return xpsr_read(env) & 0x0700edff;
4860     case 8: /* MSP */
4861         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4862     case 9: /* PSP */
4863         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4864     case 16: /* PRIMASK */
4865         return (env->daif & PSTATE_I) != 0;
4866     case 17: /* BASEPRI */
4867     case 18: /* BASEPRI_MAX */
4868         return env->v7m.basepri;
4869     case 19: /* FAULTMASK */
4870         return (env->daif & PSTATE_F) != 0;
4871     case 20: /* CONTROL */
4872         return env->v7m.control;
4873     default:
4874         /* ??? For debugging only.  */
4875         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4876         return 0;
4877     }
4878 }
4879
4880 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4881 {
4882     ARMCPU *cpu = arm_env_get_cpu(env);
4883
4884     switch (reg) {
4885     case 0: /* APSR */
4886         xpsr_write(env, val, 0xf8000000);
4887         break;
4888     case 1: /* IAPSR */
4889         xpsr_write(env, val, 0xf8000000);
4890         break;
4891     case 2: /* EAPSR */
4892         xpsr_write(env, val, 0xfe00fc00);
4893         break;
4894     case 3: /* xPSR */
4895         xpsr_write(env, val, 0xfe00fc00);
4896         break;
4897     case 5: /* IPSR */
4898         /* IPSR bits are readonly.  */
4899         break;
4900     case 6: /* EPSR */
4901         xpsr_write(env, val, 0x0600fc00);
4902         break;
4903     case 7: /* IEPSR */
4904         xpsr_write(env, val, 0x0600fc00);
4905         break;
4906     case 8: /* MSP */
4907         if (env->v7m.current_sp)
4908             env->v7m.other_sp = val;
4909         else
4910             env->regs[13] = val;
4911         break;
4912     case 9: /* PSP */
4913         if (env->v7m.current_sp)
4914             env->regs[13] = val;
4915         else
4916             env->v7m.other_sp = val;
4917         break;
4918     case 16: /* PRIMASK */
4919         if (val & 1) {
4920             env->daif |= PSTATE_I;
4921         } else {
4922             env->daif &= ~PSTATE_I;
4923         }
4924         break;
4925     case 17: /* BASEPRI */
4926         env->v7m.basepri = val & 0xff;
4927         break;
4928     case 18: /* BASEPRI_MAX */
4929         val &= 0xff;
4930         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4931             env->v7m.basepri = val;
4932         break;
4933     case 19: /* FAULTMASK */
4934         if (val & 1) {
4935             env->daif |= PSTATE_F;
4936         } else {
4937             env->daif &= ~PSTATE_F;
4938         }
4939         break;
4940     case 20: /* CONTROL */
4941         env->v7m.control = val & 3;
4942         switch_v7m_sp(env, (val & 2) != 0);
4943         break;
4944     default:
4945         /* ??? For debugging only.  */
4946         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4947         return;
4948     }
4949 }
4950
4951 #endif
4952
4953 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4954 {
4955     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4956      * Note that we do not implement the (architecturally mandated)
4957      * alignment fault for attempts to use this on Device memory
4958      * (which matches the usual QEMU behaviour of not implementing either
4959      * alignment faults or any memory attribute handling).
4960      */
4961
4962     ARMCPU *cpu = arm_env_get_cpu(env);
4963     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4964     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4965
4966 #ifndef CONFIG_USER_ONLY
4967     {
4968         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4969          * the block size so we might have to do more than one TLB lookup.
4970          * We know that in fact for any v8 CPU the page size is at least 4K
4971          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4972          * 1K as an artefact of legacy v5 subpage support being present in the
4973          * same QEMU executable.
4974          */
4975         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4976         void *hostaddr[maxidx];
4977         int try, i;
4978
4979         for (try = 0; try < 2; try++) {
4980
4981             for (i = 0; i < maxidx; i++) {
4982                 hostaddr[i] = tlb_vaddr_to_host(env,
4983                                                 vaddr + TARGET_PAGE_SIZE * i,
4984                                                 1, cpu_mmu_index(env));
4985                 if (!hostaddr[i]) {
4986                     break;
4987                 }
4988             }
4989             if (i == maxidx) {
4990                 /* If it's all in the TLB it's fair game for just writing to;
4991                  * we know we don't need to update dirty status, etc.
4992                  */
4993                 for (i = 0; i < maxidx - 1; i++) {
4994                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4995                 }
4996                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4997                 return;
4998             }
4999             /* OK, try a store and see if we can populate the tlb. This
5000              * might cause an exception if the memory isn't writable,
5001              * in which case we will longjmp out of here. We must for
5002              * this purpose use the actual register value passed to us
5003              * so that we get the fault address right.
5004              */
5005             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
5006             /* Now we can populate the other TLB entries, if any */
5007             for (i = 0; i < maxidx; i++) {
5008                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
5009                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
5010                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
5011                 }
5012             }
5013         }
5014
5015         /* Slow path (probably attempt to do this to an I/O device or
5016          * similar, or clearing of a block of code we have translations
5017          * cached for). Just do a series of byte writes as the architecture
5018          * demands. It's not worth trying to use a cpu_physical_memory_map(),
5019          * memset(), unmap() sequence here because:
5020          *  + we'd need to account for the blocksize being larger than a page
5021          *  + the direct-RAM access case is almost always going to be dealt
5022          *    with in the fastpath code above, so there's no speed benefit
5023          *  + we would have to deal with the map returning NULL because the
5024          *    bounce buffer was in use
5025          */
5026         for (i = 0; i < blocklen; i++) {
5027             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
5028         }
5029     }
5030 #else
5031     memset(g2h(vaddr), 0, blocklen);
5032 #endif
5033 }
5034
5035 /* Note that signed overflow is undefined in C.  The following routines are
5036    careful to use unsigned types where modulo arithmetic is required.
5037    Failure to do so _will_ break on newer gcc.  */
5038
5039 /* Signed saturating arithmetic.  */
5040
5041 /* Perform 16-bit signed saturating addition.  */
5042 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
5043 {
5044     uint16_t res;
5045
5046     res = a + b;
5047     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
5048         if (a & 0x8000)
5049             res = 0x8000;
5050         else
5051             res = 0x7fff;
5052     }
5053     return res;
5054 }
5055
5056 /* Perform 8-bit signed saturating addition.  */
5057 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
5058 {
5059     uint8_t res;
5060
5061     res = a + b;
5062     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
5063         if (a & 0x80)
5064             res = 0x80;
5065         else
5066             res = 0x7f;
5067     }
5068     return res;
5069 }
5070
5071 /* Perform 16-bit signed saturating subtraction.  */
5072 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
5073 {
5074     uint16_t res;
5075
5076     res = a - b;
5077     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
5078         if (a & 0x8000)
5079             res = 0x8000;
5080         else
5081             res = 0x7fff;
5082     }
5083     return res;
5084 }
5085
5086 /* Perform 8-bit signed saturating subtraction.  */
5087 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
5088 {
5089     uint8_t res;
5090
5091     res = a - b;
5092     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
5093         if (a & 0x80)
5094             res = 0x80;
5095         else
5096             res = 0x7f;
5097     }
5098     return res;
5099 }
5100
5101 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
5102 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
5103 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
5104 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
5105 #define PFX q
5106
5107 #include "op_addsub.h"
5108
5109 /* Unsigned saturating arithmetic.  */
5110 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
5111 {
5112     uint16_t res;
5113     res = a + b;
5114     if (res < a)
5115         res = 0xffff;
5116     return res;
5117 }
5118
5119 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
5120 {
5121     if (a > b)
5122         return a - b;
5123     else
5124         return 0;
5125 }
5126
5127 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
5128 {
5129     uint8_t res;
5130     res = a + b;
5131     if (res < a)
5132         res = 0xff;
5133     return res;
5134 }
5135
5136 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
5137 {
5138     if (a > b)
5139         return a - b;
5140     else
5141         return 0;
5142 }
5143
5144 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
5145 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
5146 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
5147 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
5148 #define PFX uq
5149
5150 #include "op_addsub.h"
5151
5152 /* Signed modulo arithmetic.  */
5153 #define SARITH16(a, b, n, op) do { \
5154     int32_t sum; \
5155     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
5156     RESULT(sum, n, 16); \
5157     if (sum >= 0) \
5158         ge |= 3 << (n * 2); \
5159     } while(0)
5160
5161 #define SARITH8(a, b, n, op) do { \
5162     int32_t sum; \
5163     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
5164     RESULT(sum, n, 8); \
5165     if (sum >= 0) \
5166         ge |= 1 << n; \
5167     } while(0)
5168
5169
5170 #define ADD16(a, b, n) SARITH16(a, b, n, +)
5171 #define SUB16(a, b, n) SARITH16(a, b, n, -)
5172 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
5173 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
5174 #define PFX s
5175 #define ARITH_GE
5176
5177 #include "op_addsub.h"
5178
5179 /* Unsigned modulo arithmetic.  */
5180 #define ADD16(a, b, n) do { \
5181     uint32_t sum; \
5182     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
5183     RESULT(sum, n, 16); \
5184     if ((sum >> 16) == 1) \
5185         ge |= 3 << (n * 2); \
5186     } while(0)
5187
5188 #define ADD8(a, b, n) do { \
5189     uint32_t sum; \
5190     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
5191     RESULT(sum, n, 8); \
5192     if ((sum >> 8) == 1) \
5193         ge |= 1 << n; \
5194     } while(0)
5195
5196 #define SUB16(a, b, n) do { \
5197     uint32_t sum; \
5198     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
5199     RESULT(sum, n, 16); \
5200     if ((sum >> 16) == 0) \
5201         ge |= 3 << (n * 2); \
5202     } while(0)
5203
5204 #define SUB8(a, b, n) do { \
5205     uint32_t sum; \
5206     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
5207     RESULT(sum, n, 8); \
5208     if ((sum >> 8) == 0) \
5209         ge |= 1 << n; \
5210     } while(0)
5211
5212 #define PFX u
5213 #define ARITH_GE
5214
5215 #include "op_addsub.h"
5216
5217 /* Halved signed arithmetic.  */
5218 #define ADD16(a, b, n) \
5219   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
5220 #define SUB16(a, b, n) \
5221   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
5222 #define ADD8(a, b, n) \
5223   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
5224 #define SUB8(a, b, n) \
5225   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
5226 #define PFX sh
5227
5228 #include "op_addsub.h"
5229
5230 /* Halved unsigned arithmetic.  */
5231 #define ADD16(a, b, n) \
5232   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
5233 #define SUB16(a, b, n) \
5234   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
5235 #define ADD8(a, b, n) \
5236   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
5237 #define SUB8(a, b, n) \
5238   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
5239 #define PFX uh
5240
5241 #include "op_addsub.h"
5242
5243 static inline uint8_t do_usad(uint8_t a, uint8_t b)
5244 {
5245     if (a > b)
5246         return a - b;
5247     else
5248         return b - a;
5249 }
5250
5251 /* Unsigned sum of absolute byte differences.  */
5252 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
5253 {
5254     uint32_t sum;
5255     sum = do_usad(a, b);
5256     sum += do_usad(a >> 8, b >> 8);
5257     sum += do_usad(a >> 16, b >>16);
5258     sum += do_usad(a >> 24, b >> 24);
5259     return sum;
5260 }
5261
5262 /* For ARMv6 SEL instruction.  */
5263 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
5264 {
5265     uint32_t mask;
5266
5267     mask = 0;
5268     if (flags & 1)
5269         mask |= 0xff;
5270     if (flags & 2)
5271         mask |= 0xff00;
5272     if (flags & 4)
5273         mask |= 0xff0000;
5274     if (flags & 8)
5275         mask |= 0xff000000;
5276     return (a & mask) | (b & ~mask);
5277 }
5278
5279 /* VFP support.  We follow the convention used for VFP instructions:
5280    Single precision routines have a "s" suffix, double precision a
5281    "d" suffix.  */
5282
5283 /* Convert host exception flags to vfp form.  */
5284 static inline int vfp_exceptbits_from_host(int host_bits)
5285 {
5286     int target_bits = 0;
5287
5288     if (host_bits & float_flag_invalid)
5289         target_bits |= 1;
5290     if (host_bits & float_flag_divbyzero)
5291         target_bits |= 2;
5292     if (host_bits & float_flag_overflow)
5293         target_bits |= 4;
5294     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
5295         target_bits |= 8;
5296     if (host_bits & float_flag_inexact)
5297         target_bits |= 0x10;
5298     if (host_bits & float_flag_input_denormal)
5299         target_bits |= 0x80;
5300     return target_bits;
5301 }
5302
5303 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
5304 {
5305     int i;
5306     uint32_t fpscr;
5307
5308     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
5309             | (env->vfp.vec_len << 16)
5310             | (env->vfp.vec_stride << 20);
5311     i = get_float_exception_flags(&env->vfp.fp_status);
5312     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
5313     fpscr |= vfp_exceptbits_from_host(i);
5314     return fpscr;
5315 }
5316
5317 uint32_t vfp_get_fpscr(CPUARMState *env)
5318 {
5319     return HELPER(vfp_get_fpscr)(env);
5320 }
5321
5322 /* Convert vfp exception flags to target form.  */
5323 static inline int vfp_exceptbits_to_host(int target_bits)
5324 {
5325     int host_bits = 0;
5326
5327     if (target_bits & 1)
5328         host_bits |= float_flag_invalid;
5329     if (target_bits & 2)
5330         host_bits |= float_flag_divbyzero;
5331     if (target_bits & 4)
5332         host_bits |= float_flag_overflow;
5333     if (target_bits & 8)
5334         host_bits |= float_flag_underflow;
5335     if (target_bits & 0x10)
5336         host_bits |= float_flag_inexact;
5337     if (target_bits & 0x80)
5338         host_bits |= float_flag_input_denormal;
5339     return host_bits;
5340 }
5341
5342 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
5343 {
5344     int i;
5345     uint32_t changed;
5346
5347     changed = env->vfp.xregs[ARM_VFP_FPSCR];
5348     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
5349     env->vfp.vec_len = (val >> 16) & 7;
5350     env->vfp.vec_stride = (val >> 20) & 3;
5351
5352     changed ^= val;
5353     if (changed & (3 << 22)) {
5354         i = (val >> 22) & 3;
5355         switch (i) {
5356         case FPROUNDING_TIEEVEN:
5357             i = float_round_nearest_even;
5358             break;
5359         case FPROUNDING_POSINF:
5360             i = float_round_up;
5361             break;
5362         case FPROUNDING_NEGINF:
5363             i = float_round_down;
5364             break;
5365         case FPROUNDING_ZERO:
5366             i = float_round_to_zero;
5367             break;
5368         }
5369         set_float_rounding_mode(i, &env->vfp.fp_status);
5370     }
5371     if (changed & (1 << 24)) {
5372         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
5373         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
5374     }
5375     if (changed & (1 << 25))
5376         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
5377
5378     i = vfp_exceptbits_to_host(val);
5379     set_float_exception_flags(i, &env->vfp.fp_status);
5380     set_float_exception_flags(0, &env->vfp.standard_fp_status);
5381 }
5382
5383 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
5384 {
5385     HELPER(vfp_set_fpscr)(env, val);
5386 }
5387
5388 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
5389
5390 #define VFP_BINOP(name) \
5391 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
5392 { \
5393     float_status *fpst = fpstp; \
5394     return float32_ ## name(a, b, fpst); \
5395 } \
5396 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
5397 { \
5398     float_status *fpst = fpstp; \
5399     return float64_ ## name(a, b, fpst); \
5400 }
5401 VFP_BINOP(add)
5402 VFP_BINOP(sub)
5403 VFP_BINOP(mul)
5404 VFP_BINOP(div)
5405 VFP_BINOP(min)
5406 VFP_BINOP(max)
5407 VFP_BINOP(minnum)
5408 VFP_BINOP(maxnum)
5409 #undef VFP_BINOP
5410
5411 float32 VFP_HELPER(neg, s)(float32 a)
5412 {
5413     return float32_chs(a);
5414 }
5415
5416 float64 VFP_HELPER(neg, d)(float64 a)
5417 {
5418     return float64_chs(a);
5419 }
5420
5421 float32 VFP_HELPER(abs, s)(float32 a)
5422 {
5423     return float32_abs(a);
5424 }
5425
5426 float64 VFP_HELPER(abs, d)(float64 a)
5427 {
5428     return float64_abs(a);
5429 }
5430
5431 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
5432 {
5433     return float32_sqrt(a, &env->vfp.fp_status);
5434 }
5435
5436 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
5437 {
5438     return float64_sqrt(a, &env->vfp.fp_status);
5439 }
5440
5441 /* XXX: check quiet/signaling case */
5442 #define DO_VFP_cmp(p, type) \
5443 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
5444 { \
5445     uint32_t flags; \
5446     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
5447     case 0: flags = 0x6; break; \
5448     case -1: flags = 0x8; break; \
5449     case 1: flags = 0x2; break; \
5450     default: case 2: flags = 0x3; break; \
5451     } \
5452     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
5453         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
5454 } \
5455 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
5456 { \
5457     uint32_t flags; \
5458     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
5459     case 0: flags = 0x6; break; \
5460     case -1: flags = 0x8; break; \
5461     case 1: flags = 0x2; break; \
5462     default: case 2: flags = 0x3; break; \
5463     } \
5464     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
5465         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
5466 }
5467 DO_VFP_cmp(s, float32)
5468 DO_VFP_cmp(d, float64)
5469 #undef DO_VFP_cmp
5470
5471 /* Integer to float and float to integer conversions */
5472
5473 #define CONV_ITOF(name, fsz, sign) \
5474     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
5475 { \
5476     float_status *fpst = fpstp; \
5477     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
5478 }
5479
5480 #define CONV_FTOI(name, fsz, sign, round) \
5481 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
5482 { \
5483     float_status *fpst = fpstp; \
5484     if (float##fsz##_is_any_nan(x)) { \
5485         float_raise(float_flag_invalid, fpst); \
5486         return 0; \
5487     } \
5488     return float##fsz##_to_##sign##int32##round(x, fpst); \
5489 }
5490
5491 #define FLOAT_CONVS(name, p, fsz, sign) \
5492 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
5493 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
5494 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
5495
5496 FLOAT_CONVS(si, s, 32, )
5497 FLOAT_CONVS(si, d, 64, )
5498 FLOAT_CONVS(ui, s, 32, u)
5499 FLOAT_CONVS(ui, d, 64, u)
5500
5501 #undef CONV_ITOF
5502 #undef CONV_FTOI
5503 #undef FLOAT_CONVS
5504
5505 /* floating point conversion */
5506 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
5507 {
5508     float64 r = float32_to_float64(x, &env->vfp.fp_status);
5509     /* ARM requires that S<->D conversion of any kind of NaN generates
5510      * a quiet NaN by forcing the most significant frac bit to 1.
5511      */
5512     return float64_maybe_silence_nan(r);
5513 }
5514
5515 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
5516 {
5517     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
5518     /* ARM requires that S<->D conversion of any kind of NaN generates
5519      * a quiet NaN by forcing the most significant frac bit to 1.
5520      */
5521     return float32_maybe_silence_nan(r);
5522 }
5523
5524 /* VFP3 fixed point conversion.  */
5525 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5526 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
5527                                      void *fpstp) \
5528 { \
5529     float_status *fpst = fpstp; \
5530     float##fsz tmp; \
5531     tmp = itype##_to_##float##fsz(x, fpst); \
5532     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
5533 }
5534
5535 /* Notice that we want only input-denormal exception flags from the
5536  * scalbn operation: the other possible flags (overflow+inexact if
5537  * we overflow to infinity, output-denormal) aren't correct for the
5538  * complete scale-and-convert operation.
5539  */
5540 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
5541 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
5542                                              uint32_t shift, \
5543                                              void *fpstp) \
5544 { \
5545     float_status *fpst = fpstp; \
5546     int old_exc_flags = get_float_exception_flags(fpst); \
5547     float##fsz tmp; \
5548     if (float##fsz##_is_any_nan(x)) { \
5549         float_raise(float_flag_invalid, fpst); \
5550         return 0; \
5551     } \
5552     tmp = float##fsz##_scalbn(x, shift, fpst); \
5553     old_exc_flags |= get_float_exception_flags(fpst) \
5554         & float_flag_input_denormal; \
5555     set_float_exception_flags(old_exc_flags, fpst); \
5556     return float##fsz##_to_##itype##round(tmp, fpst); \
5557 }
5558
5559 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
5560 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5561 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
5562 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5563
5564 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
5565 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5566 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5567
5568 VFP_CONV_FIX(sh, d, 64, 64, int16)
5569 VFP_CONV_FIX(sl, d, 64, 64, int32)
5570 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
5571 VFP_CONV_FIX(uh, d, 64, 64, uint16)
5572 VFP_CONV_FIX(ul, d, 64, 64, uint32)
5573 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
5574 VFP_CONV_FIX(sh, s, 32, 32, int16)
5575 VFP_CONV_FIX(sl, s, 32, 32, int32)
5576 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
5577 VFP_CONV_FIX(uh, s, 32, 32, uint16)
5578 VFP_CONV_FIX(ul, s, 32, 32, uint32)
5579 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
5580 #undef VFP_CONV_FIX
5581 #undef VFP_CONV_FIX_FLOAT
5582 #undef VFP_CONV_FLOAT_FIX_ROUND
5583
5584 /* Set the current fp rounding mode and return the old one.
5585  * The argument is a softfloat float_round_ value.
5586  */
5587 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
5588 {
5589     float_status *fp_status = &env->vfp.fp_status;
5590
5591     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5592     set_float_rounding_mode(rmode, fp_status);
5593
5594     return prev_rmode;
5595 }
5596
5597 /* Set the current fp rounding mode in the standard fp status and return
5598  * the old one. This is for NEON instructions that need to change the
5599  * rounding mode but wish to use the standard FPSCR values for everything
5600  * else. Always set the rounding mode back to the correct value after
5601  * modifying it.
5602  * The argument is a softfloat float_round_ value.
5603  */
5604 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
5605 {
5606     float_status *fp_status = &env->vfp.standard_fp_status;
5607
5608     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5609     set_float_rounding_mode(rmode, fp_status);
5610
5611     return prev_rmode;
5612 }
5613
5614 /* Half precision conversions.  */
5615 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
5616 {
5617     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5618     float32 r = float16_to_float32(make_float16(a), ieee, s);
5619     if (ieee) {
5620         return float32_maybe_silence_nan(r);
5621     }
5622     return r;
5623 }
5624
5625 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5626 {
5627     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5628     float16 r = float32_to_float16(a, ieee, s);
5629     if (ieee) {
5630         r = float16_maybe_silence_nan(r);
5631     }
5632     return float16_val(r);
5633 }
5634
5635 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5636 {
5637     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5638 }
5639
5640 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5641 {
5642     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
5643 }
5644
5645 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5646 {
5647     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
5648 }
5649
5650 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5651 {
5652     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
5653 }
5654
5655 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
5656 {
5657     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5658     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5659     if (ieee) {
5660         return float64_maybe_silence_nan(r);
5661     }
5662     return r;
5663 }
5664
5665 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5666 {
5667     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5668     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5669     if (ieee) {
5670         r = float16_maybe_silence_nan(r);
5671     }
5672     return float16_val(r);
5673 }
5674
5675 #define float32_two make_float32(0x40000000)
5676 #define float32_three make_float32(0x40400000)
5677 #define float32_one_point_five make_float32(0x3fc00000)
5678
5679 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5680 {
5681     float_status *s = &env->vfp.standard_fp_status;
5682     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5683         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5684         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5685             float_raise(float_flag_input_denormal, s);
5686         }
5687         return float32_two;
5688     }
5689     return float32_sub(float32_two, float32_mul(a, b, s), s);
5690 }
5691
5692 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5693 {
5694     float_status *s = &env->vfp.standard_fp_status;
5695     float32 product;
5696     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5697         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5698         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5699             float_raise(float_flag_input_denormal, s);
5700         }
5701         return float32_one_point_five;
5702     }
5703     product = float32_mul(a, b, s);
5704     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5705 }
5706
5707 /* NEON helpers.  */
5708
5709 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5710  * int->float conversions at run-time.  */
5711 #define float64_256 make_float64(0x4070000000000000LL)
5712 #define float64_512 make_float64(0x4080000000000000LL)
5713 #define float32_maxnorm make_float32(0x7f7fffff)
5714 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5715
5716 /* Reciprocal functions
5717  *
5718  * The algorithm that must be used to calculate the estimate
5719  * is specified by the ARM ARM, see FPRecipEstimate()
5720  */
5721
5722 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5723 {
5724     /* These calculations mustn't set any fp exception flags,
5725      * so we use a local copy of the fp_status.
5726      */
5727     float_status dummy_status = *real_fp_status;
5728     float_status *s = &dummy_status;
5729     /* q = (int)(a * 512.0) */
5730     float64 q = float64_mul(float64_512, a, s);
5731     int64_t q_int = float64_to_int64_round_to_zero(q, s);
5732
5733     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5734     q = int64_to_float64(q_int, s);
5735     q = float64_add(q, float64_half, s);
5736     q = float64_div(q, float64_512, s);
5737     q = float64_div(float64_one, q, s);
5738
5739     /* s = (int)(256.0 * r + 0.5) */
5740     q = float64_mul(q, float64_256, s);
5741     q = float64_add(q, float64_half, s);
5742     q_int = float64_to_int64_round_to_zero(q, s);
5743
5744     /* return (double)s / 256.0 */
5745     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5746 }
5747
5748 /* Common wrapper to call recip_estimate */
5749 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5750 {
5751     uint64_t val64 = float64_val(num);
5752     uint64_t frac = extract64(val64, 0, 52);
5753     int64_t exp = extract64(val64, 52, 11);
5754     uint64_t sbit;
5755     float64 scaled, estimate;
5756
5757     /* Generate the scaled number for the estimate function */
5758     if (exp == 0) {
5759         if (extract64(frac, 51, 1) == 0) {
5760             exp = -1;
5761             frac = extract64(frac, 0, 50) << 2;
5762         } else {
5763             frac = extract64(frac, 0, 51) << 1;
5764         }
5765     }
5766
5767     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5768     scaled = make_float64((0x3feULL << 52)
5769                           | extract64(frac, 44, 8) << 44);
5770
5771     estimate = recip_estimate(scaled, fpst);
5772
5773     /* Build new result */
5774     val64 = float64_val(estimate);
5775     sbit = 0x8000000000000000ULL & val64;
5776     exp = off - exp;
5777     frac = extract64(val64, 0, 52);
5778
5779     if (exp == 0) {
5780         frac = 1ULL << 51 | extract64(frac, 1, 51);
5781     } else if (exp == -1) {
5782         frac = 1ULL << 50 | extract64(frac, 2, 50);
5783         exp = 0;
5784     }
5785
5786     return make_float64(sbit | (exp << 52) | frac);
5787 }
5788
5789 static bool round_to_inf(float_status *fpst, bool sign_bit)
5790 {
5791     switch (fpst->float_rounding_mode) {
5792     case float_round_nearest_even: /* Round to Nearest */
5793         return true;
5794     case float_round_up: /* Round to +Inf */
5795         return !sign_bit;
5796     case float_round_down: /* Round to -Inf */
5797         return sign_bit;
5798     case float_round_to_zero: /* Round to Zero */
5799         return false;
5800     }
5801
5802     g_assert_not_reached();
5803 }
5804
5805 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5806 {
5807     float_status *fpst = fpstp;
5808     float32 f32 = float32_squash_input_denormal(input, fpst);
5809     uint32_t f32_val = float32_val(f32);
5810     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5811     int32_t f32_exp = extract32(f32_val, 23, 8);
5812     uint32_t f32_frac = extract32(f32_val, 0, 23);
5813     float64 f64, r64;
5814     uint64_t r64_val;
5815     int64_t r64_exp;
5816     uint64_t r64_frac;
5817
5818     if (float32_is_any_nan(f32)) {
5819         float32 nan = f32;
5820         if (float32_is_signaling_nan(f32)) {
5821             float_raise(float_flag_invalid, fpst);
5822             nan = float32_maybe_silence_nan(f32);
5823         }
5824         if (fpst->default_nan_mode) {
5825             nan =  float32_default_nan;
5826         }
5827         return nan;
5828     } else if (float32_is_infinity(f32)) {
5829         return float32_set_sign(float32_zero, float32_is_neg(f32));
5830     } else if (float32_is_zero(f32)) {
5831         float_raise(float_flag_divbyzero, fpst);
5832         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5833     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5834         /* Abs(value) < 2.0^-128 */
5835         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5836         if (round_to_inf(fpst, f32_sbit)) {
5837             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5838         } else {
5839             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5840         }
5841     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5842         float_raise(float_flag_underflow, fpst);
5843         return float32_set_sign(float32_zero, float32_is_neg(f32));
5844     }
5845
5846
5847     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5848     r64 = call_recip_estimate(f64, 253, fpst);
5849     r64_val = float64_val(r64);
5850     r64_exp = extract64(r64_val, 52, 11);
5851     r64_frac = extract64(r64_val, 0, 52);
5852
5853     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5854     return make_float32(f32_sbit |
5855                         (r64_exp & 0xff) << 23 |
5856                         extract64(r64_frac, 29, 24));
5857 }
5858
5859 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5860 {
5861     float_status *fpst = fpstp;
5862     float64 f64 = float64_squash_input_denormal(input, fpst);
5863     uint64_t f64_val = float64_val(f64);
5864     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5865     int64_t f64_exp = extract64(f64_val, 52, 11);
5866     float64 r64;
5867     uint64_t r64_val;
5868     int64_t r64_exp;
5869     uint64_t r64_frac;
5870
5871     /* Deal with any special cases */
5872     if (float64_is_any_nan(f64)) {
5873         float64 nan = f64;
5874         if (float64_is_signaling_nan(f64)) {
5875             float_raise(float_flag_invalid, fpst);
5876             nan = float64_maybe_silence_nan(f64);
5877         }
5878         if (fpst->default_nan_mode) {
5879             nan =  float64_default_nan;
5880         }
5881         return nan;
5882     } else if (float64_is_infinity(f64)) {
5883         return float64_set_sign(float64_zero, float64_is_neg(f64));
5884     } else if (float64_is_zero(f64)) {
5885         float_raise(float_flag_divbyzero, fpst);
5886         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5887     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5888         /* Abs(value) < 2.0^-1024 */
5889         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5890         if (round_to_inf(fpst, f64_sbit)) {
5891             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5892         } else {
5893             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5894         }
5895     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5896         float_raise(float_flag_underflow, fpst);
5897         return float64_set_sign(float64_zero, float64_is_neg(f64));
5898     }
5899
5900     r64 = call_recip_estimate(f64, 2045, fpst);
5901     r64_val = float64_val(r64);
5902     r64_exp = extract64(r64_val, 52, 11);
5903     r64_frac = extract64(r64_val, 0, 52);
5904
5905     /* result = sign : result_exp<10:0> : fraction<51:0> */
5906     return make_float64(f64_sbit |
5907                         ((r64_exp & 0x7ff) << 52) |
5908                         r64_frac);
5909 }
5910
5911 /* The algorithm that must be used to calculate the estimate
5912  * is specified by the ARM ARM.
5913  */
5914 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5915 {
5916     /* These calculations mustn't set any fp exception flags,
5917      * so we use a local copy of the fp_status.
5918      */
5919     float_status dummy_status = *real_fp_status;
5920     float_status *s = &dummy_status;
5921     float64 q;
5922     int64_t q_int;
5923
5924     if (float64_lt(a, float64_half, s)) {
5925         /* range 0.25 <= a < 0.5 */
5926
5927         /* a in units of 1/512 rounded down */
5928         /* q0 = (int)(a * 512.0);  */
5929         q = float64_mul(float64_512, a, s);
5930         q_int = float64_to_int64_round_to_zero(q, s);
5931
5932         /* reciprocal root r */
5933         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5934         q = int64_to_float64(q_int, s);
5935         q = float64_add(q, float64_half, s);
5936         q = float64_div(q, float64_512, s);
5937         q = float64_sqrt(q, s);
5938         q = float64_div(float64_one, q, s);
5939     } else {
5940         /* range 0.5 <= a < 1.0 */
5941
5942         /* a in units of 1/256 rounded down */
5943         /* q1 = (int)(a * 256.0); */
5944         q = float64_mul(float64_256, a, s);
5945         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5946
5947         /* reciprocal root r */
5948         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5949         q = int64_to_float64(q_int, s);
5950         q = float64_add(q, float64_half, s);
5951         q = float64_div(q, float64_256, s);
5952         q = float64_sqrt(q, s);
5953         q = float64_div(float64_one, q, s);
5954     }
5955     /* r in units of 1/256 rounded to nearest */
5956     /* s = (int)(256.0 * r + 0.5); */
5957
5958     q = float64_mul(q, float64_256,s );
5959     q = float64_add(q, float64_half, s);
5960     q_int = float64_to_int64_round_to_zero(q, s);
5961
5962     /* return (double)s / 256.0;*/
5963     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5964 }
5965
5966 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5967 {
5968     float_status *s = fpstp;
5969     float32 f32 = float32_squash_input_denormal(input, s);
5970     uint32_t val = float32_val(f32);
5971     uint32_t f32_sbit = 0x80000000 & val;
5972     int32_t f32_exp = extract32(val, 23, 8);
5973     uint32_t f32_frac = extract32(val, 0, 23);
5974     uint64_t f64_frac;
5975     uint64_t val64;
5976     int result_exp;
5977     float64 f64;
5978
5979     if (float32_is_any_nan(f32)) {
5980         float32 nan = f32;
5981         if (float32_is_signaling_nan(f32)) {
5982             float_raise(float_flag_invalid, s);
5983             nan = float32_maybe_silence_nan(f32);
5984         }
5985         if (s->default_nan_mode) {
5986             nan =  float32_default_nan;
5987         }
5988         return nan;
5989     } else if (float32_is_zero(f32)) {
5990         float_raise(float_flag_divbyzero, s);
5991         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5992     } else if (float32_is_neg(f32)) {
5993         float_raise(float_flag_invalid, s);
5994         return float32_default_nan;
5995     } else if (float32_is_infinity(f32)) {
5996         return float32_zero;
5997     }
5998
5999     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
6000      * preserving the parity of the exponent.  */
6001
6002     f64_frac = ((uint64_t) f32_frac) << 29;
6003     if (f32_exp == 0) {
6004         while (extract64(f64_frac, 51, 1) == 0) {
6005             f64_frac = f64_frac << 1;
6006             f32_exp = f32_exp-1;
6007         }
6008         f64_frac = extract64(f64_frac, 0, 51) << 1;
6009     }
6010
6011     if (extract64(f32_exp, 0, 1) == 0) {
6012         f64 = make_float64(((uint64_t) f32_sbit) << 32
6013                            | (0x3feULL << 52)
6014                            | f64_frac);
6015     } else {
6016         f64 = make_float64(((uint64_t) f32_sbit) << 32
6017                            | (0x3fdULL << 52)
6018                            | f64_frac);
6019     }
6020
6021     result_exp = (380 - f32_exp) / 2;
6022
6023     f64 = recip_sqrt_estimate(f64, s);
6024
6025     val64 = float64_val(f64);
6026
6027     val = ((result_exp & 0xff) << 23)
6028         | ((val64 >> 29)  & 0x7fffff);
6029     return make_float32(val);
6030 }
6031
6032 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
6033 {
6034     float_status *s = fpstp;
6035     float64 f64 = float64_squash_input_denormal(input, s);
6036     uint64_t val = float64_val(f64);
6037     uint64_t f64_sbit = 0x8000000000000000ULL & val;
6038     int64_t f64_exp = extract64(val, 52, 11);
6039     uint64_t f64_frac = extract64(val, 0, 52);
6040     int64_t result_exp;
6041     uint64_t result_frac;
6042
6043     if (float64_is_any_nan(f64)) {
6044         float64 nan = f64;
6045         if (float64_is_signaling_nan(f64)) {
6046             float_raise(float_flag_invalid, s);
6047             nan = float64_maybe_silence_nan(f64);
6048         }
6049         if (s->default_nan_mode) {
6050             nan =  float64_default_nan;
6051         }
6052         return nan;
6053     } else if (float64_is_zero(f64)) {
6054         float_raise(float_flag_divbyzero, s);
6055         return float64_set_sign(float64_infinity, float64_is_neg(f64));
6056     } else if (float64_is_neg(f64)) {
6057         float_raise(float_flag_invalid, s);
6058         return float64_default_nan;
6059     } else if (float64_is_infinity(f64)) {
6060         return float64_zero;
6061     }
6062
6063     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
6064      * preserving the parity of the exponent.  */
6065
6066     if (f64_exp == 0) {
6067         while (extract64(f64_frac, 51, 1) == 0) {
6068             f64_frac = f64_frac << 1;
6069             f64_exp = f64_exp - 1;
6070         }
6071         f64_frac = extract64(f64_frac, 0, 51) << 1;
6072     }
6073
6074     if (extract64(f64_exp, 0, 1) == 0) {
6075         f64 = make_float64(f64_sbit
6076                            | (0x3feULL << 52)
6077                            | f64_frac);
6078     } else {
6079         f64 = make_float64(f64_sbit
6080                            | (0x3fdULL << 52)
6081                            | f64_frac);
6082     }
6083
6084     result_exp = (3068 - f64_exp) / 2;
6085
6086     f64 = recip_sqrt_estimate(f64, s);
6087
6088     result_frac = extract64(float64_val(f64), 0, 52);
6089
6090     return make_float64(f64_sbit |
6091                         ((result_exp & 0x7ff) << 52) |
6092                         result_frac);
6093 }
6094
6095 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
6096 {
6097     float_status *s = fpstp;
6098     float64 f64;
6099
6100     if ((a & 0x80000000) == 0) {
6101         return 0xffffffff;
6102     }
6103
6104     f64 = make_float64((0x3feULL << 52)
6105                        | ((int64_t)(a & 0x7fffffff) << 21));
6106
6107     f64 = recip_estimate(f64, s);
6108
6109     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
6110 }
6111
6112 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
6113 {
6114     float_status *fpst = fpstp;
6115     float64 f64;
6116
6117     if ((a & 0xc0000000) == 0) {
6118         return 0xffffffff;
6119     }
6120
6121     if (a & 0x80000000) {
6122         f64 = make_float64((0x3feULL << 52)
6123                            | ((uint64_t)(a & 0x7fffffff) << 21));
6124     } else { /* bits 31-30 == '01' */
6125         f64 = make_float64((0x3fdULL << 52)
6126                            | ((uint64_t)(a & 0x3fffffff) << 22));
6127     }
6128
6129     f64 = recip_sqrt_estimate(f64, fpst);
6130
6131     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
6132 }
6133
6134 /* VFPv4 fused multiply-accumulate */
6135 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
6136 {
6137     float_status *fpst = fpstp;
6138     return float32_muladd(a, b, c, 0, fpst);
6139 }
6140
6141 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
6142 {
6143     float_status *fpst = fpstp;
6144     return float64_muladd(a, b, c, 0, fpst);
6145 }
6146
6147 /* ARMv8 round to integral */
6148 float32 HELPER(rints_exact)(float32 x, void *fp_status)
6149 {
6150     return float32_round_to_int(x, fp_status);
6151 }
6152
6153 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
6154 {
6155     return float64_round_to_int(x, fp_status);
6156 }
6157
6158 float32 HELPER(rints)(float32 x, void *fp_status)
6159 {
6160     int old_flags = get_float_exception_flags(fp_status), new_flags;
6161     float32 ret;
6162
6163     ret = float32_round_to_int(x, fp_status);
6164
6165     /* Suppress any inexact exceptions the conversion produced */
6166     if (!(old_flags & float_flag_inexact)) {
6167         new_flags = get_float_exception_flags(fp_status);
6168         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
6169     }
6170
6171     return ret;
6172 }
6173
6174 float64 HELPER(rintd)(float64 x, void *fp_status)
6175 {
6176     int old_flags = get_float_exception_flags(fp_status), new_flags;
6177     float64 ret;
6178
6179     ret = float64_round_to_int(x, fp_status);
6180
6181     new_flags = get_float_exception_flags(fp_status);
6182
6183     /* Suppress any inexact exceptions the conversion produced */
6184     if (!(old_flags & float_flag_inexact)) {
6185         new_flags = get_float_exception_flags(fp_status);
6186         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
6187     }
6188
6189     return ret;
6190 }
6191
6192 /* Convert ARM rounding mode to softfloat */
6193 int arm_rmode_to_sf(int rmode)
6194 {
6195     switch (rmode) {
6196     case FPROUNDING_TIEAWAY:
6197         rmode = float_round_ties_away;
6198         break;
6199     case FPROUNDING_ODD:
6200         /* FIXME: add support for TIEAWAY and ODD */
6201         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
6202                       rmode);
6203     case FPROUNDING_TIEEVEN:
6204     default:
6205         rmode = float_round_nearest_even;
6206         break;
6207     case FPROUNDING_POSINF:
6208         rmode = float_round_up;
6209         break;
6210     case FPROUNDING_NEGINF:
6211         rmode = float_round_down;
6212         break;
6213     case FPROUNDING_ZERO:
6214         rmode = float_round_to_zero;
6215         break;
6216     }
6217     return rmode;
6218 }
6219
6220 /* CRC helpers.
6221  * The upper bytes of val (above the number specified by 'bytes') must have
6222  * been zeroed out by the caller.
6223  */
6224 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
6225 {
6226     uint8_t buf[4];
6227
6228     stl_le_p(buf, val);
6229
6230     /* zlib crc32 converts the accumulator and output to one's complement.  */
6231     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
6232 }
6233
6234 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
6235 {
6236     uint8_t buf[4];
6237
6238     stl_le_p(buf, val);
6239
6240     /* Linux crc32c converts the output to one's complement.  */
6241     return crc32c(acc, buf, bytes) ^ 0xffffffff;
6242 }