hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     uint64_t hpet_offset;
  63     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  64     uint32_t flags;
  65     uint8_t rtc_irq_level;
  66     uint8_t num_timers;
  67     HPETTimer timer[HPET_MAX_TIMERS];
  68
  69     /* Memory-mapped, software visible registers */
  70     uint64_t capability;        /* capabilities */
  71     uint64_t config;            /* configuration */
  72     uint64_t isr;               /* interrupt status reg */
  73     uint64_t hpet_counter;      /* main counter */
  74     uint8_t  hpet_id;           /* instance id */
  75 } HPETState;
  76
  77 static uint32_t hpet_in_legacy_mode(HPETState *s)
  78 {
  79     return s->config & HPET_CFG_LEGACY;
  80 }
  81
  82 static uint32_t timer_int_route(struct HPETTimer *timer)
  83 {
  84     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  85 }
  86
  87 static uint32_t timer_fsb_route(HPETTimer *t)
  88 {
  89     return t->config & HPET_TN_FSB_ENABLE;
  90 }
  91
  92 static uint32_t hpet_enabled(HPETState *s)
  93 {
  94     return s->config & HPET_CFG_ENABLE;
  95 }
  96
  97 static uint32_t timer_is_periodic(HPETTimer *t)
  98 {
  99     return t->config & HPET_TN_PERIODIC;
 100 }
 101
 102 static uint32_t timer_enabled(HPETTimer *t)
 103 {
 104     return t->config & HPET_TN_ENABLE;
 105 }
 106
 107 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 108 {
 109     return ((int32_t)(b) - (int32_t)(a) < 0);
 110 }
 111
 112 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 113 {
 114     return ((int64_t)(b) - (int64_t)(a) < 0);
 115 }
 116
 117 static uint64_t ticks_to_ns(uint64_t value)
 118 {
 119     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 120 }
 121
 122 static uint64_t ns_to_ticks(uint64_t value)
 123 {
 124     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 125 }
 126
 127 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 128 {
 129     new &= mask;
 130     new |= old & ~mask;
 131     return new;
 132 }
 133
 134 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 135 {
 136     return (!(old & mask) && (new & mask));
 137 }
 138
 139 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 140 {
 141     return ((old & mask) && !(new & mask));
 142 }
 143
 144 static uint64_t hpet_get_ticks(HPETState *s)
 145 {
 146     return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
 147 }
 148
 149 /*
 150  * calculate diff between comparator value and current ticks
 151  */
 152 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 153 {
 154
 155     if (t->config & HPET_TN_32BIT) {
 156         uint32_t diff, cmp;
 157
 158         cmp = (uint32_t)t->cmp;
 159         diff = cmp - (uint32_t)current;
 160         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 161         return (uint64_t)diff;
 162     } else {
 163         uint64_t diff, cmp;
 164
 165         cmp = t->cmp;
 166         diff = cmp - current;
 167         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 168         return diff;
 169     }
 170 }
 171
 172 static void update_irq(struct HPETTimer *timer, int set)
 173 {
 174     uint64_t mask;
 175     HPETState *s;
 176     int route;
 177
 178     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 179         /* if LegacyReplacementRoute bit is set, HPET specification requires
 180          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 181          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 182          */
 183         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 184     } else {
 185         route = timer_int_route(timer);
 186     }
 187     s = timer->state;
 188     mask = 1 << timer->tn;
 189     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 190         s->isr &= ~mask;
 191         if (!timer_fsb_route(timer)) {
 192             qemu_irq_lower(s->irqs[route]);
 193         }
 194     } else if (timer_fsb_route(timer)) {
 195         stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 196     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 197         s->isr |= mask;
 198         qemu_irq_raise(s->irqs[route]);
 199     } else {
 200         s->isr &= ~mask;
 201         qemu_irq_pulse(s->irqs[route]);
 202     }
 203 }
 204
 205 static void hpet_pre_save(void *opaque)
 206 {
 207     HPETState *s = opaque;
 208
 209     /* save current counter value */
 210     s->hpet_counter = hpet_get_ticks(s);
 211 }
 212
 213 static int hpet_pre_load(void *opaque)
 214 {
 215     HPETState *s = opaque;
 216
 217     /* version 1 only supports 3, later versions will load the actual value */
 218     s->num_timers = HPET_MIN_TIMERS;
 219     return 0;
 220 }
 221
 222 static int hpet_post_load(void *opaque, int version_id)
 223 {
 224     HPETState *s = opaque;
 225
 226     /* Recalculate the offset between the main counter and guest time */
 227     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 228
 229     /* Push number of timers into capability returned via HPET_ID */
 230     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 231     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 232     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 233
 234     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 235     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 236     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 237         s->flags |= 1 << HPET_MSI_SUPPORT;
 238     }
 239     return 0;
 240 }
 241
 242 static const VMStateDescription vmstate_hpet_timer = {
 243     .name = "hpet_timer",
 244     .version_id = 1,
 245     .minimum_version_id = 1,
 246     .minimum_version_id_old = 1,
 247     .fields      = (VMStateField []) {
 248         VMSTATE_UINT8(tn, HPETTimer),
 249         VMSTATE_UINT64(config, HPETTimer),
 250         VMSTATE_UINT64(cmp, HPETTimer),
 251         VMSTATE_UINT64(fsb, HPETTimer),
 252         VMSTATE_UINT64(period, HPETTimer),
 253         VMSTATE_UINT8(wrap_flag, HPETTimer),
 254         VMSTATE_TIMER(qemu_timer, HPETTimer),
 255         VMSTATE_END_OF_LIST()
 256     }
 257 };
 258
 259 static const VMStateDescription vmstate_hpet = {
 260     .name = "hpet",
 261     .version_id = 2,
 262     .minimum_version_id = 1,
 263     .minimum_version_id_old = 1,
 264     .pre_save = hpet_pre_save,
 265     .pre_load = hpet_pre_load,
 266     .post_load = hpet_post_load,
 267     .fields      = (VMStateField []) {
 268         VMSTATE_UINT64(config, HPETState),
 269         VMSTATE_UINT64(isr, HPETState),
 270         VMSTATE_UINT64(hpet_counter, HPETState),
 271         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 272         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 273                                     vmstate_hpet_timer, HPETTimer),
 274         VMSTATE_END_OF_LIST()
 275     }
 276 };
 277
 278 /*
 279  * timer expiration callback
 280  */
 281 static void hpet_timer(void *opaque)
 282 {
 283     HPETTimer *t = opaque;
 284     uint64_t diff;
 285
 286     uint64_t period = t->period;
 287     uint64_t cur_tick = hpet_get_ticks(t->state);
 288
 289     if (timer_is_periodic(t) && period != 0) {
 290         if (t->config & HPET_TN_32BIT) {
 291             while (hpet_time_after(cur_tick, t->cmp)) {
 292                 t->cmp = (uint32_t)(t->cmp + t->period);
 293             }
 294         } else {
 295             while (hpet_time_after64(cur_tick, t->cmp)) {
 296                 t->cmp += period;
 297             }
 298         }
 299         diff = hpet_calculate_diff(t, cur_tick);
 300         qemu_mod_timer(t->qemu_timer,
 301                        qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 302     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 303         if (t->wrap_flag) {
 304             diff = hpet_calculate_diff(t, cur_tick);
 305             qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
 306                            (int64_t)ticks_to_ns(diff));
 307             t->wrap_flag = 0;
 308         }
 309     }
 310     update_irq(t, 1);
 311 }
 312
 313 static void hpet_set_timer(HPETTimer *t)
 314 {
 315     uint64_t diff;
 316     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 317     uint64_t cur_tick = hpet_get_ticks(t->state);
 318
 319     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 320     t->wrap_flag = 0;
 321     diff = hpet_calculate_diff(t, cur_tick);
 322
 323     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 324      * counter wraps in addition to an interrupt with comparator match.
 325      */
 326     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 327         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 328         if (wrap_diff < (uint32_t)diff) {
 329             diff = wrap_diff;
 330             t->wrap_flag = 1;
 331         }
 332     }
 333     qemu_mod_timer(t->qemu_timer,
 334                    qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 335 }
 336
 337 static void hpet_del_timer(HPETTimer *t)
 338 {
 339     qemu_del_timer(t->qemu_timer);
 340     update_irq(t, 0);
 341 }
 342
 343 #ifdef HPET_DEBUG
 344 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 345 {
 346     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 347     return 0;
 348 }
 349
 350 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 351 {
 352     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 353     return 0;
 354 }
 355 #endif
 356
 357 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 358 {
 359     HPETState *s = opaque;
 360     uint64_t cur_tick, index;
 361
 362     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 363     index = addr;
 364     /*address range of all TN regs*/
 365     if (index >= 0x100 && index <= 0x3ff) {
 366         uint8_t timer_id = (addr - 0x100) / 0x20;
 367         HPETTimer *timer = &s->timer[timer_id];
 368
 369         if (timer_id > s->num_timers) {
 370             DPRINTF("qemu: timer id out of range\n");
 371             return 0;
 372         }
 373
 374         switch ((addr - 0x100) % 0x20) {
 375         case HPET_TN_CFG:
 376             return timer->config;
 377         case HPET_TN_CFG + 4: // Interrupt capabilities
 378             return timer->config >> 32;
 379         case HPET_TN_CMP: // comparator register
 380             return timer->cmp;
 381         case HPET_TN_CMP + 4:
 382             return timer->cmp >> 32;
 383         case HPET_TN_ROUTE:
 384             return timer->fsb;
 385         case HPET_TN_ROUTE + 4:
 386             return timer->fsb >> 32;
 387         default:
 388             DPRINTF("qemu: invalid hpet_ram_readl\n");
 389             break;
 390         }
 391     } else {
 392         switch (index) {
 393         case HPET_ID:
 394             return s->capability;
 395         case HPET_PERIOD:
 396             return s->capability >> 32;
 397         case HPET_CFG:
 398             return s->config;
 399         case HPET_CFG + 4:
 400             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
 401             return 0;
 402         case HPET_COUNTER:
 403             if (hpet_enabled(s)) {
 404                 cur_tick = hpet_get_ticks(s);
 405             } else {
 406                 cur_tick = s->hpet_counter;
 407             }
 408             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 409             return cur_tick;
 410         case HPET_COUNTER + 4:
 411             if (hpet_enabled(s)) {
 412                 cur_tick = hpet_get_ticks(s);
 413             } else {
 414                 cur_tick = s->hpet_counter;
 415             }
 416             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 417             return cur_tick >> 32;
 418         case HPET_STATUS:
 419             return s->isr;
 420         default:
 421             DPRINTF("qemu: invalid hpet_ram_readl\n");
 422             break;
 423         }
 424     }
 425     return 0;
 426 }
 427
 428 #ifdef HPET_DEBUG
 429 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 430                             uint32_t value)
 431 {
 432     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 433            addr, value);
 434 }
 435
 436 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 437                             uint32_t value)
 438 {
 439     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 440            addr, value);
 441 }
 442 #endif
 443
 444 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 445                             uint32_t value)
 446 {
 447     int i;
 448     HPETState *s = opaque;
 449     uint64_t old_val, new_val, val, index;
 450
 451     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 452     index = addr;
 453     old_val = hpet_ram_readl(opaque, addr);
 454     new_val = value;
 455
 456     /*address range of all TN regs*/
 457     if (index >= 0x100 && index <= 0x3ff) {
 458         uint8_t timer_id = (addr - 0x100) / 0x20;
 459         HPETTimer *timer = &s->timer[timer_id];
 460
 461         DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
 462         if (timer_id > s->num_timers) {
 463             DPRINTF("qemu: timer id out of range\n");
 464             return;
 465         }
 466         switch ((addr - 0x100) % 0x20) {
 467         case HPET_TN_CFG:
 468             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 469             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 470                 update_irq(timer, 0);
 471             }
 472             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 473             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 474             if (new_val & HPET_TN_32BIT) {
 475                 timer->cmp = (uint32_t)timer->cmp;
 476                 timer->period = (uint32_t)timer->period;
 477             }
 478             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 479                 hpet_set_timer(timer);
 480             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 481                 hpet_del_timer(timer);
 482             }
 483             break;
 484         case HPET_TN_CFG + 4: // Interrupt capabilities
 485             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 486             break;
 487         case HPET_TN_CMP: // comparator register
 488             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
 489             if (timer->config & HPET_TN_32BIT) {
 490                 new_val = (uint32_t)new_val;
 491             }
 492             if (!timer_is_periodic(timer)
 493                 || (timer->config & HPET_TN_SETVAL)) {
 494                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 495             }
 496             if (timer_is_periodic(timer)) {
 497                 /*
 498                  * FIXME: Clamp period to reasonable min value?
 499                  * Clamp period to reasonable max value
 500                  */
 501                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 502                 timer->period =
 503                     (timer->period & 0xffffffff00000000ULL) | new_val;
 504             }
 505             timer->config &= ~HPET_TN_SETVAL;
 506             if (hpet_enabled(s)) {
 507                 hpet_set_timer(timer);
 508             }
 509             break;
 510         case HPET_TN_CMP + 4: // comparator register high order
 511             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 512             if (!timer_is_periodic(timer)
 513                 || (timer->config & HPET_TN_SETVAL)) {
 514                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 515             } else {
 516                 /*
 517                  * FIXME: Clamp period to reasonable min value?
 518                  * Clamp period to reasonable max value
 519                  */
 520                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 521                 timer->period =
 522                     (timer->period & 0xffffffffULL) | new_val << 32;
 523                 }
 524                 timer->config &= ~HPET_TN_SETVAL;
 525                 if (hpet_enabled(s)) {
 526                     hpet_set_timer(timer);
 527                 }
 528                 break;
 529         case HPET_TN_ROUTE:
 530             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 531             break;
 532         case HPET_TN_ROUTE + 4:
 533             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 534             break;
 535         default:
 536             DPRINTF("qemu: invalid hpet_ram_writel\n");
 537             break;
 538         }
 539         return;
 540     } else {
 541         switch (index) {
 542         case HPET_ID:
 543             return;
 544         case HPET_CFG:
 545             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 546             s->config = (s->config & 0xffffffff00000000ULL) | val;
 547             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 548                 /* Enable main counter and interrupt generation. */
 549                 s->hpet_offset =
 550                     ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 551                 for (i = 0; i < s->num_timers; i++) {
 552                     if ((&s->timer[i])->cmp != ~0ULL) {
 553                         hpet_set_timer(&s->timer[i]);
 554                     }
 555                 }
 556             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 557                 /* Halt main counter and disable interrupt generation. */
 558                 s->hpet_counter = hpet_get_ticks(s);
 559                 for (i = 0; i < s->num_timers; i++) {
 560                     hpet_del_timer(&s->timer[i]);
 561                 }
 562             }
 563             /* i8254 and RTC are disabled when HPET is in legacy mode */
 564             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 565                 hpet_pit_disable();
 566                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 567             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 568                 hpet_pit_enable();
 569                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 570             }
 571             break;
 572         case HPET_CFG + 4:
 573             DPRINTF("qemu: invalid HPET_CFG+4 write\n");
 574             break;
 575         case HPET_STATUS:
 576             val = new_val & s->isr;
 577             for (i = 0; i < s->num_timers; i++) {
 578                 if (val & (1 << i)) {
 579                     update_irq(&s->timer[i], 0);
 580                 }
 581             }
 582             break;
 583         case HPET_COUNTER:
 584             if (hpet_enabled(s)) {
 585                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 586             }
 587             s->hpet_counter =
 588                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 589             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 590                     value, s->hpet_counter);
 591             break;
 592         case HPET_COUNTER + 4:
 593             if (hpet_enabled(s)) {
 594                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 595             }
 596             s->hpet_counter =
 597                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 598             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 599                     value, s->hpet_counter);
 600             break;
 601         default:
 602             DPRINTF("qemu: invalid hpet_ram_writel\n");
 603             break;
 604         }
 605     }
 606 }
 607
 608 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 609 #ifdef HPET_DEBUG
 610     hpet_ram_readb,
 611     hpet_ram_readw,
 612 #else
 613     NULL,
 614     NULL,
 615 #endif
 616     hpet_ram_readl,
 617 };
 618
 619 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 620 #ifdef HPET_DEBUG
 621     hpet_ram_writeb,
 622     hpet_ram_writew,
 623 #else
 624     NULL,
 625     NULL,
 626 #endif
 627     hpet_ram_writel,
 628 };
 629
 630 static void hpet_reset(DeviceState *d)
 631 {
 632     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 633     int i;
 634     static int count = 0;
 635
 636     for (i = 0; i < s->num_timers; i++) {
 637         HPETTimer *timer = &s->timer[i];
 638
 639         hpet_del_timer(timer);
 640         timer->cmp = ~0ULL;
 641         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 642         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 643             timer->config |= HPET_TN_FSB_CAP;
 644         }
 645         /* advertise availability of ioapic inti2 */
 646         timer->config |=  0x00000004ULL << 32;
 647         timer->period = 0ULL;
 648         timer->wrap_flag = 0;
 649     }
 650
 651     s->hpet_counter = 0ULL;
 652     s->hpet_offset = 0ULL;
 653     s->config = 0ULL;
 654     if (count > 0) {
 655         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 656          * because hpet is taking over for pit here. On subsequent invocations,
 657          * hpet_reset is called due to system reset. At this point control must
 658          * be returned to pit until SW reenables hpet.
 659          */
 660         hpet_pit_enable();
 661     }
 662     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 663     hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
 664     count = 1;
 665 }
 666
 667 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 668 {
 669     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 670
 671     s->rtc_irq_level = level;
 672     if (!hpet_in_legacy_mode(s)) {
 673         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 674     }
 675 }
 676
 677 static int hpet_init(SysBusDevice *dev)
 678 {
 679     HPETState *s = FROM_SYSBUS(HPETState, dev);
 680     int i, iomemtype;
 681     HPETTimer *timer;
 682
 683     if (hpet_cfg.count == UINT8_MAX) {
 684         /* first instance */
 685         hpet_cfg.count = 0;
 686     }
 687
 688     if (hpet_cfg.count == 8) {
 689         fprintf(stderr, "Only 8 instances of HPET is allowed\n");
 690         return -1;
 691     }
 692
 693     s->hpet_id = hpet_cfg.count++;
 694
 695     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 696         sysbus_init_irq(dev, &s->irqs[i]);
 697     }
 698
 699     if (s->num_timers < HPET_MIN_TIMERS) {
 700         s->num_timers = HPET_MIN_TIMERS;
 701     } else if (s->num_timers > HPET_MAX_TIMERS) {
 702         s->num_timers = HPET_MAX_TIMERS;
 703     }
 704     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 705         timer = &s->timer[i];
 706         timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
 707         timer->tn = i;
 708         timer->state = s;
 709     }
 710
 711     /* 64-bit main counter; LegacyReplacementRoute. */
 712     s->capability = 0x8086a001ULL;
 713     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 714     s->capability |= ((HPET_CLK_PERIOD) << 32);
 715
 716     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 717
 718     /* HPET Area */
 719     iomemtype = cpu_register_io_memory(hpet_ram_read,
 720                                        hpet_ram_write, s,
 721                                        DEVICE_NATIVE_ENDIAN);
 722     sysbus_init_mmio(dev, 0x400, iomemtype);
 723     return 0;
 724 }
 725
 726 static SysBusDeviceInfo hpet_device_info = {
 727     .qdev.name    = "hpet",
 728     .qdev.size    = sizeof(HPETState),
 729     .qdev.no_user = 1,
 730     .qdev.vmsd    = &vmstate_hpet,
 731     .qdev.reset   = hpet_reset,
 732     .init         = hpet_init,
 733     .qdev.props = (Property[]) {
 734         DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 735         DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 736         DEFINE_PROP_END_OF_LIST(),
 737     },
 738 };
 739
 740 static void hpet_register_device(void)
 741 {
 742     sysbus_register_withprop(&hpet_device_info);
 743 }
 744
 745 device_init(hpet_register_device)