hw/net/ftgmac100.c

   1 /*
   2  * Faraday FTGMAC100 Gigabit Ethernet
   3  *
   4  * Copyright (C) 2016-2017, IBM Corporation.
   5  *
   6  * Based on Coldfire Fast Ethernet Controller emulation.
   7  *
   8  * Copyright (c) 2007 CodeSourcery.
   9  *
  10  * This code is licensed under the GPL version 2 or later. See the
  11  * COPYING file in the top-level directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/irq.h"
  16 #include "hw/net/ftgmac100.h"
  17 #include "sysemu/dma.h"
  18 #include "qapi/error.h"
  19 #include "qemu/log.h"
  20 #include "qemu/module.h"
  21 #include "net/checksum.h"
  22 #include "net/eth.h"
  23 #include "hw/net/mii.h"
  24 #include "hw/qdev-properties.h"
  25 #include "migration/vmstate.h"
  26
  27 /* For crc32 */
  28 #include <zlib.h>
  29
  30 /*
  31  * FTGMAC100 registers
  32  */
  33 #define FTGMAC100_ISR             0x00
  34 #define FTGMAC100_IER             0x04
  35 #define FTGMAC100_MAC_MADR        0x08
  36 #define FTGMAC100_MAC_LADR        0x0c
  37 #define FTGMAC100_MATH0           0x10
  38 #define FTGMAC100_MATH1           0x14
  39 #define FTGMAC100_NPTXPD          0x18
  40 #define FTGMAC100_RXPD            0x1C
  41 #define FTGMAC100_NPTXR_BADR      0x20
  42 #define FTGMAC100_RXR_BADR        0x24
  43 #define FTGMAC100_HPTXPD          0x28
  44 #define FTGMAC100_HPTXR_BADR      0x2c
  45 #define FTGMAC100_ITC             0x30
  46 #define FTGMAC100_APTC            0x34
  47 #define FTGMAC100_DBLAC           0x38
  48 #define FTGMAC100_REVR            0x40
  49 #define FTGMAC100_FEAR1           0x44
  50 #define FTGMAC100_RBSR            0x4c
  51 #define FTGMAC100_TPAFCR          0x48
  52
  53 #define FTGMAC100_MACCR           0x50
  54 #define FTGMAC100_MACSR           0x54
  55 #define FTGMAC100_PHYCR           0x60
  56 #define FTGMAC100_PHYDATA         0x64
  57 #define FTGMAC100_FCR             0x68
  58
  59 /*
  60  * Interrupt status register & interrupt enable register
  61  */
  62 #define FTGMAC100_INT_RPKT_BUF    (1 << 0)
  63 #define FTGMAC100_INT_RPKT_FIFO   (1 << 1)
  64 #define FTGMAC100_INT_NO_RXBUF    (1 << 2)
  65 #define FTGMAC100_INT_RPKT_LOST   (1 << 3)
  66 #define FTGMAC100_INT_XPKT_ETH    (1 << 4)
  67 #define FTGMAC100_INT_XPKT_FIFO   (1 << 5)
  68 #define FTGMAC100_INT_NO_NPTXBUF  (1 << 6)
  69 #define FTGMAC100_INT_XPKT_LOST   (1 << 7)
  70 #define FTGMAC100_INT_AHB_ERR     (1 << 8)
  71 #define FTGMAC100_INT_PHYSTS_CHG  (1 << 9)
  72 #define FTGMAC100_INT_NO_HPTXBUF  (1 << 10)
  73
  74 /*
  75  * Automatic polling timer control register
  76  */
  77 #define FTGMAC100_APTC_RXPOLL_CNT(x)        ((x) & 0xf)
  78 #define FTGMAC100_APTC_RXPOLL_TIME_SEL      (1 << 4)
  79 #define FTGMAC100_APTC_TXPOLL_CNT(x)        (((x) >> 8) & 0xf)
  80 #define FTGMAC100_APTC_TXPOLL_TIME_SEL      (1 << 12)
  81
  82 /*
  83  * DMA burst length and arbitration control register
  84  */
  85 #define FTGMAC100_DBLAC_RXBURST_SIZE(x)     (((x) >> 8) & 0x3)
  86 #define FTGMAC100_DBLAC_TXBURST_SIZE(x)     (((x) >> 10) & 0x3)
  87 #define FTGMAC100_DBLAC_RXDES_SIZE(x)       ((((x) >> 12) & 0xf) * 8)
  88 #define FTGMAC100_DBLAC_TXDES_SIZE(x)       ((((x) >> 16) & 0xf) * 8)
  89 #define FTGMAC100_DBLAC_IFG_CNT(x)          (((x) >> 20) & 0x7)
  90 #define FTGMAC100_DBLAC_IFG_INC             (1 << 23)
  91
  92 /*
  93  * PHY control register
  94  */
  95 #define FTGMAC100_PHYCR_MIIRD               (1 << 26)
  96 #define FTGMAC100_PHYCR_MIIWR               (1 << 27)
  97
  98 #define FTGMAC100_PHYCR_DEV(x)              (((x) >> 16) & 0x1f)
  99 #define FTGMAC100_PHYCR_REG(x)              (((x) >> 21) & 0x1f)
 100
 101 /*
 102  * PHY data register
 103  */
 104 #define FTGMAC100_PHYDATA_MIIWDATA(x)       ((x) & 0xffff)
 105 #define FTGMAC100_PHYDATA_MIIRDATA(x)       (((x) >> 16) & 0xffff)
 106
 107 /*
 108  * PHY control register - New MDC/MDIO interface
 109  */
 110 #define FTGMAC100_PHYCR_NEW_DATA(x)     (((x) >> 16) & 0xffff)
 111 #define FTGMAC100_PHYCR_NEW_FIRE        (1 << 15)
 112 #define FTGMAC100_PHYCR_NEW_ST_22       (1 << 12)
 113 #define FTGMAC100_PHYCR_NEW_OP(x)       (((x) >> 10) & 3)
 114 #define   FTGMAC100_PHYCR_NEW_OP_WRITE    0x1
 115 #define   FTGMAC100_PHYCR_NEW_OP_READ     0x2
 116 #define FTGMAC100_PHYCR_NEW_DEV(x)      (((x) >> 5) & 0x1f)
 117 #define FTGMAC100_PHYCR_NEW_REG(x)      ((x) & 0x1f)
 118
 119 /*
 120  * Feature Register
 121  */
 122 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE   (1 << 31)
 123
 124 /*
 125  * MAC control register
 126  */
 127 #define FTGMAC100_MACCR_TXDMA_EN         (1 << 0)
 128 #define FTGMAC100_MACCR_RXDMA_EN         (1 << 1)
 129 #define FTGMAC100_MACCR_TXMAC_EN         (1 << 2)
 130 #define FTGMAC100_MACCR_RXMAC_EN         (1 << 3)
 131 #define FTGMAC100_MACCR_RM_VLAN          (1 << 4)
 132 #define FTGMAC100_MACCR_HPTXR_EN         (1 << 5)
 133 #define FTGMAC100_MACCR_LOOP_EN          (1 << 6)
 134 #define FTGMAC100_MACCR_ENRX_IN_HALFTX   (1 << 7)
 135 #define FTGMAC100_MACCR_FULLDUP          (1 << 8)
 136 #define FTGMAC100_MACCR_GIGA_MODE        (1 << 9)
 137 #define FTGMAC100_MACCR_CRC_APD          (1 << 10) /* not needed */
 138 #define FTGMAC100_MACCR_RX_RUNT          (1 << 12)
 139 #define FTGMAC100_MACCR_JUMBO_LF         (1 << 13)
 140 #define FTGMAC100_MACCR_RX_ALL           (1 << 14)
 141 #define FTGMAC100_MACCR_HT_MULTI_EN      (1 << 15)
 142 #define FTGMAC100_MACCR_RX_MULTIPKT      (1 << 16)
 143 #define FTGMAC100_MACCR_RX_BROADPKT      (1 << 17)
 144 #define FTGMAC100_MACCR_DISCARD_CRCERR   (1 << 18)
 145 #define FTGMAC100_MACCR_FAST_MODE        (1 << 19)
 146 #define FTGMAC100_MACCR_SW_RST           (1 << 31)
 147
 148 /*
 149  * Transmit descriptor
 150  */
 151 #define FTGMAC100_TXDES0_TXBUF_SIZE(x)   ((x) & 0x3fff)
 152 #define FTGMAC100_TXDES0_EDOTR           (1 << 15)
 153 #define FTGMAC100_TXDES0_CRC_ERR         (1 << 19)
 154 #define FTGMAC100_TXDES0_LTS             (1 << 28)
 155 #define FTGMAC100_TXDES0_FTS             (1 << 29)
 156 #define FTGMAC100_TXDES0_EDOTR_ASPEED    (1 << 30)
 157 #define FTGMAC100_TXDES0_TXDMA_OWN       (1 << 31)
 158
 159 #define FTGMAC100_TXDES1_VLANTAG_CI(x)   ((x) & 0xffff)
 160 #define FTGMAC100_TXDES1_INS_VLANTAG     (1 << 16)
 161 #define FTGMAC100_TXDES1_TCP_CHKSUM      (1 << 17)
 162 #define FTGMAC100_TXDES1_UDP_CHKSUM      (1 << 18)
 163 #define FTGMAC100_TXDES1_IP_CHKSUM       (1 << 19)
 164 #define FTGMAC100_TXDES1_LLC             (1 << 22)
 165 #define FTGMAC100_TXDES1_TX2FIC          (1 << 30)
 166 #define FTGMAC100_TXDES1_TXIC            (1 << 31)
 167
 168 /*
 169  * Receive descriptor
 170  */
 171 #define FTGMAC100_RXDES0_VDBC            0x3fff
 172 #define FTGMAC100_RXDES0_EDORR           (1 << 15)
 173 #define FTGMAC100_RXDES0_MULTICAST       (1 << 16)
 174 #define FTGMAC100_RXDES0_BROADCAST       (1 << 17)
 175 #define FTGMAC100_RXDES0_RX_ERR          (1 << 18)
 176 #define FTGMAC100_RXDES0_CRC_ERR         (1 << 19)
 177 #define FTGMAC100_RXDES0_FTL             (1 << 20)
 178 #define FTGMAC100_RXDES0_RUNT            (1 << 21)
 179 #define FTGMAC100_RXDES0_RX_ODD_NB       (1 << 22)
 180 #define FTGMAC100_RXDES0_FIFO_FULL       (1 << 23)
 181 #define FTGMAC100_RXDES0_PAUSE_OPCODE    (1 << 24)
 182 #define FTGMAC100_RXDES0_PAUSE_FRAME     (1 << 25)
 183 #define FTGMAC100_RXDES0_LRS             (1 << 28)
 184 #define FTGMAC100_RXDES0_FRS             (1 << 29)
 185 #define FTGMAC100_RXDES0_EDORR_ASPEED    (1 << 30)
 186 #define FTGMAC100_RXDES0_RXPKT_RDY       (1 << 31)
 187
 188 #define FTGMAC100_RXDES1_VLANTAG_CI      0xffff
 189 #define FTGMAC100_RXDES1_PROT_MASK       (0x3 << 20)
 190 #define FTGMAC100_RXDES1_PROT_NONIP      (0x0 << 20)
 191 #define FTGMAC100_RXDES1_PROT_IP         (0x1 << 20)
 192 #define FTGMAC100_RXDES1_PROT_TCPIP      (0x2 << 20)
 193 #define FTGMAC100_RXDES1_PROT_UDPIP      (0x3 << 20)
 194 #define FTGMAC100_RXDES1_LLC             (1 << 22)
 195 #define FTGMAC100_RXDES1_DF              (1 << 23)
 196 #define FTGMAC100_RXDES1_VLANTAG_AVAIL   (1 << 24)
 197 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR  (1 << 25)
 198 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR  (1 << 26)
 199 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR   (1 << 27)
 200
 201 /*
 202  * Receive and transmit Buffer Descriptor
 203  */
 204 typedef struct {
 205     uint32_t        des0;
 206     uint32_t        des1;
 207     uint32_t        des2;        /* not used by HW */
 208     uint32_t        des3;
 209 } FTGMAC100Desc;
 210
 211 #define FTGMAC100_DESC_ALIGNMENT 16
 212
 213 /*
 214  * Specific RTL8211E MII Registers
 215  */
 216 #define RTL8211E_MII_PHYCR        16 /* PHY Specific Control */
 217 #define RTL8211E_MII_PHYSR        17 /* PHY Specific Status */
 218 #define RTL8211E_MII_INER         18 /* Interrupt Enable */
 219 #define RTL8211E_MII_INSR         19 /* Interrupt Status */
 220 #define RTL8211E_MII_RXERC        24 /* Receive Error Counter */
 221 #define RTL8211E_MII_LDPSR        27 /* Link Down Power Saving */
 222 #define RTL8211E_MII_EPAGSR       30 /* Extension Page Select */
 223 #define RTL8211E_MII_PAGSEL       31 /* Page Select */
 224
 225 /*
 226  * RTL8211E Interrupt Status
 227  */
 228 #define PHY_INT_AUTONEG_ERROR       (1 << 15)
 229 #define PHY_INT_PAGE_RECV           (1 << 12)
 230 #define PHY_INT_AUTONEG_COMPLETE    (1 << 11)
 231 #define PHY_INT_LINK_STATUS         (1 << 10)
 232 #define PHY_INT_ERROR               (1 << 9)
 233 #define PHY_INT_DOWN                (1 << 8)
 234 #define PHY_INT_JABBER              (1 << 0)
 235
 236 /*
 237  * Max frame size for the receiving buffer
 238  */
 239 #define FTGMAC100_MAX_FRAME_SIZE    9220
 240
 241 /* Limits depending on the type of the frame
 242  *
 243  *   9216 for Jumbo frames (+ 4 for VLAN)
 244  *   1518 for other frames (+ 4 for VLAN)
 245  */
 246 static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
 247 {
 248     int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
 249
 250     return max + (proto == ETH_P_VLAN ? 4 : 0);
 251 }
 252
 253 static void ftgmac100_update_irq(FTGMAC100State *s)
 254 {
 255     qemu_set_irq(s->irq, s->isr & s->ier);
 256 }
 257
 258 /*
 259  * The MII phy could raise a GPIO to the processor which in turn
 260  * could be handled as an interrpt by the OS.
 261  * For now we don't handle any GPIO/interrupt line, so the OS will
 262  * have to poll for the PHY status.
 263  */
 264 static void phy_update_irq(FTGMAC100State *s)
 265 {
 266     ftgmac100_update_irq(s);
 267 }
 268
 269 static void phy_update_link(FTGMAC100State *s)
 270 {
 271     /* Autonegotiation status mirrors link status.  */
 272     if (qemu_get_queue(s->nic)->link_down) {
 273         s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
 274         s->phy_int |= PHY_INT_DOWN;
 275     } else {
 276         s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
 277         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
 278     }
 279     phy_update_irq(s);
 280 }
 281
 282 static void ftgmac100_set_link(NetClientState *nc)
 283 {
 284     phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc)));
 285 }
 286
 287 static void phy_reset(FTGMAC100State *s)
 288 {
 289     s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
 290                      MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS |
 291                      MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST |
 292                      MII_BMSR_EXTCAP);
 293     s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000);
 294     s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD |
 295                         MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
 296                         MII_ANAR_CSMACD);
 297     s->phy_int_mask = 0;
 298     s->phy_int = 0;
 299 }
 300
 301 static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg)
 302 {
 303     uint16_t val;
 304
 305     switch (reg) {
 306     case MII_BMCR: /* Basic Control */
 307         val = s->phy_control;
 308         break;
 309     case MII_BMSR: /* Basic Status */
 310         val = s->phy_status;
 311         break;
 312     case MII_PHYID1: /* ID1 */
 313         val = RTL8211E_PHYID1;
 314         break;
 315     case MII_PHYID2: /* ID2 */
 316         val = RTL8211E_PHYID2;
 317         break;
 318     case MII_ANAR: /* Auto-neg advertisement */
 319         val = s->phy_advertise;
 320         break;
 321     case MII_ANLPAR: /* Auto-neg Link Partner Ability */
 322         val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD |
 323                MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 |
 324                MII_ANLPAR_CSMACD);
 325         break;
 326     case MII_ANER: /* Auto-neg Expansion */
 327         val = MII_ANER_NWAY;
 328         break;
 329     case MII_CTRL1000: /* 1000BASE-T control  */
 330         val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL);
 331         break;
 332     case MII_STAT1000: /* 1000BASE-T status  */
 333         val = MII_STAT1000_FULL;
 334         break;
 335     case RTL8211E_MII_INSR:  /* Interrupt status.  */
 336         val = s->phy_int;
 337         s->phy_int = 0;
 338         phy_update_irq(s);
 339         break;
 340     case RTL8211E_MII_INER:  /* Interrupt enable */
 341         val = s->phy_int_mask;
 342         break;
 343     case RTL8211E_MII_PHYCR:
 344     case RTL8211E_MII_PHYSR:
 345     case RTL8211E_MII_RXERC:
 346     case RTL8211E_MII_LDPSR:
 347     case RTL8211E_MII_EPAGSR:
 348     case RTL8211E_MII_PAGSEL:
 349         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
 350                       __func__, reg);
 351         val = 0;
 352         break;
 353     default:
 354         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
 355                       __func__, reg);
 356         val = 0;
 357         break;
 358     }
 359
 360     return val;
 361 }
 362
 363 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |          \
 364                        MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
 365                        MII_BMCR_FD | MII_BMCR_CTST)
 366 #define MII_ANAR_MASK 0x2d7f
 367
 368 static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val)
 369 {
 370     switch (reg) {
 371     case MII_BMCR:     /* Basic Control */
 372         if (val & MII_BMCR_RESET) {
 373             phy_reset(s);
 374         } else {
 375             s->phy_control = val & MII_BMCR_MASK;
 376             /* Complete autonegotiation immediately.  */
 377             if (val & MII_BMCR_AUTOEN) {
 378                 s->phy_status |= MII_BMSR_AN_COMP;
 379             }
 380         }
 381         break;
 382     case MII_ANAR:     /* Auto-neg advertisement */
 383         s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX;
 384         break;
 385     case RTL8211E_MII_INER: /* Interrupt enable */
 386         s->phy_int_mask = val & 0xff;
 387         phy_update_irq(s);
 388         break;
 389     case RTL8211E_MII_PHYCR:
 390     case RTL8211E_MII_PHYSR:
 391     case RTL8211E_MII_RXERC:
 392     case RTL8211E_MII_LDPSR:
 393     case RTL8211E_MII_EPAGSR:
 394     case RTL8211E_MII_PAGSEL:
 395         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
 396                       __func__, reg);
 397         break;
 398     default:
 399         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
 400                       __func__, reg);
 401         break;
 402     }
 403 }
 404
 405 static void do_phy_new_ctl(FTGMAC100State *s)
 406 {
 407     uint8_t reg;
 408     uint16_t data;
 409
 410     if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) {
 411         qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
 412         return;
 413     }
 414
 415     /* Nothing to do */
 416     if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) {
 417         return;
 418     }
 419
 420     reg = FTGMAC100_PHYCR_NEW_REG(s->phycr);
 421     data = FTGMAC100_PHYCR_NEW_DATA(s->phycr);
 422
 423     switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) {
 424     case FTGMAC100_PHYCR_NEW_OP_WRITE:
 425         do_phy_write(s, reg, data);
 426         break;
 427     case FTGMAC100_PHYCR_NEW_OP_READ:
 428         s->phydata = do_phy_read(s, reg) & 0xffff;
 429         break;
 430     default:
 431         qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
 432                       __func__, s->phycr);
 433     }
 434
 435     s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE;
 436 }
 437
 438 static void do_phy_ctl(FTGMAC100State *s)
 439 {
 440     uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr);
 441
 442     if (s->phycr & FTGMAC100_PHYCR_MIIWR) {
 443         do_phy_write(s, reg, s->phydata & 0xffff);
 444         s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
 445     } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) {
 446         s->phydata = do_phy_read(s, reg) << 16;
 447         s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
 448     } else {
 449         qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n",
 450                       __func__, s->phycr);
 451     }
 452 }
 453
 454 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
 455 {
 456     if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
 457         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
 458                       HWADDR_PRIx "\n", __func__, addr);
 459         return -1;
 460     }
 461     bd->des0 = le32_to_cpu(bd->des0);
 462     bd->des1 = le32_to_cpu(bd->des1);
 463     bd->des2 = le32_to_cpu(bd->des2);
 464     bd->des3 = le32_to_cpu(bd->des3);
 465     return 0;
 466 }
 467
 468 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
 469 {
 470     FTGMAC100Desc lebd;
 471
 472     lebd.des0 = cpu_to_le32(bd->des0);
 473     lebd.des1 = cpu_to_le32(bd->des1);
 474     lebd.des2 = cpu_to_le32(bd->des2);
 475     lebd.des3 = cpu_to_le32(bd->des3);
 476     if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) {
 477         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
 478                       HWADDR_PRIx "\n", __func__, addr);
 479         return -1;
 480     }
 481     return 0;
 482 }
 483
 484 static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
 485                             uint32_t tx_descriptor)
 486 {
 487     int frame_size = 0;
 488     uint8_t *ptr = s->frame;
 489     uint32_t addr = tx_descriptor;
 490     uint32_t flags = 0;
 491
 492     while (1) {
 493         FTGMAC100Desc bd;
 494         int len;
 495
 496         if (ftgmac100_read_bd(&bd, addr) ||
 497             ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) {
 498             /* Run out of descriptors to transmit.  */
 499             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
 500             break;
 501         }
 502
 503         /* record transmit flags as they are valid only on the first
 504          * segment */
 505         if (bd.des0 & FTGMAC100_TXDES0_FTS) {
 506             flags = bd.des1;
 507         }
 508
 509         len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
 510         if (frame_size + len > sizeof(s->frame)) {
 511             qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
 512                           __func__, len);
 513             s->isr |= FTGMAC100_INT_XPKT_LOST;
 514             len =  sizeof(s->frame) - frame_size;
 515         }
 516
 517         if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
 518             qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
 519                           __func__, bd.des3);
 520             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
 521             break;
 522         }
 523
 524         /* Check for VLAN */
 525         if (bd.des0 & FTGMAC100_TXDES0_FTS &&
 526             bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
 527             be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
 528             if (frame_size + len + 4 > sizeof(s->frame)) {
 529                 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
 530                               __func__, len);
 531                 s->isr |= FTGMAC100_INT_XPKT_LOST;
 532                 len =  sizeof(s->frame) - frame_size - 4;
 533             }
 534             memmove(ptr + 16, ptr + 12, len - 12);
 535             stw_be_p(ptr + 12, ETH_P_VLAN);
 536             stw_be_p(ptr + 14, bd.des1);
 537             len += 4;
 538         }
 539
 540         ptr += len;
 541         frame_size += len;
 542         if (bd.des0 & FTGMAC100_TXDES0_LTS) {
 543             if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
 544                 net_checksum_calculate(s->frame, frame_size);
 545             }
 546             /* Last buffer in frame.  */
 547             qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
 548             ptr = s->frame;
 549             frame_size = 0;
 550             if (flags & FTGMAC100_TXDES1_TXIC) {
 551                 s->isr |= FTGMAC100_INT_XPKT_ETH;
 552             }
 553         }
 554
 555         if (flags & FTGMAC100_TXDES1_TX2FIC) {
 556             s->isr |= FTGMAC100_INT_XPKT_FIFO;
 557         }
 558         bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
 559
 560         /* Write back the modified descriptor.  */
 561         ftgmac100_write_bd(&bd, addr);
 562         /* Advance to the next descriptor.  */
 563         if (bd.des0 & s->txdes0_edotr) {
 564             addr = tx_ring;
 565         } else {
 566             addr += FTGMAC100_DBLAC_TXDES_SIZE(s->dblac);
 567         }
 568     }
 569
 570     s->tx_descriptor = addr;
 571
 572     ftgmac100_update_irq(s);
 573 }
 574
 575 static bool ftgmac100_can_receive(NetClientState *nc)
 576 {
 577     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 578     FTGMAC100Desc bd;
 579
 580     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
 581          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
 582         return false;
 583     }
 584
 585     if (ftgmac100_read_bd(&bd, s->rx_descriptor)) {
 586         return false;
 587     }
 588     return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
 589 }
 590
 591 /*
 592  * This is purely informative. The HW can poll the RW (and RX) ring
 593  * buffers for available descriptors but we don't need to trigger a
 594  * timer for that in qemu.
 595  */
 596 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
 597 {
 598     /* Polling times :
 599      *
 600      * Speed      TIME_SEL=0    TIME_SEL=1
 601      *
 602      *    10         51.2 ms      819.2 ms
 603      *   100         5.12 ms      81.92 ms
 604      *  1000        1.024 ms     16.384 ms
 605      */
 606     static const int div[] = { 20, 200, 1000 };
 607
 608     uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr);
 609     uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0;
 610
 611     if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) {
 612         cnt <<= 4;
 613     }
 614
 615     if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) {
 616         speed = 2;
 617     }
 618
 619     return cnt / div[speed];
 620 }
 621
 622 static void ftgmac100_reset(DeviceState *d)
 623 {
 624     FTGMAC100State *s = FTGMAC100(d);
 625
 626     /* Reset the FTGMAC100 */
 627     s->isr = 0;
 628     s->ier = 0;
 629     s->rx_enabled = 0;
 630     s->rx_ring = 0;
 631     s->rbsr = 0x640;
 632     s->rx_descriptor = 0;
 633     s->tx_ring = 0;
 634     s->tx_descriptor = 0;
 635     s->math[0] = 0;
 636     s->math[1] = 0;
 637     s->itc = 0;
 638     s->aptcr = 1;
 639     s->dblac = 0x00022f00;
 640     s->revr = 0;
 641     s->fear1 = 0;
 642     s->tpafcr = 0xf1;
 643
 644     s->maccr = 0;
 645     s->phycr = 0;
 646     s->phydata = 0;
 647     s->fcr = 0x400;
 648
 649     /* and the PHY */
 650     phy_reset(s);
 651 }
 652
 653 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
 654 {
 655     FTGMAC100State *s = FTGMAC100(opaque);
 656
 657     switch (addr & 0xff) {
 658     case FTGMAC100_ISR:
 659         return s->isr;
 660     case FTGMAC100_IER:
 661         return s->ier;
 662     case FTGMAC100_MAC_MADR:
 663         return (s->conf.macaddr.a[0] << 8)  | s->conf.macaddr.a[1];
 664     case FTGMAC100_MAC_LADR:
 665         return ((uint32_t) s->conf.macaddr.a[2] << 24) |
 666             (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) |
 667             s->conf.macaddr.a[5];
 668     case FTGMAC100_MATH0:
 669         return s->math[0];
 670     case FTGMAC100_MATH1:
 671         return s->math[1];
 672     case FTGMAC100_ITC:
 673         return s->itc;
 674     case FTGMAC100_DBLAC:
 675         return s->dblac;
 676     case FTGMAC100_REVR:
 677         return s->revr;
 678     case FTGMAC100_FEAR1:
 679         return s->fear1;
 680     case FTGMAC100_TPAFCR:
 681         return s->tpafcr;
 682     case FTGMAC100_FCR:
 683         return s->fcr;
 684     case FTGMAC100_MACCR:
 685         return s->maccr;
 686     case FTGMAC100_PHYCR:
 687         return s->phycr;
 688     case FTGMAC100_PHYDATA:
 689         return s->phydata;
 690
 691         /* We might want to support these one day */
 692     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
 693     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
 694     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
 695         qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
 696                       HWADDR_PRIx "\n", __func__, addr);
 697         return 0;
 698     default:
 699         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
 700                       HWADDR_PRIx "\n", __func__, addr);
 701         return 0;
 702     }
 703 }
 704
 705 static void ftgmac100_write(void *opaque, hwaddr addr,
 706                           uint64_t value, unsigned size)
 707 {
 708     FTGMAC100State *s = FTGMAC100(opaque);
 709
 710     switch (addr & 0xff) {
 711     case FTGMAC100_ISR: /* Interrupt status */
 712         s->isr &= ~value;
 713         break;
 714     case FTGMAC100_IER: /* Interrupt control */
 715         s->ier = value;
 716         break;
 717     case FTGMAC100_MAC_MADR: /* MAC */
 718         s->conf.macaddr.a[0] = value >> 8;
 719         s->conf.macaddr.a[1] = value;
 720         break;
 721     case FTGMAC100_MAC_LADR:
 722         s->conf.macaddr.a[2] = value >> 24;
 723         s->conf.macaddr.a[3] = value >> 16;
 724         s->conf.macaddr.a[4] = value >> 8;
 725         s->conf.macaddr.a[5] = value;
 726         break;
 727     case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */
 728         s->math[0] = value;
 729         break;
 730     case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */
 731         s->math[1] = value;
 732         break;
 733     case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */
 734         s->itc = value;
 735         break;
 736     case FTGMAC100_RXR_BADR: /* Ring buffer address */
 737         if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
 738             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%"
 739                           HWADDR_PRIx "\n", __func__, value);
 740             return;
 741         }
 742
 743         s->rx_ring = value;
 744         s->rx_descriptor = s->rx_ring;
 745         break;
 746
 747     case FTGMAC100_RBSR: /* DMA buffer size */
 748         s->rbsr = value;
 749         break;
 750
 751     case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
 752         if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
 753             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%"
 754                           HWADDR_PRIx "\n", __func__, value);
 755             return;
 756         }
 757         s->tx_ring = value;
 758         s->tx_descriptor = s->tx_ring;
 759         break;
 760
 761     case FTGMAC100_NPTXPD: /* Trigger transmit */
 762         if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN))
 763             == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) {
 764             /* TODO: high priority tx ring */
 765             ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor);
 766         }
 767         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 768             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 769         }
 770         break;
 771
 772     case FTGMAC100_RXPD: /* Receive Poll Demand Register */
 773         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 774             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 775         }
 776         break;
 777
 778     case FTGMAC100_APTC: /* Automatic polling */
 779         s->aptcr = value;
 780
 781         if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) {
 782             ftgmac100_rxpoll(s);
 783         }
 784
 785         if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) {
 786             qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__);
 787         }
 788         break;
 789
 790     case FTGMAC100_MACCR: /* MAC Device control */
 791         s->maccr = value;
 792         if (value & FTGMAC100_MACCR_SW_RST) {
 793             ftgmac100_reset(DEVICE(s));
 794         }
 795
 796         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
 797             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 798         }
 799         break;
 800
 801     case FTGMAC100_PHYCR:  /* PHY Device control */
 802         s->phycr = value;
 803         if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) {
 804             do_phy_new_ctl(s);
 805         } else {
 806             do_phy_ctl(s);
 807         }
 808         break;
 809     case FTGMAC100_PHYDATA:
 810         s->phydata = value & 0xffff;
 811         break;
 812     case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */
 813         if (FTGMAC100_DBLAC_TXDES_SIZE(s->dblac) < sizeof(FTGMAC100Desc)) {
 814             qemu_log_mask(LOG_GUEST_ERROR,
 815                           "%s: transmit descriptor too small : %d bytes\n",
 816                           __func__, FTGMAC100_DBLAC_TXDES_SIZE(s->dblac));
 817             break;
 818         }
 819         if (FTGMAC100_DBLAC_RXDES_SIZE(s->dblac) < sizeof(FTGMAC100Desc)) {
 820             qemu_log_mask(LOG_GUEST_ERROR,
 821                           "%s: receive descriptor too small : %d bytes\n",
 822                           __func__, FTGMAC100_DBLAC_RXDES_SIZE(s->dblac));
 823             break;
 824         }
 825         s->dblac = value;
 826         break;
 827     case FTGMAC100_REVR:  /* Feature Register */
 828         s->revr = value;
 829         break;
 830     case FTGMAC100_FEAR1: /* Feature Register 1 */
 831         s->fear1 = value;
 832         break;
 833     case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */
 834         s->tpafcr = value;
 835         break;
 836     case FTGMAC100_FCR: /* Flow Control  */
 837         s->fcr  = value;
 838         break;
 839
 840     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
 841     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
 842     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
 843         qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
 844                       HWADDR_PRIx "\n", __func__, addr);
 845         break;
 846     default:
 847         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
 848                       HWADDR_PRIx "\n", __func__, addr);
 849         break;
 850     }
 851
 852     ftgmac100_update_irq(s);
 853 }
 854
 855 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
 856 {
 857     unsigned mcast_idx;
 858
 859     if (s->maccr & FTGMAC100_MACCR_RX_ALL) {
 860         return 1;
 861     }
 862
 863     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
 864     case ETH_PKT_BCAST:
 865         if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) {
 866             return 0;
 867         }
 868         break;
 869     case ETH_PKT_MCAST:
 870         if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) {
 871             if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) {
 872                 return 0;
 873             }
 874
 875             mcast_idx = net_crc32_le(buf, ETH_ALEN);
 876             mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
 877             if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
 878                 return 0;
 879             }
 880         }
 881         break;
 882     case ETH_PKT_UCAST:
 883         if (memcmp(s->conf.macaddr.a, buf, 6)) {
 884             return 0;
 885         }
 886         break;
 887     }
 888
 889     return 1;
 890 }
 891
 892 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
 893                                  size_t len)
 894 {
 895     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
 896     FTGMAC100Desc bd;
 897     uint32_t flags = 0;
 898     uint32_t addr;
 899     uint32_t crc;
 900     uint32_t buf_addr;
 901     uint8_t *crc_ptr;
 902     uint32_t buf_len;
 903     size_t size = len;
 904     uint32_t first = FTGMAC100_RXDES0_FRS;
 905     uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
 906     int max_frame_size = ftgmac100_max_frame_size(s, proto);
 907
 908     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
 909          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
 910         return -1;
 911     }
 912
 913     /* TODO : Pad to minimum Ethernet frame length */
 914     /* handle small packets.  */
 915     if (size < 10) {
 916         qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n",
 917                       __func__, size);
 918         return size;
 919     }
 920
 921     if (!ftgmac100_filter(s, buf, size)) {
 922         return size;
 923     }
 924
 925     /* 4 bytes for the CRC.  */
 926     size += 4;
 927     crc = cpu_to_be32(crc32(~0, buf, size));
 928     crc_ptr = (uint8_t *) &crc;
 929
 930     /* Huge frames are truncated.  */
 931     if (size > max_frame_size) {
 932         qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
 933                       __func__, size);
 934         size = max_frame_size;
 935         flags |= FTGMAC100_RXDES0_FTL;
 936     }
 937
 938     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
 939     case ETH_PKT_BCAST:
 940         flags |= FTGMAC100_RXDES0_BROADCAST;
 941         break;
 942     case ETH_PKT_MCAST:
 943         flags |= FTGMAC100_RXDES0_MULTICAST;
 944         break;
 945     case ETH_PKT_UCAST:
 946         break;
 947     }
 948
 949     addr = s->rx_descriptor;
 950     while (size > 0) {
 951         if (!ftgmac100_can_receive(nc)) {
 952             qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
 953             return -1;
 954         }
 955
 956         if (ftgmac100_read_bd(&bd, addr) ||
 957             (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) {
 958             /* No descriptors available.  Bail out.  */
 959             qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n",
 960                           __func__);
 961             s->isr |= FTGMAC100_INT_NO_RXBUF;
 962             break;
 963         }
 964         buf_len = (size <= s->rbsr) ? size : s->rbsr;
 965         bd.des0 |= buf_len & 0x3fff;
 966         size -= buf_len;
 967
 968         /* The last 4 bytes are the CRC.  */
 969         if (size < 4) {
 970             buf_len += size - 4;
 971         }
 972         buf_addr = bd.des3;
 973         if (first && proto == ETH_P_VLAN && buf_len >= 18) {
 974             bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
 975
 976             if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
 977                 dma_memory_write(&address_space_memory, buf_addr, buf, 12);
 978                 dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
 979                                  buf_len - 16);
 980             } else {
 981                 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
 982             }
 983         } else {
 984             bd.des1 = 0;
 985             dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
 986         }
 987         buf += buf_len;
 988         if (size < 4) {
 989             dma_memory_write(&address_space_memory, buf_addr + buf_len,
 990                              crc_ptr, 4 - size);
 991             crc_ptr += 4 - size;
 992         }
 993
 994         bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY;
 995         first = 0;
 996         if (size == 0) {
 997             /* Last buffer in frame.  */
 998             bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
 999             s->isr |= FTGMAC100_INT_RPKT_BUF;
1000         } else {
1001             s->isr |= FTGMAC100_INT_RPKT_FIFO;
1002         }
1003         ftgmac100_write_bd(&bd, addr);
1004         if (bd.des0 & s->rxdes0_edorr) {
1005             addr = s->rx_ring;
1006         } else {
1007             addr += FTGMAC100_DBLAC_RXDES_SIZE(s->dblac);
1008         }
1009     }
1010     s->rx_descriptor = addr;
1011
1012     ftgmac100_update_irq(s);
1013     return len;
1014 }
1015
1016 static const MemoryRegionOps ftgmac100_ops = {
1017     .read = ftgmac100_read,
1018     .write = ftgmac100_write,
1019     .valid.min_access_size = 4,
1020     .valid.max_access_size = 4,
1021     .endianness = DEVICE_LITTLE_ENDIAN,
1022 };
1023
1024 static void ftgmac100_cleanup(NetClientState *nc)
1025 {
1026     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
1027
1028     s->nic = NULL;
1029 }
1030
1031 static NetClientInfo net_ftgmac100_info = {
1032     .type = NET_CLIENT_DRIVER_NIC,
1033     .size = sizeof(NICState),
1034     .can_receive = ftgmac100_can_receive,
1035     .receive = ftgmac100_receive,
1036     .cleanup = ftgmac100_cleanup,
1037     .link_status_changed = ftgmac100_set_link,
1038 };
1039
1040 static void ftgmac100_realize(DeviceState *dev, Error **errp)
1041 {
1042     FTGMAC100State *s = FTGMAC100(dev);
1043     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1044
1045     if (s->aspeed) {
1046         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
1047         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
1048     } else {
1049         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
1050         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
1051     }
1052
1053     memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
1054                           TYPE_FTGMAC100, 0x2000);
1055     sysbus_init_mmio(sbd, &s->iomem);
1056     sysbus_init_irq(sbd, &s->irq);
1057     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1058
1059     s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
1060                           object_get_typename(OBJECT(dev)), dev->id, s);
1061     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1062 }
1063
1064 static const VMStateDescription vmstate_ftgmac100 = {
1065     .name = TYPE_FTGMAC100,
1066     .version_id = 1,
1067     .minimum_version_id = 1,
1068     .fields = (VMStateField[]) {
1069         VMSTATE_UINT32(irq_state, FTGMAC100State),
1070         VMSTATE_UINT32(isr, FTGMAC100State),
1071         VMSTATE_UINT32(ier, FTGMAC100State),
1072         VMSTATE_UINT32(rx_enabled, FTGMAC100State),
1073         VMSTATE_UINT32(rx_ring, FTGMAC100State),
1074         VMSTATE_UINT32(rbsr, FTGMAC100State),
1075         VMSTATE_UINT32(tx_ring, FTGMAC100State),
1076         VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
1077         VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
1078         VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
1079         VMSTATE_UINT32(itc, FTGMAC100State),
1080         VMSTATE_UINT32(aptcr, FTGMAC100State),
1081         VMSTATE_UINT32(dblac, FTGMAC100State),
1082         VMSTATE_UINT32(revr, FTGMAC100State),
1083         VMSTATE_UINT32(fear1, FTGMAC100State),
1084         VMSTATE_UINT32(tpafcr, FTGMAC100State),
1085         VMSTATE_UINT32(maccr, FTGMAC100State),
1086         VMSTATE_UINT32(phycr, FTGMAC100State),
1087         VMSTATE_UINT32(phydata, FTGMAC100State),
1088         VMSTATE_UINT32(fcr, FTGMAC100State),
1089         VMSTATE_UINT32(phy_status, FTGMAC100State),
1090         VMSTATE_UINT32(phy_control, FTGMAC100State),
1091         VMSTATE_UINT32(phy_advertise, FTGMAC100State),
1092         VMSTATE_UINT32(phy_int, FTGMAC100State),
1093         VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
1094         VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
1095         VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
1096         VMSTATE_END_OF_LIST()
1097     }
1098 };
1099
1100 static Property ftgmac100_properties[] = {
1101     DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
1102     DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
1103     DEFINE_PROP_END_OF_LIST(),
1104 };
1105
1106 static void ftgmac100_class_init(ObjectClass *klass, void *data)
1107 {
1108     DeviceClass *dc = DEVICE_CLASS(klass);
1109
1110     dc->vmsd = &vmstate_ftgmac100;
1111     dc->reset = ftgmac100_reset;
1112     device_class_set_props(dc, ftgmac100_properties);
1113     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1114     dc->realize = ftgmac100_realize;
1115     dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
1116 }
1117
1118 static const TypeInfo ftgmac100_info = {
1119     .name = TYPE_FTGMAC100,
1120     .parent = TYPE_SYS_BUS_DEVICE,
1121     .instance_size = sizeof(FTGMAC100State),
1122     .class_init = ftgmac100_class_init,
1123 };
1124
1125 /*
1126  * AST2600 MII controller
1127  */
1128 #define ASPEED_MII_PHYCR_FIRE        BIT(31)
1129 #define ASPEED_MII_PHYCR_ST_22       BIT(28)
1130 #define ASPEED_MII_PHYCR_OP(x)       ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \
1131                                              ASPEED_MII_PHYCR_OP_READ))
1132 #define ASPEED_MII_PHYCR_OP_WRITE    BIT(26)
1133 #define ASPEED_MII_PHYCR_OP_READ     BIT(27)
1134 #define ASPEED_MII_PHYCR_DATA(x)     (x & 0xffff)
1135 #define ASPEED_MII_PHYCR_PHY(x)      (((x) >> 21) & 0x1f)
1136 #define ASPEED_MII_PHYCR_REG(x)      (((x) >> 16) & 0x1f)
1137
1138 #define ASPEED_MII_PHYDATA_IDLE      BIT(16)
1139
1140 static void aspeed_mii_transition(AspeedMiiState *s, bool fire)
1141 {
1142     if (fire) {
1143         s->phycr |= ASPEED_MII_PHYCR_FIRE;
1144         s->phydata &= ~ASPEED_MII_PHYDATA_IDLE;
1145     } else {
1146         s->phycr &= ~ASPEED_MII_PHYCR_FIRE;
1147         s->phydata |= ASPEED_MII_PHYDATA_IDLE;
1148     }
1149 }
1150
1151 static void aspeed_mii_do_phy_ctl(AspeedMiiState *s)
1152 {
1153     uint8_t reg;
1154     uint16_t data;
1155
1156     if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) {
1157         aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
1158         qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
1159         return;
1160     }
1161
1162     /* Nothing to do */
1163     if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) {
1164         return;
1165     }
1166
1167     reg = ASPEED_MII_PHYCR_REG(s->phycr);
1168     data = ASPEED_MII_PHYCR_DATA(s->phycr);
1169
1170     switch (ASPEED_MII_PHYCR_OP(s->phycr)) {
1171     case ASPEED_MII_PHYCR_OP_WRITE:
1172         do_phy_write(s->nic, reg, data);
1173         break;
1174     case ASPEED_MII_PHYCR_OP_READ:
1175         s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg);
1176         break;
1177     default:
1178         qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
1179                       __func__, s->phycr);
1180     }
1181
1182     aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
1183 }
1184
1185 static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size)
1186 {
1187     AspeedMiiState *s = ASPEED_MII(opaque);
1188
1189     switch (addr) {
1190     case 0x0:
1191         return s->phycr;
1192     case 0x4:
1193         return s->phydata;
1194     default:
1195         g_assert_not_reached();
1196     }
1197 }
1198
1199 static void aspeed_mii_write(void *opaque, hwaddr addr,
1200                              uint64_t value, unsigned size)
1201 {
1202     AspeedMiiState *s = ASPEED_MII(opaque);
1203
1204     switch (addr) {
1205     case 0x0:
1206         s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE);
1207         break;
1208     case 0x4:
1209         s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE);
1210         break;
1211     default:
1212         g_assert_not_reached();
1213     }
1214
1215     aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
1216     aspeed_mii_do_phy_ctl(s);
1217 }
1218
1219 static const MemoryRegionOps aspeed_mii_ops = {
1220     .read = aspeed_mii_read,
1221     .write = aspeed_mii_write,
1222     .valid.min_access_size = 4,
1223     .valid.max_access_size = 4,
1224     .endianness = DEVICE_LITTLE_ENDIAN,
1225 };
1226
1227 static void aspeed_mii_reset(DeviceState *dev)
1228 {
1229     AspeedMiiState *s = ASPEED_MII(dev);
1230
1231     s->phycr = 0;
1232     s->phydata = 0;
1233
1234     aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
1235 };
1236
1237 static void aspeed_mii_realize(DeviceState *dev, Error **errp)
1238 {
1239     AspeedMiiState *s = ASPEED_MII(dev);
1240     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1241
1242     assert(s->nic);
1243
1244     memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s,
1245                           TYPE_ASPEED_MII, 0x8);
1246     sysbus_init_mmio(sbd, &s->iomem);
1247 }
1248
1249 static const VMStateDescription vmstate_aspeed_mii = {
1250     .name = TYPE_ASPEED_MII,
1251     .version_id = 1,
1252     .minimum_version_id = 1,
1253     .fields = (VMStateField[]) {
1254         VMSTATE_UINT32(phycr, FTGMAC100State),
1255         VMSTATE_UINT32(phydata, FTGMAC100State),
1256         VMSTATE_END_OF_LIST()
1257     }
1258 };
1259
1260 static Property aspeed_mii_properties[] = {
1261     DEFINE_PROP_LINK("nic", AspeedMiiState, nic, TYPE_FTGMAC100,
1262                      FTGMAC100State *),
1263     DEFINE_PROP_END_OF_LIST(),
1264 };
1265
1266 static void aspeed_mii_class_init(ObjectClass *klass, void *data)
1267 {
1268     DeviceClass *dc = DEVICE_CLASS(klass);
1269
1270     dc->vmsd = &vmstate_aspeed_mii;
1271     dc->reset = aspeed_mii_reset;
1272     dc->realize = aspeed_mii_realize;
1273     dc->desc = "Aspeed MII controller";
1274     device_class_set_props(dc, aspeed_mii_properties);
1275 }
1276
1277 static const TypeInfo aspeed_mii_info = {
1278     .name = TYPE_ASPEED_MII,
1279     .parent = TYPE_SYS_BUS_DEVICE,
1280     .instance_size = sizeof(AspeedMiiState),
1281     .class_init = aspeed_mii_class_init,
1282 };
1283
1284 static void ftgmac100_register_types(void)
1285 {
1286     type_register_static(&ftgmac100_info);
1287     type_register_static(&aspeed_mii_info);
1288 }
1289
1290 type_init(ftgmac100_register_types)