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nvme: simplify plug/unplug
[qemu/ar7.git] / hw / xen / xen_pt_config_init.c
blobaee31c62bb99a9e13a8bddff49ea4f0f0e94b015
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include "qemu/timer.h"
18 #include "hw/xen/xen_backend.h"
19 #include "xen_pt.h"
20
21 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
22 (((value) & (val_mask)) | ((data) & ~(val_mask)))
23
24 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
25
26 /* prototype */
27
28 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
29 uint32_t real_offset, uint32_t *data);
30
31
32 /* helper */
33
34 /* A return value of 1 means the capability should NOT be exposed to guest. */
35 static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
36 {
37 switch (grp_id) {
38 case PCI_CAP_ID_EXP:
39 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
40 * Controller looks trivial, e.g., the PCI Express Capabilities
41 * Register is 0. We should not try to expose it to guest.
42 *
43 * The datasheet is available at
44 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
45 *
46 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
47 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
48 * Controller looks trivial, e.g., the PCI Express Capabilities
49 * Register is 0, so the Capability Version is 0 and
50 * xen_pt_pcie_size_init() would fail.
51 */
52 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
53 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
54 return 1;
55 }
56 break;
57 }
58 return 0;
59 }
60
61 /* find emulate register group entry */
62 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
63 {
64 XenPTRegGroup *entry = NULL;
65
66 /* find register group entry */
67 QLIST_FOREACH(entry, &s->reg_grps, entries) {
68 /* check address */
69 if ((entry->base_offset <= address)
70 && ((entry->base_offset + entry->size) > address)) {
71 return entry;
72 }
73 }
74
75 /* group entry not found */
76 return NULL;
77 }
78
79 /* find emulate register entry */
80 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
81 {
82 XenPTReg *reg_entry = NULL;
83 XenPTRegInfo *reg = NULL;
84 uint32_t real_offset = 0;
85
86 /* find register entry */
87 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
88 reg = reg_entry->reg;
89 real_offset = reg_grp->base_offset + reg->offset;
90 /* check address */
91 if ((real_offset <= address)
92 && ((real_offset + reg->size) > address)) {
93 return reg_entry;
94 }
95 }
96
97 return NULL;
98 }
99
100 static uint32_t get_throughable_mask(const XenPCIPassthroughState *s,
101 XenPTRegInfo *reg, uint32_t valid_mask)
102 {
103 uint32_t throughable_mask = ~(reg->emu_mask | reg->ro_mask);
104
105 if (!s->permissive) {
106 throughable_mask &= ~reg->res_mask;
107 }
108
109 return throughable_mask & valid_mask;
110 }
111
112 /****************
113 * general register functions
114 */
115
116 /* register initialization function */
117
118 static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
119 XenPTRegInfo *reg, uint32_t real_offset,
120 uint32_t *data)
121 {
122 *data = reg->init_val;
123 return 0;
124 }
125
126 /* Read register functions */
127
128 static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
129 uint8_t *value, uint8_t valid_mask)
130 {
131 XenPTRegInfo *reg = cfg_entry->reg;
132 uint8_t valid_emu_mask = 0;
133 uint8_t *data = cfg_entry->ptr.byte;
134
135 /* emulate byte register */
136 valid_emu_mask = reg->emu_mask & valid_mask;
137 *value = XEN_PT_MERGE_VALUE(*value, *data, ~valid_emu_mask);
138
139 return 0;
140 }
141 static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
142 uint16_t *value, uint16_t valid_mask)
143 {
144 XenPTRegInfo *reg = cfg_entry->reg;
145 uint16_t valid_emu_mask = 0;
146 uint16_t *data = cfg_entry->ptr.half_word;
147
148 /* emulate word register */
149 valid_emu_mask = reg->emu_mask & valid_mask;
150 *value = XEN_PT_MERGE_VALUE(*value, *data, ~valid_emu_mask);
151
152 return 0;
153 }
154 static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
155 uint32_t *value, uint32_t valid_mask)
156 {
157 XenPTRegInfo *reg = cfg_entry->reg;
158 uint32_t valid_emu_mask = 0;
159 uint32_t *data = cfg_entry->ptr.word;
160
161 /* emulate long register */
162 valid_emu_mask = reg->emu_mask & valid_mask;
163 *value = XEN_PT_MERGE_VALUE(*value, *data, ~valid_emu_mask);
164
165 return 0;
166 }
167
168 /* Write register functions */
169
170 static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
171 uint8_t *val, uint8_t dev_value,
172 uint8_t valid_mask)
173 {
174 XenPTRegInfo *reg = cfg_entry->reg;
175 uint8_t writable_mask = 0;
176 uint8_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
177 uint8_t *data = cfg_entry->ptr.byte;
178
179 /* modify emulate register */
180 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
181 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
182
183 /* create value for writing to I/O device register */
184 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,
185 throughable_mask);
186
187 return 0;
188 }
189 static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
190 uint16_t *val, uint16_t dev_value,
191 uint16_t valid_mask)
192 {
193 XenPTRegInfo *reg = cfg_entry->reg;
194 uint16_t writable_mask = 0;
195 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
196 uint16_t *data = cfg_entry->ptr.half_word;
197
198 /* modify emulate register */
199 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
200 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
201
202 /* create value for writing to I/O device register */
203 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,
204 throughable_mask);
205
206 return 0;
207 }
208 static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
209 uint32_t *val, uint32_t dev_value,
210 uint32_t valid_mask)
211 {
212 XenPTRegInfo *reg = cfg_entry->reg;
213 uint32_t writable_mask = 0;
214 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
215 uint32_t *data = cfg_entry->ptr.word;
216
217 /* modify emulate register */
218 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
219 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
220
221 /* create value for writing to I/O device register */
222 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,
223 throughable_mask);
224
225 return 0;
226 }
227
228
229 /* XenPTRegInfo declaration
230 * - only for emulated register (either a part or whole bit).
231 * - for passthrough register that need special behavior (like interacting with
232 * other component), set emu_mask to all 0 and specify r/w func properly.
233 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
234 */
235
236 /********************
237 * Header Type0
238 */
239
240 static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
241 XenPTRegInfo *reg, uint32_t real_offset,
242 uint32_t *data)
243 {
244 *data = s->real_device.vendor_id;
245 return 0;
246 }
247 static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
248 XenPTRegInfo *reg, uint32_t real_offset,
249 uint32_t *data)
250 {
251 *data = s->real_device.device_id;
252 return 0;
253 }
254 static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
255 XenPTRegInfo *reg, uint32_t real_offset,
256 uint32_t *data)
257 {
258 XenPTRegGroup *reg_grp_entry = NULL;
259 XenPTReg *reg_entry = NULL;
260 uint32_t reg_field = 0;
261
262 /* find Header register group */
263 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
264 if (reg_grp_entry) {
265 /* find Capabilities Pointer register */
266 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
267 if (reg_entry) {
268 /* check Capabilities Pointer register */
269 if (*reg_entry->ptr.half_word) {
270 reg_field |= PCI_STATUS_CAP_LIST;
271 } else {
272 reg_field &= ~PCI_STATUS_CAP_LIST;
273 }
274 } else {
275 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
276 " for Capabilities Pointer register."
277 " (%s)\n", __func__);
278 return -1;
279 }
280 } else {
281 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
282 " for Header. (%s)\n", __func__);
283 return -1;
284 }
285
286 *data = reg_field;
287 return 0;
288 }
289 static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
290 XenPTRegInfo *reg, uint32_t real_offset,
291 uint32_t *data)
292 {
293 /* read PCI_HEADER_TYPE */
294 *data = reg->init_val | 0x80;
295 return 0;
296 }
297
298 /* initialize Interrupt Pin register */
299 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
300 XenPTRegInfo *reg, uint32_t real_offset,
301 uint32_t *data)
302 {
303 *data = xen_pt_pci_read_intx(s);
304 return 0;
305 }
306
307 /* Command register */
308 static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
309 uint16_t *val, uint16_t dev_value,
310 uint16_t valid_mask)
311 {
312 XenPTRegInfo *reg = cfg_entry->reg;
313 uint16_t writable_mask = 0;
314 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
315 uint16_t *data = cfg_entry->ptr.half_word;
316
317 /* modify emulate register */
318 writable_mask = ~reg->ro_mask & valid_mask;
319 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
320
321 /* create value for writing to I/O device register */
322 if (*val & PCI_COMMAND_INTX_DISABLE) {
323 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
324 } else {
325 if (s->machine_irq) {
326 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
327 }
328 }
329
330 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
331
332 return 0;
333 }
334
335 /* BAR */
336 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
337 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
338 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
339 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
340
341 static bool is_64bit_bar(PCIIORegion *r)
342 {
343 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
344 }
345
346 static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
347 {
348 if (is_64bit_bar(r)) {
349 uint64_t size64;
350 size64 = (r + 1)->size;
351 size64 <<= 32;
352 size64 += r->size;
353 return size64;
354 }
355 return r->size;
356 }
357
358 static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
359 int index)
360 {
361 PCIDevice *d = &s->dev;
362 XenPTRegion *region = NULL;
363 PCIIORegion *r;
364
365 /* check 64bit BAR */
366 if ((0 < index) && (index < PCI_ROM_SLOT)) {
367 int type = s->real_device.io_regions[index - 1].type;
368
369 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
370 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
371 region = &s->bases[index - 1];
372 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
373 return XEN_PT_BAR_FLAG_UPPER;
374 }
375 }
376 }
377
378 /* check unused BAR */
379 r = &d->io_regions[index];
380 if (!xen_pt_get_bar_size(r)) {
381 return XEN_PT_BAR_FLAG_UNUSED;
382 }
383
384 /* for ExpROM BAR */
385 if (index == PCI_ROM_SLOT) {
386 return XEN_PT_BAR_FLAG_MEM;
387 }
388
389 /* check BAR I/O indicator */
390 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
391 return XEN_PT_BAR_FLAG_IO;
392 } else {
393 return XEN_PT_BAR_FLAG_MEM;
394 }
395 }
396
397 static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
398 {
399 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
400 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
401 } else {
402 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
403 }
404 }
405
406 static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
407 uint32_t real_offset, uint32_t *data)
408 {
409 uint32_t reg_field = 0;
410 int index;
411
412 index = xen_pt_bar_offset_to_index(reg->offset);
413 if (index < 0 || index >= PCI_NUM_REGIONS) {
414 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
415 return -1;
416 }
417
418 /* set BAR flag */
419 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index);
420 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
421 reg_field = XEN_PT_INVALID_REG;
422 }
423
424 *data = reg_field;
425 return 0;
426 }
427 static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
428 uint32_t *value, uint32_t valid_mask)
429 {
430 XenPTRegInfo *reg = cfg_entry->reg;
431 uint32_t valid_emu_mask = 0;
432 uint32_t bar_emu_mask = 0;
433 int index;
434
435 /* get BAR index */
436 index = xen_pt_bar_offset_to_index(reg->offset);
437 if (index < 0 || index >= PCI_NUM_REGIONS - 1) {
438 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
439 return -1;
440 }
441
442 /* use fixed-up value from kernel sysfs */
443 *value = base_address_with_flags(&s->real_device.io_regions[index]);
444
445 /* set emulate mask depend on BAR flag */
446 switch (s->bases[index].bar_flag) {
447 case XEN_PT_BAR_FLAG_MEM:
448 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
449 break;
450 case XEN_PT_BAR_FLAG_IO:
451 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
452 break;
453 case XEN_PT_BAR_FLAG_UPPER:
454 bar_emu_mask = XEN_PT_BAR_ALLF;
455 break;
456 default:
457 break;
458 }
459
460 /* emulate BAR */
461 valid_emu_mask = bar_emu_mask & valid_mask;
462 *value = XEN_PT_MERGE_VALUE(*value, *cfg_entry->ptr.word, ~valid_emu_mask);
463
464 return 0;
465 }
466 static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
467 uint32_t *val, uint32_t dev_value,
468 uint32_t valid_mask)
469 {
470 XenPTRegInfo *reg = cfg_entry->reg;
471 XenPTRegion *base = NULL;
472 PCIDevice *d = &s->dev;
473 const PCIIORegion *r;
474 uint32_t writable_mask = 0;
475 uint32_t bar_emu_mask = 0;
476 uint32_t bar_ro_mask = 0;
477 uint32_t r_size = 0;
478 int index = 0;
479 uint32_t *data = cfg_entry->ptr.word;
480
481 index = xen_pt_bar_offset_to_index(reg->offset);
482 if (index < 0 || index >= PCI_NUM_REGIONS) {
483 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
484 return -1;
485 }
486
487 r = &d->io_regions[index];
488 base = &s->bases[index];
489 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
490
491 /* set emulate mask and read-only mask values depend on the BAR flag */
492 switch (s->bases[index].bar_flag) {
493 case XEN_PT_BAR_FLAG_MEM:
494 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
495 if (!r_size) {
496 /* low 32 bits mask for 64 bit bars */
497 bar_ro_mask = XEN_PT_BAR_ALLF;
498 } else {
499 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
500 }
501 break;
502 case XEN_PT_BAR_FLAG_IO:
503 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
504 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
505 break;
506 case XEN_PT_BAR_FLAG_UPPER:
507 assert(index > 0);
508 r_size = d->io_regions[index - 1].size >> 32;
509 bar_emu_mask = XEN_PT_BAR_ALLF;
510 bar_ro_mask = r_size ? r_size - 1 : 0;
511 break;
512 default:
513 break;
514 }
515
516 /* modify emulate register */
517 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
518 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
519
520 /* check whether we need to update the virtual region address or not */
521 switch (s->bases[index].bar_flag) {
522 case XEN_PT_BAR_FLAG_UPPER:
523 case XEN_PT_BAR_FLAG_MEM:
524 /* nothing to do */
525 break;
526 case XEN_PT_BAR_FLAG_IO:
527 /* nothing to do */
528 break;
529 default:
530 break;
531 }
532
533 /* create value for writing to I/O device register */
534 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
535
536 return 0;
537 }
538
539 /* write Exp ROM BAR */
540 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
541 XenPTReg *cfg_entry, uint32_t *val,
542 uint32_t dev_value, uint32_t valid_mask)
543 {
544 XenPTRegInfo *reg = cfg_entry->reg;
545 XenPTRegion *base = NULL;
546 PCIDevice *d = (PCIDevice *)&s->dev;
547 uint32_t writable_mask = 0;
548 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
549 pcibus_t r_size = 0;
550 uint32_t bar_ro_mask = 0;
551 uint32_t *data = cfg_entry->ptr.word;
552
553 r_size = d->io_regions[PCI_ROM_SLOT].size;
554 base = &s->bases[PCI_ROM_SLOT];
555 /* align memory type resource size */
556 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
557
558 /* set emulate mask and read-only mask */
559 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
560
561 /* modify emulate register */
562 writable_mask = ~bar_ro_mask & valid_mask;
563 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
564
565 /* create value for writing to I/O device register */
566 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
567
568 return 0;
569 }
570
571 static int xen_pt_intel_opregion_read(XenPCIPassthroughState *s,
572 XenPTReg *cfg_entry,
573 uint32_t *value, uint32_t valid_mask)
574 {
575 *value = igd_read_opregion(s);
576 return 0;
577 }
578
579 static int xen_pt_intel_opregion_write(XenPCIPassthroughState *s,
580 XenPTReg *cfg_entry, uint32_t *value,
581 uint32_t dev_value, uint32_t valid_mask)
582 {
583 igd_write_opregion(s, *value);
584 return 0;
585 }
586
587 /* Header Type0 reg static information table */
588 static XenPTRegInfo xen_pt_emu_reg_header0[] = {
589 /* Vendor ID reg */
590 {
591 .offset = PCI_VENDOR_ID,
592 .size = 2,
593 .init_val = 0x0000,
594 .ro_mask = 0xFFFF,
595 .emu_mask = 0xFFFF,
596 .init = xen_pt_vendor_reg_init,
597 .u.w.read = xen_pt_word_reg_read,
598 .u.w.write = xen_pt_word_reg_write,
599 },
600 /* Device ID reg */
601 {
602 .offset = PCI_DEVICE_ID,
603 .size = 2,
604 .init_val = 0x0000,
605 .ro_mask = 0xFFFF,
606 .emu_mask = 0xFFFF,
607 .init = xen_pt_device_reg_init,
608 .u.w.read = xen_pt_word_reg_read,
609 .u.w.write = xen_pt_word_reg_write,
610 },
611 /* Command reg */
612 {
613 .offset = PCI_COMMAND,
614 .size = 2,
615 .init_val = 0x0000,
616 .res_mask = 0xF880,
617 .emu_mask = 0x0743,
618 .init = xen_pt_common_reg_init,
619 .u.w.read = xen_pt_word_reg_read,
620 .u.w.write = xen_pt_cmd_reg_write,
621 },
622 /* Capabilities Pointer reg */
623 {
624 .offset = PCI_CAPABILITY_LIST,
625 .size = 1,
626 .init_val = 0x00,
627 .ro_mask = 0xFF,
628 .emu_mask = 0xFF,
629 .init = xen_pt_ptr_reg_init,
630 .u.b.read = xen_pt_byte_reg_read,
631 .u.b.write = xen_pt_byte_reg_write,
632 },
633 /* Status reg */
634 /* use emulated Cap Ptr value to initialize,
635 * so need to be declared after Cap Ptr reg
636 */
637 {
638 .offset = PCI_STATUS,
639 .size = 2,
640 .init_val = 0x0000,
641 .res_mask = 0x0007,
642 .ro_mask = 0x06F8,
643 .rw1c_mask = 0xF900,
644 .emu_mask = 0x0010,
645 .init = xen_pt_status_reg_init,
646 .u.w.read = xen_pt_word_reg_read,
647 .u.w.write = xen_pt_word_reg_write,
648 },
649 /* Cache Line Size reg */
650 {
651 .offset = PCI_CACHE_LINE_SIZE,
652 .size = 1,
653 .init_val = 0x00,
654 .ro_mask = 0x00,
655 .emu_mask = 0xFF,
656 .init = xen_pt_common_reg_init,
657 .u.b.read = xen_pt_byte_reg_read,
658 .u.b.write = xen_pt_byte_reg_write,
659 },
660 /* Latency Timer reg */
661 {
662 .offset = PCI_LATENCY_TIMER,
663 .size = 1,
664 .init_val = 0x00,
665 .ro_mask = 0x00,
666 .emu_mask = 0xFF,
667 .init = xen_pt_common_reg_init,
668 .u.b.read = xen_pt_byte_reg_read,
669 .u.b.write = xen_pt_byte_reg_write,
670 },
671 /* Header Type reg */
672 {
673 .offset = PCI_HEADER_TYPE,
674 .size = 1,
675 .init_val = 0x00,
676 .ro_mask = 0xFF,
677 .emu_mask = 0x00,
678 .init = xen_pt_header_type_reg_init,
679 .u.b.read = xen_pt_byte_reg_read,
680 .u.b.write = xen_pt_byte_reg_write,
681 },
682 /* Interrupt Line reg */
683 {
684 .offset = PCI_INTERRUPT_LINE,
685 .size = 1,
686 .init_val = 0x00,
687 .ro_mask = 0x00,
688 .emu_mask = 0xFF,
689 .init = xen_pt_common_reg_init,
690 .u.b.read = xen_pt_byte_reg_read,
691 .u.b.write = xen_pt_byte_reg_write,
692 },
693 /* Interrupt Pin reg */
694 {
695 .offset = PCI_INTERRUPT_PIN,
696 .size = 1,
697 .init_val = 0x00,
698 .ro_mask = 0xFF,
699 .emu_mask = 0xFF,
700 .init = xen_pt_irqpin_reg_init,
701 .u.b.read = xen_pt_byte_reg_read,
702 .u.b.write = xen_pt_byte_reg_write,
703 },
704 /* BAR 0 reg */
705 /* mask of BAR need to be decided later, depends on IO/MEM type */
706 {
707 .offset = PCI_BASE_ADDRESS_0,
708 .size = 4,
709 .init_val = 0x00000000,
710 .init = xen_pt_bar_reg_init,
711 .u.dw.read = xen_pt_bar_reg_read,
712 .u.dw.write = xen_pt_bar_reg_write,
713 },
714 /* BAR 1 reg */
715 {
716 .offset = PCI_BASE_ADDRESS_1,
717 .size = 4,
718 .init_val = 0x00000000,
719 .init = xen_pt_bar_reg_init,
720 .u.dw.read = xen_pt_bar_reg_read,
721 .u.dw.write = xen_pt_bar_reg_write,
722 },
723 /* BAR 2 reg */
724 {
725 .offset = PCI_BASE_ADDRESS_2,
726 .size = 4,
727 .init_val = 0x00000000,
728 .init = xen_pt_bar_reg_init,
729 .u.dw.read = xen_pt_bar_reg_read,
730 .u.dw.write = xen_pt_bar_reg_write,
731 },
732 /* BAR 3 reg */
733 {
734 .offset = PCI_BASE_ADDRESS_3,
735 .size = 4,
736 .init_val = 0x00000000,
737 .init = xen_pt_bar_reg_init,
738 .u.dw.read = xen_pt_bar_reg_read,
739 .u.dw.write = xen_pt_bar_reg_write,
740 },
741 /* BAR 4 reg */
742 {
743 .offset = PCI_BASE_ADDRESS_4,
744 .size = 4,
745 .init_val = 0x00000000,
746 .init = xen_pt_bar_reg_init,
747 .u.dw.read = xen_pt_bar_reg_read,
748 .u.dw.write = xen_pt_bar_reg_write,
749 },
750 /* BAR 5 reg */
751 {
752 .offset = PCI_BASE_ADDRESS_5,
753 .size = 4,
754 .init_val = 0x00000000,
755 .init = xen_pt_bar_reg_init,
756 .u.dw.read = xen_pt_bar_reg_read,
757 .u.dw.write = xen_pt_bar_reg_write,
758 },
759 /* Expansion ROM BAR reg */
760 {
761 .offset = PCI_ROM_ADDRESS,
762 .size = 4,
763 .init_val = 0x00000000,
764 .ro_mask = ~PCI_ROM_ADDRESS_MASK & ~PCI_ROM_ADDRESS_ENABLE,
765 .emu_mask = (uint32_t)PCI_ROM_ADDRESS_MASK,
766 .init = xen_pt_bar_reg_init,
767 .u.dw.read = xen_pt_long_reg_read,
768 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
769 },
770 {
771 .size = 0,
772 },
773 };
774
775
776 /*********************************
777 * Vital Product Data Capability
778 */
779
780 /* Vital Product Data Capability Structure reg static information table */
781 static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
782 {
783 .offset = PCI_CAP_LIST_NEXT,
784 .size = 1,
785 .init_val = 0x00,
786 .ro_mask = 0xFF,
787 .emu_mask = 0xFF,
788 .init = xen_pt_ptr_reg_init,
789 .u.b.read = xen_pt_byte_reg_read,
790 .u.b.write = xen_pt_byte_reg_write,
791 },
792 {
793 .offset = PCI_VPD_ADDR,
794 .size = 2,
795 .ro_mask = 0x0003,
796 .emu_mask = 0x0003,
797 .init = xen_pt_common_reg_init,
798 .u.w.read = xen_pt_word_reg_read,
799 .u.w.write = xen_pt_word_reg_write,
800 },
801 {
802 .size = 0,
803 },
804 };
805
806
807 /**************************************
808 * Vendor Specific Capability
809 */
810
811 /* Vendor Specific Capability Structure reg static information table */
812 static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
813 {
814 .offset = PCI_CAP_LIST_NEXT,
815 .size = 1,
816 .init_val = 0x00,
817 .ro_mask = 0xFF,
818 .emu_mask = 0xFF,
819 .init = xen_pt_ptr_reg_init,
820 .u.b.read = xen_pt_byte_reg_read,
821 .u.b.write = xen_pt_byte_reg_write,
822 },
823 {
824 .size = 0,
825 },
826 };
827
828
829 /*****************************
830 * PCI Express Capability
831 */
832
833 static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
834 uint32_t offset)
835 {
836 uint8_t flag;
837 if (xen_host_pci_get_byte(&s->real_device, offset + PCI_EXP_FLAGS, &flag)) {
838 return 0;
839 }
840 return flag & PCI_EXP_FLAGS_VERS;
841 }
842
843 static inline uint8_t get_device_type(XenPCIPassthroughState *s,
844 uint32_t offset)
845 {
846 uint8_t flag;
847 if (xen_host_pci_get_byte(&s->real_device, offset + PCI_EXP_FLAGS, &flag)) {
848 return 0;
849 }
850 return (flag & PCI_EXP_FLAGS_TYPE) >> 4;
851 }
852
853 /* initialize Link Control register */
854 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
855 XenPTRegInfo *reg, uint32_t real_offset,
856 uint32_t *data)
857 {
858 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
859 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
860
861 /* no need to initialize in case of Root Complex Integrated Endpoint
862 * with cap_ver 1.x
863 */
864 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
865 *data = XEN_PT_INVALID_REG;
866 }
867
868 *data = reg->init_val;
869 return 0;
870 }
871 /* initialize Device Control 2 register */
872 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
873 XenPTRegInfo *reg, uint32_t real_offset,
874 uint32_t *data)
875 {
876 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
877
878 /* no need to initialize in case of cap_ver 1.x */
879 if (cap_ver == 1) {
880 *data = XEN_PT_INVALID_REG;
881 }
882
883 *data = reg->init_val;
884 return 0;
885 }
886 /* initialize Link Control 2 register */
887 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
888 XenPTRegInfo *reg, uint32_t real_offset,
889 uint32_t *data)
890 {
891 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
892 uint32_t reg_field = 0;
893
894 /* no need to initialize in case of cap_ver 1.x */
895 if (cap_ver == 1) {
896 reg_field = XEN_PT_INVALID_REG;
897 } else {
898 /* set Supported Link Speed */
899 uint8_t lnkcap;
900 int rc;
901 rc = xen_host_pci_get_byte(&s->real_device,
902 real_offset - reg->offset + PCI_EXP_LNKCAP,
903 &lnkcap);
904 if (rc) {
905 return rc;
906 }
907 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
908 }
909
910 *data = reg_field;
911 return 0;
912 }
913
914 /* PCI Express Capability Structure reg static information table */
915 static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
916 /* Next Pointer reg */
917 {
918 .offset = PCI_CAP_LIST_NEXT,
919 .size = 1,
920 .init_val = 0x00,
921 .ro_mask = 0xFF,
922 .emu_mask = 0xFF,
923 .init = xen_pt_ptr_reg_init,
924 .u.b.read = xen_pt_byte_reg_read,
925 .u.b.write = xen_pt_byte_reg_write,
926 },
927 /* Device Capabilities reg */
928 {
929 .offset = PCI_EXP_DEVCAP,
930 .size = 4,
931 .init_val = 0x00000000,
932 .ro_mask = 0xFFFFFFFF,
933 .emu_mask = 0x10000000,
934 .init = xen_pt_common_reg_init,
935 .u.dw.read = xen_pt_long_reg_read,
936 .u.dw.write = xen_pt_long_reg_write,
937 },
938 /* Device Control reg */
939 {
940 .offset = PCI_EXP_DEVCTL,
941 .size = 2,
942 .init_val = 0x2810,
943 .ro_mask = 0x8400,
944 .emu_mask = 0xFFFF,
945 .init = xen_pt_common_reg_init,
946 .u.w.read = xen_pt_word_reg_read,
947 .u.w.write = xen_pt_word_reg_write,
948 },
949 /* Device Status reg */
950 {
951 .offset = PCI_EXP_DEVSTA,
952 .size = 2,
953 .res_mask = 0xFFC0,
954 .ro_mask = 0x0030,
955 .rw1c_mask = 0x000F,
956 .init = xen_pt_common_reg_init,
957 .u.w.read = xen_pt_word_reg_read,
958 .u.w.write = xen_pt_word_reg_write,
959 },
960 /* Link Control reg */
961 {
962 .offset = PCI_EXP_LNKCTL,
963 .size = 2,
964 .init_val = 0x0000,
965 .ro_mask = 0xFC34,
966 .emu_mask = 0xFFFF,
967 .init = xen_pt_linkctrl_reg_init,
968 .u.w.read = xen_pt_word_reg_read,
969 .u.w.write = xen_pt_word_reg_write,
970 },
971 /* Link Status reg */
972 {
973 .offset = PCI_EXP_LNKSTA,
974 .size = 2,
975 .ro_mask = 0x3FFF,
976 .rw1c_mask = 0xC000,
977 .init = xen_pt_common_reg_init,
978 .u.w.read = xen_pt_word_reg_read,
979 .u.w.write = xen_pt_word_reg_write,
980 },
981 /* Device Control 2 reg */
982 {
983 .offset = 0x28,
984 .size = 2,
985 .init_val = 0x0000,
986 .ro_mask = 0xFFE0,
987 .emu_mask = 0xFFFF,
988 .init = xen_pt_devctrl2_reg_init,
989 .u.w.read = xen_pt_word_reg_read,
990 .u.w.write = xen_pt_word_reg_write,
991 },
992 /* Link Control 2 reg */
993 {
994 .offset = 0x30,
995 .size = 2,
996 .init_val = 0x0000,
997 .ro_mask = 0xE040,
998 .emu_mask = 0xFFFF,
999 .init = xen_pt_linkctrl2_reg_init,
1000 .u.w.read = xen_pt_word_reg_read,
1001 .u.w.write = xen_pt_word_reg_write,
1002 },
1003 {
1004 .size = 0,
1005 },
1006 };
1007
1008
1009 /*********************************
1010 * Power Management Capability
1011 */
1012
1013 /* Power Management Capability reg static information table */
1014 static XenPTRegInfo xen_pt_emu_reg_pm[] = {
1015 /* Next Pointer reg */
1016 {
1017 .offset = PCI_CAP_LIST_NEXT,
1018 .size = 1,
1019 .init_val = 0x00,
1020 .ro_mask = 0xFF,
1021 .emu_mask = 0xFF,
1022 .init = xen_pt_ptr_reg_init,
1023 .u.b.read = xen_pt_byte_reg_read,
1024 .u.b.write = xen_pt_byte_reg_write,
1025 },
1026 /* Power Management Capabilities reg */
1027 {
1028 .offset = PCI_CAP_FLAGS,
1029 .size = 2,
1030 .init_val = 0x0000,
1031 .ro_mask = 0xFFFF,
1032 .emu_mask = 0xF9C8,
1033 .init = xen_pt_common_reg_init,
1034 .u.w.read = xen_pt_word_reg_read,
1035 .u.w.write = xen_pt_word_reg_write,
1036 },
1037 /* PCI Power Management Control/Status reg */
1038 {
1039 .offset = PCI_PM_CTRL,
1040 .size = 2,
1041 .init_val = 0x0008,
1042 .res_mask = 0x00F0,
1043 .ro_mask = 0x610C,
1044 .rw1c_mask = 0x8000,
1045 .emu_mask = 0x810B,
1046 .init = xen_pt_common_reg_init,
1047 .u.w.read = xen_pt_word_reg_read,
1048 .u.w.write = xen_pt_word_reg_write,
1049 },
1050 {
1051 .size = 0,
1052 },
1053 };
1054
1055
1056 /********************************
1057 * MSI Capability
1058 */
1059
1060 /* Helper */
1061 #define xen_pt_msi_check_type(offset, flags, what) \
1062 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1063 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
1064
1065 /* Message Control register */
1066 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1067 XenPTRegInfo *reg, uint32_t real_offset,
1068 uint32_t *data)
1069 {
1070 XenPTMSI *msi = s->msi;
1071 uint16_t reg_field;
1072 int rc;
1073
1074 /* use I/O device register's value as initial value */
1075 rc = xen_host_pci_get_word(&s->real_device, real_offset, &reg_field);
1076 if (rc) {
1077 return rc;
1078 }
1079 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1080 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1081 xen_host_pci_set_word(&s->real_device, real_offset,
1082 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1083 }
1084 msi->flags |= reg_field;
1085 msi->ctrl_offset = real_offset;
1086 msi->initialized = false;
1087 msi->mapped = false;
1088
1089 *data = reg->init_val;
1090 return 0;
1091 }
1092 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1093 XenPTReg *cfg_entry, uint16_t *val,
1094 uint16_t dev_value, uint16_t valid_mask)
1095 {
1096 XenPTRegInfo *reg = cfg_entry->reg;
1097 XenPTMSI *msi = s->msi;
1098 uint16_t writable_mask = 0;
1099 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
1100 uint16_t *data = cfg_entry->ptr.half_word;
1101
1102 /* Currently no support for multi-vector */
1103 if (*val & PCI_MSI_FLAGS_QSIZE) {
1104 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1105 }
1106
1107 /* modify emulate register */
1108 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1109 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
1110 msi->flags |= *data & ~PCI_MSI_FLAGS_ENABLE;
1111
1112 /* create value for writing to I/O device register */
1113 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1114
1115 /* update MSI */
1116 if (*val & PCI_MSI_FLAGS_ENABLE) {
1117 /* setup MSI pirq for the first time */
1118 if (!msi->initialized) {
1119 /* Init physical one */
1120 XEN_PT_LOG(&s->dev, "setup MSI (register: %x).\n", *val);
1121 if (xen_pt_msi_setup(s)) {
1122 /* We do not broadcast the error to the framework code, so
1123 * that MSI errors are contained in MSI emulation code and
1124 * QEMU can go on running.
1125 * Guest MSI would be actually not working.
1126 */
1127 *val &= ~PCI_MSI_FLAGS_ENABLE;
1128 XEN_PT_WARN(&s->dev, "Can not map MSI (register: %x)!\n", *val);
1129 return 0;
1130 }
1131 if (xen_pt_msi_update(s)) {
1132 *val &= ~PCI_MSI_FLAGS_ENABLE;
1133 XEN_PT_WARN(&s->dev, "Can not bind MSI (register: %x)!\n", *val);
1134 return 0;
1135 }
1136 msi->initialized = true;
1137 msi->mapped = true;
1138 }
1139 msi->flags |= PCI_MSI_FLAGS_ENABLE;
1140 } else if (msi->mapped) {
1141 xen_pt_msi_disable(s);
1142 }
1143
1144 return 0;
1145 }
1146
1147 /* initialize Message Upper Address register */
1148 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1149 XenPTRegInfo *reg, uint32_t real_offset,
1150 uint32_t *data)
1151 {
1152 /* no need to initialize in case of 32 bit type */
1153 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1154 *data = XEN_PT_INVALID_REG;
1155 } else {
1156 *data = reg->init_val;
1157 }
1158
1159 return 0;
1160 }
1161 /* this function will be called twice (for 32 bit and 64 bit type) */
1162 /* initialize Message Data register */
1163 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1164 XenPTRegInfo *reg, uint32_t real_offset,
1165 uint32_t *data)
1166 {
1167 uint32_t flags = s->msi->flags;
1168 uint32_t offset = reg->offset;
1169
1170 /* check the offset whether matches the type or not */
1171 if (xen_pt_msi_check_type(offset, flags, DATA)) {
1172 *data = reg->init_val;
1173 } else {
1174 *data = XEN_PT_INVALID_REG;
1175 }
1176 return 0;
1177 }
1178
1179 /* this function will be called twice (for 32 bit and 64 bit type) */
1180 /* initialize Mask register */
1181 static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
1182 XenPTRegInfo *reg, uint32_t real_offset,
1183 uint32_t *data)
1184 {
1185 uint32_t flags = s->msi->flags;
1186
1187 /* check the offset whether matches the type or not */
1188 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1189 *data = XEN_PT_INVALID_REG;
1190 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
1191 *data = reg->init_val;
1192 } else {
1193 *data = XEN_PT_INVALID_REG;
1194 }
1195 return 0;
1196 }
1197
1198 /* this function will be called twice (for 32 bit and 64 bit type) */
1199 /* initialize Pending register */
1200 static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
1201 XenPTRegInfo *reg, uint32_t real_offset,
1202 uint32_t *data)
1203 {
1204 uint32_t flags = s->msi->flags;
1205
1206 /* check the offset whether matches the type or not */
1207 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1208 *data = XEN_PT_INVALID_REG;
1209 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
1210 *data = reg->init_val;
1211 } else {
1212 *data = XEN_PT_INVALID_REG;
1213 }
1214 return 0;
1215 }
1216
1217 /* write Message Address register */
1218 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1219 XenPTReg *cfg_entry, uint32_t *val,
1220 uint32_t dev_value, uint32_t valid_mask)
1221 {
1222 XenPTRegInfo *reg = cfg_entry->reg;
1223 uint32_t writable_mask = 0;
1224 uint32_t old_addr = *cfg_entry->ptr.word;
1225 uint32_t *data = cfg_entry->ptr.word;
1226
1227 /* modify emulate register */
1228 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1229 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
1230 s->msi->addr_lo = *data;
1231
1232 /* create value for writing to I/O device register */
1233 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
1234
1235 /* update MSI */
1236 if (*data != old_addr) {
1237 if (s->msi->mapped) {
1238 xen_pt_msi_update(s);
1239 }
1240 }
1241
1242 return 0;
1243 }
1244 /* write Message Upper Address register */
1245 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1246 XenPTReg *cfg_entry, uint32_t *val,
1247 uint32_t dev_value, uint32_t valid_mask)
1248 {
1249 XenPTRegInfo *reg = cfg_entry->reg;
1250 uint32_t writable_mask = 0;
1251 uint32_t old_addr = *cfg_entry->ptr.word;
1252 uint32_t *data = cfg_entry->ptr.word;
1253
1254 /* check whether the type is 64 bit or not */
1255 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1256 XEN_PT_ERR(&s->dev,
1257 "Can't write to the upper address without 64 bit support\n");
1258 return -1;
1259 }
1260
1261 /* modify emulate register */
1262 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1263 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
1264 /* update the msi_info too */
1265 s->msi->addr_hi = *data;
1266
1267 /* create value for writing to I/O device register */
1268 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
1269
1270 /* update MSI */
1271 if (*data != old_addr) {
1272 if (s->msi->mapped) {
1273 xen_pt_msi_update(s);
1274 }
1275 }
1276
1277 return 0;
1278 }
1279
1280
1281 /* this function will be called twice (for 32 bit and 64 bit type) */
1282 /* write Message Data register */
1283 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1284 XenPTReg *cfg_entry, uint16_t *val,
1285 uint16_t dev_value, uint16_t valid_mask)
1286 {
1287 XenPTRegInfo *reg = cfg_entry->reg;
1288 XenPTMSI *msi = s->msi;
1289 uint16_t writable_mask = 0;
1290 uint16_t old_data = *cfg_entry->ptr.half_word;
1291 uint32_t offset = reg->offset;
1292 uint16_t *data = cfg_entry->ptr.half_word;
1293
1294 /* check the offset whether matches the type or not */
1295 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
1296 /* exit I/O emulator */
1297 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1298 return -1;
1299 }
1300
1301 /* modify emulate register */
1302 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1303 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
1304 /* update the msi_info too */
1305 msi->data = *data;
1306
1307 /* create value for writing to I/O device register */
1308 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
1309
1310 /* update MSI */
1311 if (*data != old_data) {
1312 if (msi->mapped) {
1313 xen_pt_msi_update(s);
1314 }
1315 }
1316
1317 return 0;
1318 }
1319
1320 static int xen_pt_mask_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
1321 uint32_t *val, uint32_t dev_value,
1322 uint32_t valid_mask)
1323 {
1324 int rc;
1325
1326 rc = xen_pt_long_reg_write(s, cfg_entry, val, dev_value, valid_mask);
1327 if (rc) {
1328 return rc;
1329 }
1330
1331 s->msi->mask = *val;
1332
1333 return 0;
1334 }
1335
1336 /* MSI Capability Structure reg static information table */
1337 static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1338 /* Next Pointer reg */
1339 {
1340 .offset = PCI_CAP_LIST_NEXT,
1341 .size = 1,
1342 .init_val = 0x00,
1343 .ro_mask = 0xFF,
1344 .emu_mask = 0xFF,
1345 .init = xen_pt_ptr_reg_init,
1346 .u.b.read = xen_pt_byte_reg_read,
1347 .u.b.write = xen_pt_byte_reg_write,
1348 },
1349 /* Message Control reg */
1350 {
1351 .offset = PCI_MSI_FLAGS,
1352 .size = 2,
1353 .init_val = 0x0000,
1354 .res_mask = 0xFE00,
1355 .ro_mask = 0x018E,
1356 .emu_mask = 0x017E,
1357 .init = xen_pt_msgctrl_reg_init,
1358 .u.w.read = xen_pt_word_reg_read,
1359 .u.w.write = xen_pt_msgctrl_reg_write,
1360 },
1361 /* Message Address reg */
1362 {
1363 .offset = PCI_MSI_ADDRESS_LO,
1364 .size = 4,
1365 .init_val = 0x00000000,
1366 .ro_mask = 0x00000003,
1367 .emu_mask = 0xFFFFFFFF,
1368 .init = xen_pt_common_reg_init,
1369 .u.dw.read = xen_pt_long_reg_read,
1370 .u.dw.write = xen_pt_msgaddr32_reg_write,
1371 },
1372 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1373 {
1374 .offset = PCI_MSI_ADDRESS_HI,
1375 .size = 4,
1376 .init_val = 0x00000000,
1377 .ro_mask = 0x00000000,
1378 .emu_mask = 0xFFFFFFFF,
1379 .init = xen_pt_msgaddr64_reg_init,
1380 .u.dw.read = xen_pt_long_reg_read,
1381 .u.dw.write = xen_pt_msgaddr64_reg_write,
1382 },
1383 /* Message Data reg (16 bits of data for 32-bit devices) */
1384 {
1385 .offset = PCI_MSI_DATA_32,
1386 .size = 2,
1387 .init_val = 0x0000,
1388 .ro_mask = 0x0000,
1389 .emu_mask = 0xFFFF,
1390 .init = xen_pt_msgdata_reg_init,
1391 .u.w.read = xen_pt_word_reg_read,
1392 .u.w.write = xen_pt_msgdata_reg_write,
1393 },
1394 /* Message Data reg (16 bits of data for 64-bit devices) */
1395 {
1396 .offset = PCI_MSI_DATA_64,
1397 .size = 2,
1398 .init_val = 0x0000,
1399 .ro_mask = 0x0000,
1400 .emu_mask = 0xFFFF,
1401 .init = xen_pt_msgdata_reg_init,
1402 .u.w.read = xen_pt_word_reg_read,
1403 .u.w.write = xen_pt_msgdata_reg_write,
1404 },
1405 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1406 {
1407 .offset = PCI_MSI_MASK_32,
1408 .size = 4,
1409 .init_val = 0x00000000,
1410 .ro_mask = 0xFFFFFFFF,
1411 .emu_mask = 0xFFFFFFFF,
1412 .init = xen_pt_mask_reg_init,
1413 .u.dw.read = xen_pt_long_reg_read,
1414 .u.dw.write = xen_pt_mask_reg_write,
1415 },
1416 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1417 {
1418 .offset = PCI_MSI_MASK_64,
1419 .size = 4,
1420 .init_val = 0x00000000,
1421 .ro_mask = 0xFFFFFFFF,
1422 .emu_mask = 0xFFFFFFFF,
1423 .init = xen_pt_mask_reg_init,
1424 .u.dw.read = xen_pt_long_reg_read,
1425 .u.dw.write = xen_pt_mask_reg_write,
1426 },
1427 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1428 {
1429 .offset = PCI_MSI_MASK_32 + 4,
1430 .size = 4,
1431 .init_val = 0x00000000,
1432 .ro_mask = 0xFFFFFFFF,
1433 .emu_mask = 0x00000000,
1434 .init = xen_pt_pending_reg_init,
1435 .u.dw.read = xen_pt_long_reg_read,
1436 .u.dw.write = xen_pt_long_reg_write,
1437 },
1438 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1439 {
1440 .offset = PCI_MSI_MASK_64 + 4,
1441 .size = 4,
1442 .init_val = 0x00000000,
1443 .ro_mask = 0xFFFFFFFF,
1444 .emu_mask = 0x00000000,
1445 .init = xen_pt_pending_reg_init,
1446 .u.dw.read = xen_pt_long_reg_read,
1447 .u.dw.write = xen_pt_long_reg_write,
1448 },
1449 {
1450 .size = 0,
1451 },
1452 };
1453
1454
1455 /**************************************
1456 * MSI-X Capability
1457 */
1458
1459 /* Message Control register for MSI-X */
1460 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1461 XenPTRegInfo *reg, uint32_t real_offset,
1462 uint32_t *data)
1463 {
1464 uint16_t reg_field;
1465 int rc;
1466
1467 /* use I/O device register's value as initial value */
1468 rc = xen_host_pci_get_word(&s->real_device, real_offset, &reg_field);
1469 if (rc) {
1470 return rc;
1471 }
1472 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
1473 XEN_PT_LOG(&s->dev, "MSIX already enabled, disabling it first\n");
1474 xen_host_pci_set_word(&s->real_device, real_offset,
1475 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1476 }
1477
1478 s->msix->ctrl_offset = real_offset;
1479
1480 *data = reg->init_val;
1481 return 0;
1482 }
1483 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1484 XenPTReg *cfg_entry, uint16_t *val,
1485 uint16_t dev_value, uint16_t valid_mask)
1486 {
1487 XenPTRegInfo *reg = cfg_entry->reg;
1488 uint16_t writable_mask = 0;
1489 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
1490 int debug_msix_enabled_old;
1491 uint16_t *data = cfg_entry->ptr.half_word;
1492
1493 /* modify emulate register */
1494 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1495 *data = XEN_PT_MERGE_VALUE(*val, *data, writable_mask);
1496
1497 /* create value for writing to I/O device register */
1498 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1499
1500 /* update MSI-X */
1501 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1502 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1503 xen_pt_msix_update(s);
1504 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {
1505 xen_pt_msix_disable(s);
1506 }
1507
1508 s->msix->maskall = *val & PCI_MSIX_FLAGS_MASKALL;
1509
1510 debug_msix_enabled_old = s->msix->enabled;
1511 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1512 if (s->msix->enabled != debug_msix_enabled_old) {
1513 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1514 s->msix->enabled ? "enable" : "disable");
1515 }
1516
1517 return 0;
1518 }
1519
1520 /* MSI-X Capability Structure reg static information table */
1521 static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1522 /* Next Pointer reg */
1523 {
1524 .offset = PCI_CAP_LIST_NEXT,
1525 .size = 1,
1526 .init_val = 0x00,
1527 .ro_mask = 0xFF,
1528 .emu_mask = 0xFF,
1529 .init = xen_pt_ptr_reg_init,
1530 .u.b.read = xen_pt_byte_reg_read,
1531 .u.b.write = xen_pt_byte_reg_write,
1532 },
1533 /* Message Control reg */
1534 {
1535 .offset = PCI_MSI_FLAGS,
1536 .size = 2,
1537 .init_val = 0x0000,
1538 .res_mask = 0x3800,
1539 .ro_mask = 0x07FF,
1540 .emu_mask = 0x0000,
1541 .init = xen_pt_msixctrl_reg_init,
1542 .u.w.read = xen_pt_word_reg_read,
1543 .u.w.write = xen_pt_msixctrl_reg_write,
1544 },
1545 {
1546 .size = 0,
1547 },
1548 };
1549
1550 static XenPTRegInfo xen_pt_emu_reg_igd_opregion[] = {
1551 /* Intel IGFX OpRegion reg */
1552 {
1553 .offset = 0x0,
1554 .size = 4,
1555 .init_val = 0,
1556 .emu_mask = 0xFFFFFFFF,
1557 .u.dw.read = xen_pt_intel_opregion_read,
1558 .u.dw.write = xen_pt_intel_opregion_write,
1559 },
1560 {
1561 .size = 0,
1562 },
1563 };
1564
1565 /****************************
1566 * Capabilities
1567 */
1568
1569 /* capability structure register group size functions */
1570
1571 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1572 const XenPTRegGroupInfo *grp_reg,
1573 uint32_t base_offset, uint8_t *size)
1574 {
1575 *size = grp_reg->grp_size;
1576 return 0;
1577 }
1578 /* get Vendor Specific Capability Structure register group size */
1579 static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1580 const XenPTRegGroupInfo *grp_reg,
1581 uint32_t base_offset, uint8_t *size)
1582 {
1583 return xen_host_pci_get_byte(&s->real_device, base_offset + 0x02, size);
1584 }
1585 /* get PCI Express Capability Structure register group size */
1586 static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1587 const XenPTRegGroupInfo *grp_reg,
1588 uint32_t base_offset, uint8_t *size)
1589 {
1590 PCIDevice *d = &s->dev;
1591 uint8_t version = get_capability_version(s, base_offset);
1592 uint8_t type = get_device_type(s, base_offset);
1593 uint8_t pcie_size = 0;
1594
1595
1596 /* calculate size depend on capability version and device/port type */
1597 /* in case of PCI Express Base Specification Rev 1.x */
1598 if (version == 1) {
1599 /* The PCI Express Capabilities, Device Capabilities, and Device
1600 * Status/Control registers are required for all PCI Express devices.
1601 * The Link Capabilities and Link Status/Control are required for all
1602 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1603 * are not required to implement registers other than those listed
1604 * above and terminate the capability structure.
1605 */
1606 switch (type) {
1607 case PCI_EXP_TYPE_ENDPOINT:
1608 case PCI_EXP_TYPE_LEG_END:
1609 pcie_size = 0x14;
1610 break;
1611 case PCI_EXP_TYPE_RC_END:
1612 /* has no link */
1613 pcie_size = 0x0C;
1614 break;
1615 /* only EndPoint passthrough is supported */
1616 case PCI_EXP_TYPE_ROOT_PORT:
1617 case PCI_EXP_TYPE_UPSTREAM:
1618 case PCI_EXP_TYPE_DOWNSTREAM:
1619 case PCI_EXP_TYPE_PCI_BRIDGE:
1620 case PCI_EXP_TYPE_PCIE_BRIDGE:
1621 case PCI_EXP_TYPE_RC_EC:
1622 default:
1623 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1624 return -1;
1625 }
1626 }
1627 /* in case of PCI Express Base Specification Rev 2.0 */
1628 else if (version == 2) {
1629 switch (type) {
1630 case PCI_EXP_TYPE_ENDPOINT:
1631 case PCI_EXP_TYPE_LEG_END:
1632 case PCI_EXP_TYPE_RC_END:
1633 /* For Functions that do not implement the registers,
1634 * these spaces must be hardwired to 0b.
1635 */
1636 pcie_size = 0x3C;
1637 break;
1638 /* only EndPoint passthrough is supported */
1639 case PCI_EXP_TYPE_ROOT_PORT:
1640 case PCI_EXP_TYPE_UPSTREAM:
1641 case PCI_EXP_TYPE_DOWNSTREAM:
1642 case PCI_EXP_TYPE_PCI_BRIDGE:
1643 case PCI_EXP_TYPE_PCIE_BRIDGE:
1644 case PCI_EXP_TYPE_RC_EC:
1645 default:
1646 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1647 return -1;
1648 }
1649 } else {
1650 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1651 return -1;
1652 }
1653
1654 *size = pcie_size;
1655 return 0;
1656 }
1657 /* get MSI Capability Structure register group size */
1658 static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1659 const XenPTRegGroupInfo *grp_reg,
1660 uint32_t base_offset, uint8_t *size)
1661 {
1662 uint16_t msg_ctrl = 0;
1663 uint8_t msi_size = 0xa;
1664 int rc;
1665
1666 rc = xen_host_pci_get_word(&s->real_device, base_offset + PCI_MSI_FLAGS,
1667 &msg_ctrl);
1668 if (rc) {
1669 return rc;
1670 }
1671 /* check if 64-bit address is capable of per-vector masking */
1672 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1673 msi_size += 4;
1674 }
1675 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1676 msi_size += 10;
1677 }
1678
1679 s->msi = g_new0(XenPTMSI, 1);
1680 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1681
1682 *size = msi_size;
1683 return 0;
1684 }
1685 /* get MSI-X Capability Structure register group size */
1686 static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1687 const XenPTRegGroupInfo *grp_reg,
1688 uint32_t base_offset, uint8_t *size)
1689 {
1690 int rc = 0;
1691
1692 rc = xen_pt_msix_init(s, base_offset);
1693
1694 if (rc < 0) {
1695 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1696 return rc;
1697 }
1698
1699 *size = grp_reg->grp_size;
1700 return 0;
1701 }
1702
1703
1704 static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1705 /* Header Type0 reg group */
1706 {
1707 .grp_id = 0xFF,
1708 .grp_type = XEN_PT_GRP_TYPE_EMU,
1709 .grp_size = 0x40,
1710 .size_init = xen_pt_reg_grp_size_init,
1711 .emu_regs = xen_pt_emu_reg_header0,
1712 },
1713 /* PCI PowerManagement Capability reg group */
1714 {
1715 .grp_id = PCI_CAP_ID_PM,
1716 .grp_type = XEN_PT_GRP_TYPE_EMU,
1717 .grp_size = PCI_PM_SIZEOF,
1718 .size_init = xen_pt_reg_grp_size_init,
1719 .emu_regs = xen_pt_emu_reg_pm,
1720 },
1721 /* AGP Capability Structure reg group */
1722 {
1723 .grp_id = PCI_CAP_ID_AGP,
1724 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1725 .grp_size = 0x30,
1726 .size_init = xen_pt_reg_grp_size_init,
1727 },
1728 /* Vital Product Data Capability Structure reg group */
1729 {
1730 .grp_id = PCI_CAP_ID_VPD,
1731 .grp_type = XEN_PT_GRP_TYPE_EMU,
1732 .grp_size = 0x08,
1733 .size_init = xen_pt_reg_grp_size_init,
1734 .emu_regs = xen_pt_emu_reg_vpd,
1735 },
1736 /* Slot Identification reg group */
1737 {
1738 .grp_id = PCI_CAP_ID_SLOTID,
1739 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1740 .grp_size = 0x04,
1741 .size_init = xen_pt_reg_grp_size_init,
1742 },
1743 /* MSI Capability Structure reg group */
1744 {
1745 .grp_id = PCI_CAP_ID_MSI,
1746 .grp_type = XEN_PT_GRP_TYPE_EMU,
1747 .grp_size = 0xFF,
1748 .size_init = xen_pt_msi_size_init,
1749 .emu_regs = xen_pt_emu_reg_msi,
1750 },
1751 /* PCI-X Capabilities List Item reg group */
1752 {
1753 .grp_id = PCI_CAP_ID_PCIX,
1754 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1755 .grp_size = 0x18,
1756 .size_init = xen_pt_reg_grp_size_init,
1757 },
1758 /* Vendor Specific Capability Structure reg group */
1759 {
1760 .grp_id = PCI_CAP_ID_VNDR,
1761 .grp_type = XEN_PT_GRP_TYPE_EMU,
1762 .grp_size = 0xFF,
1763 .size_init = xen_pt_vendor_size_init,
1764 .emu_regs = xen_pt_emu_reg_vendor,
1765 },
1766 /* SHPC Capability List Item reg group */
1767 {
1768 .grp_id = PCI_CAP_ID_SHPC,
1769 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1770 .grp_size = 0x08,
1771 .size_init = xen_pt_reg_grp_size_init,
1772 },
1773 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1774 {
1775 .grp_id = PCI_CAP_ID_SSVID,
1776 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1777 .grp_size = 0x08,
1778 .size_init = xen_pt_reg_grp_size_init,
1779 },
1780 /* AGP 8x Capability Structure reg group */
1781 {
1782 .grp_id = PCI_CAP_ID_AGP3,
1783 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1784 .grp_size = 0x30,
1785 .size_init = xen_pt_reg_grp_size_init,
1786 },
1787 /* PCI Express Capability Structure reg group */
1788 {
1789 .grp_id = PCI_CAP_ID_EXP,
1790 .grp_type = XEN_PT_GRP_TYPE_EMU,
1791 .grp_size = 0xFF,
1792 .size_init = xen_pt_pcie_size_init,
1793 .emu_regs = xen_pt_emu_reg_pcie,
1794 },
1795 /* MSI-X Capability Structure reg group */
1796 {
1797 .grp_id = PCI_CAP_ID_MSIX,
1798 .grp_type = XEN_PT_GRP_TYPE_EMU,
1799 .grp_size = 0x0C,
1800 .size_init = xen_pt_msix_size_init,
1801 .emu_regs = xen_pt_emu_reg_msix,
1802 },
1803 /* Intel IGD Opregion group */
1804 {
1805 .grp_id = XEN_PCI_INTEL_OPREGION,
1806 .grp_type = XEN_PT_GRP_TYPE_EMU,
1807 .grp_size = 0x4,
1808 .size_init = xen_pt_reg_grp_size_init,
1809 .emu_regs = xen_pt_emu_reg_igd_opregion,
1810 },
1811 {
1812 .grp_size = 0,
1813 },
1814 };
1815
1816 /* initialize Capabilities Pointer or Next Pointer register */
1817 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1818 XenPTRegInfo *reg, uint32_t real_offset,
1819 uint32_t *data)
1820 {
1821 int i, rc;
1822 uint8_t reg_field;
1823 uint8_t cap_id = 0;
1824
1825 rc = xen_host_pci_get_byte(&s->real_device, real_offset, &reg_field);
1826 if (rc) {
1827 return rc;
1828 }
1829 /* find capability offset */
1830 while (reg_field) {
1831 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1832 if (xen_pt_hide_dev_cap(&s->real_device,
1833 xen_pt_emu_reg_grps[i].grp_id)) {
1834 continue;
1835 }
1836
1837 rc = xen_host_pci_get_byte(&s->real_device,
1838 reg_field + PCI_CAP_LIST_ID, &cap_id);
1839 if (rc) {
1840 XEN_PT_ERR(&s->dev, "Failed to read capability @0x%x (rc:%d)\n",
1841 reg_field + PCI_CAP_LIST_ID, rc);
1842 return rc;
1843 }
1844 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1845 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1846 goto out;
1847 }
1848 /* ignore the 0 hardwired capability, find next one */
1849 break;
1850 }
1851 }
1852
1853 /* next capability */
1854 rc = xen_host_pci_get_byte(&s->real_device,
1855 reg_field + PCI_CAP_LIST_NEXT, &reg_field);
1856 if (rc) {
1857 return rc;
1858 }
1859 }
1860
1861 out:
1862 *data = reg_field;
1863 return 0;
1864 }
1865
1866
1867 /*************
1868 * Main
1869 */
1870
1871 static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1872 {
1873 uint8_t id;
1874 unsigned max_cap = XEN_PCI_CAP_MAX;
1875 uint8_t pos = PCI_CAPABILITY_LIST;
1876 uint8_t status = 0;
1877
1878 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1879 return 0;
1880 }
1881 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1882 return 0;
1883 }
1884
1885 while (max_cap--) {
1886 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1887 break;
1888 }
1889 if (pos < PCI_CONFIG_HEADER_SIZE) {
1890 break;
1891 }
1892
1893 pos &= ~3;
1894 if (xen_host_pci_get_byte(&s->real_device,
1895 pos + PCI_CAP_LIST_ID, &id)) {
1896 break;
1897 }
1898
1899 if (id == 0xff) {
1900 break;
1901 }
1902 if (id == cap) {
1903 return pos;
1904 }
1905
1906 pos += PCI_CAP_LIST_NEXT;
1907 }
1908 return 0;
1909 }
1910
1911 static void xen_pt_config_reg_init(XenPCIPassthroughState *s,
1912 XenPTRegGroup *reg_grp, XenPTRegInfo *reg,
1913 Error **errp)
1914 {
1915 XenPTReg *reg_entry;
1916 uint32_t data = 0;
1917 int rc = 0;
1918
1919 reg_entry = g_new0(XenPTReg, 1);
1920 reg_entry->reg = reg;
1921
1922 if (reg->init) {
1923 uint32_t host_mask, size_mask;
1924 unsigned int offset;
1925 uint32_t val;
1926
1927 /* initialize emulate register */
1928 rc = reg->init(s, reg_entry->reg,
1929 reg_grp->base_offset + reg->offset, &data);
1930 if (rc < 0) {
1931 g_free(reg_entry);
1932 error_setg(errp, "Init emulate register fail");
1933 return;
1934 }
1935 if (data == XEN_PT_INVALID_REG) {
1936 /* free unused BAR register entry */
1937 g_free(reg_entry);
1938 return;
1939 }
1940 /* Sync up the data to dev.config */
1941 offset = reg_grp->base_offset + reg->offset;
1942 size_mask = 0xFFFFFFFF >> ((4 - reg->size) << 3);
1943
1944 switch (reg->size) {
1945 case 1: rc = xen_host_pci_get_byte(&s->real_device, offset, (uint8_t *)&val);
1946 break;
1947 case 2: rc = xen_host_pci_get_word(&s->real_device, offset, (uint16_t *)&val);
1948 break;
1949 case 4: rc = xen_host_pci_get_long(&s->real_device, offset, &val);
1950 break;
1951 default: abort();
1952 }
1953 if (rc) {
1954 /* Serious issues when we cannot read the host values! */
1955 g_free(reg_entry);
1956 error_setg(errp, "Cannot read host values");
1957 return;
1958 }
1959 /* Set bits in emu_mask are the ones we emulate. The dev.config shall
1960 * contain the emulated view of the guest - therefore we flip the mask
1961 * to mask out the host values (which dev.config initially has) . */
1962 host_mask = size_mask & ~reg->emu_mask;
1963
1964 if ((data & host_mask) != (val & host_mask)) {
1965 uint32_t new_val;
1966
1967 /* Mask out host (including past size). */
1968 new_val = val & host_mask;
1969 /* Merge emulated ones (excluding the non-emulated ones). */
1970 new_val |= data & host_mask;
1971 /* Leave intact host and emulated values past the size - even though
1972 * we do not care as we write per reg->size granularity, but for the
1973 * logging below lets have the proper value. */
1974 new_val |= ((val | data)) & ~size_mask;
1975 XEN_PT_LOG(&s->dev,"Offset 0x%04x mismatch! Emulated=0x%04x, host=0x%04x, syncing to 0x%04x.\n",
1976 offset, data, val, new_val);
1977 val = new_val;
1978 } else
1979 val = data;
1980
1981 if (val & ~size_mask) {
1982 error_setg(errp, "Offset 0x%04x:0x%04x expands past"
1983 " register size (%d)", offset, val, reg->size);
1984 g_free(reg_entry);
1985 return;
1986 }
1987 /* This could be just pci_set_long as we don't modify the bits
1988 * past reg->size, but in case this routine is run in parallel or the
1989 * init value is larger, we do not want to over-write registers. */
1990 switch (reg->size) {
1991 case 1: pci_set_byte(s->dev.config + offset, (uint8_t)val);
1992 break;
1993 case 2: pci_set_word(s->dev.config + offset, (uint16_t)val);
1994 break;
1995 case 4: pci_set_long(s->dev.config + offset, val);
1996 break;
1997 default: abort();
1998 }
1999 /* set register value pointer to the data. */
2000 reg_entry->ptr.byte = s->dev.config + offset;
2001
2002 }
2003 /* list add register entry */
2004 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
2005 }
2006
2007 void xen_pt_config_init(XenPCIPassthroughState *s, Error **errp)
2008 {
2009 int i, rc;
2010 Error *err = NULL;
2011
2012 QLIST_INIT(&s->reg_grps);
2013
2014 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
2015 uint32_t reg_grp_offset = 0;
2016 XenPTRegGroup *reg_grp_entry = NULL;
2017
2018 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF
2019 && xen_pt_emu_reg_grps[i].grp_id != XEN_PCI_INTEL_OPREGION) {
2020 if (xen_pt_hide_dev_cap(&s->real_device,
2021 xen_pt_emu_reg_grps[i].grp_id)) {
2022 continue;
2023 }
2024
2025 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
2026
2027 if (!reg_grp_offset) {
2028 continue;
2029 }
2030 }
2031
2032 /*
2033 * By default we will trap up to 0x40 in the cfg space.
2034 * If an intel device is pass through we need to trap 0xfc,
2035 * therefore the size should be 0xff.
2036 */
2037 if (xen_pt_emu_reg_grps[i].grp_id == XEN_PCI_INTEL_OPREGION) {
2038 reg_grp_offset = XEN_PCI_INTEL_OPREGION;
2039 }
2040
2041 reg_grp_entry = g_new0(XenPTRegGroup, 1);
2042 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
2043 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
2044
2045 reg_grp_entry->base_offset = reg_grp_offset;
2046 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
2047 if (xen_pt_emu_reg_grps[i].size_init) {
2048 /* get register group size */
2049 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
2050 reg_grp_offset,
2051 &reg_grp_entry->size);
2052 if (rc < 0) {
2053 error_setg(&err, "Failed to initialize %d/%zu, type = 0x%x,"
2054 " rc: %d", i, ARRAY_SIZE(xen_pt_emu_reg_grps),
2055 xen_pt_emu_reg_grps[i].grp_type, rc);
2056 error_propagate(errp, err);
2057 xen_pt_config_delete(s);
2058 return;
2059 }
2060 }
2061
2062 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
2063 if (xen_pt_emu_reg_grps[i].emu_regs) {
2064 int j = 0;
2065 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
2066
2067 /* initialize capability register */
2068 for (j = 0; regs->size != 0; j++, regs++) {
2069 xen_pt_config_reg_init(s, reg_grp_entry, regs, &err);
2070 if (err) {
2071 error_append_hint(&err, "Failed to init register %d"
2072 " offsets 0x%x in grp_type = 0x%x (%d/%zu)", j,
2073 regs->offset, xen_pt_emu_reg_grps[i].grp_type,
2074 i, ARRAY_SIZE(xen_pt_emu_reg_grps));
2075 error_propagate(errp, err);
2076 xen_pt_config_delete(s);
2077 return;
2078 }
2079 }
2080 }
2081 }
2082 }
2083 }
2084
2085 /* delete all emulate register */
2086 void xen_pt_config_delete(XenPCIPassthroughState *s)
2087 {
2088 struct XenPTRegGroup *reg_group, *next_grp;
2089 struct XenPTReg *reg, *next_reg;
2090
2091 /* free MSI/MSI-X info table */
2092 if (s->msix) {
2093 xen_pt_msix_unmap(s);
2094 }
2095 g_free(s->msi);
2096
2097 /* free all register group entry */
2098 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
2099 /* free all register entry */
2100 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
2101 QLIST_REMOVE(reg, entries);
2102 g_free(reg);
2103 }
2104
2105 QLIST_REMOVE(reg_group, entries);
2106 g_free(reg_group);
2107 }
2108 }
AR7 emulation for QEMU