tests/ide-test.c

   1 /*
   2  * IDE test cases
   3  *
   4  * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/libqos.h"
  33 #include "libqos/pci-pc.h"
  34 #include "libqos/malloc-pc.h"
  35
  36 #include "qemu-common.h"
  37 #include "hw/pci/pci_ids.h"
  38 #include "hw/pci/pci_regs.h"
  39
  40 #define TEST_IMAGE_SIZE 64 * 1024 * 1024
  41
  42 #define IDE_PCI_DEV     1
  43 #define IDE_PCI_FUNC    1
  44
  45 #define IDE_BASE 0x1f0
  46 #define IDE_PRIMARY_IRQ 14
  47
  48 #define ATAPI_BLOCK_SIZE 2048
  49
  50 /* How many bytes to receive via ATAPI PIO at one time.
  51  * Must be less than 0xFFFF. */
  52 #define BYTE_COUNT_LIMIT 5120
  53
  54 enum {
  55     reg_data        = 0x0,
  56     reg_feature     = 0x1,
  57     reg_nsectors    = 0x2,
  58     reg_lba_low     = 0x3,
  59     reg_lba_middle  = 0x4,
  60     reg_lba_high    = 0x5,
  61     reg_device      = 0x6,
  62     reg_status      = 0x7,
  63     reg_command     = 0x7,
  64 };
  65
  66 enum {
  67     BSY     = 0x80,
  68     DRDY    = 0x40,
  69     DF      = 0x20,
  70     DRQ     = 0x08,
  71     ERR     = 0x01,
  72 };
  73
  74 enum {
  75     DEV     = 0x10,
  76     LBA     = 0x40,
  77 };
  78
  79 enum {
  80     bmreg_cmd       = 0x0,
  81     bmreg_status    = 0x2,
  82     bmreg_prdt      = 0x4,
  83 };
  84
  85 enum {
  86     CMD_READ_DMA    = 0xc8,
  87     CMD_WRITE_DMA   = 0xca,
  88     CMD_FLUSH_CACHE = 0xe7,
  89     CMD_IDENTIFY    = 0xec,
  90     CMD_PACKET      = 0xa0,
  91
  92     CMDF_ABORT      = 0x100,
  93     CMDF_NO_BM      = 0x200,
  94 };
  95
  96 enum {
  97     BM_CMD_START    =  0x1,
  98     BM_CMD_WRITE    =  0x8, /* write = from device to memory */
  99 };
 100
 101 enum {
 102     BM_STS_ACTIVE   =  0x1,
 103     BM_STS_ERROR    =  0x2,
 104     BM_STS_INTR     =  0x4,
 105 };
 106
 107 enum {
 108     PRDT_EOT        = 0x80000000,
 109 };
 110
 111 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
 112 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
 113
 114 static QPCIBus *pcibus = NULL;
 115 static QGuestAllocator *guest_malloc;
 116
 117 static char tmp_path[] = "/tmp/qtest.XXXXXX";
 118 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
 119
 120 static void ide_test_start(const char *cmdline_fmt, ...)
 121 {
 122     va_list ap;
 123     char *cmdline;
 124
 125     va_start(ap, cmdline_fmt);
 126     cmdline = g_strdup_vprintf(cmdline_fmt, ap);
 127     va_end(ap);
 128
 129     qtest_start(cmdline);
 130     guest_malloc = pc_alloc_init();
 131
 132     g_free(cmdline);
 133 }
 134
 135 static void ide_test_quit(void)
 136 {
 137     pc_alloc_uninit(guest_malloc);
 138     guest_malloc = NULL;
 139     qtest_end();
 140 }
 141
 142 static QPCIDevice *get_pci_device(uint16_t *bmdma_base)
 143 {
 144     QPCIDevice *dev;
 145     uint16_t vendor_id, device_id;
 146
 147     if (!pcibus) {
 148         pcibus = qpci_init_pc();
 149     }
 150
 151     /* Find PCI device and verify it's the right one */
 152     dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC));
 153     g_assert(dev != NULL);
 154
 155     vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
 156     device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
 157     g_assert(vendor_id == PCI_VENDOR_ID_INTEL);
 158     g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
 159
 160     /* Map bmdma BAR */
 161     *bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4, NULL);
 162
 163     qpci_device_enable(dev);
 164
 165     return dev;
 166 }
 167
 168 static void free_pci_device(QPCIDevice *dev)
 169 {
 170     /* libqos doesn't have a function for this, so free it manually */
 171     g_free(dev);
 172 }
 173
 174 typedef struct PrdtEntry {
 175     uint32_t addr;
 176     uint32_t size;
 177 } QEMU_PACKED PrdtEntry;
 178
 179 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
 180 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
 181
 182 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
 183                             PrdtEntry *prdt, int prdt_entries,
 184                             void(*post_exec)(uint64_t sector, int nb_sectors))
 185 {
 186     QPCIDevice *dev;
 187     uint16_t bmdma_base;
 188     uintptr_t guest_prdt;
 189     size_t len;
 190     bool from_dev;
 191     uint8_t status;
 192     int flags;
 193
 194     dev = get_pci_device(&bmdma_base);
 195
 196     flags = cmd & ~0xff;
 197     cmd &= 0xff;
 198
 199     switch (cmd) {
 200     case CMD_READ_DMA:
 201     case CMD_PACKET:
 202         /* Assuming we only test data reads w/ ATAPI, otherwise we need to know
 203          * the SCSI command being sent in the packet, too. */
 204         from_dev = true;
 205         break;
 206     case CMD_WRITE_DMA:
 207         from_dev = false;
 208         break;
 209     default:
 210         g_assert_not_reached();
 211     }
 212
 213     if (flags & CMDF_NO_BM) {
 214         qpci_config_writew(dev, PCI_COMMAND,
 215                            PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
 216     }
 217
 218     /* Select device 0 */
 219     outb(IDE_BASE + reg_device, 0 | LBA);
 220
 221     /* Stop any running transfer, clear any pending interrupt */
 222     outb(bmdma_base + bmreg_cmd, 0);
 223     outb(bmdma_base + bmreg_status, BM_STS_INTR);
 224
 225     /* Setup PRDT */
 226     len = sizeof(*prdt) * prdt_entries;
 227     guest_prdt = guest_alloc(guest_malloc, len);
 228     memwrite(guest_prdt, prdt, len);
 229     outl(bmdma_base + bmreg_prdt, guest_prdt);
 230
 231     /* ATA DMA command */
 232     if (cmd == CMD_PACKET) {
 233         /* Enables ATAPI DMA; otherwise PIO is attempted */
 234         outb(IDE_BASE + reg_feature, 0x01);
 235     } else {
 236         outb(IDE_BASE + reg_nsectors, nb_sectors);
 237         outb(IDE_BASE + reg_lba_low,    sector & 0xff);
 238         outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff);
 239         outb(IDE_BASE + reg_lba_high,   (sector >> 16) & 0xff);
 240     }
 241
 242     outb(IDE_BASE + reg_command, cmd);
 243
 244     if (post_exec) {
 245         post_exec(sector, nb_sectors);
 246     }
 247
 248     /* Start DMA transfer */
 249     outb(bmdma_base + bmreg_cmd, BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));
 250
 251     if (flags & CMDF_ABORT) {
 252         outb(bmdma_base + bmreg_cmd, 0);
 253     }
 254
 255     /* Wait for the DMA transfer to complete */
 256     do {
 257         status = inb(bmdma_base + bmreg_status);
 258     } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);
 259
 260     g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));
 261
 262     /* Check IDE status code */
 263     assert_bit_set(inb(IDE_BASE + reg_status), DRDY);
 264     assert_bit_clear(inb(IDE_BASE + reg_status), BSY | DRQ);
 265
 266     /* Reading the status register clears the IRQ */
 267     g_assert(!get_irq(IDE_PRIMARY_IRQ));
 268
 269     /* Stop DMA transfer if still active */
 270     if (status & BM_STS_ACTIVE) {
 271         outb(bmdma_base + bmreg_cmd, 0);
 272     }
 273
 274     free_pci_device(dev);
 275
 276     return status;
 277 }
 278
 279 static void test_bmdma_simple_rw(void)
 280 {
 281     uint8_t status;
 282     uint8_t *buf;
 283     uint8_t *cmpbuf;
 284     size_t len = 512;
 285     uintptr_t guest_buf = guest_alloc(guest_malloc, len);
 286
 287     PrdtEntry prdt[] = {
 288         {
 289             .addr = cpu_to_le32(guest_buf),
 290             .size = cpu_to_le32(len | PRDT_EOT),
 291         },
 292     };
 293
 294     buf = g_malloc(len);
 295     cmpbuf = g_malloc(len);
 296
 297     /* Write 0x55 pattern to sector 0 */
 298     memset(buf, 0x55, len);
 299     memwrite(guest_buf, buf, len);
 300
 301     status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt,
 302                               ARRAY_SIZE(prdt), NULL);
 303     g_assert_cmphex(status, ==, BM_STS_INTR);
 304     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 305
 306     /* Write 0xaa pattern to sector 1 */
 307     memset(buf, 0xaa, len);
 308     memwrite(guest_buf, buf, len);
 309
 310     status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
 311                               ARRAY_SIZE(prdt), NULL);
 312     g_assert_cmphex(status, ==, BM_STS_INTR);
 313     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 314
 315     /* Read and verify 0x55 pattern in sector 0 */
 316     memset(cmpbuf, 0x55, len);
 317
 318     status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL);
 319     g_assert_cmphex(status, ==, BM_STS_INTR);
 320     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 321
 322     memread(guest_buf, buf, len);
 323     g_assert(memcmp(buf, cmpbuf, len) == 0);
 324
 325     /* Read and verify 0xaa pattern in sector 1 */
 326     memset(cmpbuf, 0xaa, len);
 327
 328     status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL);
 329     g_assert_cmphex(status, ==, BM_STS_INTR);
 330     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 331
 332     memread(guest_buf, buf, len);
 333     g_assert(memcmp(buf, cmpbuf, len) == 0);
 334
 335
 336     g_free(buf);
 337     g_free(cmpbuf);
 338 }
 339
 340 static void test_bmdma_short_prdt(void)
 341 {
 342     uint8_t status;
 343
 344     PrdtEntry prdt[] = {
 345         {
 346             .addr = 0,
 347             .size = cpu_to_le32(0x10 | PRDT_EOT),
 348         },
 349     };
 350
 351     /* Normal request */
 352     status = send_dma_request(CMD_READ_DMA, 0, 1,
 353                               prdt, ARRAY_SIZE(prdt), NULL);
 354     g_assert_cmphex(status, ==, 0);
 355     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 356
 357     /* Abort the request before it completes */
 358     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
 359                               prdt, ARRAY_SIZE(prdt), NULL);
 360     g_assert_cmphex(status, ==, 0);
 361     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 362 }
 363
 364 static void test_bmdma_one_sector_short_prdt(void)
 365 {
 366     uint8_t status;
 367
 368     /* Read 2 sectors but only give 1 sector in PRDT */
 369     PrdtEntry prdt[] = {
 370         {
 371             .addr = 0,
 372             .size = cpu_to_le32(0x200 | PRDT_EOT),
 373         },
 374     };
 375
 376     /* Normal request */
 377     status = send_dma_request(CMD_READ_DMA, 0, 2,
 378                               prdt, ARRAY_SIZE(prdt), NULL);
 379     g_assert_cmphex(status, ==, 0);
 380     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 381
 382     /* Abort the request before it completes */
 383     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2,
 384                               prdt, ARRAY_SIZE(prdt), NULL);
 385     g_assert_cmphex(status, ==, 0);
 386     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 387 }
 388
 389 static void test_bmdma_long_prdt(void)
 390 {
 391     uint8_t status;
 392
 393     PrdtEntry prdt[] = {
 394         {
 395             .addr = 0,
 396             .size = cpu_to_le32(0x1000 | PRDT_EOT),
 397         },
 398     };
 399
 400     /* Normal request */
 401     status = send_dma_request(CMD_READ_DMA, 0, 1,
 402                               prdt, ARRAY_SIZE(prdt), NULL);
 403     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
 404     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 405
 406     /* Abort the request before it completes */
 407     status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
 408                               prdt, ARRAY_SIZE(prdt), NULL);
 409     g_assert_cmphex(status, ==, BM_STS_INTR);
 410     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 411 }
 412
 413 static void test_bmdma_no_busmaster(void)
 414 {
 415     uint8_t status;
 416
 417     /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
 418      * able to access it anyway because the Bus Master bit in the PCI command
 419      * register isn't set. This is complete nonsense, but it used to be pretty
 420      * good at confusing and occasionally crashing qemu. */
 421     PrdtEntry prdt[4096] = { };
 422
 423     status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512,
 424                               prdt, ARRAY_SIZE(prdt), NULL);
 425
 426     /* Not entirely clear what the expected result is, but this is what we get
 427      * in practice. At least we want to be aware of any changes. */
 428     g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
 429     assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
 430 }
 431
 432 static void test_bmdma_setup(void)
 433 {
 434     ide_test_start(
 435         "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw "
 436         "-global ide-hd.ver=%s",
 437         tmp_path, "testdisk", "version");
 438     qtest_irq_intercept_in(global_qtest, "ioapic");
 439 }
 440
 441 static void test_bmdma_teardown(void)
 442 {
 443     ide_test_quit();
 444 }
 445
 446 static void string_cpu_to_be16(uint16_t *s, size_t bytes)
 447 {
 448     g_assert((bytes & 1) == 0);
 449     bytes /= 2;
 450
 451     while (bytes--) {
 452         *s = cpu_to_be16(*s);
 453         s++;
 454     }
 455 }
 456
 457 static void test_identify(void)
 458 {
 459     uint8_t data;
 460     uint16_t buf[256];
 461     int i;
 462     int ret;
 463
 464     ide_test_start(
 465         "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw "
 466         "-global ide-hd.ver=%s",
 467         tmp_path, "testdisk", "version");
 468
 469     /* IDENTIFY command on device 0*/
 470     outb(IDE_BASE + reg_device, 0);
 471     outb(IDE_BASE + reg_command, CMD_IDENTIFY);
 472
 473     /* Read in the IDENTIFY buffer and check registers */
 474     data = inb(IDE_BASE + reg_device);
 475     g_assert_cmpint(data & DEV, ==, 0);
 476
 477     for (i = 0; i < 256; i++) {
 478         data = inb(IDE_BASE + reg_status);
 479         assert_bit_set(data, DRDY | DRQ);
 480         assert_bit_clear(data, BSY | DF | ERR);
 481
 482         ((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data);
 483     }
 484
 485     data = inb(IDE_BASE + reg_status);
 486     assert_bit_set(data, DRDY);
 487     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 488
 489     /* Check serial number/version in the buffer */
 490     string_cpu_to_be16(&buf[10], 20);
 491     ret = memcmp(&buf[10], "testdisk            ", 20);
 492     g_assert(ret == 0);
 493
 494     string_cpu_to_be16(&buf[23], 8);
 495     ret = memcmp(&buf[23], "version ", 8);
 496     g_assert(ret == 0);
 497
 498     /* Write cache enabled bit */
 499     assert_bit_set(buf[85], 0x20);
 500
 501     ide_test_quit();
 502 }
 503
 504 static void test_flush(void)
 505 {
 506     uint8_t data;
 507
 508     ide_test_start(
 509         "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
 510         tmp_path);
 511
 512     /* Delay the completion of the flush request until we explicitly do it */
 513     g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\""));
 514
 515     /* FLUSH CACHE command on device 0*/
 516     outb(IDE_BASE + reg_device, 0);
 517     outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
 518
 519     /* Check status while request is in flight*/
 520     data = inb(IDE_BASE + reg_status);
 521     assert_bit_set(data, BSY | DRDY);
 522     assert_bit_clear(data, DF | ERR | DRQ);
 523
 524     /* Complete the command */
 525     g_free(hmp("qemu-io ide0-hd0 \"resume A\""));
 526
 527     /* Check registers */
 528     data = inb(IDE_BASE + reg_device);
 529     g_assert_cmpint(data & DEV, ==, 0);
 530
 531     do {
 532         data = inb(IDE_BASE + reg_status);
 533     } while (data & BSY);
 534
 535     assert_bit_set(data, DRDY);
 536     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 537
 538     ide_test_quit();
 539 }
 540
 541 static void test_retry_flush(const char *machine)
 542 {
 543     uint8_t data;
 544     const char *s;
 545
 546     prepare_blkdebug_script(debug_path, "flush_to_disk");
 547
 548     ide_test_start(
 549         "-vnc none "
 550         "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
 551         "rerror=stop,werror=stop",
 552         debug_path, tmp_path);
 553
 554     /* FLUSH CACHE command on device 0*/
 555     outb(IDE_BASE + reg_device, 0);
 556     outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
 557
 558     /* Check status while request is in flight*/
 559     data = inb(IDE_BASE + reg_status);
 560     assert_bit_set(data, BSY | DRDY);
 561     assert_bit_clear(data, DF | ERR | DRQ);
 562
 563     qmp_eventwait("STOP");
 564
 565     /* Complete the command */
 566     s = "{'execute':'cont' }";
 567     qmp_discard_response(s);
 568
 569     /* Check registers */
 570     data = inb(IDE_BASE + reg_device);
 571     g_assert_cmpint(data & DEV, ==, 0);
 572
 573     do {
 574         data = inb(IDE_BASE + reg_status);
 575     } while (data & BSY);
 576
 577     assert_bit_set(data, DRDY);
 578     assert_bit_clear(data, BSY | DF | ERR | DRQ);
 579
 580     ide_test_quit();
 581 }
 582
 583 static void test_flush_nodev(void)
 584 {
 585     ide_test_start("");
 586
 587     /* FLUSH CACHE command on device 0*/
 588     outb(IDE_BASE + reg_device, 0);
 589     outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
 590
 591     /* Just testing that qemu doesn't crash... */
 592
 593     ide_test_quit();
 594 }
 595
 596 static void test_pci_retry_flush(void)
 597 {
 598     test_retry_flush("pc");
 599 }
 600
 601 static void test_isa_retry_flush(void)
 602 {
 603     test_retry_flush("isapc");
 604 }
 605
 606 typedef struct Read10CDB {
 607     uint8_t opcode;
 608     uint8_t flags;
 609     uint32_t lba;
 610     uint8_t reserved;
 611     uint16_t nblocks;
 612     uint8_t control;
 613     uint16_t padding;
 614 } __attribute__((__packed__)) Read10CDB;
 615
 616 static void send_scsi_cdb_read10(uint64_t lba, int nblocks)
 617 {
 618     Read10CDB pkt = { .padding = 0 };
 619     int i;
 620
 621     g_assert_cmpint(lba, <=, UINT32_MAX);
 622     g_assert_cmpint(nblocks, <=, UINT16_MAX);
 623     g_assert_cmpint(nblocks, >=, 0);
 624
 625     /* Construct SCSI CDB packet */
 626     pkt.opcode = 0x28;
 627     pkt.lba = cpu_to_be32(lba);
 628     pkt.nblocks = cpu_to_be16(nblocks);
 629
 630     /* Send Packet */
 631     for (i = 0; i < sizeof(Read10CDB)/2; i++) {
 632         outw(IDE_BASE + reg_data, cpu_to_le16(((uint16_t *)&pkt)[i]));
 633     }
 634 }
 635
 636 static void nsleep(int64_t nsecs)
 637 {
 638     const struct timespec val = { .tv_nsec = nsecs };
 639     nanosleep(&val, NULL);
 640     clock_set(nsecs);
 641 }
 642
 643 static uint8_t ide_wait_clear(uint8_t flag)
 644 {
 645     uint8_t data;
 646     time_t st;
 647
 648     /* Wait with a 5 second timeout */
 649     time(&st);
 650     while (true) {
 651         data = inb(IDE_BASE + reg_status);
 652         if (!(data & flag)) {
 653             return data;
 654         }
 655         if (difftime(time(NULL), st) > 5.0) {
 656             break;
 657         }
 658         nsleep(400);
 659     }
 660     g_assert_not_reached();
 661 }
 662
 663 static void ide_wait_intr(int irq)
 664 {
 665     time_t st;
 666     bool intr;
 667
 668     time(&st);
 669     while (true) {
 670         intr = get_irq(irq);
 671         if (intr) {
 672             return;
 673         }
 674         if (difftime(time(NULL), st) > 5.0) {
 675             break;
 676         }
 677         nsleep(400);
 678     }
 679
 680     g_assert_not_reached();
 681 }
 682
 683 static void cdrom_pio_impl(int nblocks)
 684 {
 685     FILE *fh;
 686     int patt_blocks = MAX(16, nblocks);
 687     size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks;
 688     char *pattern = g_malloc(patt_len);
 689     size_t rxsize = ATAPI_BLOCK_SIZE * nblocks;
 690     uint16_t *rx = g_malloc0(rxsize);
 691     int i, j;
 692     uint8_t data;
 693     uint16_t limit;
 694
 695     /* Prepopulate the CDROM with an interesting pattern */
 696     generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE);
 697     fh = fopen(tmp_path, "w+");
 698     fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh);
 699     fclose(fh);
 700
 701     ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
 702                    "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
 703     qtest_irq_intercept_in(global_qtest, "ioapic");
 704
 705     /* PACKET command on device 0 */
 706     outb(IDE_BASE + reg_device, 0);
 707     outb(IDE_BASE + reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF);
 708     outb(IDE_BASE + reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF));
 709     outb(IDE_BASE + reg_command, CMD_PACKET);
 710     /* HP0: Check_Status_A State */
 711     nsleep(400);
 712     data = ide_wait_clear(BSY);
 713     /* HP1: Send_Packet State */
 714     assert_bit_set(data, DRQ | DRDY);
 715     assert_bit_clear(data, ERR | DF | BSY);
 716
 717     /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
 718     send_scsi_cdb_read10(0, nblocks);
 719
 720     /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
 721      * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
 722      * We allow an odd limit only when the remaining transfer size is
 723      * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only
 724      * request n blocks, so our request size is always even.
 725      * For this reason, we assume there is never a hanging byte to fetch. */
 726     g_assert(!(rxsize & 1));
 727     limit = BYTE_COUNT_LIMIT & ~1;
 728     for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
 729         size_t offset = i * (limit / 2);
 730         size_t rem = (rxsize / 2) - offset;
 731
 732         /* HP3: INTRQ_Wait */
 733         ide_wait_intr(IDE_PRIMARY_IRQ);
 734
 735         /* HP2: Check_Status_B (and clear IRQ) */
 736         data = ide_wait_clear(BSY);
 737         assert_bit_set(data, DRQ | DRDY);
 738         assert_bit_clear(data, ERR | DF | BSY);
 739
 740         /* HP4: Transfer_Data */
 741         for (j = 0; j < MIN((limit / 2), rem); j++) {
 742             rx[offset + j] = le16_to_cpu(inw(IDE_BASE + reg_data));
 743         }
 744     }
 745
 746     /* Check for final completion IRQ */
 747     ide_wait_intr(IDE_PRIMARY_IRQ);
 748
 749     /* Sanity check final state */
 750     data = ide_wait_clear(DRQ);
 751     assert_bit_set(data, DRDY);
 752     assert_bit_clear(data, DRQ | ERR | DF | BSY);
 753
 754     g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0);
 755     g_free(pattern);
 756     g_free(rx);
 757     test_bmdma_teardown();
 758 }
 759
 760 static void test_cdrom_pio(void)
 761 {
 762     cdrom_pio_impl(1);
 763 }
 764
 765 static void test_cdrom_pio_large(void)
 766 {
 767     /* Test a few loops of the PIO DRQ mechanism. */
 768     cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE);
 769 }
 770
 771
 772 static void test_cdrom_dma(void)
 773 {
 774     static const size_t len = ATAPI_BLOCK_SIZE;
 775     char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16);
 776     char *rx = g_malloc0(len);
 777     uintptr_t guest_buf;
 778     PrdtEntry prdt[1];
 779     FILE *fh;
 780
 781     ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
 782                    "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
 783     qtest_irq_intercept_in(global_qtest, "ioapic");
 784
 785     guest_buf = guest_alloc(guest_malloc, len);
 786     prdt[0].addr = cpu_to_le32(guest_buf);
 787     prdt[0].size = cpu_to_le32(len | PRDT_EOT);
 788
 789     generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE);
 790     fh = fopen(tmp_path, "w+");
 791     fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh);
 792     fclose(fh);
 793
 794     send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10);
 795
 796     /* Read back data from guest memory into local qtest memory */
 797     memread(guest_buf, rx, len);
 798     g_assert_cmpint(memcmp(pattern, rx, len), ==, 0);
 799
 800     g_free(pattern);
 801     g_free(rx);
 802     test_bmdma_teardown();
 803 }
 804
 805 int main(int argc, char **argv)
 806 {
 807     const char *arch = qtest_get_arch();
 808     int fd;
 809     int ret;
 810
 811     /* Check architecture */
 812     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
 813         g_test_message("Skipping test for non-x86\n");
 814         return 0;
 815     }
 816
 817     /* Create temporary blkdebug instructions */
 818     fd = mkstemp(debug_path);
 819     g_assert(fd >= 0);
 820     close(fd);
 821
 822     /* Create a temporary raw image */
 823     fd = mkstemp(tmp_path);
 824     g_assert(fd >= 0);
 825     ret = ftruncate(fd, TEST_IMAGE_SIZE);
 826     g_assert(ret == 0);
 827     close(fd);
 828
 829     /* Run the tests */
 830     g_test_init(&argc, &argv, NULL);
 831
 832     qtest_add_func("/ide/identify", test_identify);
 833
 834     qtest_add_func("/ide/bmdma/setup", test_bmdma_setup);
 835     qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw);
 836     qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt);
 837     qtest_add_func("/ide/bmdma/one_sector_short_prdt",
 838                    test_bmdma_one_sector_short_prdt);
 839     qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt);
 840     qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster);
 841     qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown);
 842
 843     qtest_add_func("/ide/flush", test_flush);
 844     qtest_add_func("/ide/flush/nodev", test_flush_nodev);
 845     qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush);
 846     qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush);
 847
 848     qtest_add_func("/ide/cdrom/pio", test_cdrom_pio);
 849     qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large);
 850     qtest_add_func("/ide/cdrom/dma", test_cdrom_dma);
 851
 852     ret = g_test_run();
 853
 854     /* Cleanup */
 855     unlink(tmp_path);
 856     unlink(debug_path);
 857
 858     return ret;
 859 }