virtio-gpu: change licence from GPLv2 to GPLv2+
[qemu/ar7.git] / target-s390x / insn-format.def
blob0e898b90bd6cc676351691bfb8630c6b62fedd90
1 /* Description of s390 insn formats. */
2 /* NAME F1, F2... */
3 F0(E)
4 F1(I, I(1, 8, 8))
5 F2(RI_a, R(1, 8), I(2,16,16))
6 F2(RI_b, R(1, 8), I(2,16,16))
7 F2(RI_c, M(1, 8), I(2,16,16))
8 F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
9 F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
10 F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
11 F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
12 F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
14 F2(RIL_a, R(1, 8), I(2,16,32))
15 F2(RIL_b, R(1, 8), I(2,16,32))
16 F2(RIL_c, M(1, 8), I(2,16,32))
17 F4(RIS, R(1, 8), I(2,32, 8), M(3,12), BD(4,16,20))
18 /* ??? The PoO does not call out subtypes _a and _b for RR, as it does
19 for e.g. RX. Our checking requires this for e.g. BCR. */
20 F2(RR_a, R(1, 8), R(2,12))
21 F2(RR_b, M(1, 8), R(2,12))
22 F2(RRE, R(1,24), R(2,28))
23 F3(RRD, R(1,16), R(2,28), R(3,24))
24 F4(RRF_a, R(1,24), R(2,28), R(3,16), M(4,20))
25 F4(RRF_b, R(1,24), R(2,28), R(3,16), M(4,20))
26 F4(RRF_c, R(1,24), R(2,28), M(3,16), M(4,20))
27 F4(RRF_d, R(1,24), R(2,28), M(3,16), M(4,20))
28 F4(RRF_e, R(1,24), R(2,28), M(3,16), M(4,20))
29 F4(RRS, R(1, 8), R(2,12), M(3,32), BD(4,16,20))
30 F3(RS_a, R(1, 8), BD(2,16,20), R(3,12))
31 F3(RS_b, R(1, 8), BD(2,16,20), M(3,12))
32 F3(RSI, R(1, 8), I(2,16,16), R(3,12))
33 F2(RSL, L(1, 8, 4), BD(1,16,20))
34 F3(RSY_a, R(1, 8), BDL(2), R(3,12))
35 F3(RSY_b, R(1, 8), BDL(2), M(3,12))
36 F2(RX_a, R(1, 8), BXD(2))
37 F2(RX_b, M(1, 8), BXD(2))
38 F2(RXE, R(1, 8), BXD(2))
39 F3(RXF, R(1,32), BXD(2), R(3, 8))
40 F2(RXY_a, R(1, 8), BXDL(2))
41 F2(RXY_b, M(1, 8), BXDL(2))
42 F1(S, BD(2,16,20))
43 F2(SI, BD(1,16,20), I(2,8,8))
44 F2(SIL, BD(1,16,20), I(2,32,16))
45 F2(SIY, BDL(1), I(2, 8, 8))
46 F3(SS_a, L(1, 8, 8), BD(1,16,20), BD(2,32,36))
47 F4(SS_b, L(1, 8, 4), BD(1,16,20), L(2,12,4), BD(2,32,36))
48 F4(SS_c, L(1, 8, 4), BD(1,16,20), BD(2,32,36), I(3,12, 4))
49 /* ??? Odd man out. The L1 field here is really a register, but the
50 easy way to compress the fields has R1 and B1 overlap. */
51 F4(SS_d, L(1, 8, 4), BD(1,16,20), BD(2,32,36), R(3,12))
52 F4(SS_e, R(1, 8), BD(2,16,20), R(3,12), BD(4,32,36))
53 F3(SS_f, BD(1,16,20), L(2,8,8), BD(2,32,36))
54 F2(SSE, BD(1,16,20), BD(2,32,36))
55 F3(SSF, BD(1,16,20), BD(2,32,36), R(3,8))