target/openrisc/gdbstub.c

   1 /*
   2  * OpenRISC gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "gdbstub/helpers.h"
  23
  24 int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
  25 {
  26     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  27     CPUOpenRISCState *env = &cpu->env;
  28
  29     if (n < 32) {
  30         return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
  31     } else {
  32         switch (n) {
  33         case 32:    /* PPC */
  34             return gdb_get_reg32(mem_buf, env->ppc);
  35
  36         case 33:    /* NPC (equals PC) */
  37             return gdb_get_reg32(mem_buf, env->pc);
  38
  39         case 34:    /* SR */
  40             return gdb_get_reg32(mem_buf, cpu_get_sr(env));
  41
  42         default:
  43             break;
  44         }
  45     }
  46     return 0;
  47 }
  48
  49 int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  50 {
  51     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  52     CPUClass *cc = CPU_GET_CLASS(cs);
  53     CPUOpenRISCState *env = &cpu->env;
  54     uint32_t tmp;
  55
  56     if (n > cc->gdb_num_core_regs) {
  57         return 0;
  58     }
  59
  60     tmp = ldl_p(mem_buf);
  61
  62     if (n < 32) {
  63         cpu_set_gpr(env, n, tmp);
  64     } else {
  65         switch (n) {
  66         case 32: /* PPC */
  67             env->ppc = tmp;
  68             break;
  69
  70         case 33: /* NPC (equals PC) */
  71             /* If setting PC to something different,
  72                also clear delayed branch status.  */
  73             if (env->pc != tmp) {
  74                 env->pc = tmp;
  75                 env->dflag = 0;
  76             }
  77             break;
  78
  79         case 34: /* SR */
  80             cpu_set_sr(env, tmp);
  81             break;
  82
  83         default:
  84             break;
  85         }
  86     }
  87     return 4;
  88 }