target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  59                             int srcreg, int operand, uint32_t value);
  60 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  61                                int dstreg, int operand);
  62
  63 struct arm_boot_info;
  64
  65 #define NB_MMU_MODES 2
  66
  67 /* We currently assume float and double are IEEE single and double
  68    precision respectively.
  69    Doing runtime conversions is tricky because VFP registers may contain
  70    integer values (eg. as the result of a FTOSI instruction).
  71    s<2n> maps to the least significant half of d<n>
  72    s<2n+1> maps to the most significant half of d<n>
  73  */
  74
  75 typedef struct CPUARMState {
  76     /* Regs for current mode.  */
  77     uint32_t regs[16];
  78     /* Frequently accessed CPSR bits are stored separately for efficiently.
  79        This contains all the other bits.  Use cpsr_{read,write} to access
  80        the whole CPSR.  */
  81     uint32_t uncached_cpsr;
  82     uint32_t spsr;
  83
  84     /* Banked registers.  */
  85     uint32_t banked_spsr[6];
  86     uint32_t banked_r13[6];
  87     uint32_t banked_r14[6];
  88
  89     /* These hold r8-r12.  */
  90     uint32_t usr_regs[5];
  91     uint32_t fiq_regs[5];
  92
  93     /* cpsr flag cache for faster execution */
  94     uint32_t CF; /* 0 or 1 */
  95     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  96     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  97     uint32_t ZF; /* Z set if zero.  */
  98     uint32_t QF; /* 0 or 1 */
  99     uint32_t GE; /* cpsr[19:16] */
 100     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 101     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 102
 103     /* System control coprocessor (cp15) */
 104     struct {
 105         uint32_t c0_cpuid;
 106         uint32_t c0_cachetype;
 107         uint32_t c0_ccsid[16]; /* Cache size.  */
 108         uint32_t c0_clid; /* Cache level.  */
 109         uint32_t c0_cssel; /* Cache size selection.  */
 110         uint32_t c0_c1[8]; /* Feature registers.  */
 111         uint32_t c0_c2[8]; /* Instruction set registers.  */
 112         uint32_t c1_sys; /* System control register.  */
 113         uint32_t c1_coproc; /* Coprocessor access register.  */
 114         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 115         uint32_t c2_base0; /* MMU translation table base 0.  */
 116         uint32_t c2_base1; /* MMU translation table base 1.  */
 117         uint32_t c2_control; /* MMU translation table base control.  */
 118         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 119         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 120         uint32_t c2_data; /* MPU data cachable bits.  */
 121         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 122         uint32_t c3; /* MMU domain access control register
 123                         MPU write buffer control.  */
 124         uint32_t c5_insn; /* Fault status registers.  */
 125         uint32_t c5_data;
 126         uint32_t c6_region[8]; /* MPU base/size registers.  */
 127         uint32_t c6_insn; /* Fault address registers.  */
 128         uint32_t c6_data;
 129         uint32_t c9_insn; /* Cache lockdown registers.  */
 130         uint32_t c9_data;
 131         uint32_t c13_fcse; /* FCSE PID.  */
 132         uint32_t c13_context; /* Context ID.  */
 133         uint32_t c13_tls1; /* User RW Thread register.  */
 134         uint32_t c13_tls2; /* User RO Thread register.  */
 135         uint32_t c13_tls3; /* Privileged Thread register.  */
 136         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 137         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 138         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 139         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 140         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 141     } cp15;
 142
 143     struct {
 144         uint32_t other_sp;
 145         uint32_t vecbase;
 146         uint32_t basepri;
 147         uint32_t control;
 148         int current_sp;
 149         int exception;
 150         int pending_exception;
 151     } v7m;
 152
 153     /* Thumb-2 EE state.  */
 154     uint32_t teecr;
 155     uint32_t teehbr;
 156
 157     /* Internal CPU feature flags.  */
 158     uint32_t features;
 159
 160     /* Callback for vectored interrupt controller.  */
 161     int (*get_irq_vector)(struct CPUARMState *);
 162     void *irq_opaque;
 163
 164     /* VFP coprocessor state.  */
 165     struct {
 166         float64 regs[32];
 167
 168         uint32_t xregs[16];
 169         /* We store these fpcsr fields separately for convenience.  */
 170         int vec_len;
 171         int vec_stride;
 172
 173         /* scratch space when Tn are not sufficient.  */
 174         uint32_t scratch[8];
 175
 176         float_status fp_status;
 177     } vfp;
 178     uint32_t exclusive_addr;
 179     uint32_t exclusive_val;
 180     uint32_t exclusive_high;
 181 #if defined(CONFIG_USER_ONLY)
 182     uint32_t exclusive_test;
 183     uint32_t exclusive_info;
 184 #endif
 185
 186     /* iwMMXt coprocessor state.  */
 187     struct {
 188         uint64_t regs[16];
 189         uint64_t val;
 190
 191         uint32_t cregs[16];
 192     } iwmmxt;
 193
 194 #if defined(CONFIG_USER_ONLY)
 195     /* For usermode syscall translation.  */
 196     int eabi;
 197 #endif
 198
 199     CPU_COMMON
 200
 201     /* These fields after the common ones so they are preserved on reset.  */
 202
 203     /* Coprocessor IO used by peripherals */
 204     struct {
 205         ARMReadCPFunc *cp_read;
 206         ARMWriteCPFunc *cp_write;
 207         void *opaque;
 208     } cp[15];
 209     void *nvic;
 210     struct arm_boot_info *boot_info;
 211 } CPUARMState;
 212
 213 CPUARMState *cpu_arm_init(const char *cpu_model);
 214 void arm_translate_init(void);
 215 int cpu_arm_exec(CPUARMState *s);
 216 void cpu_arm_close(CPUARMState *s);
 217 void do_interrupt(CPUARMState *);
 218 void switch_mode(CPUARMState *, int);
 219 uint32_t do_arm_semihosting(CPUARMState *env);
 220
 221 /* you can call this signal handler from your SIGBUS and SIGSEGV
 222    signal handlers to inform the virtual CPU of exceptions. non zero
 223    is returned if the signal was handled by the virtual CPU.  */
 224 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 225                            void *puc);
 226 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 227                               int mmu_idx, int is_softmuu);
 228 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 229
 230 void cpu_lock(void);
 231 void cpu_unlock(void);
 232 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 233 {
 234   env->cp15.c13_tls2 = newtls;
 235 }
 236
 237 #define CPSR_M (0x1f)
 238 #define CPSR_T (1 << 5)
 239 #define CPSR_F (1 << 6)
 240 #define CPSR_I (1 << 7)
 241 #define CPSR_A (1 << 8)
 242 #define CPSR_E (1 << 9)
 243 #define CPSR_IT_2_7 (0xfc00)
 244 #define CPSR_GE (0xf << 16)
 245 #define CPSR_RESERVED (0xf << 20)
 246 #define CPSR_J (1 << 24)
 247 #define CPSR_IT_0_1 (3 << 25)
 248 #define CPSR_Q (1 << 27)
 249 #define CPSR_V (1 << 28)
 250 #define CPSR_C (1 << 29)
 251 #define CPSR_Z (1 << 30)
 252 #define CPSR_N (1 << 31)
 253 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 254
 255 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 256 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 257 /* Bits writable in user mode.  */
 258 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 259 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 260 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 261
 262 /* Return the current CPSR value.  */
 263 uint32_t cpsr_read(CPUARMState *env);
 264 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 265 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 266
 267 /* Return the current xPSR value.  */
 268 static inline uint32_t xpsr_read(CPUARMState *env)
 269 {
 270     int ZF;
 271     ZF = (env->ZF == 0);
 272     return (env->NF & 0x80000000) | (ZF << 30)
 273         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 274         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 275         | ((env->condexec_bits & 0xfc) << 8)
 276         | env->v7m.exception;
 277 }
 278
 279 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 280 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 281 {
 282     if (mask & CPSR_NZCV) {
 283         env->ZF = (~val) & CPSR_Z;
 284         env->NF = val;
 285         env->CF = (val >> 29) & 1;
 286         env->VF = (val << 3) & 0x80000000;
 287     }
 288     if (mask & CPSR_Q)
 289         env->QF = ((val & CPSR_Q) != 0);
 290     if (mask & (1 << 24))
 291         env->thumb = ((val & (1 << 24)) != 0);
 292     if (mask & CPSR_IT_0_1) {
 293         env->condexec_bits &= ~3;
 294         env->condexec_bits |= (val >> 25) & 3;
 295     }
 296     if (mask & CPSR_IT_2_7) {
 297         env->condexec_bits &= 3;
 298         env->condexec_bits |= (val >> 8) & 0xfc;
 299     }
 300     if (mask & 0x1ff) {
 301         env->v7m.exception = val & 0x1ff;
 302     }
 303 }
 304
 305 enum arm_cpu_mode {
 306   ARM_CPU_MODE_USR = 0x10,
 307   ARM_CPU_MODE_FIQ = 0x11,
 308   ARM_CPU_MODE_IRQ = 0x12,
 309   ARM_CPU_MODE_SVC = 0x13,
 310   ARM_CPU_MODE_ABT = 0x17,
 311   ARM_CPU_MODE_UND = 0x1b,
 312   ARM_CPU_MODE_SYS = 0x1f
 313 };
 314
 315 /* VFP system registers.  */
 316 #define ARM_VFP_FPSID   0
 317 #define ARM_VFP_FPSCR   1
 318 #define ARM_VFP_MVFR1   6
 319 #define ARM_VFP_MVFR0   7
 320 #define ARM_VFP_FPEXC   8
 321 #define ARM_VFP_FPINST  9
 322 #define ARM_VFP_FPINST2 10
 323
 324 /* iwMMXt coprocessor control registers.  */
 325 #define ARM_IWMMXT_wCID         0
 326 #define ARM_IWMMXT_wCon         1
 327 #define ARM_IWMMXT_wCSSF        2
 328 #define ARM_IWMMXT_wCASF        3
 329 #define ARM_IWMMXT_wCGR0        8
 330 #define ARM_IWMMXT_wCGR1        9
 331 #define ARM_IWMMXT_wCGR2        10
 332 #define ARM_IWMMXT_wCGR3        11
 333
 334 enum arm_features {
 335     ARM_FEATURE_VFP,
 336     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 337     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 338     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 339     ARM_FEATURE_V6,
 340     ARM_FEATURE_V6K,
 341     ARM_FEATURE_V7,
 342     ARM_FEATURE_THUMB2,
 343     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 344     ARM_FEATURE_VFP3,
 345     ARM_FEATURE_VFP_FP16,
 346     ARM_FEATURE_NEON,
 347     ARM_FEATURE_DIV,
 348     ARM_FEATURE_M, /* Microcontroller profile.  */
 349     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 350     ARM_FEATURE_THUMB2EE
 351 };
 352
 353 static inline int arm_feature(CPUARMState *env, int feature)
 354 {
 355     return (env->features & (1u << feature)) != 0;
 356 }
 357
 358 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 359
 360 /* Interface between CPU and Interrupt controller.  */
 361 void armv7m_nvic_set_pending(void *opaque, int irq);
 362 int armv7m_nvic_acknowledge_irq(void *opaque);
 363 void armv7m_nvic_complete_irq(void *opaque, int irq);
 364
 365 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 366                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 367                        void *opaque);
 368
 369 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 370    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 371    conventional cores (ie. Application or Realtime profile).  */
 372
 373 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 374 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 375
 376 #define ARM_CPUID_ARM1026     0x4106a262
 377 #define ARM_CPUID_ARM926      0x41069265
 378 #define ARM_CPUID_ARM946      0x41059461
 379 #define ARM_CPUID_TI915T      0x54029152
 380 #define ARM_CPUID_TI925T      0x54029252
 381 #define ARM_CPUID_PXA250      0x69052100
 382 #define ARM_CPUID_PXA255      0x69052d00
 383 #define ARM_CPUID_PXA260      0x69052903
 384 #define ARM_CPUID_PXA261      0x69052d05
 385 #define ARM_CPUID_PXA262      0x69052d06
 386 #define ARM_CPUID_PXA270      0x69054110
 387 #define ARM_CPUID_PXA270_A0   0x69054110
 388 #define ARM_CPUID_PXA270_A1   0x69054111
 389 #define ARM_CPUID_PXA270_B0   0x69054112
 390 #define ARM_CPUID_PXA270_B1   0x69054113
 391 #define ARM_CPUID_PXA270_C0   0x69054114
 392 #define ARM_CPUID_PXA270_C5   0x69054117
 393 #define ARM_CPUID_ARM1136     0x4117b363
 394 #define ARM_CPUID_ARM1136_R2  0x4107b362
 395 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 396 #define ARM_CPUID_CORTEXA8    0x410fc080
 397 #define ARM_CPUID_CORTEXA9    0x410fc090
 398 #define ARM_CPUID_CORTEXM3    0x410fc231
 399 #define ARM_CPUID_ANY         0xffffffff
 400
 401 #if defined(CONFIG_USER_ONLY)
 402 #define TARGET_PAGE_BITS 12
 403 #else
 404 /* The ARM MMU allows 1k pages.  */
 405 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 406    architecture revisions.  Maybe a configure option to disable them.  */
 407 #define TARGET_PAGE_BITS 10
 408 #endif
 409
 410 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 411 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 412
 413 #define cpu_init cpu_arm_init
 414 #define cpu_exec cpu_arm_exec
 415 #define cpu_gen_code cpu_arm_gen_code
 416 #define cpu_signal_handler cpu_arm_signal_handler
 417 #define cpu_list arm_cpu_list
 418
 419 #define CPU_SAVE_VERSION 2
 420
 421 /* MMU modes definitions */
 422 #define MMU_MODE0_SUFFIX _kernel
 423 #define MMU_MODE1_SUFFIX _user
 424 #define MMU_USER_IDX 1
 425 static inline int cpu_mmu_index (CPUState *env)
 426 {
 427     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 428 }
 429
 430 #if defined(CONFIG_USER_ONLY)
 431 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 432 {
 433     if (newsp)
 434         env->regs[13] = newsp;
 435     env->regs[0] = 0;
 436 }
 437 #endif
 438
 439 #include "cpu-all.h"
 440
 441 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 442                                         target_ulong *cs_base, int *flags)
 443 {
 444     *pc = env->regs[15];
 445     *cs_base = 0;
 446     *flags = env->thumb | (env->vfp.vec_len << 1)
 447             | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8);
 448     if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
 449         *flags |= (1 << 6);
 450     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
 451         *flags |= (1 << 7);
 452 }
 453
 454 #endif