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translate-all: Mark map_exec() with the 'unused' attribute
[qemu/ar7.git] / hw / usb / hcd-ehci.c
blob1cc0fc116d3ab82765d925e9f7f6419fc971d1da
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
6 *
7 * Red Hat Authors:
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
10 *
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
14 *
15 *
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
20 *
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
28 */
29
30 #include "hw/usb/ehci-regs.h"
31 #include "hw/usb/hcd-ehci.h"
32 #include "trace.h"
33
34 #define FRAME_TIMER_FREQ 1000
35 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
36 #define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8)
37
38 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
39 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
40 #define MAX_QH 100 // Max allowable queue heads in a chain
41 #define MIN_UFR_PER_TICK 24 /* Min frames to process when catching up */
42 #define PERIODIC_ACTIVE 512 /* Micro-frames */
43
44 /* Internal periodic / asynchronous schedule state machine states
45 */
46 typedef enum {
47 EST_INACTIVE = 1000,
48 EST_ACTIVE,
49 EST_EXECUTING,
50 EST_SLEEPING,
51 /* The following states are internal to the state machine function
52 */
53 EST_WAITLISTHEAD,
54 EST_FETCHENTRY,
55 EST_FETCHQH,
56 EST_FETCHITD,
57 EST_FETCHSITD,
58 EST_ADVANCEQUEUE,
59 EST_FETCHQTD,
60 EST_EXECUTE,
61 EST_WRITEBACK,
62 EST_HORIZONTALQH
63 } EHCI_STATES;
64
65 /* macros for accessing fields within next link pointer entry */
66 #define NLPTR_GET(x) ((x) & 0xffffffe0)
67 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
68 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
69
70 /* link pointer types */
71 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
72 #define NLPTR_TYPE_QH 1 // queue head
73 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
74 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
75
76 #define SET_LAST_RUN_CLOCK(s) \
77 (s)->last_run_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
78
79 /* nifty macros from Arnon's EHCI version */
80 #define get_field(data, field) \
81 (((data) & field##_MASK) >> field##_SH)
82
83 #define set_field(data, newval, field) do { \
84 uint32_t val = *data; \
85 val &= ~ field##_MASK; \
86 val |= ((newval) << field##_SH) & field##_MASK; \
87 *data = val; \
88 } while(0)
89
90 static const char *ehci_state_names[] = {
91 [EST_INACTIVE] = "INACTIVE",
92 [EST_ACTIVE] = "ACTIVE",
93 [EST_EXECUTING] = "EXECUTING",
94 [EST_SLEEPING] = "SLEEPING",
95 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
96 [EST_FETCHENTRY] = "FETCH ENTRY",
97 [EST_FETCHQH] = "FETCH QH",
98 [EST_FETCHITD] = "FETCH ITD",
99 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
100 [EST_FETCHQTD] = "FETCH QTD",
101 [EST_EXECUTE] = "EXECUTE",
102 [EST_WRITEBACK] = "WRITEBACK",
103 [EST_HORIZONTALQH] = "HORIZONTALQH",
104 };
105
106 static const char *ehci_mmio_names[] = {
107 [USBCMD] = "USBCMD",
108 [USBSTS] = "USBSTS",
109 [USBINTR] = "USBINTR",
110 [FRINDEX] = "FRINDEX",
111 [PERIODICLISTBASE] = "P-LIST BASE",
112 [ASYNCLISTADDR] = "A-LIST ADDR",
113 [CONFIGFLAG] = "CONFIGFLAG",
114 };
115
116 static int ehci_state_executing(EHCIQueue *q);
117 static int ehci_state_writeback(EHCIQueue *q);
118 static int ehci_state_advqueue(EHCIQueue *q);
119 static int ehci_fill_queue(EHCIPacket *p);
120 static void ehci_free_packet(EHCIPacket *p);
121
122 static const char *nr2str(const char **n, size_t len, uint32_t nr)
123 {
124 if (nr < len && n[nr] != NULL) {
125 return n[nr];
126 } else {
127 return "unknown";
128 }
129 }
130
131 static const char *state2str(uint32_t state)
132 {
133 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
134 }
135
136 static const char *addr2str(hwaddr addr)
137 {
138 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
139 }
140
141 static void ehci_trace_usbsts(uint32_t mask, int state)
142 {
143 /* interrupts */
144 if (mask & USBSTS_INT) {
145 trace_usb_ehci_usbsts("INT", state);
146 }
147 if (mask & USBSTS_ERRINT) {
148 trace_usb_ehci_usbsts("ERRINT", state);
149 }
150 if (mask & USBSTS_PCD) {
151 trace_usb_ehci_usbsts("PCD", state);
152 }
153 if (mask & USBSTS_FLR) {
154 trace_usb_ehci_usbsts("FLR", state);
155 }
156 if (mask & USBSTS_HSE) {
157 trace_usb_ehci_usbsts("HSE", state);
158 }
159 if (mask & USBSTS_IAA) {
160 trace_usb_ehci_usbsts("IAA", state);
161 }
162
163 /* status */
164 if (mask & USBSTS_HALT) {
165 trace_usb_ehci_usbsts("HALT", state);
166 }
167 if (mask & USBSTS_REC) {
168 trace_usb_ehci_usbsts("REC", state);
169 }
170 if (mask & USBSTS_PSS) {
171 trace_usb_ehci_usbsts("PSS", state);
172 }
173 if (mask & USBSTS_ASS) {
174 trace_usb_ehci_usbsts("ASS", state);
175 }
176 }
177
178 static inline void ehci_set_usbsts(EHCIState *s, int mask)
179 {
180 if ((s->usbsts & mask) == mask) {
181 return;
182 }
183 ehci_trace_usbsts(mask, 1);
184 s->usbsts |= mask;
185 }
186
187 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
188 {
189 if ((s->usbsts & mask) == 0) {
190 return;
191 }
192 ehci_trace_usbsts(mask, 0);
193 s->usbsts &= ~mask;
194 }
195
196 /* update irq line */
197 static inline void ehci_update_irq(EHCIState *s)
198 {
199 int level = 0;
200
201 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
202 level = 1;
203 }
204
205 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
206 qemu_set_irq(s->irq, level);
207 }
208
209 /* flag interrupt condition */
210 static inline void ehci_raise_irq(EHCIState *s, int intr)
211 {
212 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
213 s->usbsts |= intr;
214 ehci_update_irq(s);
215 } else {
216 s->usbsts_pending |= intr;
217 }
218 }
219
220 /*
221 * Commit pending interrupts (added via ehci_raise_irq),
222 * at the rate allowed by "Interrupt Threshold Control".
223 */
224 static inline void ehci_commit_irq(EHCIState *s)
225 {
226 uint32_t itc;
227
228 if (!s->usbsts_pending) {
229 return;
230 }
231 if (s->usbsts_frindex > s->frindex) {
232 return;
233 }
234
235 itc = (s->usbcmd >> 16) & 0xff;
236 s->usbsts |= s->usbsts_pending;
237 s->usbsts_pending = 0;
238 s->usbsts_frindex = s->frindex + itc;
239 ehci_update_irq(s);
240 }
241
242 static void ehci_update_halt(EHCIState *s)
243 {
244 if (s->usbcmd & USBCMD_RUNSTOP) {
245 ehci_clear_usbsts(s, USBSTS_HALT);
246 } else {
247 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
248 ehci_set_usbsts(s, USBSTS_HALT);
249 }
250 }
251 }
252
253 static void ehci_set_state(EHCIState *s, int async, int state)
254 {
255 if (async) {
256 trace_usb_ehci_state("async", state2str(state));
257 s->astate = state;
258 if (s->astate == EST_INACTIVE) {
259 ehci_clear_usbsts(s, USBSTS_ASS);
260 ehci_update_halt(s);
261 } else {
262 ehci_set_usbsts(s, USBSTS_ASS);
263 }
264 } else {
265 trace_usb_ehci_state("periodic", state2str(state));
266 s->pstate = state;
267 if (s->pstate == EST_INACTIVE) {
268 ehci_clear_usbsts(s, USBSTS_PSS);
269 ehci_update_halt(s);
270 } else {
271 ehci_set_usbsts(s, USBSTS_PSS);
272 }
273 }
274 }
275
276 static int ehci_get_state(EHCIState *s, int async)
277 {
278 return async ? s->astate : s->pstate;
279 }
280
281 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
282 {
283 if (async) {
284 s->a_fetch_addr = addr;
285 } else {
286 s->p_fetch_addr = addr;
287 }
288 }
289
290 static int ehci_get_fetch_addr(EHCIState *s, int async)
291 {
292 return async ? s->a_fetch_addr : s->p_fetch_addr;
293 }
294
295 static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
296 {
297 /* need three here due to argument count limits */
298 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
299 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
300 trace_usb_ehci_qh_fields(addr,
301 get_field(qh->epchar, QH_EPCHAR_RL),
302 get_field(qh->epchar, QH_EPCHAR_MPLEN),
303 get_field(qh->epchar, QH_EPCHAR_EPS),
304 get_field(qh->epchar, QH_EPCHAR_EP),
305 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
306 trace_usb_ehci_qh_bits(addr,
307 (bool)(qh->epchar & QH_EPCHAR_C),
308 (bool)(qh->epchar & QH_EPCHAR_H),
309 (bool)(qh->epchar & QH_EPCHAR_DTC),
310 (bool)(qh->epchar & QH_EPCHAR_I));
311 }
312
313 static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
314 {
315 /* need three here due to argument count limits */
316 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
317 trace_usb_ehci_qtd_fields(addr,
318 get_field(qtd->token, QTD_TOKEN_TBYTES),
319 get_field(qtd->token, QTD_TOKEN_CPAGE),
320 get_field(qtd->token, QTD_TOKEN_CERR),
321 get_field(qtd->token, QTD_TOKEN_PID));
322 trace_usb_ehci_qtd_bits(addr,
323 (bool)(qtd->token & QTD_TOKEN_IOC),
324 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
325 (bool)(qtd->token & QTD_TOKEN_HALT),
326 (bool)(qtd->token & QTD_TOKEN_BABBLE),
327 (bool)(qtd->token & QTD_TOKEN_XACTERR));
328 }
329
330 static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
331 {
332 trace_usb_ehci_itd(addr, itd->next,
333 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
334 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
335 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
336 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
337 }
338
339 static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
340 EHCIsitd *sitd)
341 {
342 trace_usb_ehci_sitd(addr, sitd->next,
343 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
344 }
345
346 static void ehci_trace_guest_bug(EHCIState *s, const char *message)
347 {
348 trace_usb_ehci_guest_bug(message);
349 fprintf(stderr, "ehci warning: %s\n", message);
350 }
351
352 static inline bool ehci_enabled(EHCIState *s)
353 {
354 return s->usbcmd & USBCMD_RUNSTOP;
355 }
356
357 static inline bool ehci_async_enabled(EHCIState *s)
358 {
359 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
360 }
361
362 static inline bool ehci_periodic_enabled(EHCIState *s)
363 {
364 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
365 }
366
367 /* Get an array of dwords from main memory */
368 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
369 uint32_t *buf, int num)
370 {
371 int i;
372
373 if (!ehci->as) {
374 ehci_raise_irq(ehci, USBSTS_HSE);
375 ehci->usbcmd &= ~USBCMD_RUNSTOP;
376 trace_usb_ehci_dma_error();
377 return -1;
378 }
379
380 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
381 dma_memory_read(ehci->as, addr, buf, sizeof(*buf));
382 *buf = le32_to_cpu(*buf);
383 }
384
385 return num;
386 }
387
388 /* Put an array of dwords in to main memory */
389 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
390 uint32_t *buf, int num)
391 {
392 int i;
393
394 if (!ehci->as) {
395 ehci_raise_irq(ehci, USBSTS_HSE);
396 ehci->usbcmd &= ~USBCMD_RUNSTOP;
397 trace_usb_ehci_dma_error();
398 return -1;
399 }
400
401 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
402 uint32_t tmp = cpu_to_le32(*buf);
403 dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp));
404 }
405
406 return num;
407 }
408
409 static int ehci_get_pid(EHCIqtd *qtd)
410 {
411 switch (get_field(qtd->token, QTD_TOKEN_PID)) {
412 case 0:
413 return USB_TOKEN_OUT;
414 case 1:
415 return USB_TOKEN_IN;
416 case 2:
417 return USB_TOKEN_SETUP;
418 default:
419 fprintf(stderr, "bad token\n");
420 return 0;
421 }
422 }
423
424 static bool ehci_verify_qh(EHCIQueue *q, EHCIqh *qh)
425 {
426 uint32_t devaddr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
427 uint32_t endp = get_field(qh->epchar, QH_EPCHAR_EP);
428 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
429 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) ||
430 (qh->current_qtd != q->qh.current_qtd) ||
431 (q->async && qh->next_qtd != q->qh.next_qtd) ||
432 (memcmp(&qh->altnext_qtd, &q->qh.altnext_qtd,
433 7 * sizeof(uint32_t)) != 0) ||
434 (q->dev != NULL && q->dev->addr != devaddr)) {
435 return false;
436 } else {
437 return true;
438 }
439 }
440
441 static bool ehci_verify_qtd(EHCIPacket *p, EHCIqtd *qtd)
442 {
443 if (p->qtdaddr != p->queue->qtdaddr ||
444 (p->queue->async && !NLPTR_TBIT(p->qtd.next) &&
445 (p->qtd.next != qtd->next)) ||
446 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd->altnext)) ||
447 p->qtd.token != qtd->token ||
448 p->qtd.bufptr[0] != qtd->bufptr[0]) {
449 return false;
450 } else {
451 return true;
452 }
453 }
454
455 static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd)
456 {
457 int ep = get_field(q->qh.epchar, QH_EPCHAR_EP);
458 int pid = ehci_get_pid(qtd);
459
460 /* Note the pid changing is normal for ep 0 (the control ep) */
461 if (q->last_pid && ep != 0 && pid != q->last_pid) {
462 return false;
463 } else {
464 return true;
465 }
466 }
467
468 /* Finish executing and writeback a packet outside of the regular
469 fetchqh -> fetchqtd -> execute -> writeback cycle */
470 static void ehci_writeback_async_complete_packet(EHCIPacket *p)
471 {
472 EHCIQueue *q = p->queue;
473 EHCIqtd qtd;
474 EHCIqh qh;
475 int state;
476
477 /* Verify the qh + qtd, like we do when going through fetchqh & fetchqtd */
478 get_dwords(q->ehci, NLPTR_GET(q->qhaddr),
479 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
480 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr),
481 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
482 if (!ehci_verify_qh(q, &qh) || !ehci_verify_qtd(p, &qtd)) {
483 p->async = EHCI_ASYNC_INITIALIZED;
484 ehci_free_packet(p);
485 return;
486 }
487
488 state = ehci_get_state(q->ehci, q->async);
489 ehci_state_executing(q);
490 ehci_state_writeback(q); /* Frees the packet! */
491 if (!(q->qh.token & QTD_TOKEN_HALT)) {
492 ehci_state_advqueue(q);
493 }
494 ehci_set_state(q->ehci, q->async, state);
495 }
496
497 /* packet management */
498
499 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
500 {
501 EHCIPacket *p;
502
503 p = g_new0(EHCIPacket, 1);
504 p->queue = q;
505 usb_packet_init(&p->packet);
506 QTAILQ_INSERT_TAIL(&q->packets, p, next);
507 trace_usb_ehci_packet_action(p->queue, p, "alloc");
508 return p;
509 }
510
511 static void ehci_free_packet(EHCIPacket *p)
512 {
513 if (p->async == EHCI_ASYNC_FINISHED &&
514 !(p->queue->qh.token & QTD_TOKEN_HALT)) {
515 ehci_writeback_async_complete_packet(p);
516 return;
517 }
518 trace_usb_ehci_packet_action(p->queue, p, "free");
519 if (p->async == EHCI_ASYNC_INFLIGHT) {
520 usb_cancel_packet(&p->packet);
521 }
522 if (p->async == EHCI_ASYNC_FINISHED &&
523 p->packet.status == USB_RET_SUCCESS) {
524 fprintf(stderr,
525 "EHCI: Dropping completed packet from halted %s ep %02X\n",
526 (p->pid == USB_TOKEN_IN) ? "in" : "out",
527 get_field(p->queue->qh.epchar, QH_EPCHAR_EP));
528 }
529 if (p->async != EHCI_ASYNC_NONE) {
530 usb_packet_unmap(&p->packet, &p->sgl);
531 qemu_sglist_destroy(&p->sgl);
532 }
533 QTAILQ_REMOVE(&p->queue->packets, p, next);
534 usb_packet_cleanup(&p->packet);
535 g_free(p);
536 }
537
538 /* queue management */
539
540 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
541 {
542 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
543 EHCIQueue *q;
544
545 q = g_malloc0(sizeof(*q));
546 q->ehci = ehci;
547 q->qhaddr = addr;
548 q->async = async;
549 QTAILQ_INIT(&q->packets);
550 QTAILQ_INSERT_HEAD(head, q, next);
551 trace_usb_ehci_queue_action(q, "alloc");
552 return q;
553 }
554
555 static void ehci_queue_stopped(EHCIQueue *q)
556 {
557 int endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
558
559 if (!q->last_pid || !q->dev) {
560 return;
561 }
562
563 usb_device_ep_stopped(q->dev, usb_ep_get(q->dev, q->last_pid, endp));
564 }
565
566 static int ehci_cancel_queue(EHCIQueue *q)
567 {
568 EHCIPacket *p;
569 int packets = 0;
570
571 p = QTAILQ_FIRST(&q->packets);
572 if (p == NULL) {
573 goto leave;
574 }
575
576 trace_usb_ehci_queue_action(q, "cancel");
577 do {
578 ehci_free_packet(p);
579 packets++;
580 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL);
581
582 leave:
583 ehci_queue_stopped(q);
584 return packets;
585 }
586
587 static int ehci_reset_queue(EHCIQueue *q)
588 {
589 int packets;
590
591 trace_usb_ehci_queue_action(q, "reset");
592 packets = ehci_cancel_queue(q);
593 q->dev = NULL;
594 q->qtdaddr = 0;
595 q->last_pid = 0;
596 return packets;
597 }
598
599 static void ehci_free_queue(EHCIQueue *q, const char *warn)
600 {
601 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
602 int cancelled;
603
604 trace_usb_ehci_queue_action(q, "free");
605 cancelled = ehci_cancel_queue(q);
606 if (warn && cancelled > 0) {
607 ehci_trace_guest_bug(q->ehci, warn);
608 }
609 QTAILQ_REMOVE(head, q, next);
610 g_free(q);
611 }
612
613 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
614 int async)
615 {
616 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
617 EHCIQueue *q;
618
619 QTAILQ_FOREACH(q, head, next) {
620 if (addr == q->qhaddr) {
621 return q;
622 }
623 }
624 return NULL;
625 }
626
627 static void ehci_queues_rip_unused(EHCIState *ehci, int async)
628 {
629 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
630 const char *warn = async ? "guest unlinked busy QH" : NULL;
631 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
632 EHCIQueue *q, *tmp;
633
634 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
635 if (q->seen) {
636 q->seen = 0;
637 q->ts = ehci->last_run_ns;
638 continue;
639 }
640 if (ehci->last_run_ns < q->ts + maxage) {
641 continue;
642 }
643 ehci_free_queue(q, warn);
644 }
645 }
646
647 static void ehci_queues_rip_unseen(EHCIState *ehci, int async)
648 {
649 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
650 EHCIQueue *q, *tmp;
651
652 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
653 if (!q->seen) {
654 ehci_free_queue(q, NULL);
655 }
656 }
657 }
658
659 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
660 {
661 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
662 EHCIQueue *q, *tmp;
663
664 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
665 if (q->dev != dev) {
666 continue;
667 }
668 ehci_free_queue(q, NULL);
669 }
670 }
671
672 static void ehci_queues_rip_all(EHCIState *ehci, int async)
673 {
674 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
675 const char *warn = async ? "guest stopped busy async schedule" : NULL;
676 EHCIQueue *q, *tmp;
677
678 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
679 ehci_free_queue(q, warn);
680 }
681 }
682
683 /* Attach or detach a device on root hub */
684
685 static void ehci_attach(USBPort *port)
686 {
687 EHCIState *s = port->opaque;
688 uint32_t *portsc = &s->portsc[port->index];
689 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
690
691 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
692
693 if (*portsc & PORTSC_POWNER) {
694 USBPort *companion = s->companion_ports[port->index];
695 companion->dev = port->dev;
696 companion->ops->attach(companion);
697 return;
698 }
699
700 *portsc |= PORTSC_CONNECT;
701 *portsc |= PORTSC_CSC;
702
703 ehci_raise_irq(s, USBSTS_PCD);
704 }
705
706 static void ehci_detach(USBPort *port)
707 {
708 EHCIState *s = port->opaque;
709 uint32_t *portsc = &s->portsc[port->index];
710 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
711
712 trace_usb_ehci_port_detach(port->index, owner);
713
714 if (*portsc & PORTSC_POWNER) {
715 USBPort *companion = s->companion_ports[port->index];
716 companion->ops->detach(companion);
717 companion->dev = NULL;
718 /*
719 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
720 * the port ownership is returned immediately to the EHCI controller."
721 */
722 *portsc &= ~PORTSC_POWNER;
723 return;
724 }
725
726 ehci_queues_rip_device(s, port->dev, 0);
727 ehci_queues_rip_device(s, port->dev, 1);
728
729 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
730 *portsc |= PORTSC_CSC;
731
732 ehci_raise_irq(s, USBSTS_PCD);
733 }
734
735 static void ehci_child_detach(USBPort *port, USBDevice *child)
736 {
737 EHCIState *s = port->opaque;
738 uint32_t portsc = s->portsc[port->index];
739
740 if (portsc & PORTSC_POWNER) {
741 USBPort *companion = s->companion_ports[port->index];
742 companion->ops->child_detach(companion, child);
743 return;
744 }
745
746 ehci_queues_rip_device(s, child, 0);
747 ehci_queues_rip_device(s, child, 1);
748 }
749
750 static void ehci_wakeup(USBPort *port)
751 {
752 EHCIState *s = port->opaque;
753 uint32_t *portsc = &s->portsc[port->index];
754
755 if (*portsc & PORTSC_POWNER) {
756 USBPort *companion = s->companion_ports[port->index];
757 if (companion->ops->wakeup) {
758 companion->ops->wakeup(companion);
759 }
760 return;
761 }
762
763 if (*portsc & PORTSC_SUSPEND) {
764 trace_usb_ehci_port_wakeup(port->index);
765 *portsc |= PORTSC_FPRES;
766 ehci_raise_irq(s, USBSTS_PCD);
767 }
768
769 qemu_bh_schedule(s->async_bh);
770 }
771
772 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
773 uint32_t portcount, uint32_t firstport)
774 {
775 EHCIState *s = container_of(bus, EHCIState, bus);
776 uint32_t i;
777
778 if (firstport + portcount > NB_PORTS) {
779 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
780 "firstport on masterbus");
781 error_printf_unless_qmp(
782 "firstport value of %u makes companion take ports %u - %u, which "
783 "is outside of the valid range of 0 - %u\n", firstport, firstport,
784 firstport + portcount - 1, NB_PORTS - 1);
785 return -1;
786 }
787
788 for (i = 0; i < portcount; i++) {
789 if (s->companion_ports[firstport + i]) {
790 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
791 "an USB masterbus");
792 error_printf_unless_qmp(
793 "port %u on masterbus %s already has a companion assigned\n",
794 firstport + i, bus->qbus.name);
795 return -1;
796 }
797 }
798
799 for (i = 0; i < portcount; i++) {
800 s->companion_ports[firstport + i] = ports[i];
801 s->ports[firstport + i].speedmask |=
802 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
803 /* Ensure devs attached before the initial reset go to the companion */
804 s->portsc[firstport + i] = PORTSC_POWNER;
805 }
806
807 s->companion_count++;
808 s->caps[0x05] = (s->companion_count << 4) | portcount;
809
810 return 0;
811 }
812
813 static void ehci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
814 unsigned int stream)
815 {
816 EHCIState *s = container_of(bus, EHCIState, bus);
817 uint32_t portsc = s->portsc[ep->dev->port->index];
818
819 if (portsc & PORTSC_POWNER) {
820 return;
821 }
822
823 s->periodic_sched_active = PERIODIC_ACTIVE;
824 qemu_bh_schedule(s->async_bh);
825 }
826
827 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
828 {
829 USBDevice *dev;
830 USBPort *port;
831 int i;
832
833 for (i = 0; i < NB_PORTS; i++) {
834 port = &ehci->ports[i];
835 if (!(ehci->portsc[i] & PORTSC_PED)) {
836 DPRINTF("Port %d not enabled\n", i);
837 continue;
838 }
839 dev = usb_find_device(port, addr);
840 if (dev != NULL) {
841 return dev;
842 }
843 }
844 return NULL;
845 }
846
847 /* 4.1 host controller initialization */
848 static void ehci_reset(void *opaque)
849 {
850 EHCIState *s = opaque;
851 int i;
852 USBDevice *devs[NB_PORTS];
853
854 trace_usb_ehci_reset();
855
856 /*
857 * Do the detach before touching portsc, so that it correctly gets send to
858 * us or to our companion based on PORTSC_POWNER before the reset.
859 */
860 for(i = 0; i < NB_PORTS; i++) {
861 devs[i] = s->ports[i].dev;
862 if (devs[i] && devs[i]->attached) {
863 usb_detach(&s->ports[i]);
864 }
865 }
866
867 memset(&s->opreg, 0x00, sizeof(s->opreg));
868 memset(&s->portsc, 0x00, sizeof(s->portsc));
869
870 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
871 s->usbsts = USBSTS_HALT;
872 s->usbsts_pending = 0;
873 s->usbsts_frindex = 0;
874
875 s->astate = EST_INACTIVE;
876 s->pstate = EST_INACTIVE;
877
878 for(i = 0; i < NB_PORTS; i++) {
879 if (s->companion_ports[i]) {
880 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
881 } else {
882 s->portsc[i] = PORTSC_PPOWER;
883 }
884 if (devs[i] && devs[i]->attached) {
885 usb_attach(&s->ports[i]);
886 usb_device_reset(devs[i]);
887 }
888 }
889 ehci_queues_rip_all(s, 0);
890 ehci_queues_rip_all(s, 1);
891 timer_del(s->frame_timer);
892 qemu_bh_cancel(s->async_bh);
893 }
894
895 static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
896 unsigned size)
897 {
898 EHCIState *s = ptr;
899 return s->caps[addr];
900 }
901
902 static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
903 unsigned size)
904 {
905 EHCIState *s = ptr;
906 uint32_t val;
907
908 switch (addr) {
909 case FRINDEX:
910 /* Round down to mult of 8, else it can go backwards on migration */
911 val = s->frindex & ~7;
912 break;
913 default:
914 val = s->opreg[addr >> 2];
915 }
916
917 trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val);
918 return val;
919 }
920
921 static uint64_t ehci_port_read(void *ptr, hwaddr addr,
922 unsigned size)
923 {
924 EHCIState *s = ptr;
925 uint32_t val;
926
927 val = s->portsc[addr >> 2];
928 trace_usb_ehci_portsc_read(addr + s->portscbase, addr >> 2, val);
929 return val;
930 }
931
932 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
933 {
934 USBDevice *dev = s->ports[port].dev;
935 uint32_t *portsc = &s->portsc[port];
936 uint32_t orig;
937
938 if (s->companion_ports[port] == NULL)
939 return;
940
941 owner = owner & PORTSC_POWNER;
942 orig = *portsc & PORTSC_POWNER;
943
944 if (!(owner ^ orig)) {
945 return;
946 }
947
948 if (dev && dev->attached) {
949 usb_detach(&s->ports[port]);
950 }
951
952 *portsc &= ~PORTSC_POWNER;
953 *portsc |= owner;
954
955 if (dev && dev->attached) {
956 usb_attach(&s->ports[port]);
957 }
958 }
959
960 static void ehci_port_write(void *ptr, hwaddr addr,
961 uint64_t val, unsigned size)
962 {
963 EHCIState *s = ptr;
964 int port = addr >> 2;
965 uint32_t *portsc = &s->portsc[port];
966 uint32_t old = *portsc;
967 USBDevice *dev = s->ports[port].dev;
968
969 trace_usb_ehci_portsc_write(addr + s->portscbase, addr >> 2, val);
970
971 /* Clear rwc bits */
972 *portsc &= ~(val & PORTSC_RWC_MASK);
973 /* The guest may clear, but not set the PED bit */
974 *portsc &= val | ~PORTSC_PED;
975 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
976 handle_port_owner_write(s, port, val);
977 /* And finally apply RO_MASK */
978 val &= PORTSC_RO_MASK;
979
980 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
981 trace_usb_ehci_port_reset(port, 1);
982 }
983
984 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
985 trace_usb_ehci_port_reset(port, 0);
986 if (dev && dev->attached) {
987 usb_port_reset(&s->ports[port]);
988 *portsc &= ~PORTSC_CSC;
989 }
990
991 /*
992 * Table 2.16 Set the enable bit(and enable bit change) to indicate
993 * to SW that this port has a high speed device attached
994 */
995 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
996 val |= PORTSC_PED;
997 }
998 }
999
1000 if ((val & PORTSC_SUSPEND) && !(*portsc & PORTSC_SUSPEND)) {
1001 trace_usb_ehci_port_suspend(port);
1002 }
1003 if (!(val & PORTSC_FPRES) && (*portsc & PORTSC_FPRES)) {
1004 trace_usb_ehci_port_resume(port);
1005 val &= ~PORTSC_SUSPEND;
1006 }
1007
1008 *portsc &= ~PORTSC_RO_MASK;
1009 *portsc |= val;
1010 trace_usb_ehci_portsc_change(addr + s->portscbase, addr >> 2, *portsc, old);
1011 }
1012
1013 static void ehci_opreg_write(void *ptr, hwaddr addr,
1014 uint64_t val, unsigned size)
1015 {
1016 EHCIState *s = ptr;
1017 uint32_t *mmio = s->opreg + (addr >> 2);
1018 uint32_t old = *mmio;
1019 int i;
1020
1021 trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val);
1022
1023 switch (addr) {
1024 case USBCMD:
1025 if (val & USBCMD_HCRESET) {
1026 ehci_reset(s);
1027 val = s->usbcmd;
1028 break;
1029 }
1030
1031 /* not supporting dynamic frame list size at the moment */
1032 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1033 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1034 (int)val & USBCMD_FLS);
1035 val &= ~USBCMD_FLS;
1036 }
1037
1038 if (val & USBCMD_IAAD) {
1039 /*
1040 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1041 * trigger and re-use a qh without us seeing the unlink.
1042 */
1043 s->async_stepdown = 0;
1044 qemu_bh_schedule(s->async_bh);
1045 trace_usb_ehci_doorbell_ring();
1046 }
1047
1048 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1049 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1050 if (s->pstate == EST_INACTIVE) {
1051 SET_LAST_RUN_CLOCK(s);
1052 }
1053 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
1054 ehci_update_halt(s);
1055 s->async_stepdown = 0;
1056 qemu_bh_schedule(s->async_bh);
1057 }
1058 break;
1059
1060 case USBSTS:
1061 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1062 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1063 val = s->usbsts;
1064 ehci_update_irq(s);
1065 break;
1066
1067 case USBINTR:
1068 val &= USBINTR_MASK;
1069 if (ehci_enabled(s) && (USBSTS_FLR & val)) {
1070 qemu_bh_schedule(s->async_bh);
1071 }
1072 break;
1073
1074 case FRINDEX:
1075 val &= 0x00003fff; /* frindex is 14bits */
1076 s->usbsts_frindex = val;
1077 break;
1078
1079 case CONFIGFLAG:
1080 val &= 0x1;
1081 if (val) {
1082 for(i = 0; i < NB_PORTS; i++)
1083 handle_port_owner_write(s, i, 0);
1084 }
1085 break;
1086
1087 case PERIODICLISTBASE:
1088 if (ehci_periodic_enabled(s)) {
1089 fprintf(stderr,
1090 "ehci: PERIODIC list base register set while periodic schedule\n"
1091 " is enabled and HC is enabled\n");
1092 }
1093 break;
1094
1095 case ASYNCLISTADDR:
1096 if (ehci_async_enabled(s)) {
1097 fprintf(stderr,
1098 "ehci: ASYNC list address register set while async schedule\n"
1099 " is enabled and HC is enabled\n");
1100 }
1101 break;
1102 }
1103
1104 *mmio = val;
1105 trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr),
1106 *mmio, old);
1107 }
1108
1109 /*
1110 * Write the qh back to guest physical memory. This step isn't
1111 * in the EHCI spec but we need to do it since we don't share
1112 * physical memory with our guest VM.
1113 *
1114 * The first three dwords are read-only for the EHCI, so skip them
1115 * when writing back the qh.
1116 */
1117 static void ehci_flush_qh(EHCIQueue *q)
1118 {
1119 uint32_t *qh = (uint32_t *) &q->qh;
1120 uint32_t dwords = sizeof(EHCIqh) >> 2;
1121 uint32_t addr = NLPTR_GET(q->qhaddr);
1122
1123 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1124 }
1125
1126 // 4.10.2
1127
1128 static int ehci_qh_do_overlay(EHCIQueue *q)
1129 {
1130 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1131 int i;
1132 int dtoggle;
1133 int ping;
1134 int eps;
1135 int reload;
1136
1137 assert(p != NULL);
1138 assert(p->qtdaddr == q->qtdaddr);
1139
1140 // remember values in fields to preserve in qh after overlay
1141
1142 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1143 ping = q->qh.token & QTD_TOKEN_PING;
1144
1145 q->qh.current_qtd = p->qtdaddr;
1146 q->qh.next_qtd = p->qtd.next;
1147 q->qh.altnext_qtd = p->qtd.altnext;
1148 q->qh.token = p->qtd.token;
1149
1150
1151 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1152 if (eps == EHCI_QH_EPS_HIGH) {
1153 q->qh.token &= ~QTD_TOKEN_PING;
1154 q->qh.token |= ping;
1155 }
1156
1157 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1158 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1159
1160 for (i = 0; i < 5; i++) {
1161 q->qh.bufptr[i] = p->qtd.bufptr[i];
1162 }
1163
1164 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1165 // preserve QH DT bit
1166 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1167 q->qh.token |= dtoggle;
1168 }
1169
1170 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1171 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1172
1173 ehci_flush_qh(q);
1174
1175 return 0;
1176 }
1177
1178 static int ehci_init_transfer(EHCIPacket *p)
1179 {
1180 uint32_t cpage, offset, bytes, plen;
1181 dma_addr_t page;
1182
1183 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1184 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1185 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1186 qemu_sglist_init(&p->sgl, p->queue->ehci->device, 5, p->queue->ehci->as);
1187
1188 while (bytes > 0) {
1189 if (cpage > 4) {
1190 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1191 return -1;
1192 }
1193
1194 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1195 page += offset;
1196 plen = bytes;
1197 if (plen > 4096 - offset) {
1198 plen = 4096 - offset;
1199 offset = 0;
1200 cpage++;
1201 }
1202
1203 qemu_sglist_add(&p->sgl, page, plen);
1204 bytes -= plen;
1205 }
1206 return 0;
1207 }
1208
1209 static void ehci_finish_transfer(EHCIQueue *q, int len)
1210 {
1211 uint32_t cpage, offset;
1212
1213 if (len > 0) {
1214 /* update cpage & offset */
1215 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1216 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1217
1218 offset += len;
1219 cpage += offset >> QTD_BUFPTR_SH;
1220 offset &= ~QTD_BUFPTR_MASK;
1221
1222 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1223 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1224 q->qh.bufptr[0] |= offset;
1225 }
1226 }
1227
1228 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1229 {
1230 EHCIPacket *p;
1231 EHCIState *s = port->opaque;
1232 uint32_t portsc = s->portsc[port->index];
1233
1234 if (portsc & PORTSC_POWNER) {
1235 USBPort *companion = s->companion_ports[port->index];
1236 companion->ops->complete(companion, packet);
1237 return;
1238 }
1239
1240 p = container_of(packet, EHCIPacket, packet);
1241 assert(p->async == EHCI_ASYNC_INFLIGHT);
1242
1243 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
1244 trace_usb_ehci_packet_action(p->queue, p, "remove");
1245 ehci_free_packet(p);
1246 return;
1247 }
1248
1249 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1250 p->async = EHCI_ASYNC_FINISHED;
1251
1252 if (!p->queue->async) {
1253 s->periodic_sched_active = PERIODIC_ACTIVE;
1254 }
1255 qemu_bh_schedule(s->async_bh);
1256 }
1257
1258 static void ehci_execute_complete(EHCIQueue *q)
1259 {
1260 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1261 uint32_t tbytes;
1262
1263 assert(p != NULL);
1264 assert(p->qtdaddr == q->qtdaddr);
1265 assert(p->async == EHCI_ASYNC_INITIALIZED ||
1266 p->async == EHCI_ASYNC_FINISHED);
1267
1268 DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, "
1269 "status %d, actual_length %d\n",
1270 q->qhaddr, q->qh.next, q->qtdaddr,
1271 p->packet.status, p->packet.actual_length);
1272
1273 switch (p->packet.status) {
1274 case USB_RET_SUCCESS:
1275 break;
1276 case USB_RET_IOERROR:
1277 case USB_RET_NODEV:
1278 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1279 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1280 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1281 break;
1282 case USB_RET_STALL:
1283 q->qh.token |= QTD_TOKEN_HALT;
1284 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1285 break;
1286 case USB_RET_NAK:
1287 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1288 return; /* We're not done yet with this transaction */
1289 case USB_RET_BABBLE:
1290 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1291 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1292 break;
1293 default:
1294 /* should not be triggerable */
1295 fprintf(stderr, "USB invalid response %d\n", p->packet.status);
1296 g_assert_not_reached();
1297 break;
1298 }
1299
1300 /* TODO check 4.12 for splits */
1301 tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1302 if (tbytes && p->pid == USB_TOKEN_IN) {
1303 tbytes -= p->packet.actual_length;
1304 if (tbytes) {
1305 /* 4.15.1.2 must raise int on a short input packet */
1306 ehci_raise_irq(q->ehci, USBSTS_INT);
1307 if (q->async) {
1308 q->ehci->int_req_by_async = true;
1309 }
1310 }
1311 } else {
1312 tbytes = 0;
1313 }
1314 DPRINTF("updating tbytes to %d\n", tbytes);
1315 set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES);
1316
1317 ehci_finish_transfer(q, p->packet.actual_length);
1318 usb_packet_unmap(&p->packet, &p->sgl);
1319 qemu_sglist_destroy(&p->sgl);
1320 p->async = EHCI_ASYNC_NONE;
1321
1322 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1323 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1324
1325 if (q->qh.token & QTD_TOKEN_IOC) {
1326 ehci_raise_irq(q->ehci, USBSTS_INT);
1327 if (q->async) {
1328 q->ehci->int_req_by_async = true;
1329 }
1330 }
1331 }
1332
1333 /* 4.10.3 returns "again" */
1334 static int ehci_execute(EHCIPacket *p, const char *action)
1335 {
1336 USBEndpoint *ep;
1337 int endp;
1338 bool spd;
1339
1340 assert(p->async == EHCI_ASYNC_NONE ||
1341 p->async == EHCI_ASYNC_INITIALIZED);
1342
1343 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1344 fprintf(stderr, "Attempting to execute inactive qtd\n");
1345 return -1;
1346 }
1347
1348 if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
1349 ehci_trace_guest_bug(p->queue->ehci,
1350 "guest requested more bytes than allowed");
1351 return -1;
1352 }
1353
1354 if (!ehci_verify_pid(p->queue, &p->qtd)) {
1355 ehci_queue_stopped(p->queue); /* Mark the ep in the prev dir stopped */
1356 }
1357 p->pid = ehci_get_pid(&p->qtd);
1358 p->queue->last_pid = p->pid;
1359 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1360 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1361
1362 if (p->async == EHCI_ASYNC_NONE) {
1363 if (ehci_init_transfer(p) != 0) {
1364 return -1;
1365 }
1366
1367 spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
1368 usb_packet_setup(&p->packet, p->pid, ep, 0, p->qtdaddr, spd,
1369 (p->qtd.token & QTD_TOKEN_IOC) != 0);
1370 usb_packet_map(&p->packet, &p->sgl);
1371 p->async = EHCI_ASYNC_INITIALIZED;
1372 }
1373
1374 trace_usb_ehci_packet_action(p->queue, p, action);
1375 usb_handle_packet(p->queue->dev, &p->packet);
1376 DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
1377 "status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next,
1378 p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status,
1379 p->packet.actual_length);
1380
1381 if (p->packet.actual_length > BUFF_SIZE) {
1382 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1383 return -1;
1384 }
1385
1386 return 1;
1387 }
1388
1389 /* 4.7.2
1390 */
1391
1392 static int ehci_process_itd(EHCIState *ehci,
1393 EHCIitd *itd,
1394 uint32_t addr)
1395 {
1396 USBDevice *dev;
1397 USBEndpoint *ep;
1398 uint32_t i, len, pid, dir, devaddr, endp;
1399 uint32_t pg, off, ptr1, ptr2, max, mult;
1400
1401 ehci->periodic_sched_active = PERIODIC_ACTIVE;
1402
1403 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1404 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1405 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1406 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1407 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1408
1409 for(i = 0; i < 8; i++) {
1410 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1411 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1412 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1413 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1414 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1415 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1416
1417 if (len > max * mult) {
1418 len = max * mult;
1419 }
1420
1421 if (len > BUFF_SIZE) {
1422 return -1;
1423 }
1424
1425 qemu_sglist_init(&ehci->isgl, ehci->device, 2, ehci->as);
1426 if (off + len > 4096) {
1427 /* transfer crosses page border */
1428 uint32_t len2 = off + len - 4096;
1429 uint32_t len1 = len - len2;
1430 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1431 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1432 } else {
1433 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1434 }
1435
1436 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1437
1438 dev = ehci_find_device(ehci, devaddr);
1439 ep = usb_ep_get(dev, pid, endp);
1440 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
1441 usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false,
1442 (itd->transact[i] & ITD_XACT_IOC) != 0);
1443 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1444 usb_handle_packet(dev, &ehci->ipacket);
1445 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1446 } else {
1447 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1448 ehci->ipacket.status = USB_RET_NAK;
1449 ehci->ipacket.actual_length = 0;
1450 }
1451 qemu_sglist_destroy(&ehci->isgl);
1452
1453 switch (ehci->ipacket.status) {
1454 case USB_RET_SUCCESS:
1455 break;
1456 default:
1457 fprintf(stderr, "Unexpected iso usb result: %d\n",
1458 ehci->ipacket.status);
1459 /* Fall through */
1460 case USB_RET_IOERROR:
1461 case USB_RET_NODEV:
1462 /* 3.3.2: XACTERR is only allowed on IN transactions */
1463 if (dir) {
1464 itd->transact[i] |= ITD_XACT_XACTERR;
1465 ehci_raise_irq(ehci, USBSTS_ERRINT);
1466 }
1467 break;
1468 case USB_RET_BABBLE:
1469 itd->transact[i] |= ITD_XACT_BABBLE;
1470 ehci_raise_irq(ehci, USBSTS_ERRINT);
1471 break;
1472 case USB_RET_NAK:
1473 /* no data for us, so do a zero-length transfer */
1474 ehci->ipacket.actual_length = 0;
1475 break;
1476 }
1477 if (!dir) {
1478 set_field(&itd->transact[i], len - ehci->ipacket.actual_length,
1479 ITD_XACT_LENGTH); /* OUT */
1480 } else {
1481 set_field(&itd->transact[i], ehci->ipacket.actual_length,
1482 ITD_XACT_LENGTH); /* IN */
1483 }
1484 if (itd->transact[i] & ITD_XACT_IOC) {
1485 ehci_raise_irq(ehci, USBSTS_INT);
1486 }
1487 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1488 }
1489 }
1490 return 0;
1491 }
1492
1493
1494 /* This state is the entry point for asynchronous schedule
1495 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1496 */
1497 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1498 {
1499 EHCIqh qh;
1500 int i = 0;
1501 int again = 0;
1502 uint32_t entry = ehci->asynclistaddr;
1503
1504 /* set reclamation flag at start event (4.8.6) */
1505 if (async) {
1506 ehci_set_usbsts(ehci, USBSTS_REC);
1507 }
1508
1509 ehci_queues_rip_unused(ehci, async);
1510
1511 /* Find the head of the list (4.9.1.1) */
1512 for(i = 0; i < MAX_QH; i++) {
1513 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1514 sizeof(EHCIqh) >> 2) < 0) {
1515 return 0;
1516 }
1517 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1518
1519 if (qh.epchar & QH_EPCHAR_H) {
1520 if (async) {
1521 entry |= (NLPTR_TYPE_QH << 1);
1522 }
1523
1524 ehci_set_fetch_addr(ehci, async, entry);
1525 ehci_set_state(ehci, async, EST_FETCHENTRY);
1526 again = 1;
1527 goto out;
1528 }
1529
1530 entry = qh.next;
1531 if (entry == ehci->asynclistaddr) {
1532 break;
1533 }
1534 }
1535
1536 /* no head found for list. */
1537
1538 ehci_set_state(ehci, async, EST_ACTIVE);
1539
1540 out:
1541 return again;
1542 }
1543
1544
1545 /* This state is the entry point for periodic schedule processing as
1546 * well as being a continuation state for async processing.
1547 */
1548 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1549 {
1550 int again = 0;
1551 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1552
1553 if (NLPTR_TBIT(entry)) {
1554 ehci_set_state(ehci, async, EST_ACTIVE);
1555 goto out;
1556 }
1557
1558 /* section 4.8, only QH in async schedule */
1559 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1560 fprintf(stderr, "non queue head request in async schedule\n");
1561 return -1;
1562 }
1563
1564 switch (NLPTR_TYPE_GET(entry)) {
1565 case NLPTR_TYPE_QH:
1566 ehci_set_state(ehci, async, EST_FETCHQH);
1567 again = 1;
1568 break;
1569
1570 case NLPTR_TYPE_ITD:
1571 ehci_set_state(ehci, async, EST_FETCHITD);
1572 again = 1;
1573 break;
1574
1575 case NLPTR_TYPE_STITD:
1576 ehci_set_state(ehci, async, EST_FETCHSITD);
1577 again = 1;
1578 break;
1579
1580 default:
1581 /* TODO: handle FSTN type */
1582 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1583 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1584 return -1;
1585 }
1586
1587 out:
1588 return again;
1589 }
1590
1591 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1592 {
1593 uint32_t entry;
1594 EHCIQueue *q;
1595 EHCIqh qh;
1596
1597 entry = ehci_get_fetch_addr(ehci, async);
1598 q = ehci_find_queue_by_qh(ehci, entry, async);
1599 if (q == NULL) {
1600 q = ehci_alloc_queue(ehci, entry, async);
1601 }
1602
1603 q->seen++;
1604 if (q->seen > 1) {
1605 /* we are going in circles -- stop processing */
1606 ehci_set_state(ehci, async, EST_ACTIVE);
1607 q = NULL;
1608 goto out;
1609 }
1610
1611 if (get_dwords(ehci, NLPTR_GET(q->qhaddr),
1612 (uint32_t *) &qh, sizeof(EHCIqh) >> 2) < 0) {
1613 q = NULL;
1614 goto out;
1615 }
1616 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh);
1617
1618 /*
1619 * The overlay area of the qh should never be changed by the guest,
1620 * except when idle, in which case the reset is a nop.
1621 */
1622 if (!ehci_verify_qh(q, &qh)) {
1623 if (ehci_reset_queue(q) > 0) {
1624 ehci_trace_guest_bug(ehci, "guest updated active QH");
1625 }
1626 }
1627 q->qh = qh;
1628
1629 q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1630 if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */
1631 q->transact_ctr = 4;
1632 }
1633
1634 if (q->dev == NULL) {
1635 q->dev = ehci_find_device(q->ehci,
1636 get_field(q->qh.epchar, QH_EPCHAR_DEVADDR));
1637 }
1638
1639 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1640
1641 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1642 if (ehci->usbsts & USBSTS_REC) {
1643 ehci_clear_usbsts(ehci, USBSTS_REC);
1644 } else {
1645 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1646 " - done processing\n", q->qhaddr);
1647 ehci_set_state(ehci, async, EST_ACTIVE);
1648 q = NULL;
1649 goto out;
1650 }
1651 }
1652
1653 #if EHCI_DEBUG
1654 if (q->qhaddr != q->qh.next) {
1655 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1656 q->qhaddr,
1657 q->qh.epchar & QH_EPCHAR_H,
1658 q->qh.token & QTD_TOKEN_HALT,
1659 q->qh.token & QTD_TOKEN_ACTIVE,
1660 q->qh.next);
1661 }
1662 #endif
1663
1664 if (q->qh.token & QTD_TOKEN_HALT) {
1665 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1666
1667 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1668 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1669 q->qtdaddr = q->qh.current_qtd;
1670 ehci_set_state(ehci, async, EST_FETCHQTD);
1671
1672 } else {
1673 /* EHCI spec version 1.0 Section 4.10.2 */
1674 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1675 }
1676
1677 out:
1678 return q;
1679 }
1680
1681 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1682 {
1683 uint32_t entry;
1684 EHCIitd itd;
1685
1686 assert(!async);
1687 entry = ehci_get_fetch_addr(ehci, async);
1688
1689 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1690 sizeof(EHCIitd) >> 2) < 0) {
1691 return -1;
1692 }
1693 ehci_trace_itd(ehci, entry, &itd);
1694
1695 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1696 return -1;
1697 }
1698
1699 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1700 sizeof(EHCIitd) >> 2);
1701 ehci_set_fetch_addr(ehci, async, itd.next);
1702 ehci_set_state(ehci, async, EST_FETCHENTRY);
1703
1704 return 1;
1705 }
1706
1707 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1708 {
1709 uint32_t entry;
1710 EHCIsitd sitd;
1711
1712 assert(!async);
1713 entry = ehci_get_fetch_addr(ehci, async);
1714
1715 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1716 sizeof(EHCIsitd) >> 2) < 0) {
1717 return 0;
1718 }
1719 ehci_trace_sitd(ehci, entry, &sitd);
1720
1721 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1722 /* siTD is not active, nothing to do */;
1723 } else {
1724 /* TODO: split transfers are not implemented */
1725 fprintf(stderr, "WARNING: Skipping active siTD\n");
1726 }
1727
1728 ehci_set_fetch_addr(ehci, async, sitd.next);
1729 ehci_set_state(ehci, async, EST_FETCHENTRY);
1730 return 1;
1731 }
1732
1733 /* Section 4.10.2 - paragraph 3 */
1734 static int ehci_state_advqueue(EHCIQueue *q)
1735 {
1736 #if 0
1737 /* TO-DO: 4.10.2 - paragraph 2
1738 * if I-bit is set to 1 and QH is not active
1739 * go to horizontal QH
1740 */
1741 if (I-bit set) {
1742 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1743 goto out;
1744 }
1745 #endif
1746
1747 /*
1748 * want data and alt-next qTD is valid
1749 */
1750 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1751 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1752 q->qtdaddr = q->qh.altnext_qtd;
1753 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1754
1755 /*
1756 * next qTD is valid
1757 */
1758 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1759 q->qtdaddr = q->qh.next_qtd;
1760 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1761
1762 /*
1763 * no valid qTD, try next QH
1764 */
1765 } else {
1766 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1767 }
1768
1769 return 1;
1770 }
1771
1772 /* Section 4.10.2 - paragraph 4 */
1773 static int ehci_state_fetchqtd(EHCIQueue *q)
1774 {
1775 EHCIqtd qtd;
1776 EHCIPacket *p;
1777 int again = 1;
1778
1779 if (get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1780 sizeof(EHCIqtd) >> 2) < 0) {
1781 return 0;
1782 }
1783 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1784
1785 p = QTAILQ_FIRST(&q->packets);
1786 if (p != NULL) {
1787 if (!ehci_verify_qtd(p, &qtd)) {
1788 ehci_cancel_queue(q);
1789 if (qtd.token & QTD_TOKEN_ACTIVE) {
1790 ehci_trace_guest_bug(q->ehci, "guest updated active qTD");
1791 }
1792 p = NULL;
1793 } else {
1794 p->qtd = qtd;
1795 ehci_qh_do_overlay(q);
1796 }
1797 }
1798
1799 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1800 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1801 } else if (p != NULL) {
1802 switch (p->async) {
1803 case EHCI_ASYNC_NONE:
1804 case EHCI_ASYNC_INITIALIZED:
1805 /* Not yet executed (MULT), or previously nacked (int) packet */
1806 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1807 break;
1808 case EHCI_ASYNC_INFLIGHT:
1809 /* Check if the guest has added new tds to the queue */
1810 again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head));
1811 /* Unfinished async handled packet, go horizontal */
1812 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1813 break;
1814 case EHCI_ASYNC_FINISHED:
1815 /* Complete executing of the packet */
1816 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1817 break;
1818 }
1819 } else {
1820 p = ehci_alloc_packet(q);
1821 p->qtdaddr = q->qtdaddr;
1822 p->qtd = qtd;
1823 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1824 }
1825
1826 return again;
1827 }
1828
1829 static int ehci_state_horizqh(EHCIQueue *q)
1830 {
1831 int again = 0;
1832
1833 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1834 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1835 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1836 again = 1;
1837 } else {
1838 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1839 }
1840
1841 return again;
1842 }
1843
1844 /* Returns "again" */
1845 static int ehci_fill_queue(EHCIPacket *p)
1846 {
1847 USBEndpoint *ep = p->packet.ep;
1848 EHCIQueue *q = p->queue;
1849 EHCIqtd qtd = p->qtd;
1850 uint32_t qtdaddr;
1851
1852 for (;;) {
1853 if (NLPTR_TBIT(qtd.next) != 0) {
1854 break;
1855 }
1856 qtdaddr = qtd.next;
1857 /*
1858 * Detect circular td lists, Windows creates these, counting on the
1859 * active bit going low after execution to make the queue stop.
1860 */
1861 QTAILQ_FOREACH(p, &q->packets, next) {
1862 if (p->qtdaddr == qtdaddr) {
1863 goto leave;
1864 }
1865 }
1866 if (get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1867 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2) < 0) {
1868 return -1;
1869 }
1870 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1871 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1872 break;
1873 }
1874 if (!ehci_verify_pid(q, &qtd)) {
1875 ehci_trace_guest_bug(q->ehci, "guest queued token with wrong pid");
1876 break;
1877 }
1878 p = ehci_alloc_packet(q);
1879 p->qtdaddr = qtdaddr;
1880 p->qtd = qtd;
1881 if (ehci_execute(p, "queue") == -1) {
1882 return -1;
1883 }
1884 assert(p->packet.status == USB_RET_ASYNC);
1885 p->async = EHCI_ASYNC_INFLIGHT;
1886 }
1887 leave:
1888 usb_device_flush_ep_queue(ep->dev, ep);
1889 return 1;
1890 }
1891
1892 static int ehci_state_execute(EHCIQueue *q)
1893 {
1894 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1895 int again = 0;
1896
1897 assert(p != NULL);
1898 assert(p->qtdaddr == q->qtdaddr);
1899
1900 if (ehci_qh_do_overlay(q) != 0) {
1901 return -1;
1902 }
1903
1904 // TODO verify enough time remains in the uframe as in 4.4.1.1
1905 // TODO write back ptr to async list when done or out of time
1906
1907 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
1908 if (!q->async && q->transact_ctr == 0) {
1909 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1910 again = 1;
1911 goto out;
1912 }
1913
1914 if (q->async) {
1915 ehci_set_usbsts(q->ehci, USBSTS_REC);
1916 }
1917
1918 again = ehci_execute(p, "process");
1919 if (again == -1) {
1920 goto out;
1921 }
1922 if (p->packet.status == USB_RET_ASYNC) {
1923 ehci_flush_qh(q);
1924 trace_usb_ehci_packet_action(p->queue, p, "async");
1925 p->async = EHCI_ASYNC_INFLIGHT;
1926 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1927 if (q->async) {
1928 again = ehci_fill_queue(p);
1929 } else {
1930 again = 1;
1931 }
1932 goto out;
1933 }
1934
1935 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1936 again = 1;
1937
1938 out:
1939 return again;
1940 }
1941
1942 static int ehci_state_executing(EHCIQueue *q)
1943 {
1944 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1945
1946 assert(p != NULL);
1947 assert(p->qtdaddr == q->qtdaddr);
1948
1949 ehci_execute_complete(q);
1950
1951 /* 4.10.3 */
1952 if (!q->async && q->transact_ctr > 0) {
1953 q->transact_ctr--;
1954 }
1955
1956 /* 4.10.5 */
1957 if (p->packet.status == USB_RET_NAK) {
1958 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1959 } else {
1960 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
1961 }
1962
1963 ehci_flush_qh(q);
1964 return 1;
1965 }
1966
1967
1968 static int ehci_state_writeback(EHCIQueue *q)
1969 {
1970 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1971 uint32_t *qtd, addr;
1972 int again = 0;
1973
1974 /* Write back the QTD from the QH area */
1975 assert(p != NULL);
1976 assert(p->qtdaddr == q->qtdaddr);
1977
1978 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
1979 qtd = (uint32_t *) &q->qh.next_qtd;
1980 addr = NLPTR_GET(p->qtdaddr);
1981 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
1982 ehci_free_packet(p);
1983
1984 /*
1985 * EHCI specs say go horizontal here.
1986 *
1987 * We can also advance the queue here for performance reasons. We
1988 * need to take care to only take that shortcut in case we've
1989 * processed the qtd just written back without errors, i.e. halt
1990 * bit is clear.
1991 */
1992 if (q->qh.token & QTD_TOKEN_HALT) {
1993 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1994 again = 1;
1995 } else {
1996 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
1997 again = 1;
1998 }
1999 return again;
2000 }
2001
2002 /*
2003 * This is the state machine that is common to both async and periodic
2004 */
2005
2006 static void ehci_advance_state(EHCIState *ehci, int async)
2007 {
2008 EHCIQueue *q = NULL;
2009 int again;
2010
2011 do {
2012 switch(ehci_get_state(ehci, async)) {
2013 case EST_WAITLISTHEAD:
2014 again = ehci_state_waitlisthead(ehci, async);
2015 break;
2016
2017 case EST_FETCHENTRY:
2018 again = ehci_state_fetchentry(ehci, async);
2019 break;
2020
2021 case EST_FETCHQH:
2022 q = ehci_state_fetchqh(ehci, async);
2023 if (q != NULL) {
2024 assert(q->async == async);
2025 again = 1;
2026 } else {
2027 again = 0;
2028 }
2029 break;
2030
2031 case EST_FETCHITD:
2032 again = ehci_state_fetchitd(ehci, async);
2033 break;
2034
2035 case EST_FETCHSITD:
2036 again = ehci_state_fetchsitd(ehci, async);
2037 break;
2038
2039 case EST_ADVANCEQUEUE:
2040 assert(q != NULL);
2041 again = ehci_state_advqueue(q);
2042 break;
2043
2044 case EST_FETCHQTD:
2045 assert(q != NULL);
2046 again = ehci_state_fetchqtd(q);
2047 break;
2048
2049 case EST_HORIZONTALQH:
2050 assert(q != NULL);
2051 again = ehci_state_horizqh(q);
2052 break;
2053
2054 case EST_EXECUTE:
2055 assert(q != NULL);
2056 again = ehci_state_execute(q);
2057 if (async) {
2058 ehci->async_stepdown = 0;
2059 }
2060 break;
2061
2062 case EST_EXECUTING:
2063 assert(q != NULL);
2064 if (async) {
2065 ehci->async_stepdown = 0;
2066 }
2067 again = ehci_state_executing(q);
2068 break;
2069
2070 case EST_WRITEBACK:
2071 assert(q != NULL);
2072 again = ehci_state_writeback(q);
2073 if (!async) {
2074 ehci->periodic_sched_active = PERIODIC_ACTIVE;
2075 }
2076 break;
2077
2078 default:
2079 fprintf(stderr, "Bad state!\n");
2080 again = -1;
2081 g_assert_not_reached();
2082 break;
2083 }
2084
2085 if (again < 0) {
2086 fprintf(stderr, "processing error - resetting ehci HC\n");
2087 ehci_reset(ehci);
2088 again = 0;
2089 }
2090 }
2091 while (again);
2092 }
2093
2094 static void ehci_advance_async_state(EHCIState *ehci)
2095 {
2096 const int async = 1;
2097
2098 switch(ehci_get_state(ehci, async)) {
2099 case EST_INACTIVE:
2100 if (!ehci_async_enabled(ehci)) {
2101 break;
2102 }
2103 ehci_set_state(ehci, async, EST_ACTIVE);
2104 // No break, fall through to ACTIVE
2105
2106 case EST_ACTIVE:
2107 if (!ehci_async_enabled(ehci)) {
2108 ehci_queues_rip_all(ehci, async);
2109 ehci_set_state(ehci, async, EST_INACTIVE);
2110 break;
2111 }
2112
2113 /* make sure guest has acknowledged the doorbell interrupt */
2114 /* TO-DO: is this really needed? */
2115 if (ehci->usbsts & USBSTS_IAA) {
2116 DPRINTF("IAA status bit still set.\n");
2117 break;
2118 }
2119
2120 /* check that address register has been set */
2121 if (ehci->asynclistaddr == 0) {
2122 break;
2123 }
2124
2125 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2126 ehci_advance_state(ehci, async);
2127
2128 /* If the doorbell is set, the guest wants to make a change to the
2129 * schedule. The host controller needs to release cached data.
2130 * (section 4.8.2)
2131 */
2132 if (ehci->usbcmd & USBCMD_IAAD) {
2133 /* Remove all unseen qhs from the async qhs queue */
2134 ehci_queues_rip_unseen(ehci, async);
2135 trace_usb_ehci_doorbell_ack();
2136 ehci->usbcmd &= ~USBCMD_IAAD;
2137 ehci_raise_irq(ehci, USBSTS_IAA);
2138 }
2139 break;
2140
2141 default:
2142 /* this should only be due to a developer mistake */
2143 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2144 "Resetting to active\n", ehci->astate);
2145 g_assert_not_reached();
2146 }
2147 }
2148
2149 static void ehci_advance_periodic_state(EHCIState *ehci)
2150 {
2151 uint32_t entry;
2152 uint32_t list;
2153 const int async = 0;
2154
2155 // 4.6
2156
2157 switch(ehci_get_state(ehci, async)) {
2158 case EST_INACTIVE:
2159 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2160 ehci_set_state(ehci, async, EST_ACTIVE);
2161 // No break, fall through to ACTIVE
2162 } else
2163 break;
2164
2165 case EST_ACTIVE:
2166 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2167 ehci_queues_rip_all(ehci, async);
2168 ehci_set_state(ehci, async, EST_INACTIVE);
2169 break;
2170 }
2171
2172 list = ehci->periodiclistbase & 0xfffff000;
2173 /* check that register has been set */
2174 if (list == 0) {
2175 break;
2176 }
2177 list |= ((ehci->frindex & 0x1ff8) >> 1);
2178
2179 if (get_dwords(ehci, list, &entry, 1) < 0) {
2180 break;
2181 }
2182
2183 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2184 ehci->frindex / 8, list, entry);
2185 ehci_set_fetch_addr(ehci, async,entry);
2186 ehci_set_state(ehci, async, EST_FETCHENTRY);
2187 ehci_advance_state(ehci, async);
2188 ehci_queues_rip_unused(ehci, async);
2189 break;
2190
2191 default:
2192 /* this should only be due to a developer mistake */
2193 fprintf(stderr, "ehci: Bad periodic state %d. "
2194 "Resetting to active\n", ehci->pstate);
2195 g_assert_not_reached();
2196 }
2197 }
2198
2199 static void ehci_update_frindex(EHCIState *ehci, int uframes)
2200 {
2201 int i;
2202
2203 if (!ehci_enabled(ehci) && ehci->pstate == EST_INACTIVE) {
2204 return;
2205 }
2206
2207 for (i = 0; i < uframes; i++) {
2208 ehci->frindex++;
2209
2210 if (ehci->frindex == 0x00002000) {
2211 ehci_raise_irq(ehci, USBSTS_FLR);
2212 }
2213
2214 if (ehci->frindex == 0x00004000) {
2215 ehci_raise_irq(ehci, USBSTS_FLR);
2216 ehci->frindex = 0;
2217 if (ehci->usbsts_frindex >= 0x00004000) {
2218 ehci->usbsts_frindex -= 0x00004000;
2219 } else {
2220 ehci->usbsts_frindex = 0;
2221 }
2222 }
2223 }
2224 }
2225
2226 static void ehci_frame_timer(void *opaque)
2227 {
2228 EHCIState *ehci = opaque;
2229 int need_timer = 0;
2230 int64_t expire_time, t_now;
2231 uint64_t ns_elapsed;
2232 int uframes, skipped_uframes;
2233 int i;
2234
2235 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2236 ns_elapsed = t_now - ehci->last_run_ns;
2237 uframes = ns_elapsed / UFRAME_TIMER_NS;
2238
2239 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2240 need_timer++;
2241
2242 if (uframes > (ehci->maxframes * 8)) {
2243 skipped_uframes = uframes - (ehci->maxframes * 8);
2244 ehci_update_frindex(ehci, skipped_uframes);
2245 ehci->last_run_ns += UFRAME_TIMER_NS * skipped_uframes;
2246 uframes -= skipped_uframes;
2247 DPRINTF("WARNING - EHCI skipped %d uframes\n", skipped_uframes);
2248 }
2249
2250 for (i = 0; i < uframes; i++) {
2251 /*
2252 * If we're running behind schedule, we should not catch up
2253 * too fast, as that will make some guests unhappy:
2254 * 1) We must process a minimum of MIN_UFR_PER_TICK frames,
2255 * otherwise we will never catch up
2256 * 2) Process frames until the guest has requested an irq (IOC)
2257 */
2258 if (i >= MIN_UFR_PER_TICK) {
2259 ehci_commit_irq(ehci);
2260 if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
2261 break;
2262 }
2263 }
2264 if (ehci->periodic_sched_active) {
2265 ehci->periodic_sched_active--;
2266 }
2267 ehci_update_frindex(ehci, 1);
2268 if ((ehci->frindex & 7) == 0) {
2269 ehci_advance_periodic_state(ehci);
2270 }
2271 ehci->last_run_ns += UFRAME_TIMER_NS;
2272 }
2273 } else {
2274 ehci->periodic_sched_active = 0;
2275 ehci_update_frindex(ehci, uframes);
2276 ehci->last_run_ns += UFRAME_TIMER_NS * uframes;
2277 }
2278
2279 if (ehci->periodic_sched_active) {
2280 ehci->async_stepdown = 0;
2281 } else if (ehci->async_stepdown < ehci->maxframes / 2) {
2282 ehci->async_stepdown++;
2283 }
2284
2285 /* Async is not inside loop since it executes everything it can once
2286 * called
2287 */
2288 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2289 need_timer++;
2290 ehci_advance_async_state(ehci);
2291 }
2292
2293 ehci_commit_irq(ehci);
2294 if (ehci->usbsts_pending) {
2295 need_timer++;
2296 ehci->async_stepdown = 0;
2297 }
2298
2299 if (ehci_enabled(ehci) && (ehci->usbintr & USBSTS_FLR)) {
2300 need_timer++;
2301 }
2302
2303 if (need_timer) {
2304 /* If we've raised int, we speed up the timer, so that we quickly
2305 * notice any new packets queued up in response */
2306 if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
2307 expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 4);
2308 ehci->int_req_by_async = false;
2309 } else {
2310 expire_time = t_now + (get_ticks_per_sec()
2311 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2312 }
2313 timer_mod(ehci->frame_timer, expire_time);
2314 }
2315 }
2316
2317 static const MemoryRegionOps ehci_mmio_caps_ops = {
2318 .read = ehci_caps_read,
2319 .valid.min_access_size = 1,
2320 .valid.max_access_size = 4,
2321 .impl.min_access_size = 1,
2322 .impl.max_access_size = 1,
2323 .endianness = DEVICE_LITTLE_ENDIAN,
2324 };
2325
2326 static const MemoryRegionOps ehci_mmio_opreg_ops = {
2327 .read = ehci_opreg_read,
2328 .write = ehci_opreg_write,
2329 .valid.min_access_size = 4,
2330 .valid.max_access_size = 4,
2331 .endianness = DEVICE_LITTLE_ENDIAN,
2332 };
2333
2334 static const MemoryRegionOps ehci_mmio_port_ops = {
2335 .read = ehci_port_read,
2336 .write = ehci_port_write,
2337 .valid.min_access_size = 4,
2338 .valid.max_access_size = 4,
2339 .endianness = DEVICE_LITTLE_ENDIAN,
2340 };
2341
2342 static USBPortOps ehci_port_ops = {
2343 .attach = ehci_attach,
2344 .detach = ehci_detach,
2345 .child_detach = ehci_child_detach,
2346 .wakeup = ehci_wakeup,
2347 .complete = ehci_async_complete_packet,
2348 };
2349
2350 static USBBusOps ehci_bus_ops_companion = {
2351 .register_companion = ehci_register_companion,
2352 .wakeup_endpoint = ehci_wakeup_endpoint,
2353 };
2354 static USBBusOps ehci_bus_ops_standalone = {
2355 .wakeup_endpoint = ehci_wakeup_endpoint,
2356 };
2357
2358 static void usb_ehci_pre_save(void *opaque)
2359 {
2360 EHCIState *ehci = opaque;
2361 uint32_t new_frindex;
2362
2363 /* Round down frindex to a multiple of 8 for migration compatibility */
2364 new_frindex = ehci->frindex & ~7;
2365 ehci->last_run_ns -= (ehci->frindex - new_frindex) * UFRAME_TIMER_NS;
2366 ehci->frindex = new_frindex;
2367 }
2368
2369 static int usb_ehci_post_load(void *opaque, int version_id)
2370 {
2371 EHCIState *s = opaque;
2372 int i;
2373
2374 for (i = 0; i < NB_PORTS; i++) {
2375 USBPort *companion = s->companion_ports[i];
2376 if (companion == NULL) {
2377 continue;
2378 }
2379 if (s->portsc[i] & PORTSC_POWNER) {
2380 companion->dev = s->ports[i].dev;
2381 } else {
2382 companion->dev = NULL;
2383 }
2384 }
2385
2386 return 0;
2387 }
2388
2389 static void usb_ehci_vm_state_change(void *opaque, int running, RunState state)
2390 {
2391 EHCIState *ehci = opaque;
2392
2393 /*
2394 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2395 * schedule in guest memory. We must do the rebuilt ASAP, so that
2396 * USB-devices which have async handled packages have a packet in the
2397 * ep queue to match the completion with.
2398 */
2399 if (state == RUN_STATE_RUNNING) {
2400 ehci_advance_async_state(ehci);
2401 }
2402
2403 /*
2404 * The schedule rebuilt from guest memory could cause the migration dest
2405 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2406 * will never have existed on the destination. Therefor we must flush the
2407 * async schedule on savevm to catch any not yet noticed unlinks.
2408 */
2409 if (state == RUN_STATE_SAVE_VM) {
2410 ehci_advance_async_state(ehci);
2411 ehci_queues_rip_unseen(ehci, 1);
2412 }
2413 }
2414
2415 const VMStateDescription vmstate_ehci = {
2416 .name = "ehci-core",
2417 .version_id = 2,
2418 .minimum_version_id = 1,
2419 .pre_save = usb_ehci_pre_save,
2420 .post_load = usb_ehci_post_load,
2421 .fields = (VMStateField[]) {
2422 /* mmio registers */
2423 VMSTATE_UINT32(usbcmd, EHCIState),
2424 VMSTATE_UINT32(usbsts, EHCIState),
2425 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2426 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2427 VMSTATE_UINT32(usbintr, EHCIState),
2428 VMSTATE_UINT32(frindex, EHCIState),
2429 VMSTATE_UINT32(ctrldssegment, EHCIState),
2430 VMSTATE_UINT32(periodiclistbase, EHCIState),
2431 VMSTATE_UINT32(asynclistaddr, EHCIState),
2432 VMSTATE_UINT32(configflag, EHCIState),
2433 VMSTATE_UINT32(portsc[0], EHCIState),
2434 VMSTATE_UINT32(portsc[1], EHCIState),
2435 VMSTATE_UINT32(portsc[2], EHCIState),
2436 VMSTATE_UINT32(portsc[3], EHCIState),
2437 VMSTATE_UINT32(portsc[4], EHCIState),
2438 VMSTATE_UINT32(portsc[5], EHCIState),
2439 /* frame timer */
2440 VMSTATE_TIMER(frame_timer, EHCIState),
2441 VMSTATE_UINT64(last_run_ns, EHCIState),
2442 VMSTATE_UINT32(async_stepdown, EHCIState),
2443 /* schedule state */
2444 VMSTATE_UINT32(astate, EHCIState),
2445 VMSTATE_UINT32(pstate, EHCIState),
2446 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2447 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2448 VMSTATE_END_OF_LIST()
2449 }
2450 };
2451
2452 void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)
2453 {
2454 int i;
2455
2456 if (s->portnr > NB_PORTS) {
2457 error_setg(errp, "Too many ports! Max. port number is %d.",
2458 NB_PORTS);
2459 return;
2460 }
2461
2462 usb_bus_new(&s->bus, sizeof(s->bus), s->companion_enable ?
2463 &ehci_bus_ops_companion : &ehci_bus_ops_standalone, dev);
2464 for (i = 0; i < s->portnr; i++) {
2465 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2466 USB_SPEED_MASK_HIGH);
2467 s->ports[i].dev = 0;
2468 }
2469
2470 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ehci_frame_timer, s);
2471 s->async_bh = qemu_bh_new(ehci_frame_timer, s);
2472 s->device = dev;
2473
2474 qemu_register_reset(ehci_reset, s);
2475 s->vmstate = qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s);
2476 }
2477
2478 void usb_ehci_unrealize(EHCIState *s, DeviceState *dev, Error **errp)
2479 {
2480 trace_usb_ehci_unrealize();
2481
2482 if (s->frame_timer) {
2483 timer_del(s->frame_timer);
2484 timer_free(s->frame_timer);
2485 s->frame_timer = NULL;
2486 }
2487 if (s->async_bh) {
2488 qemu_bh_delete(s->async_bh);
2489 }
2490
2491 ehci_queues_rip_all(s, 0);
2492 ehci_queues_rip_all(s, 1);
2493
2494 memory_region_del_subregion(&s->mem, &s->mem_caps);
2495 memory_region_del_subregion(&s->mem, &s->mem_opreg);
2496 memory_region_del_subregion(&s->mem, &s->mem_ports);
2497
2498 usb_bus_release(&s->bus);
2499
2500 if (s->vmstate) {
2501 qemu_del_vm_change_state_handler(s->vmstate);
2502 }
2503 }
2504
2505 void usb_ehci_init(EHCIState *s, DeviceState *dev)
2506 {
2507 /* 2.2 host controller interface version */
2508 s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
2509 s->caps[0x01] = 0x00;
2510 s->caps[0x02] = 0x00;
2511 s->caps[0x03] = 0x01; /* HC version */
2512 s->caps[0x04] = s->portnr; /* Number of downstream ports */
2513 s->caps[0x05] = 0x00; /* No companion ports at present */
2514 s->caps[0x06] = 0x00;
2515 s->caps[0x07] = 0x00;
2516 s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2517 s->caps[0x0a] = 0x00;
2518 s->caps[0x0b] = 0x00;
2519
2520 QTAILQ_INIT(&s->aqueues);
2521 QTAILQ_INIT(&s->pqueues);
2522 usb_packet_init(&s->ipacket);
2523
2524 memory_region_init(&s->mem, OBJECT(dev), "ehci", MMIO_SIZE);
2525 memory_region_init_io(&s->mem_caps, OBJECT(dev), &ehci_mmio_caps_ops, s,
2526 "capabilities", CAPA_SIZE);
2527 memory_region_init_io(&s->mem_opreg, OBJECT(dev), &ehci_mmio_opreg_ops, s,
2528 "operational", s->portscbase);
2529 memory_region_init_io(&s->mem_ports, OBJECT(dev), &ehci_mmio_port_ops, s,
2530 "ports", 4 * s->portnr);
2531
2532 memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps);
2533 memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
2534 memory_region_add_subregion(&s->mem, s->opregbase + s->portscbase,
2535 &s->mem_ports);
2536 }
2537
2538 /*
2539 * vim: expandtab ts=4
2540 */
AR7 emulation for QEMU