hw/mips/cps.c

   1 /*
   2  * Coherent Processing System emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/module.h"
  23 #include "hw/mips/cps.h"
  24 #include "hw/mips/mips.h"
  25 #include "hw/qdev-clock.h"
  26 #include "hw/qdev-properties.h"
  27 #include "hw/mips/cpudevs.h"
  28 #include "sysemu/kvm.h"
  29 #include "sysemu/reset.h"
  30
  31 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
  32 {
  33     assert(pin_number < s->num_irq);
  34     return s->gic.irq_state[pin_number].irq;
  35 }
  36
  37 static void mips_cps_init(Object *obj)
  38 {
  39     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  40     MIPSCPSState *s = MIPS_CPS(obj);
  41
  42     s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL);
  43     /*
  44      * Cover entire address space as there do not seem to be any
  45      * constraints for the base address of CPC and GIC.
  46      */
  47     memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
  48     sysbus_init_mmio(sbd, &s->container);
  49 }
  50
  51 static void main_cpu_reset(void *opaque)
  52 {
  53     MIPSCPU *cpu = opaque;
  54     CPUState *cs = CPU(cpu);
  55
  56     cpu_reset(cs);
  57 }
  58
  59 static bool cpu_mips_itu_supported(CPUMIPSState *env)
  60 {
  61     bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
  62                  (env->CP0_Config3 & (1 << CP0C3_MT));
  63
  64     return is_mt && !kvm_enabled();
  65 }
  66
  67 static void mips_cps_realize(DeviceState *dev, Error **errp)
  68 {
  69     MIPSCPSState *s = MIPS_CPS(dev);
  70     CPUMIPSState *env;
  71     MIPSCPU *cpu;
  72     int i;
  73     target_ulong gcr_base;
  74     bool itu_present = false;
  75     bool saar_present = false;
  76
  77     if (!clock_get(s->clock)) {
  78         error_setg(errp, "CPS input clock is not connected to an output clock");
  79         return;
  80     }
  81
  82     for (i = 0; i < s->num_vp; i++) {
  83         cpu = MIPS_CPU(object_new(s->cpu_type));
  84
  85         /* All VPs are halted on reset. Leave powering up to CPC. */
  86         if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
  87                                       errp)) {
  88             return;
  89         }
  90         /* All cores use the same clock tree */
  91         qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);
  92
  93         if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
  94             return;
  95         }
  96
  97         /* Init internal devices */
  98         cpu_mips_irq_init_cpu(cpu);
  99         cpu_mips_clock_init(cpu);
 100
 101         env = &cpu->env;
 102         if (cpu_mips_itu_supported(env)) {
 103             itu_present = true;
 104             /* Attach ITC Tag to the VP */
 105             env->itc_tag = mips_itu_get_tag_region(&s->itu);
 106             env->itu = &s->itu;
 107         }
 108         qemu_register_reset(main_cpu_reset, cpu);
 109     }
 110
 111     cpu = MIPS_CPU(first_cpu);
 112     env = &cpu->env;
 113     saar_present = (bool)env->saarp;
 114
 115     /* Inter-Thread Communication Unit */
 116     if (itu_present) {
 117         object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
 118         object_property_set_int(OBJECT(&s->itu), "num-fifo", 16,
 119                                 &error_abort);
 120         object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16,
 121                                 &error_abort);
 122         object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present,
 123                                  &error_abort);
 124         if (saar_present) {
 125             s->itu.saar = &env->CP0_SAAR;
 126         }
 127         if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
 128             return;
 129         }
 130
 131         memory_region_add_subregion(&s->container, 0,
 132                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
 133     }
 134
 135     /* Cluster Power Controller */
 136     object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
 137     object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp,
 138                             &error_abort);
 139     object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
 140                             &error_abort);
 141     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
 142         return;
 143     }
 144
 145     memory_region_add_subregion(&s->container, 0,
 146                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
 147
 148     /* Global Interrupt Controller */
 149     object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
 150     object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp,
 151                             &error_abort);
 152     object_property_set_int(OBJECT(&s->gic), "num-irq", 128,
 153                             &error_abort);
 154     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
 155         return;
 156     }
 157
 158     memory_region_add_subregion(&s->container, 0,
 159                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
 160
 161     /* Global Configuration Registers */
 162     gcr_base = env->CP0_CMGCRBase << 4;
 163
 164     object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
 165     object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp,
 166                             &error_abort);
 167     object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
 168                             &error_abort);
 169     object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
 170                             &error_abort);
 171     object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
 172                              &error_abort);
 173     object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
 174                              &error_abort);
 175     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
 176         return;
 177     }
 178
 179     memory_region_add_subregion(&s->container, gcr_base,
 180                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
 181 }
 182
 183 static Property mips_cps_properties[] = {
 184     DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
 185     DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
 186     DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
 187     DEFINE_PROP_END_OF_LIST()
 188 };
 189
 190 static void mips_cps_class_init(ObjectClass *klass, void *data)
 191 {
 192     DeviceClass *dc = DEVICE_CLASS(klass);
 193
 194     dc->realize = mips_cps_realize;
 195     device_class_set_props(dc, mips_cps_properties);
 196 }
 197
 198 static const TypeInfo mips_cps_info = {
 199     .name = TYPE_MIPS_CPS,
 200     .parent = TYPE_SYS_BUS_DEVICE,
 201     .instance_size = sizeof(MIPSCPSState),
 202     .instance_init = mips_cps_init,
 203     .class_init = mips_cps_class_init,
 204 };
 205
 206 static void mips_cps_register_types(void)
 207 {
 208     type_register_static(&mips_cps_info);
 209 }
 210
 211 type_init(mips_cps_register_types)