4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
30 static void alpha_cpu_set_pc(CPUState
*cs
, vaddr value
)
32 AlphaCPU
*cpu
= ALPHA_CPU(cs
);
37 static bool alpha_cpu_has_work(CPUState
*cs
)
39 /* Here we are checking to see if the CPU should wake up from HALT.
40 We will have gotten into this state only for WTINT from PALmode. */
41 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
42 asleep even if (some) interrupts have been asserted. For now,
43 assume that if a CPU really wants to stay asleep, it will mask
44 interrupts at the chipset level, which will prevent these bits
45 from being set in the first place. */
46 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
49 | CPU_INTERRUPT_MCHK
);
52 static void alpha_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
54 info
->mach
= bfd_mach_alpha_ev6
;
55 info
->print_insn
= print_insn_alpha
;
58 static void alpha_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
60 CPUState
*cs
= CPU(dev
);
61 AlphaCPUClass
*acc
= ALPHA_CPU_GET_CLASS(dev
);
62 Error
*local_err
= NULL
;
64 cpu_exec_realizefn(cs
, &local_err
);
65 if (local_err
!= NULL
) {
66 error_propagate(errp
, local_err
);
72 acc
->parent_realize(dev
, errp
);
75 static void alpha_cpu_list_entry(gpointer data
, gpointer user_data
)
77 ObjectClass
*oc
= data
;
79 qemu_printf(" %s\n", object_class_get_name(oc
));
82 void alpha_cpu_list(void)
86 list
= object_class_get_list_sorted(TYPE_ALPHA_CPU
, false);
87 qemu_printf("Available CPUs:\n");
88 g_slist_foreach(list
, alpha_cpu_list_entry
, NULL
);
93 typedef struct AlphaCPUAlias
{
98 static const AlphaCPUAlias alpha_cpu_aliases
[] = {
99 { "21064", ALPHA_CPU_TYPE_NAME("ev4") },
100 { "21164", ALPHA_CPU_TYPE_NAME("ev5") },
101 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") },
102 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
103 { "21264", ALPHA_CPU_TYPE_NAME("ev6") },
104 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") },
107 static ObjectClass
*alpha_cpu_class_by_name(const char *cpu_model
)
113 oc
= object_class_by_name(cpu_model
);
114 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_ALPHA_CPU
) != NULL
&&
115 !object_class_is_abstract(oc
)) {
119 for (i
= 0; i
< ARRAY_SIZE(alpha_cpu_aliases
); i
++) {
120 if (strcmp(cpu_model
, alpha_cpu_aliases
[i
].alias
) == 0) {
121 oc
= object_class_by_name(alpha_cpu_aliases
[i
].typename
);
122 assert(oc
!= NULL
&& !object_class_is_abstract(oc
));
127 typename
= g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model
);
128 oc
= object_class_by_name(typename
);
130 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
134 /* TODO: remove match everything nonsense */
135 /* Default to ev67; no reason not to emulate insns by default. */
137 oc
= object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
143 static void ev4_cpu_initfn(Object
*obj
)
145 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
146 CPUAlphaState
*env
= &cpu
->env
;
148 env
->implver
= IMPLVER_2106x
;
151 static void ev5_cpu_initfn(Object
*obj
)
153 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
154 CPUAlphaState
*env
= &cpu
->env
;
156 env
->implver
= IMPLVER_21164
;
159 static void ev56_cpu_initfn(Object
*obj
)
161 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
162 CPUAlphaState
*env
= &cpu
->env
;
164 env
->amask
|= AMASK_BWX
;
167 static void pca56_cpu_initfn(Object
*obj
)
169 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
170 CPUAlphaState
*env
= &cpu
->env
;
172 env
->amask
|= AMASK_MVI
;
175 static void ev6_cpu_initfn(Object
*obj
)
177 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
178 CPUAlphaState
*env
= &cpu
->env
;
180 env
->implver
= IMPLVER_21264
;
181 env
->amask
= AMASK_BWX
| AMASK_FIX
| AMASK_MVI
| AMASK_TRAP
;
184 static void ev67_cpu_initfn(Object
*obj
)
186 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
187 CPUAlphaState
*env
= &cpu
->env
;
189 env
->amask
|= AMASK_CIX
| AMASK_PREFETCH
;
192 static void alpha_cpu_initfn(Object
*obj
)
194 CPUState
*cs
= CPU(obj
);
195 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
196 CPUAlphaState
*env
= &cpu
->env
;
201 #if defined(CONFIG_USER_ONLY)
202 env
->flags
= ENV_FLAG_PS_USER
| ENV_FLAG_FEN
;
203 cpu_alpha_store_fpcr(env
, (uint64_t)(FPCR_INVD
| FPCR_DZED
| FPCR_OVFD
204 | FPCR_UNFD
| FPCR_INED
| FPCR_DNOD
205 | FPCR_DYN_NORMAL
) << 32);
207 env
->flags
= ENV_FLAG_PAL_MODE
| ENV_FLAG_FEN
;
211 static void alpha_cpu_class_init(ObjectClass
*oc
, void *data
)
213 DeviceClass
*dc
= DEVICE_CLASS(oc
);
214 CPUClass
*cc
= CPU_CLASS(oc
);
215 AlphaCPUClass
*acc
= ALPHA_CPU_CLASS(oc
);
217 device_class_set_parent_realize(dc
, alpha_cpu_realizefn
,
218 &acc
->parent_realize
);
220 cc
->class_by_name
= alpha_cpu_class_by_name
;
221 cc
->has_work
= alpha_cpu_has_work
;
222 cc
->do_interrupt
= alpha_cpu_do_interrupt
;
223 cc
->cpu_exec_interrupt
= alpha_cpu_exec_interrupt
;
224 cc
->dump_state
= alpha_cpu_dump_state
;
225 cc
->set_pc
= alpha_cpu_set_pc
;
226 cc
->gdb_read_register
= alpha_cpu_gdb_read_register
;
227 cc
->gdb_write_register
= alpha_cpu_gdb_write_register
;
228 #ifdef CONFIG_USER_ONLY
229 cc
->handle_mmu_fault
= alpha_cpu_handle_mmu_fault
;
231 cc
->do_transaction_failed
= alpha_cpu_do_transaction_failed
;
232 cc
->do_unaligned_access
= alpha_cpu_do_unaligned_access
;
233 cc
->get_phys_page_debug
= alpha_cpu_get_phys_page_debug
;
234 dc
->vmsd
= &vmstate_alpha_cpu
;
236 cc
->disas_set_info
= alpha_cpu_disas_set_info
;
237 cc
->tcg_initialize
= alpha_translate_init
;
239 cc
->gdb_num_core_regs
= 67;
242 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
244 .parent = base_type, \
245 .instance_init = initfn, \
246 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \
249 static const TypeInfo alpha_cpu_type_infos
[] = {
251 .name
= TYPE_ALPHA_CPU
,
253 .instance_size
= sizeof(AlphaCPU
),
254 .instance_init
= alpha_cpu_initfn
,
256 .class_size
= sizeof(AlphaCPUClass
),
257 .class_init
= alpha_cpu_class_init
,
259 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev4", ev4_cpu_initfn
),
260 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev5", ev5_cpu_initfn
),
261 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn
),
262 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
264 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev6", ev6_cpu_initfn
),
265 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn
),
266 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL
),
269 DEFINE_TYPES(alpha_cpu_type_infos
)