Support default block interfaces per QEMUMachine
[qemu/ar7.git] / hw / spapr.h
blobefe7f5758fc675b8bdbdca30ceb41f740e871203
1 #if !defined(__HW_SPAPR_H__)
2 #define __HW_SPAPR_H__
4 #include "dma.h"
5 #include "hw/xics.h"
7 struct VIOsPAPRBus;
8 struct sPAPRPHBState;
9 struct icp_state;
11 typedef struct sPAPREnvironment {
12 struct VIOsPAPRBus *vio_bus;
13 QLIST_HEAD(, sPAPRPHBState) phbs;
14 struct icp_state *icp;
16 hwaddr ram_limit;
17 void *htab;
18 long htab_shift;
19 hwaddr rma_size;
20 int vrma_adjust;
21 hwaddr fdt_addr, rtas_addr;
22 long rtas_size;
23 void *fdt_skel;
24 target_ulong entry_point;
25 int next_irq;
26 int rtc_offset;
27 char *cpu_model;
28 bool has_graphics;
30 uint32_t epow_irq;
31 Notifier epow_notifier;
32 } sPAPREnvironment;
34 #define H_SUCCESS 0
35 #define H_BUSY 1 /* Hardware busy -- retry later */
36 #define H_CLOSED 2 /* Resource closed */
37 #define H_NOT_AVAILABLE 3
38 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
39 #define H_PARTIAL 5
40 #define H_IN_PROGRESS 14 /* Kind of like busy */
41 #define H_PAGE_REGISTERED 15
42 #define H_PARTIAL_STORE 16
43 #define H_PENDING 17 /* returned from H_POLL_PENDING */
44 #define H_CONTINUE 18 /* Returned from H_Join on success */
45 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
46 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
47 is a good time to retry */
48 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
49 is a good time to retry */
50 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
51 is a good time to retry */
52 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
53 is a good time to retry */
54 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
55 is a good time to retry */
56 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
57 is a good time to retry */
58 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
59 #define H_HARDWARE -1 /* Hardware error */
60 #define H_FUNCTION -2 /* Function not supported */
61 #define H_PRIVILEGE -3 /* Caller not privileged */
62 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
63 #define H_BAD_MODE -5 /* Illegal msr value */
64 #define H_PTEG_FULL -6 /* PTEG is full */
65 #define H_NOT_FOUND -7 /* PTE was not found" */
66 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
67 #define H_NO_MEM -9
68 #define H_AUTHORITY -10
69 #define H_PERMISSION -11
70 #define H_DROPPED -12
71 #define H_SOURCE_PARM -13
72 #define H_DEST_PARM -14
73 #define H_REMOTE_PARM -15
74 #define H_RESOURCE -16
75 #define H_ADAPTER_PARM -17
76 #define H_RH_PARM -18
77 #define H_RCQ_PARM -19
78 #define H_SCQ_PARM -20
79 #define H_EQ_PARM -21
80 #define H_RT_PARM -22
81 #define H_ST_PARM -23
82 #define H_SIGT_PARM -24
83 #define H_TOKEN_PARM -25
84 #define H_MLENGTH_PARM -27
85 #define H_MEM_PARM -28
86 #define H_MEM_ACCESS_PARM -29
87 #define H_ATTR_PARM -30
88 #define H_PORT_PARM -31
89 #define H_MCG_PARM -32
90 #define H_VL_PARM -33
91 #define H_TSIZE_PARM -34
92 #define H_TRACE_PARM -35
94 #define H_MASK_PARM -37
95 #define H_MCG_FULL -38
96 #define H_ALIAS_EXIST -39
97 #define H_P_COUNTER -40
98 #define H_TABLE_FULL -41
99 #define H_ALT_TABLE -42
100 #define H_MR_CONDITION -43
101 #define H_NOT_ENOUGH_RESOURCES -44
102 #define H_R_STATE -45
103 #define H_RESCINDEND -46
104 #define H_MULTI_THREADS_ACTIVE -9005
107 /* Long Busy is a condition that can be returned by the firmware
108 * when a call cannot be completed now, but the identical call
109 * should be retried later. This prevents calls blocking in the
110 * firmware for long periods of time. Annoyingly the firmware can return
111 * a range of return codes, hinting at how long we should wait before
112 * retrying. If you don't care for the hint, the macro below is a good
113 * way to check for the long_busy return codes
115 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
116 && (x <= H_LONG_BUSY_END_RANGE))
118 /* Flags */
119 #define H_LARGE_PAGE (1ULL<<(63-16))
120 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
121 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
122 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
123 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
124 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
125 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
126 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
127 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
128 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
129 #define H_ANDCOND (1ULL<<(63-33))
130 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
131 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
132 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
133 #define H_COPY_PAGE (1ULL<<(63-49))
134 #define H_N (1ULL<<(63-61))
135 #define H_PP1 (1ULL<<(63-62))
136 #define H_PP2 (1ULL<<(63-63))
138 /* VASI States */
139 #define H_VASI_INVALID 0
140 #define H_VASI_ENABLED 1
141 #define H_VASI_ABORTED 2
142 #define H_VASI_SUSPENDING 3
143 #define H_VASI_SUSPENDED 4
144 #define H_VASI_RESUMED 5
145 #define H_VASI_COMPLETED 6
147 /* DABRX flags */
148 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
149 #define H_DABRX_KERNEL (1ULL<<(63-62))
150 #define H_DABRX_USER (1ULL<<(63-63))
152 /* Each control block has to be on a 4K boundary */
153 #define H_CB_ALIGNMENT 4096
155 /* pSeries hypervisor opcodes */
156 #define H_REMOVE 0x04
157 #define H_ENTER 0x08
158 #define H_READ 0x0c
159 #define H_CLEAR_MOD 0x10
160 #define H_CLEAR_REF 0x14
161 #define H_PROTECT 0x18
162 #define H_GET_TCE 0x1c
163 #define H_PUT_TCE 0x20
164 #define H_SET_SPRG0 0x24
165 #define H_SET_DABR 0x28
166 #define H_PAGE_INIT 0x2c
167 #define H_SET_ASR 0x30
168 #define H_ASR_ON 0x34
169 #define H_ASR_OFF 0x38
170 #define H_LOGICAL_CI_LOAD 0x3c
171 #define H_LOGICAL_CI_STORE 0x40
172 #define H_LOGICAL_CACHE_LOAD 0x44
173 #define H_LOGICAL_CACHE_STORE 0x48
174 #define H_LOGICAL_ICBI 0x4c
175 #define H_LOGICAL_DCBF 0x50
176 #define H_GET_TERM_CHAR 0x54
177 #define H_PUT_TERM_CHAR 0x58
178 #define H_REAL_TO_LOGICAL 0x5c
179 #define H_HYPERVISOR_DATA 0x60
180 #define H_EOI 0x64
181 #define H_CPPR 0x68
182 #define H_IPI 0x6c
183 #define H_IPOLL 0x70
184 #define H_XIRR 0x74
185 #define H_PERFMON 0x7c
186 #define H_MIGRATE_DMA 0x78
187 #define H_REGISTER_VPA 0xDC
188 #define H_CEDE 0xE0
189 #define H_CONFER 0xE4
190 #define H_PROD 0xE8
191 #define H_GET_PPP 0xEC
192 #define H_SET_PPP 0xF0
193 #define H_PURR 0xF4
194 #define H_PIC 0xF8
195 #define H_REG_CRQ 0xFC
196 #define H_FREE_CRQ 0x100
197 #define H_VIO_SIGNAL 0x104
198 #define H_SEND_CRQ 0x108
199 #define H_COPY_RDMA 0x110
200 #define H_REGISTER_LOGICAL_LAN 0x114
201 #define H_FREE_LOGICAL_LAN 0x118
202 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
203 #define H_SEND_LOGICAL_LAN 0x120
204 #define H_BULK_REMOVE 0x124
205 #define H_MULTICAST_CTRL 0x130
206 #define H_SET_XDABR 0x134
207 #define H_STUFF_TCE 0x138
208 #define H_PUT_TCE_INDIRECT 0x13C
209 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
210 #define H_VTERM_PARTNER_INFO 0x150
211 #define H_REGISTER_VTERM 0x154
212 #define H_FREE_VTERM 0x158
213 #define H_RESET_EVENTS 0x15C
214 #define H_ALLOC_RESOURCE 0x160
215 #define H_FREE_RESOURCE 0x164
216 #define H_MODIFY_QP 0x168
217 #define H_QUERY_QP 0x16C
218 #define H_REREGISTER_PMR 0x170
219 #define H_REGISTER_SMR 0x174
220 #define H_QUERY_MR 0x178
221 #define H_QUERY_MW 0x17C
222 #define H_QUERY_HCA 0x180
223 #define H_QUERY_PORT 0x184
224 #define H_MODIFY_PORT 0x188
225 #define H_DEFINE_AQP1 0x18C
226 #define H_GET_TRACE_BUFFER 0x190
227 #define H_DEFINE_AQP0 0x194
228 #define H_RESIZE_MR 0x198
229 #define H_ATTACH_MCQP 0x19C
230 #define H_DETACH_MCQP 0x1A0
231 #define H_CREATE_RPT 0x1A4
232 #define H_REMOVE_RPT 0x1A8
233 #define H_REGISTER_RPAGES 0x1AC
234 #define H_DISABLE_AND_GETC 0x1B0
235 #define H_ERROR_DATA 0x1B4
236 #define H_GET_HCA_INFO 0x1B8
237 #define H_GET_PERF_COUNT 0x1BC
238 #define H_MANAGE_TRACE 0x1C0
239 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
240 #define H_QUERY_INT_STATE 0x1E4
241 #define H_POLL_PENDING 0x1D8
242 #define H_ILLAN_ATTRIBUTES 0x244
243 #define H_MODIFY_HEA_QP 0x250
244 #define H_QUERY_HEA_QP 0x254
245 #define H_QUERY_HEA 0x258
246 #define H_QUERY_HEA_PORT 0x25C
247 #define H_MODIFY_HEA_PORT 0x260
248 #define H_REG_BCMC 0x264
249 #define H_DEREG_BCMC 0x268
250 #define H_REGISTER_HEA_RPAGES 0x26C
251 #define H_DISABLE_AND_GET_HEA 0x270
252 #define H_GET_HEA_INFO 0x274
253 #define H_ALLOC_HEA_RESOURCE 0x278
254 #define H_ADD_CONN 0x284
255 #define H_DEL_CONN 0x288
256 #define H_JOIN 0x298
257 #define H_VASI_STATE 0x2A4
258 #define H_ENABLE_CRQ 0x2B0
259 #define H_GET_EM_PARMS 0x2B8
260 #define H_SET_MPP 0x2D0
261 #define H_GET_MPP 0x2D4
262 #define MAX_HCALL_OPCODE H_GET_MPP
264 /* The hcalls above are standardized in PAPR and implemented by pHyp
265 * as well.
267 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
268 * So far we just need one for H_RTAS, but in future we'll need more
269 * for extensions like virtio. We put those into the 0xf000-0xfffc
270 * range which is reserved by PAPR for "platform-specific" hcalls.
272 #define KVMPPC_HCALL_BASE 0xf000
273 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
274 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
275 #define KVMPPC_HCALL_MAX KVMPPC_H_LOGICAL_MEMOP
277 extern sPAPREnvironment *spapr;
279 /*#define DEBUG_SPAPR_HCALLS*/
281 #ifdef DEBUG_SPAPR_HCALLS
282 #define hcall_dprintf(fmt, ...) \
283 do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0)
284 #else
285 #define hcall_dprintf(fmt, ...) \
286 do { } while (0)
287 #endif
289 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr,
290 target_ulong opcode,
291 target_ulong *args);
293 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
294 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
295 target_ulong *args);
297 int spapr_allocate_irq(int hint, bool lsi);
298 int spapr_allocate_irq_block(int num, bool lsi);
300 static inline int spapr_allocate_msi(int hint)
302 return spapr_allocate_irq(hint, false);
305 static inline int spapr_allocate_lsi(int hint)
307 return spapr_allocate_irq(hint, true);
310 static inline uint32_t rtas_ld(target_ulong phys, int n)
312 return ldl_be_phys(phys + 4*n);
315 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
317 stl_be_phys(phys + 4*n, val);
320 typedef void (*spapr_rtas_fn)(sPAPREnvironment *spapr, uint32_t token,
321 uint32_t nargs, target_ulong args,
322 uint32_t nret, target_ulong rets);
323 void spapr_rtas_register(const char *name, spapr_rtas_fn fn);
324 target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
325 uint32_t token, uint32_t nargs, target_ulong args,
326 uint32_t nret, target_ulong rets);
327 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
328 hwaddr rtas_size);
330 #define SPAPR_TCE_PAGE_SHIFT 12
331 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
332 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
334 typedef struct sPAPRTCE {
335 uint64_t tce;
336 } sPAPRTCE;
338 #define SPAPR_VIO_BASE_LIOBN 0x00000000
339 #define SPAPR_PCI_BASE_LIOBN 0x80000000
341 #define RTAS_ERROR_LOG_MAX 2048
344 void spapr_iommu_init(void);
345 void spapr_events_init(sPAPREnvironment *spapr);
346 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
347 DMAContext *spapr_tce_new_dma_context(uint32_t liobn, size_t window_size);
348 void spapr_tce_free(DMAContext *dma);
349 void spapr_tce_reset(DMAContext *dma);
350 void spapr_tce_set_bypass(DMAContext *dma, bool bypass);
351 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
352 uint32_t liobn, uint64_t window, uint32_t size);
353 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
354 DMAContext *dma);
356 #endif /* !defined (__HW_SPAPR_H__) */