target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "mmu-hash64.h"
  25
  26 //#define DEBUG_MMU
  27 //#define DEBUG_SLB
  28
  29 #ifdef DEBUG_MMU
  30 #  define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
  31 #else
  32 #  define LOG_MMU_STATE(cpu) do { } while (0)
  33 #endif
  34
  35 #ifdef DEBUG_SLB
  36 #  define LOG_SLB(...) qemu_log(__VA_ARGS__)
  37 #else
  38 #  define LOG_SLB(...) do { } while (0)
  39 #endif
  40
  41 /*
  42  * Used to indicate whether we have allocated htab in the
  43  * host kernel
  44  */
  45 bool kvmppc_kern_htab;
  46 /*
  47  * SLB handling
  48  */
  49
  50 static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
  51 {
  52     uint64_t esid_256M, esid_1T;
  53     int n;
  54
  55     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  56
  57     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  58     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  59
  60     for (n = 0; n < env->slb_nr; n++) {
  61         ppc_slb_t *slb = &env->slb[n];
  62
  63         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  64                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  65         /* We check for 1T matches on all MMUs here - if the MMU
  66          * doesn't have 1T segment support, we will have prevented 1T
  67          * entries from being inserted in the slbmte code. */
  68         if (((slb->esid == esid_256M) &&
  69              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  70             || ((slb->esid == esid_1T) &&
  71                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  72             return slb;
  73         }
  74     }
  75
  76     return NULL;
  77 }
  78
  79 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
  80 {
  81     int i;
  82     uint64_t slbe, slbv;
  83
  84     cpu_synchronize_state(CPU(ppc_env_get_cpu(env)));
  85
  86     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  87     for (i = 0; i < env->slb_nr; i++) {
  88         slbe = env->slb[i].esid;
  89         slbv = env->slb[i].vsid;
  90         if (slbe == 0 && slbv == 0) {
  91             continue;
  92         }
  93         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  94                     i, slbe, slbv);
  95     }
  96 }
  97
  98 void helper_slbia(CPUPPCState *env)
  99 {
 100     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 101     int n, do_invalidate;
 102
 103     do_invalidate = 0;
 104     /* XXX: Warning: slbia never invalidates the first segment */
 105     for (n = 1; n < env->slb_nr; n++) {
 106         ppc_slb_t *slb = &env->slb[n];
 107
 108         if (slb->esid & SLB_ESID_V) {
 109             slb->esid &= ~SLB_ESID_V;
 110             /* XXX: given the fact that segment size is 256 MB or 1TB,
 111              *      and we still don't have a tlb_flush_mask(env, n, mask)
 112              *      in QEMU, we just invalidate all TLBs
 113              */
 114             do_invalidate = 1;
 115         }
 116     }
 117     if (do_invalidate) {
 118         tlb_flush(CPU(cpu), 1);
 119     }
 120 }
 121
 122 void helper_slbie(CPUPPCState *env, target_ulong addr)
 123 {
 124     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 125     ppc_slb_t *slb;
 126
 127     slb = slb_lookup(env, addr);
 128     if (!slb) {
 129         return;
 130     }
 131
 132     if (slb->esid & SLB_ESID_V) {
 133         slb->esid &= ~SLB_ESID_V;
 134
 135         /* XXX: given the fact that segment size is 256 MB or 1TB,
 136          *      and we still don't have a tlb_flush_mask(env, n, mask)
 137          *      in QEMU, we just invalidate all TLBs
 138          */
 139         tlb_flush(CPU(cpu), 1);
 140     }
 141 }
 142
 143 int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 144 {
 145     int slot = rb & 0xfff;
 146     ppc_slb_t *slb = &env->slb[slot];
 147
 148     if (rb & (0x1000 - env->slb_nr)) {
 149         return -1; /* Reserved bits set or slot too high */
 150     }
 151     if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 152         return -1; /* Bad segment size */
 153     }
 154     if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 155         return -1; /* 1T segment on MMU that doesn't support it */
 156     }
 157
 158     /* Mask out the slot number as we store the entry */
 159     slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
 160     slb->vsid = rs;
 161
 162     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 163             " %016" PRIx64 "\n", __func__, slot, rb, rs,
 164             slb->esid, slb->vsid);
 165
 166     return 0;
 167 }
 168
 169 static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
 170                              target_ulong *rt)
 171 {
 172     int slot = rb & 0xfff;
 173     ppc_slb_t *slb = &env->slb[slot];
 174
 175     if (slot >= env->slb_nr) {
 176         return -1;
 177     }
 178
 179     *rt = slb->esid;
 180     return 0;
 181 }
 182
 183 static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
 184                              target_ulong *rt)
 185 {
 186     int slot = rb & 0xfff;
 187     ppc_slb_t *slb = &env->slb[slot];
 188
 189     if (slot >= env->slb_nr) {
 190         return -1;
 191     }
 192
 193     *rt = slb->vsid;
 194     return 0;
 195 }
 196
 197 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 198 {
 199     if (ppc_store_slb(env, rb, rs) < 0) {
 200         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 201                                    POWERPC_EXCP_INVAL);
 202     }
 203 }
 204
 205 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 206 {
 207     target_ulong rt = 0;
 208
 209     if (ppc_load_slb_esid(env, rb, &rt) < 0) {
 210         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 211                                    POWERPC_EXCP_INVAL);
 212     }
 213     return rt;
 214 }
 215
 216 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 217 {
 218     target_ulong rt = 0;
 219
 220     if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
 221         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 222                                    POWERPC_EXCP_INVAL);
 223     }
 224     return rt;
 225 }
 226
 227 /*
 228  * 64-bit hash table MMU handling
 229  */
 230
 231 static int ppc_hash64_pte_prot(CPUPPCState *env,
 232                                ppc_slb_t *slb, ppc_hash_pte64_t pte)
 233 {
 234     unsigned pp, key;
 235     /* Some pp bit combinations have undefined behaviour, so default
 236      * to no access in those cases */
 237     int prot = 0;
 238
 239     key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 240              : (slb->vsid & SLB_VSID_KS));
 241     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 242
 243     if (key == 0) {
 244         switch (pp) {
 245         case 0x0:
 246         case 0x1:
 247         case 0x2:
 248             prot = PAGE_READ | PAGE_WRITE;
 249             break;
 250
 251         case 0x3:
 252         case 0x6:
 253             prot = PAGE_READ;
 254             break;
 255         }
 256     } else {
 257         switch (pp) {
 258         case 0x0:
 259         case 0x6:
 260             prot = 0;
 261             break;
 262
 263         case 0x1:
 264         case 0x3:
 265             prot = PAGE_READ;
 266             break;
 267
 268         case 0x2:
 269             prot = PAGE_READ | PAGE_WRITE;
 270             break;
 271         }
 272     }
 273
 274     /* No execute if either noexec or guarded bits set */
 275     if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
 276         || (slb->vsid & SLB_VSID_N)) {
 277         prot |= PAGE_EXEC;
 278     }
 279
 280     return prot;
 281 }
 282
 283 static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
 284 {
 285     int key, amrbits;
 286     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 287
 288
 289     /* Only recent MMUs implement Virtual Page Class Key Protection */
 290     if (!(env->mmu_model & POWERPC_MMU_AMR)) {
 291         return prot;
 292     }
 293
 294     key = HPTE64_R_KEY(pte.pte1);
 295     amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
 296
 297     /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
 298     /*         env->spr[SPR_AMR]); */
 299
 300     /*
 301      * A store is permitted if the AMR bit is 0. Remove write
 302      * protection if it is set.
 303      */
 304     if (amrbits & 0x2) {
 305         prot &= ~PAGE_WRITE;
 306     }
 307     /*
 308      * A load is permitted if the AMR bit is 0. Remove read
 309      * protection if it is set.
 310      */
 311     if (amrbits & 0x1) {
 312         prot &= ~PAGE_READ;
 313     }
 314
 315     return prot;
 316 }
 317
 318 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
 319 {
 320     uint64_t token = 0;
 321     hwaddr pte_offset;
 322
 323     pte_offset = pte_index * HASH_PTE_SIZE_64;
 324     if (kvmppc_kern_htab) {
 325         /*
 326          * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
 327          */
 328         token = kvmppc_hash64_read_pteg(cpu, pte_index);
 329         if (token) {
 330             return token;
 331         }
 332         /*
 333          * pteg read failed, even though we have allocated htab via
 334          * kvmppc_reset_htab.
 335          */
 336         return 0;
 337     }
 338     /*
 339      * HTAB is controlled by QEMU. Just point to the internally
 340      * accessible PTEG.
 341      */
 342     if (cpu->env.external_htab) {
 343         token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
 344     } else if (cpu->env.htab_base) {
 345         token = cpu->env.htab_base + pte_offset;
 346     }
 347     return token;
 348 }
 349
 350 void ppc_hash64_stop_access(uint64_t token)
 351 {
 352     if (kvmppc_kern_htab) {
 353         kvmppc_hash64_free_pteg(token);
 354     }
 355 }
 356
 357 static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr hash,
 358                                      bool secondary, target_ulong ptem,
 359                                      ppc_hash_pte64_t *pte)
 360 {
 361     int i;
 362     uint64_t token;
 363     target_ulong pte0, pte1;
 364     target_ulong pte_index;
 365
 366     pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
 367     token = ppc_hash64_start_access(ppc_env_get_cpu(env), pte_index);
 368     if (!token) {
 369         return -1;
 370     }
 371     for (i = 0; i < HPTES_PER_GROUP; i++) {
 372         pte0 = ppc_hash64_load_hpte0(env, token, i);
 373         pte1 = ppc_hash64_load_hpte1(env, token, i);
 374
 375         if ((pte0 & HPTE64_V_VALID)
 376             && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
 377             && HPTE64_V_COMPARE(pte0, ptem)) {
 378             pte->pte0 = pte0;
 379             pte->pte1 = pte1;
 380             ppc_hash64_stop_access(token);
 381             return (pte_index + i) * HASH_PTE_SIZE_64;
 382         }
 383     }
 384     ppc_hash64_stop_access(token);
 385     /*
 386      * We didn't find a valid entry.
 387      */
 388     return -1;
 389 }
 390
 391 static uint64_t ppc_hash64_page_shift(ppc_slb_t *slb)
 392 {
 393     uint64_t epnshift;
 394
 395     /* Page size according to the SLB, which we use to generate the
 396      * EPN for hash table lookup..  When we implement more recent MMU
 397      * extensions this might be different from the actual page size
 398      * encoded in the PTE */
 399     if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_4K) {
 400         epnshift = TARGET_PAGE_BITS;
 401     } else if ((slb->vsid & SLB_VSID_LLP_MASK) == SLB_VSID_64K) {
 402         epnshift = TARGET_PAGE_BITS_64K;
 403     } else {
 404         epnshift = TARGET_PAGE_BITS_16M;
 405     }
 406     return epnshift;
 407 }
 408
 409 static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
 410                                      ppc_slb_t *slb, target_ulong eaddr,
 411                                      ppc_hash_pte64_t *pte)
 412 {
 413     hwaddr pte_offset;
 414     hwaddr hash;
 415     uint64_t vsid, epnshift, epnmask, epn, ptem;
 416
 417     epnshift = ppc_hash64_page_shift(slb);
 418     epnmask = ~((1ULL << epnshift) - 1);
 419
 420     if (slb->vsid & SLB_VSID_B) {
 421         /* 1TB segment */
 422         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 423         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 424         hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
 425     } else {
 426         /* 256M segment */
 427         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 428         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 429         hash = vsid ^ (epn >> epnshift);
 430     }
 431     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 432
 433     /* Page address translation */
 434     qemu_log_mask(CPU_LOG_MMU,
 435             "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 436             " hash " TARGET_FMT_plx "\n",
 437             env->htab_base, env->htab_mask, hash);
 438
 439     /* Primary PTEG lookup */
 440     qemu_log_mask(CPU_LOG_MMU,
 441             "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 442             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 443             " hash=" TARGET_FMT_plx "\n",
 444             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 445     pte_offset = ppc_hash64_pteg_search(env, hash, 0, ptem, pte);
 446
 447     if (pte_offset == -1) {
 448         /* Secondary PTEG lookup */
 449         qemu_log_mask(CPU_LOG_MMU,
 450                 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 451                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 452                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 453                 env->htab_mask, vsid, ptem, ~hash);
 454
 455         pte_offset = ppc_hash64_pteg_search(env, ~hash, 1, ptem, pte);
 456     }
 457
 458     return pte_offset;
 459 }
 460
 461 static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
 462                                    target_ulong eaddr)
 463 {
 464     hwaddr mask;
 465     int target_page_bits;
 466     hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
 467     /*
 468      * We support 4K, 64K and 16M now
 469      */
 470     target_page_bits = ppc_hash64_page_shift(slb);
 471     mask = (1ULL << target_page_bits) - 1;
 472     return (rpn & ~mask) | (eaddr & mask);
 473 }
 474
 475 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
 476                                 int rwx, int mmu_idx)
 477 {
 478     CPUState *cs = CPU(cpu);
 479     CPUPPCState *env = &cpu->env;
 480     ppc_slb_t *slb;
 481     hwaddr pte_offset;
 482     ppc_hash_pte64_t pte;
 483     int pp_prot, amr_prot, prot;
 484     uint64_t new_pte1;
 485     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 486     hwaddr raddr;
 487
 488     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 489
 490     /* 1. Handle real mode accesses */
 491     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 492         /* Translation is off */
 493         /* In real mode the top 4 effective address bits are ignored */
 494         raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 495         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 496                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 497                      TARGET_PAGE_SIZE);
 498         return 0;
 499     }
 500
 501     /* 2. Translation is on, so look up the SLB */
 502     slb = slb_lookup(env, eaddr);
 503
 504     if (!slb) {
 505         if (rwx == 2) {
 506             cs->exception_index = POWERPC_EXCP_ISEG;
 507             env->error_code = 0;
 508         } else {
 509             cs->exception_index = POWERPC_EXCP_DSEG;
 510             env->error_code = 0;
 511             env->spr[SPR_DAR] = eaddr;
 512         }
 513         return 1;
 514     }
 515
 516     /* 3. Check for segment level no-execute violation */
 517     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 518         cs->exception_index = POWERPC_EXCP_ISI;
 519         env->error_code = 0x10000000;
 520         return 1;
 521     }
 522
 523     /* 4. Locate the PTE in the hash table */
 524     pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
 525     if (pte_offset == -1) {
 526         if (rwx == 2) {
 527             cs->exception_index = POWERPC_EXCP_ISI;
 528             env->error_code = 0x40000000;
 529         } else {
 530             cs->exception_index = POWERPC_EXCP_DSI;
 531             env->error_code = 0;
 532             env->spr[SPR_DAR] = eaddr;
 533             if (rwx == 1) {
 534                 env->spr[SPR_DSISR] = 0x42000000;
 535             } else {
 536                 env->spr[SPR_DSISR] = 0x40000000;
 537             }
 538         }
 539         return 1;
 540     }
 541     qemu_log_mask(CPU_LOG_MMU,
 542                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 543
 544     /* 5. Check access permissions */
 545
 546     pp_prot = ppc_hash64_pte_prot(env, slb, pte);
 547     amr_prot = ppc_hash64_amr_prot(env, pte);
 548     prot = pp_prot & amr_prot;
 549
 550     if ((need_prot[rwx] & ~prot) != 0) {
 551         /* Access right violation */
 552         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 553         if (rwx == 2) {
 554             cs->exception_index = POWERPC_EXCP_ISI;
 555             env->error_code = 0x08000000;
 556         } else {
 557             target_ulong dsisr = 0;
 558
 559             cs->exception_index = POWERPC_EXCP_DSI;
 560             env->error_code = 0;
 561             env->spr[SPR_DAR] = eaddr;
 562             if (need_prot[rwx] & ~pp_prot) {
 563                 dsisr |= 0x08000000;
 564             }
 565             if (rwx == 1) {
 566                 dsisr |= 0x02000000;
 567             }
 568             if (need_prot[rwx] & ~amr_prot) {
 569                 dsisr |= 0x00200000;
 570             }
 571             env->spr[SPR_DSISR] = dsisr;
 572         }
 573         return 1;
 574     }
 575
 576     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 577
 578     /* 6. Update PTE referenced and changed bits if necessary */
 579
 580     new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
 581     if (rwx == 1) {
 582         new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
 583     } else {
 584         /* Treat the page as read-only for now, so that a later write
 585          * will pass through this function again to set the C bit */
 586         prot &= ~PAGE_WRITE;
 587     }
 588
 589     if (new_pte1 != pte.pte1) {
 590         ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
 591                               pte.pte0, new_pte1);
 592     }
 593
 594     /* 7. Determine the real address from the PTE */
 595
 596     raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
 597
 598     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 599                  prot, mmu_idx, TARGET_PAGE_SIZE);
 600
 601     return 0;
 602 }
 603
 604 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 605 {
 606     ppc_slb_t *slb;
 607     hwaddr pte_offset;
 608     ppc_hash_pte64_t pte;
 609
 610     if (msr_dr == 0) {
 611         /* In real mode the top 4 effective address bits are ignored */
 612         return addr & 0x0FFFFFFFFFFFFFFFULL;
 613     }
 614
 615     slb = slb_lookup(env, addr);
 616     if (!slb) {
 617         return -1;
 618     }
 619
 620     pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
 621     if (pte_offset == -1) {
 622         return -1;
 623     }
 624
 625     return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
 626 }
 627
 628 void ppc_hash64_store_hpte(CPUPPCState *env,
 629                            target_ulong pte_index,
 630                            target_ulong pte0, target_ulong pte1)
 631 {
 632     CPUState *cs = CPU(ppc_env_get_cpu(env));
 633
 634     if (kvmppc_kern_htab) {
 635         kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
 636         return;
 637     }
 638
 639     pte_index *= HASH_PTE_SIZE_64;
 640     if (env->external_htab) {
 641         stq_p(env->external_htab + pte_index, pte0);
 642         stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
 643     } else {
 644         stq_phys(cs->as, env->htab_base + pte_index, pte0);
 645         stq_phys(cs->as, env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
 646     }
 647 }