target/ppc: Fix lxv/stxv MSR facility check
[qemu/ar7.git] / stubs / icount.c
blob9f9a59f55b9150788e925401d0826395f6a3fc0e
1 #include "qemu/osdep.h"
2 #include "qapi/error.h"
3 #include "sysemu/cpu-timers.h"
5 /* icount - Instruction Counter API */
7 ICountMode use_icount = ICOUNT_DISABLED;
9 bool icount_configure(QemuOpts *opts, Error **errp)
11 /* signal error */
12 error_setg(errp, "cannot configure icount, TCG support not available");
14 return false;
16 int64_t icount_get_raw(void)
18 abort();
19 return 0;
21 void icount_start_warp_timer(void)
23 abort();
25 void icount_account_warp_timer(void)
27 abort();
29 void icount_notify_exit(void)
31 abort();