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memory: add owner argument to initialization functions
[qemu/ar7.git] / hw / block / fdc.c
blob1bec805e043a44787f0e0d792044df2c3da5c840
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw/hw.h"
31 #include "hw/block/fdc.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/isa/isa.h"
35 #include "hw/sysbus.h"
36 #include "sysemu/blockdev.h"
37 #include "sysemu/sysemu.h"
38 #include "qemu/log.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 /********************************************************/
52 /* Floppy drive emulation */
53
54 typedef enum FDriveRate {
55 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
56 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
57 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
58 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
59 } FDriveRate;
60
61 typedef struct FDFormat {
62 FDriveType drive;
63 uint8_t last_sect;
64 uint8_t max_track;
65 uint8_t max_head;
66 FDriveRate rate;
67 } FDFormat;
68
69 static const FDFormat fd_formats[] = {
70 /* First entry is default format */
71 /* 1.44 MB 3"1/2 floppy disks */
72 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, },
73 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, },
74 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, },
75 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, },
76 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, },
77 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, },
78 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, },
79 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, },
80 /* 2.88 MB 3"1/2 floppy disks */
81 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, },
82 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, },
83 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, },
84 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, },
85 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, },
86 /* 720 kB 3"1/2 floppy disks */
87 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, },
88 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, },
89 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, },
90 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, },
91 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, },
92 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, },
93 /* 1.2 MB 5"1/4 floppy disks */
94 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, },
95 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, },
96 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, },
97 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, },
98 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, },
99 /* 720 kB 5"1/4 floppy disks */
100 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, },
101 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, },
102 /* 360 kB 5"1/4 floppy disks */
103 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, },
104 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, },
105 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, },
106 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, },
107 /* 320 kB 5"1/4 floppy disks */
108 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, },
109 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, },
110 /* 360 kB must match 5"1/4 better than 3"1/2... */
111 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, },
112 /* end */
113 { FDRIVE_DRV_NONE, -1, -1, 0, 0, },
114 };
115
116 static void pick_geometry(BlockDriverState *bs, int *nb_heads,
117 int *max_track, int *last_sect,
118 FDriveType drive_in, FDriveType *drive,
119 FDriveRate *rate)
120 {
121 const FDFormat *parse;
122 uint64_t nb_sectors, size;
123 int i, first_match, match;
124
125 bdrv_get_geometry(bs, &nb_sectors);
126 match = -1;
127 first_match = -1;
128 for (i = 0; ; i++) {
129 parse = &fd_formats[i];
130 if (parse->drive == FDRIVE_DRV_NONE) {
131 break;
132 }
133 if (drive_in == parse->drive ||
134 drive_in == FDRIVE_DRV_NONE) {
135 size = (parse->max_head + 1) * parse->max_track *
136 parse->last_sect;
137 if (nb_sectors == size) {
138 match = i;
139 break;
140 }
141 if (first_match == -1) {
142 first_match = i;
143 }
144 }
145 }
146 if (match == -1) {
147 if (first_match == -1) {
148 match = 1;
149 } else {
150 match = first_match;
151 }
152 parse = &fd_formats[match];
153 }
154 *nb_heads = parse->max_head + 1;
155 *max_track = parse->max_track;
156 *last_sect = parse->last_sect;
157 *drive = parse->drive;
158 *rate = parse->rate;
159 }
160
161 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
162 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
163
164 /* Will always be a fixed parameter for us */
165 #define FD_SECTOR_LEN 512
166 #define FD_SECTOR_SC 2 /* Sector size code */
167 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
168
169 typedef struct FDCtrl FDCtrl;
170
171 /* Floppy disk drive emulation */
172 typedef enum FDiskFlags {
173 FDISK_DBL_SIDES = 0x01,
174 } FDiskFlags;
175
176 typedef struct FDrive {
177 FDCtrl *fdctrl;
178 BlockDriverState *bs;
179 /* Drive status */
180 FDriveType drive;
181 uint8_t perpendicular; /* 2.88 MB access mode */
182 /* Position */
183 uint8_t head;
184 uint8_t track;
185 uint8_t sect;
186 /* Media */
187 FDiskFlags flags;
188 uint8_t last_sect; /* Nb sector per track */
189 uint8_t max_track; /* Nb of tracks */
190 uint16_t bps; /* Bytes per sector */
191 uint8_t ro; /* Is read-only */
192 uint8_t media_changed; /* Is media changed */
193 uint8_t media_rate; /* Data rate of medium */
194 } FDrive;
195
196 static void fd_init(FDrive *drv)
197 {
198 /* Drive */
199 drv->drive = FDRIVE_DRV_NONE;
200 drv->perpendicular = 0;
201 /* Disk */
202 drv->last_sect = 0;
203 drv->max_track = 0;
204 }
205
206 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
207
208 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
209 uint8_t last_sect, uint8_t num_sides)
210 {
211 return (((track * num_sides) + head) * last_sect) + sect - 1;
212 }
213
214 /* Returns current position, in sectors, for given drive */
215 static int fd_sector(FDrive *drv)
216 {
217 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
218 NUM_SIDES(drv));
219 }
220
221 /* Seek to a new position:
222 * returns 0 if already on right track
223 * returns 1 if track changed
224 * returns 2 if track is invalid
225 * returns 3 if sector is invalid
226 * returns 4 if seek is disabled
227 */
228 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
229 int enable_seek)
230 {
231 uint32_t sector;
232 int ret;
233
234 if (track > drv->max_track ||
235 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
236 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
237 head, track, sect, 1,
238 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
239 drv->max_track, drv->last_sect);
240 return 2;
241 }
242 if (sect > drv->last_sect) {
243 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
244 head, track, sect, 1,
245 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
246 drv->max_track, drv->last_sect);
247 return 3;
248 }
249 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
250 ret = 0;
251 if (sector != fd_sector(drv)) {
252 #if 0
253 if (!enable_seek) {
254 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
255 " (max=%d %02x %02x)\n",
256 head, track, sect, 1, drv->max_track,
257 drv->last_sect);
258 return 4;
259 }
260 #endif
261 drv->head = head;
262 if (drv->track != track) {
263 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
264 drv->media_changed = 0;
265 }
266 ret = 1;
267 }
268 drv->track = track;
269 drv->sect = sect;
270 }
271
272 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) {
273 ret = 2;
274 }
275
276 return ret;
277 }
278
279 /* Set drive back to track 0 */
280 static void fd_recalibrate(FDrive *drv)
281 {
282 FLOPPY_DPRINTF("recalibrate\n");
283 fd_seek(drv, 0, 0, 1, 1);
284 }
285
286 /* Revalidate a disk drive after a disk change */
287 static void fd_revalidate(FDrive *drv)
288 {
289 int nb_heads, max_track, last_sect, ro;
290 FDriveType drive;
291 FDriveRate rate;
292
293 FLOPPY_DPRINTF("revalidate\n");
294 if (drv->bs != NULL) {
295 ro = bdrv_is_read_only(drv->bs);
296 pick_geometry(drv->bs, &nb_heads, &max_track,
297 &last_sect, drv->drive, &drive, &rate);
298 if (!bdrv_is_inserted(drv->bs)) {
299 FLOPPY_DPRINTF("No disk in drive\n");
300 } else {
301 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
302 max_track, last_sect, ro ? "ro" : "rw");
303 }
304 if (nb_heads == 1) {
305 drv->flags &= ~FDISK_DBL_SIDES;
306 } else {
307 drv->flags |= FDISK_DBL_SIDES;
308 }
309 drv->max_track = max_track;
310 drv->last_sect = last_sect;
311 drv->ro = ro;
312 drv->drive = drive;
313 drv->media_rate = rate;
314 } else {
315 FLOPPY_DPRINTF("No drive connected\n");
316 drv->last_sect = 0;
317 drv->max_track = 0;
318 drv->flags &= ~FDISK_DBL_SIDES;
319 }
320 }
321
322 /********************************************************/
323 /* Intel 82078 floppy disk controller emulation */
324
325 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
326 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
327 static int fdctrl_transfer_handler (void *opaque, int nchan,
328 int dma_pos, int dma_len);
329 static void fdctrl_raise_irq(FDCtrl *fdctrl);
330 static FDrive *get_cur_drv(FDCtrl *fdctrl);
331
332 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
333 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
334 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
335 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
336 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
337 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
338 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
339 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
340 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
341 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
342 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
343 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
344
345 enum {
346 FD_DIR_WRITE = 0,
347 FD_DIR_READ = 1,
348 FD_DIR_SCANE = 2,
349 FD_DIR_SCANL = 3,
350 FD_DIR_SCANH = 4,
351 FD_DIR_VERIFY = 5,
352 };
353
354 enum {
355 FD_STATE_MULTI = 0x01, /* multi track flag */
356 FD_STATE_FORMAT = 0x02, /* format flag */
357 };
358
359 enum {
360 FD_REG_SRA = 0x00,
361 FD_REG_SRB = 0x01,
362 FD_REG_DOR = 0x02,
363 FD_REG_TDR = 0x03,
364 FD_REG_MSR = 0x04,
365 FD_REG_DSR = 0x04,
366 FD_REG_FIFO = 0x05,
367 FD_REG_DIR = 0x07,
368 FD_REG_CCR = 0x07,
369 };
370
371 enum {
372 FD_CMD_READ_TRACK = 0x02,
373 FD_CMD_SPECIFY = 0x03,
374 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
375 FD_CMD_WRITE = 0x05,
376 FD_CMD_READ = 0x06,
377 FD_CMD_RECALIBRATE = 0x07,
378 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
379 FD_CMD_WRITE_DELETED = 0x09,
380 FD_CMD_READ_ID = 0x0a,
381 FD_CMD_READ_DELETED = 0x0c,
382 FD_CMD_FORMAT_TRACK = 0x0d,
383 FD_CMD_DUMPREG = 0x0e,
384 FD_CMD_SEEK = 0x0f,
385 FD_CMD_VERSION = 0x10,
386 FD_CMD_SCAN_EQUAL = 0x11,
387 FD_CMD_PERPENDICULAR_MODE = 0x12,
388 FD_CMD_CONFIGURE = 0x13,
389 FD_CMD_LOCK = 0x14,
390 FD_CMD_VERIFY = 0x16,
391 FD_CMD_POWERDOWN_MODE = 0x17,
392 FD_CMD_PART_ID = 0x18,
393 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
394 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
395 FD_CMD_SAVE = 0x2e,
396 FD_CMD_OPTION = 0x33,
397 FD_CMD_RESTORE = 0x4e,
398 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
399 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
400 FD_CMD_FORMAT_AND_WRITE = 0xcd,
401 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
402 };
403
404 enum {
405 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
406 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
407 FD_CONFIG_POLL = 0x10, /* Poll enabled */
408 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
409 FD_CONFIG_EIS = 0x40, /* No implied seeks */
410 };
411
412 enum {
413 FD_SR0_DS0 = 0x01,
414 FD_SR0_DS1 = 0x02,
415 FD_SR0_HEAD = 0x04,
416 FD_SR0_EQPMT = 0x10,
417 FD_SR0_SEEK = 0x20,
418 FD_SR0_ABNTERM = 0x40,
419 FD_SR0_INVCMD = 0x80,
420 FD_SR0_RDYCHG = 0xc0,
421 };
422
423 enum {
424 FD_SR1_MA = 0x01, /* Missing address mark */
425 FD_SR1_NW = 0x02, /* Not writable */
426 FD_SR1_EC = 0x80, /* End of cylinder */
427 };
428
429 enum {
430 FD_SR2_SNS = 0x04, /* Scan not satisfied */
431 FD_SR2_SEH = 0x08, /* Scan equal hit */
432 };
433
434 enum {
435 FD_SRA_DIR = 0x01,
436 FD_SRA_nWP = 0x02,
437 FD_SRA_nINDX = 0x04,
438 FD_SRA_HDSEL = 0x08,
439 FD_SRA_nTRK0 = 0x10,
440 FD_SRA_STEP = 0x20,
441 FD_SRA_nDRV2 = 0x40,
442 FD_SRA_INTPEND = 0x80,
443 };
444
445 enum {
446 FD_SRB_MTR0 = 0x01,
447 FD_SRB_MTR1 = 0x02,
448 FD_SRB_WGATE = 0x04,
449 FD_SRB_RDATA = 0x08,
450 FD_SRB_WDATA = 0x10,
451 FD_SRB_DR0 = 0x20,
452 };
453
454 enum {
455 #if MAX_FD == 4
456 FD_DOR_SELMASK = 0x03,
457 #else
458 FD_DOR_SELMASK = 0x01,
459 #endif
460 FD_DOR_nRESET = 0x04,
461 FD_DOR_DMAEN = 0x08,
462 FD_DOR_MOTEN0 = 0x10,
463 FD_DOR_MOTEN1 = 0x20,
464 FD_DOR_MOTEN2 = 0x40,
465 FD_DOR_MOTEN3 = 0x80,
466 };
467
468 enum {
469 #if MAX_FD == 4
470 FD_TDR_BOOTSEL = 0x0c,
471 #else
472 FD_TDR_BOOTSEL = 0x04,
473 #endif
474 };
475
476 enum {
477 FD_DSR_DRATEMASK= 0x03,
478 FD_DSR_PWRDOWN = 0x40,
479 FD_DSR_SWRESET = 0x80,
480 };
481
482 enum {
483 FD_MSR_DRV0BUSY = 0x01,
484 FD_MSR_DRV1BUSY = 0x02,
485 FD_MSR_DRV2BUSY = 0x04,
486 FD_MSR_DRV3BUSY = 0x08,
487 FD_MSR_CMDBUSY = 0x10,
488 FD_MSR_NONDMA = 0x20,
489 FD_MSR_DIO = 0x40,
490 FD_MSR_RQM = 0x80,
491 };
492
493 enum {
494 FD_DIR_DSKCHG = 0x80,
495 };
496
497 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
498 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
499
500 struct FDCtrl {
501 MemoryRegion iomem;
502 qemu_irq irq;
503 /* Controller state */
504 QEMUTimer *result_timer;
505 int dma_chann;
506 /* Controller's identification */
507 uint8_t version;
508 /* HW */
509 uint8_t sra;
510 uint8_t srb;
511 uint8_t dor;
512 uint8_t dor_vmstate; /* only used as temp during vmstate */
513 uint8_t tdr;
514 uint8_t dsr;
515 uint8_t msr;
516 uint8_t cur_drv;
517 uint8_t status0;
518 uint8_t status1;
519 uint8_t status2;
520 /* Command FIFO */
521 uint8_t *fifo;
522 int32_t fifo_size;
523 uint32_t data_pos;
524 uint32_t data_len;
525 uint8_t data_state;
526 uint8_t data_dir;
527 uint8_t eot; /* last wanted sector */
528 /* States kept only to be returned back */
529 /* precompensation */
530 uint8_t precomp_trk;
531 uint8_t config;
532 uint8_t lock;
533 /* Power down config (also with status regB access mode */
534 uint8_t pwrd;
535 /* Floppy drives */
536 uint8_t num_floppies;
537 /* Sun4m quirks? */
538 int sun4m;
539 FDrive drives[MAX_FD];
540 int reset_sensei;
541 uint32_t check_media_rate;
542 /* Timers state */
543 uint8_t timer0;
544 uint8_t timer1;
545 };
546
547 typedef struct FDCtrlSysBus {
548 SysBusDevice busdev;
549 struct FDCtrl state;
550 } FDCtrlSysBus;
551
552 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
553
554 typedef struct FDCtrlISABus {
555 ISADevice parent_obj;
556
557 uint32_t iobase;
558 uint32_t irq;
559 uint32_t dma;
560 struct FDCtrl state;
561 int32_t bootindexA;
562 int32_t bootindexB;
563 } FDCtrlISABus;
564
565 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
566 {
567 FDCtrl *fdctrl = opaque;
568 uint32_t retval;
569
570 reg &= 7;
571 switch (reg) {
572 case FD_REG_SRA:
573 retval = fdctrl_read_statusA(fdctrl);
574 break;
575 case FD_REG_SRB:
576 retval = fdctrl_read_statusB(fdctrl);
577 break;
578 case FD_REG_DOR:
579 retval = fdctrl_read_dor(fdctrl);
580 break;
581 case FD_REG_TDR:
582 retval = fdctrl_read_tape(fdctrl);
583 break;
584 case FD_REG_MSR:
585 retval = fdctrl_read_main_status(fdctrl);
586 break;
587 case FD_REG_FIFO:
588 retval = fdctrl_read_data(fdctrl);
589 break;
590 case FD_REG_DIR:
591 retval = fdctrl_read_dir(fdctrl);
592 break;
593 default:
594 retval = (uint32_t)(-1);
595 break;
596 }
597 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
598
599 return retval;
600 }
601
602 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
603 {
604 FDCtrl *fdctrl = opaque;
605
606 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
607
608 reg &= 7;
609 switch (reg) {
610 case FD_REG_DOR:
611 fdctrl_write_dor(fdctrl, value);
612 break;
613 case FD_REG_TDR:
614 fdctrl_write_tape(fdctrl, value);
615 break;
616 case FD_REG_DSR:
617 fdctrl_write_rate(fdctrl, value);
618 break;
619 case FD_REG_FIFO:
620 fdctrl_write_data(fdctrl, value);
621 break;
622 case FD_REG_CCR:
623 fdctrl_write_ccr(fdctrl, value);
624 break;
625 default:
626 break;
627 }
628 }
629
630 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
631 unsigned ize)
632 {
633 return fdctrl_read(opaque, (uint32_t)reg);
634 }
635
636 static void fdctrl_write_mem (void *opaque, hwaddr reg,
637 uint64_t value, unsigned size)
638 {
639 fdctrl_write(opaque, (uint32_t)reg, value);
640 }
641
642 static const MemoryRegionOps fdctrl_mem_ops = {
643 .read = fdctrl_read_mem,
644 .write = fdctrl_write_mem,
645 .endianness = DEVICE_NATIVE_ENDIAN,
646 };
647
648 static const MemoryRegionOps fdctrl_mem_strict_ops = {
649 .read = fdctrl_read_mem,
650 .write = fdctrl_write_mem,
651 .endianness = DEVICE_NATIVE_ENDIAN,
652 .valid = {
653 .min_access_size = 1,
654 .max_access_size = 1,
655 },
656 };
657
658 static bool fdrive_media_changed_needed(void *opaque)
659 {
660 FDrive *drive = opaque;
661
662 return (drive->bs != NULL && drive->media_changed != 1);
663 }
664
665 static const VMStateDescription vmstate_fdrive_media_changed = {
666 .name = "fdrive/media_changed",
667 .version_id = 1,
668 .minimum_version_id = 1,
669 .minimum_version_id_old = 1,
670 .fields = (VMStateField[]) {
671 VMSTATE_UINT8(media_changed, FDrive),
672 VMSTATE_END_OF_LIST()
673 }
674 };
675
676 static bool fdrive_media_rate_needed(void *opaque)
677 {
678 FDrive *drive = opaque;
679
680 return drive->fdctrl->check_media_rate;
681 }
682
683 static const VMStateDescription vmstate_fdrive_media_rate = {
684 .name = "fdrive/media_rate",
685 .version_id = 1,
686 .minimum_version_id = 1,
687 .minimum_version_id_old = 1,
688 .fields = (VMStateField[]) {
689 VMSTATE_UINT8(media_rate, FDrive),
690 VMSTATE_END_OF_LIST()
691 }
692 };
693
694 static const VMStateDescription vmstate_fdrive = {
695 .name = "fdrive",
696 .version_id = 1,
697 .minimum_version_id = 1,
698 .minimum_version_id_old = 1,
699 .fields = (VMStateField[]) {
700 VMSTATE_UINT8(head, FDrive),
701 VMSTATE_UINT8(track, FDrive),
702 VMSTATE_UINT8(sect, FDrive),
703 VMSTATE_END_OF_LIST()
704 },
705 .subsections = (VMStateSubsection[]) {
706 {
707 .vmsd = &vmstate_fdrive_media_changed,
708 .needed = &fdrive_media_changed_needed,
709 } , {
710 .vmsd = &vmstate_fdrive_media_rate,
711 .needed = &fdrive_media_rate_needed,
712 } , {
713 /* empty */
714 }
715 }
716 };
717
718 static void fdc_pre_save(void *opaque)
719 {
720 FDCtrl *s = opaque;
721
722 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
723 }
724
725 static int fdc_post_load(void *opaque, int version_id)
726 {
727 FDCtrl *s = opaque;
728
729 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
730 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
731 return 0;
732 }
733
734 static const VMStateDescription vmstate_fdc = {
735 .name = "fdc",
736 .version_id = 2,
737 .minimum_version_id = 2,
738 .minimum_version_id_old = 2,
739 .pre_save = fdc_pre_save,
740 .post_load = fdc_post_load,
741 .fields = (VMStateField []) {
742 /* Controller State */
743 VMSTATE_UINT8(sra, FDCtrl),
744 VMSTATE_UINT8(srb, FDCtrl),
745 VMSTATE_UINT8(dor_vmstate, FDCtrl),
746 VMSTATE_UINT8(tdr, FDCtrl),
747 VMSTATE_UINT8(dsr, FDCtrl),
748 VMSTATE_UINT8(msr, FDCtrl),
749 VMSTATE_UINT8(status0, FDCtrl),
750 VMSTATE_UINT8(status1, FDCtrl),
751 VMSTATE_UINT8(status2, FDCtrl),
752 /* Command FIFO */
753 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
754 uint8_t),
755 VMSTATE_UINT32(data_pos, FDCtrl),
756 VMSTATE_UINT32(data_len, FDCtrl),
757 VMSTATE_UINT8(data_state, FDCtrl),
758 VMSTATE_UINT8(data_dir, FDCtrl),
759 VMSTATE_UINT8(eot, FDCtrl),
760 /* States kept only to be returned back */
761 VMSTATE_UINT8(timer0, FDCtrl),
762 VMSTATE_UINT8(timer1, FDCtrl),
763 VMSTATE_UINT8(precomp_trk, FDCtrl),
764 VMSTATE_UINT8(config, FDCtrl),
765 VMSTATE_UINT8(lock, FDCtrl),
766 VMSTATE_UINT8(pwrd, FDCtrl),
767 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
768 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
769 vmstate_fdrive, FDrive),
770 VMSTATE_END_OF_LIST()
771 }
772 };
773
774 static void fdctrl_external_reset_sysbus(DeviceState *d)
775 {
776 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
777 FDCtrl *s = &sys->state;
778
779 fdctrl_reset(s, 0);
780 }
781
782 static void fdctrl_external_reset_isa(DeviceState *d)
783 {
784 FDCtrlISABus *isa = ISA_FDC(d);
785 FDCtrl *s = &isa->state;
786
787 fdctrl_reset(s, 0);
788 }
789
790 static void fdctrl_handle_tc(void *opaque, int irq, int level)
791 {
792 //FDCtrl *s = opaque;
793
794 if (level) {
795 // XXX
796 FLOPPY_DPRINTF("TC pulsed\n");
797 }
798 }
799
800 /* Change IRQ state */
801 static void fdctrl_reset_irq(FDCtrl *fdctrl)
802 {
803 fdctrl->status0 = 0;
804 if (!(fdctrl->sra & FD_SRA_INTPEND))
805 return;
806 FLOPPY_DPRINTF("Reset interrupt\n");
807 qemu_set_irq(fdctrl->irq, 0);
808 fdctrl->sra &= ~FD_SRA_INTPEND;
809 }
810
811 static void fdctrl_raise_irq(FDCtrl *fdctrl)
812 {
813 /* Sparc mutation */
814 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
815 /* XXX: not sure */
816 fdctrl->msr &= ~FD_MSR_CMDBUSY;
817 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
818 return;
819 }
820 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
821 qemu_set_irq(fdctrl->irq, 1);
822 fdctrl->sra |= FD_SRA_INTPEND;
823 }
824
825 fdctrl->reset_sensei = 0;
826 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
827 }
828
829 /* Reset controller */
830 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
831 {
832 int i;
833
834 FLOPPY_DPRINTF("reset controller\n");
835 fdctrl_reset_irq(fdctrl);
836 /* Initialise controller */
837 fdctrl->sra = 0;
838 fdctrl->srb = 0xc0;
839 if (!fdctrl->drives[1].bs)
840 fdctrl->sra |= FD_SRA_nDRV2;
841 fdctrl->cur_drv = 0;
842 fdctrl->dor = FD_DOR_nRESET;
843 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
844 fdctrl->msr = FD_MSR_RQM;
845 /* FIFO state */
846 fdctrl->data_pos = 0;
847 fdctrl->data_len = 0;
848 fdctrl->data_state = 0;
849 fdctrl->data_dir = FD_DIR_WRITE;
850 for (i = 0; i < MAX_FD; i++)
851 fd_recalibrate(&fdctrl->drives[i]);
852 fdctrl_reset_fifo(fdctrl);
853 if (do_irq) {
854 fdctrl->status0 |= FD_SR0_RDYCHG;
855 fdctrl_raise_irq(fdctrl);
856 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
857 }
858 }
859
860 static inline FDrive *drv0(FDCtrl *fdctrl)
861 {
862 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
863 }
864
865 static inline FDrive *drv1(FDCtrl *fdctrl)
866 {
867 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
868 return &fdctrl->drives[1];
869 else
870 return &fdctrl->drives[0];
871 }
872
873 #if MAX_FD == 4
874 static inline FDrive *drv2(FDCtrl *fdctrl)
875 {
876 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
877 return &fdctrl->drives[2];
878 else
879 return &fdctrl->drives[1];
880 }
881
882 static inline FDrive *drv3(FDCtrl *fdctrl)
883 {
884 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
885 return &fdctrl->drives[3];
886 else
887 return &fdctrl->drives[2];
888 }
889 #endif
890
891 static FDrive *get_cur_drv(FDCtrl *fdctrl)
892 {
893 switch (fdctrl->cur_drv) {
894 case 0: return drv0(fdctrl);
895 case 1: return drv1(fdctrl);
896 #if MAX_FD == 4
897 case 2: return drv2(fdctrl);
898 case 3: return drv3(fdctrl);
899 #endif
900 default: return NULL;
901 }
902 }
903
904 /* Status A register : 0x00 (read-only) */
905 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
906 {
907 uint32_t retval = fdctrl->sra;
908
909 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
910
911 return retval;
912 }
913
914 /* Status B register : 0x01 (read-only) */
915 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
916 {
917 uint32_t retval = fdctrl->srb;
918
919 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
920
921 return retval;
922 }
923
924 /* Digital output register : 0x02 */
925 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
926 {
927 uint32_t retval = fdctrl->dor;
928
929 /* Selected drive */
930 retval |= fdctrl->cur_drv;
931 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
932
933 return retval;
934 }
935
936 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
937 {
938 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
939
940 /* Motors */
941 if (value & FD_DOR_MOTEN0)
942 fdctrl->srb |= FD_SRB_MTR0;
943 else
944 fdctrl->srb &= ~FD_SRB_MTR0;
945 if (value & FD_DOR_MOTEN1)
946 fdctrl->srb |= FD_SRB_MTR1;
947 else
948 fdctrl->srb &= ~FD_SRB_MTR1;
949
950 /* Drive */
951 if (value & 1)
952 fdctrl->srb |= FD_SRB_DR0;
953 else
954 fdctrl->srb &= ~FD_SRB_DR0;
955
956 /* Reset */
957 if (!(value & FD_DOR_nRESET)) {
958 if (fdctrl->dor & FD_DOR_nRESET) {
959 FLOPPY_DPRINTF("controller enter RESET state\n");
960 }
961 } else {
962 if (!(fdctrl->dor & FD_DOR_nRESET)) {
963 FLOPPY_DPRINTF("controller out of RESET state\n");
964 fdctrl_reset(fdctrl, 1);
965 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
966 }
967 }
968 /* Selected drive */
969 fdctrl->cur_drv = value & FD_DOR_SELMASK;
970
971 fdctrl->dor = value;
972 }
973
974 /* Tape drive register : 0x03 */
975 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
976 {
977 uint32_t retval = fdctrl->tdr;
978
979 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
980
981 return retval;
982 }
983
984 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
985 {
986 /* Reset mode */
987 if (!(fdctrl->dor & FD_DOR_nRESET)) {
988 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
989 return;
990 }
991 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
992 /* Disk boot selection indicator */
993 fdctrl->tdr = value & FD_TDR_BOOTSEL;
994 /* Tape indicators: never allow */
995 }
996
997 /* Main status register : 0x04 (read) */
998 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
999 {
1000 uint32_t retval = fdctrl->msr;
1001
1002 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1003 fdctrl->dor |= FD_DOR_nRESET;
1004
1005 /* Sparc mutation */
1006 if (fdctrl->sun4m) {
1007 retval |= FD_MSR_DIO;
1008 fdctrl_reset_irq(fdctrl);
1009 };
1010
1011 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1012
1013 return retval;
1014 }
1015
1016 /* Data select rate register : 0x04 (write) */
1017 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1018 {
1019 /* Reset mode */
1020 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1021 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1022 return;
1023 }
1024 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1025 /* Reset: autoclear */
1026 if (value & FD_DSR_SWRESET) {
1027 fdctrl->dor &= ~FD_DOR_nRESET;
1028 fdctrl_reset(fdctrl, 1);
1029 fdctrl->dor |= FD_DOR_nRESET;
1030 }
1031 if (value & FD_DSR_PWRDOWN) {
1032 fdctrl_reset(fdctrl, 1);
1033 }
1034 fdctrl->dsr = value;
1035 }
1036
1037 /* Configuration control register: 0x07 (write) */
1038 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1039 {
1040 /* Reset mode */
1041 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1042 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1043 return;
1044 }
1045 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1046
1047 /* Only the rate selection bits used in AT mode, and we
1048 * store those in the DSR.
1049 */
1050 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1051 (value & FD_DSR_DRATEMASK);
1052 }
1053
1054 static int fdctrl_media_changed(FDrive *drv)
1055 {
1056 return drv->media_changed;
1057 }
1058
1059 /* Digital input register : 0x07 (read-only) */
1060 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1061 {
1062 uint32_t retval = 0;
1063
1064 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1065 retval |= FD_DIR_DSKCHG;
1066 }
1067 if (retval != 0) {
1068 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1069 }
1070
1071 return retval;
1072 }
1073
1074 /* FIFO state control */
1075 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1076 {
1077 fdctrl->data_dir = FD_DIR_WRITE;
1078 fdctrl->data_pos = 0;
1079 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1080 }
1081
1082 /* Set FIFO status for the host to read */
1083 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len)
1084 {
1085 fdctrl->data_dir = FD_DIR_READ;
1086 fdctrl->data_len = fifo_len;
1087 fdctrl->data_pos = 0;
1088 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1089 }
1090
1091 /* Set an error: unimplemented/unknown command */
1092 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1093 {
1094 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1095 fdctrl->fifo[0]);
1096 fdctrl->fifo[0] = FD_SR0_INVCMD;
1097 fdctrl_set_fifo(fdctrl, 1);
1098 }
1099
1100 /* Seek to next sector
1101 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1102 * otherwise returns 1
1103 */
1104 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1105 {
1106 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1107 cur_drv->head, cur_drv->track, cur_drv->sect,
1108 fd_sector(cur_drv));
1109 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1110 error in fact */
1111 uint8_t new_head = cur_drv->head;
1112 uint8_t new_track = cur_drv->track;
1113 uint8_t new_sect = cur_drv->sect;
1114
1115 int ret = 1;
1116
1117 if (new_sect >= cur_drv->last_sect ||
1118 new_sect == fdctrl->eot) {
1119 new_sect = 1;
1120 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1121 if (new_head == 0 &&
1122 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1123 new_head = 1;
1124 } else {
1125 new_head = 0;
1126 new_track++;
1127 fdctrl->status0 |= FD_SR0_SEEK;
1128 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1129 ret = 0;
1130 }
1131 }
1132 } else {
1133 fdctrl->status0 |= FD_SR0_SEEK;
1134 new_track++;
1135 ret = 0;
1136 }
1137 if (ret == 1) {
1138 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1139 new_head, new_track, new_sect, fd_sector(cur_drv));
1140 }
1141 } else {
1142 new_sect++;
1143 }
1144 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1145 return ret;
1146 }
1147
1148 /* Callback for transfer end (stop or abort) */
1149 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1150 uint8_t status1, uint8_t status2)
1151 {
1152 FDrive *cur_drv;
1153 cur_drv = get_cur_drv(fdctrl);
1154
1155 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1156 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1157 if (cur_drv->head) {
1158 fdctrl->status0 |= FD_SR0_HEAD;
1159 }
1160 fdctrl->status0 |= status0;
1161
1162 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1163 status0, status1, status2, fdctrl->status0);
1164 fdctrl->fifo[0] = fdctrl->status0;
1165 fdctrl->fifo[1] = status1;
1166 fdctrl->fifo[2] = status2;
1167 fdctrl->fifo[3] = cur_drv->track;
1168 fdctrl->fifo[4] = cur_drv->head;
1169 fdctrl->fifo[5] = cur_drv->sect;
1170 fdctrl->fifo[6] = FD_SECTOR_SC;
1171 fdctrl->data_dir = FD_DIR_READ;
1172 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1173 DMA_release_DREQ(fdctrl->dma_chann);
1174 }
1175 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1176 fdctrl->msr &= ~FD_MSR_NONDMA;
1177
1178 fdctrl_set_fifo(fdctrl, 7);
1179 fdctrl_raise_irq(fdctrl);
1180 }
1181
1182 /* Prepare a data transfer (either DMA or FIFO) */
1183 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1184 {
1185 FDrive *cur_drv;
1186 uint8_t kh, kt, ks;
1187
1188 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1189 cur_drv = get_cur_drv(fdctrl);
1190 kt = fdctrl->fifo[2];
1191 kh = fdctrl->fifo[3];
1192 ks = fdctrl->fifo[4];
1193 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1194 GET_CUR_DRV(fdctrl), kh, kt, ks,
1195 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1196 NUM_SIDES(cur_drv)));
1197 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1198 case 2:
1199 /* sect too big */
1200 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1201 fdctrl->fifo[3] = kt;
1202 fdctrl->fifo[4] = kh;
1203 fdctrl->fifo[5] = ks;
1204 return;
1205 case 3:
1206 /* track too big */
1207 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1208 fdctrl->fifo[3] = kt;
1209 fdctrl->fifo[4] = kh;
1210 fdctrl->fifo[5] = ks;
1211 return;
1212 case 4:
1213 /* No seek enabled */
1214 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1215 fdctrl->fifo[3] = kt;
1216 fdctrl->fifo[4] = kh;
1217 fdctrl->fifo[5] = ks;
1218 return;
1219 case 1:
1220 fdctrl->status0 |= FD_SR0_SEEK;
1221 break;
1222 default:
1223 break;
1224 }
1225
1226 /* Check the data rate. If the programmed data rate does not match
1227 * the currently inserted medium, the operation has to fail. */
1228 if (fdctrl->check_media_rate &&
1229 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1230 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1231 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1232 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1233 fdctrl->fifo[3] = kt;
1234 fdctrl->fifo[4] = kh;
1235 fdctrl->fifo[5] = ks;
1236 return;
1237 }
1238
1239 /* Set the FIFO state */
1240 fdctrl->data_dir = direction;
1241 fdctrl->data_pos = 0;
1242 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1243 if (fdctrl->fifo[0] & 0x80)
1244 fdctrl->data_state |= FD_STATE_MULTI;
1245 else
1246 fdctrl->data_state &= ~FD_STATE_MULTI;
1247 if (fdctrl->fifo[5] == 0) {
1248 fdctrl->data_len = fdctrl->fifo[8];
1249 } else {
1250 int tmp;
1251 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1252 tmp = (fdctrl->fifo[6] - ks + 1);
1253 if (fdctrl->fifo[0] & 0x80)
1254 tmp += fdctrl->fifo[6];
1255 fdctrl->data_len *= tmp;
1256 }
1257 fdctrl->eot = fdctrl->fifo[6];
1258 if (fdctrl->dor & FD_DOR_DMAEN) {
1259 int dma_mode;
1260 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1261 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1262 dma_mode = (dma_mode >> 2) & 3;
1263 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1264 dma_mode, direction,
1265 (128 << fdctrl->fifo[5]) *
1266 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1267 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1268 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1269 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1270 (direction == FD_DIR_READ && dma_mode == 1) ||
1271 (direction == FD_DIR_VERIFY)) {
1272 /* No access is allowed until DMA transfer has completed */
1273 fdctrl->msr &= ~FD_MSR_RQM;
1274 if (direction != FD_DIR_VERIFY) {
1275 /* Now, we just have to wait for the DMA controller to
1276 * recall us...
1277 */
1278 DMA_hold_DREQ(fdctrl->dma_chann);
1279 DMA_schedule(fdctrl->dma_chann);
1280 } else {
1281 /* Start transfer */
1282 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1283 fdctrl->data_len);
1284 }
1285 return;
1286 } else {
1287 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1288 direction);
1289 }
1290 }
1291 FLOPPY_DPRINTF("start non-DMA transfer\n");
1292 fdctrl->msr |= FD_MSR_NONDMA;
1293 if (direction != FD_DIR_WRITE)
1294 fdctrl->msr |= FD_MSR_DIO;
1295 /* IO based transfer: calculate len */
1296 fdctrl_raise_irq(fdctrl);
1297 }
1298
1299 /* Prepare a transfer of deleted data */
1300 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1301 {
1302 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1303
1304 /* We don't handle deleted data,
1305 * so we don't return *ANYTHING*
1306 */
1307 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1308 }
1309
1310 /* handlers for DMA transfers */
1311 static int fdctrl_transfer_handler (void *opaque, int nchan,
1312 int dma_pos, int dma_len)
1313 {
1314 FDCtrl *fdctrl;
1315 FDrive *cur_drv;
1316 int len, start_pos, rel_pos;
1317 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1318
1319 fdctrl = opaque;
1320 if (fdctrl->msr & FD_MSR_RQM) {
1321 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1322 return 0;
1323 }
1324 cur_drv = get_cur_drv(fdctrl);
1325 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1326 fdctrl->data_dir == FD_DIR_SCANH)
1327 status2 = FD_SR2_SNS;
1328 if (dma_len > fdctrl->data_len)
1329 dma_len = fdctrl->data_len;
1330 if (cur_drv->bs == NULL) {
1331 if (fdctrl->data_dir == FD_DIR_WRITE)
1332 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1333 else
1334 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1335 len = 0;
1336 goto transfer_error;
1337 }
1338 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1339 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1340 len = dma_len - fdctrl->data_pos;
1341 if (len + rel_pos > FD_SECTOR_LEN)
1342 len = FD_SECTOR_LEN - rel_pos;
1343 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1344 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1345 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1346 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1347 fd_sector(cur_drv) * FD_SECTOR_LEN);
1348 if (fdctrl->data_dir != FD_DIR_WRITE ||
1349 len < FD_SECTOR_LEN || rel_pos != 0) {
1350 /* READ & SCAN commands and realign to a sector for WRITE */
1351 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1352 fdctrl->fifo, 1) < 0) {
1353 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1354 fd_sector(cur_drv));
1355 /* Sure, image size is too small... */
1356 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1357 }
1358 }
1359 switch (fdctrl->data_dir) {
1360 case FD_DIR_READ:
1361 /* READ commands */
1362 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1363 fdctrl->data_pos, len);
1364 break;
1365 case FD_DIR_WRITE:
1366 /* WRITE commands */
1367 if (cur_drv->ro) {
1368 /* Handle readonly medium early, no need to do DMA, touch the
1369 * LED or attempt any writes. A real floppy doesn't attempt
1370 * to write to readonly media either. */
1371 fdctrl_stop_transfer(fdctrl,
1372 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1373 0x00);
1374 goto transfer_error;
1375 }
1376
1377 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1378 fdctrl->data_pos, len);
1379 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1380 fdctrl->fifo, 1) < 0) {
1381 FLOPPY_DPRINTF("error writing sector %d\n",
1382 fd_sector(cur_drv));
1383 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1384 goto transfer_error;
1385 }
1386 break;
1387 case FD_DIR_VERIFY:
1388 /* VERIFY commands */
1389 break;
1390 default:
1391 /* SCAN commands */
1392 {
1393 uint8_t tmpbuf[FD_SECTOR_LEN];
1394 int ret;
1395 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1396 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1397 if (ret == 0) {
1398 status2 = FD_SR2_SEH;
1399 goto end_transfer;
1400 }
1401 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1402 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1403 status2 = 0x00;
1404 goto end_transfer;
1405 }
1406 }
1407 break;
1408 }
1409 fdctrl->data_pos += len;
1410 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1411 if (rel_pos == 0) {
1412 /* Seek to next sector */
1413 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1414 break;
1415 }
1416 }
1417 end_transfer:
1418 len = fdctrl->data_pos - start_pos;
1419 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1420 fdctrl->data_pos, len, fdctrl->data_len);
1421 if (fdctrl->data_dir == FD_DIR_SCANE ||
1422 fdctrl->data_dir == FD_DIR_SCANL ||
1423 fdctrl->data_dir == FD_DIR_SCANH)
1424 status2 = FD_SR2_SEH;
1425 fdctrl->data_len -= len;
1426 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1427 transfer_error:
1428
1429 return len;
1430 }
1431
1432 /* Data register : 0x05 */
1433 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1434 {
1435 FDrive *cur_drv;
1436 uint32_t retval = 0;
1437 int pos;
1438
1439 cur_drv = get_cur_drv(fdctrl);
1440 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1441 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1442 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1443 return 0;
1444 }
1445 pos = fdctrl->data_pos;
1446 if (fdctrl->msr & FD_MSR_NONDMA) {
1447 pos %= FD_SECTOR_LEN;
1448 if (pos == 0) {
1449 if (fdctrl->data_pos != 0)
1450 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1451 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1452 fd_sector(cur_drv));
1453 return 0;
1454 }
1455 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1456 FLOPPY_DPRINTF("error getting sector %d\n",
1457 fd_sector(cur_drv));
1458 /* Sure, image size is too small... */
1459 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1460 }
1461 }
1462 }
1463 retval = fdctrl->fifo[pos];
1464 if (++fdctrl->data_pos == fdctrl->data_len) {
1465 fdctrl->data_pos = 0;
1466 /* Switch from transfer mode to status mode
1467 * then from status mode to command mode
1468 */
1469 if (fdctrl->msr & FD_MSR_NONDMA) {
1470 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1471 } else {
1472 fdctrl_reset_fifo(fdctrl);
1473 fdctrl_reset_irq(fdctrl);
1474 }
1475 }
1476 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1477
1478 return retval;
1479 }
1480
1481 static void fdctrl_format_sector(FDCtrl *fdctrl)
1482 {
1483 FDrive *cur_drv;
1484 uint8_t kh, kt, ks;
1485
1486 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1487 cur_drv = get_cur_drv(fdctrl);
1488 kt = fdctrl->fifo[6];
1489 kh = fdctrl->fifo[7];
1490 ks = fdctrl->fifo[8];
1491 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1492 GET_CUR_DRV(fdctrl), kh, kt, ks,
1493 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1494 NUM_SIDES(cur_drv)));
1495 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1496 case 2:
1497 /* sect too big */
1498 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1499 fdctrl->fifo[3] = kt;
1500 fdctrl->fifo[4] = kh;
1501 fdctrl->fifo[5] = ks;
1502 return;
1503 case 3:
1504 /* track too big */
1505 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1506 fdctrl->fifo[3] = kt;
1507 fdctrl->fifo[4] = kh;
1508 fdctrl->fifo[5] = ks;
1509 return;
1510 case 4:
1511 /* No seek enabled */
1512 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1513 fdctrl->fifo[3] = kt;
1514 fdctrl->fifo[4] = kh;
1515 fdctrl->fifo[5] = ks;
1516 return;
1517 case 1:
1518 fdctrl->status0 |= FD_SR0_SEEK;
1519 break;
1520 default:
1521 break;
1522 }
1523 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1524 if (cur_drv->bs == NULL ||
1525 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1526 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1527 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1528 } else {
1529 if (cur_drv->sect == cur_drv->last_sect) {
1530 fdctrl->data_state &= ~FD_STATE_FORMAT;
1531 /* Last sector done */
1532 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1533 } else {
1534 /* More to do */
1535 fdctrl->data_pos = 0;
1536 fdctrl->data_len = 4;
1537 }
1538 }
1539 }
1540
1541 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1542 {
1543 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1544 fdctrl->fifo[0] = fdctrl->lock << 4;
1545 fdctrl_set_fifo(fdctrl, 1);
1546 }
1547
1548 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1549 {
1550 FDrive *cur_drv = get_cur_drv(fdctrl);
1551
1552 /* Drives position */
1553 fdctrl->fifo[0] = drv0(fdctrl)->track;
1554 fdctrl->fifo[1] = drv1(fdctrl)->track;
1555 #if MAX_FD == 4
1556 fdctrl->fifo[2] = drv2(fdctrl)->track;
1557 fdctrl->fifo[3] = drv3(fdctrl)->track;
1558 #else
1559 fdctrl->fifo[2] = 0;
1560 fdctrl->fifo[3] = 0;
1561 #endif
1562 /* timers */
1563 fdctrl->fifo[4] = fdctrl->timer0;
1564 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1565 fdctrl->fifo[6] = cur_drv->last_sect;
1566 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1567 (cur_drv->perpendicular << 2);
1568 fdctrl->fifo[8] = fdctrl->config;
1569 fdctrl->fifo[9] = fdctrl->precomp_trk;
1570 fdctrl_set_fifo(fdctrl, 10);
1571 }
1572
1573 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1574 {
1575 /* Controller's version */
1576 fdctrl->fifo[0] = fdctrl->version;
1577 fdctrl_set_fifo(fdctrl, 1);
1578 }
1579
1580 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1581 {
1582 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1583 fdctrl_set_fifo(fdctrl, 1);
1584 }
1585
1586 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1587 {
1588 FDrive *cur_drv = get_cur_drv(fdctrl);
1589
1590 /* Drives position */
1591 drv0(fdctrl)->track = fdctrl->fifo[3];
1592 drv1(fdctrl)->track = fdctrl->fifo[4];
1593 #if MAX_FD == 4
1594 drv2(fdctrl)->track = fdctrl->fifo[5];
1595 drv3(fdctrl)->track = fdctrl->fifo[6];
1596 #endif
1597 /* timers */
1598 fdctrl->timer0 = fdctrl->fifo[7];
1599 fdctrl->timer1 = fdctrl->fifo[8];
1600 cur_drv->last_sect = fdctrl->fifo[9];
1601 fdctrl->lock = fdctrl->fifo[10] >> 7;
1602 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1603 fdctrl->config = fdctrl->fifo[11];
1604 fdctrl->precomp_trk = fdctrl->fifo[12];
1605 fdctrl->pwrd = fdctrl->fifo[13];
1606 fdctrl_reset_fifo(fdctrl);
1607 }
1608
1609 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1610 {
1611 FDrive *cur_drv = get_cur_drv(fdctrl);
1612
1613 fdctrl->fifo[0] = 0;
1614 fdctrl->fifo[1] = 0;
1615 /* Drives position */
1616 fdctrl->fifo[2] = drv0(fdctrl)->track;
1617 fdctrl->fifo[3] = drv1(fdctrl)->track;
1618 #if MAX_FD == 4
1619 fdctrl->fifo[4] = drv2(fdctrl)->track;
1620 fdctrl->fifo[5] = drv3(fdctrl)->track;
1621 #else
1622 fdctrl->fifo[4] = 0;
1623 fdctrl->fifo[5] = 0;
1624 #endif
1625 /* timers */
1626 fdctrl->fifo[6] = fdctrl->timer0;
1627 fdctrl->fifo[7] = fdctrl->timer1;
1628 fdctrl->fifo[8] = cur_drv->last_sect;
1629 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1630 (cur_drv->perpendicular << 2);
1631 fdctrl->fifo[10] = fdctrl->config;
1632 fdctrl->fifo[11] = fdctrl->precomp_trk;
1633 fdctrl->fifo[12] = fdctrl->pwrd;
1634 fdctrl->fifo[13] = 0;
1635 fdctrl->fifo[14] = 0;
1636 fdctrl_set_fifo(fdctrl, 15);
1637 }
1638
1639 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1640 {
1641 FDrive *cur_drv = get_cur_drv(fdctrl);
1642
1643 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1644 qemu_mod_timer(fdctrl->result_timer,
1645 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1646 }
1647
1648 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1649 {
1650 FDrive *cur_drv;
1651
1652 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1653 cur_drv = get_cur_drv(fdctrl);
1654 fdctrl->data_state |= FD_STATE_FORMAT;
1655 if (fdctrl->fifo[0] & 0x80)
1656 fdctrl->data_state |= FD_STATE_MULTI;
1657 else
1658 fdctrl->data_state &= ~FD_STATE_MULTI;
1659 cur_drv->bps =
1660 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1661 #if 0
1662 cur_drv->last_sect =
1663 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1664 fdctrl->fifo[3] / 2;
1665 #else
1666 cur_drv->last_sect = fdctrl->fifo[3];
1667 #endif
1668 /* TODO: implement format using DMA expected by the Bochs BIOS
1669 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1670 * the sector with the specified fill byte
1671 */
1672 fdctrl->data_state &= ~FD_STATE_FORMAT;
1673 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1674 }
1675
1676 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1677 {
1678 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1679 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1680 if (fdctrl->fifo[2] & 1)
1681 fdctrl->dor &= ~FD_DOR_DMAEN;
1682 else
1683 fdctrl->dor |= FD_DOR_DMAEN;
1684 /* No result back */
1685 fdctrl_reset_fifo(fdctrl);
1686 }
1687
1688 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1689 {
1690 FDrive *cur_drv;
1691
1692 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1693 cur_drv = get_cur_drv(fdctrl);
1694 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1695 /* 1 Byte status back */
1696 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1697 (cur_drv->track == 0 ? 0x10 : 0x00) |
1698 (cur_drv->head << 2) |
1699 GET_CUR_DRV(fdctrl) |
1700 0x28;
1701 fdctrl_set_fifo(fdctrl, 1);
1702 }
1703
1704 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1705 {
1706 FDrive *cur_drv;
1707
1708 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1709 cur_drv = get_cur_drv(fdctrl);
1710 fd_recalibrate(cur_drv);
1711 fdctrl_reset_fifo(fdctrl);
1712 /* Raise Interrupt */
1713 fdctrl->status0 |= FD_SR0_SEEK;
1714 fdctrl_raise_irq(fdctrl);
1715 }
1716
1717 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1718 {
1719 FDrive *cur_drv = get_cur_drv(fdctrl);
1720
1721 if (fdctrl->reset_sensei > 0) {
1722 fdctrl->fifo[0] =
1723 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1724 fdctrl->reset_sensei--;
1725 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1726 fdctrl->fifo[0] = FD_SR0_INVCMD;
1727 fdctrl_set_fifo(fdctrl, 1);
1728 return;
1729 } else {
1730 fdctrl->fifo[0] =
1731 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1732 | GET_CUR_DRV(fdctrl);
1733 }
1734
1735 fdctrl->fifo[1] = cur_drv->track;
1736 fdctrl_set_fifo(fdctrl, 2);
1737 fdctrl_reset_irq(fdctrl);
1738 fdctrl->status0 = FD_SR0_RDYCHG;
1739 }
1740
1741 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1742 {
1743 FDrive *cur_drv;
1744
1745 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1746 cur_drv = get_cur_drv(fdctrl);
1747 fdctrl_reset_fifo(fdctrl);
1748 /* The seek command just sends step pulses to the drive and doesn't care if
1749 * there is a medium inserted of if it's banging the head against the drive.
1750 */
1751 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1752 /* Raise Interrupt */
1753 fdctrl->status0 |= FD_SR0_SEEK;
1754 fdctrl_raise_irq(fdctrl);
1755 }
1756
1757 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1758 {
1759 FDrive *cur_drv = get_cur_drv(fdctrl);
1760
1761 if (fdctrl->fifo[1] & 0x80)
1762 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1763 /* No result back */
1764 fdctrl_reset_fifo(fdctrl);
1765 }
1766
1767 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1768 {
1769 fdctrl->config = fdctrl->fifo[2];
1770 fdctrl->precomp_trk = fdctrl->fifo[3];
1771 /* No result back */
1772 fdctrl_reset_fifo(fdctrl);
1773 }
1774
1775 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1776 {
1777 fdctrl->pwrd = fdctrl->fifo[1];
1778 fdctrl->fifo[0] = fdctrl->fifo[1];
1779 fdctrl_set_fifo(fdctrl, 1);
1780 }
1781
1782 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1783 {
1784 /* No result back */
1785 fdctrl_reset_fifo(fdctrl);
1786 }
1787
1788 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1789 {
1790 FDrive *cur_drv = get_cur_drv(fdctrl);
1791
1792 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1793 /* Command parameters done */
1794 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1795 fdctrl->fifo[0] = fdctrl->fifo[1];
1796 fdctrl->fifo[2] = 0;
1797 fdctrl->fifo[3] = 0;
1798 fdctrl_set_fifo(fdctrl, 4);
1799 } else {
1800 fdctrl_reset_fifo(fdctrl);
1801 }
1802 } else if (fdctrl->data_len > 7) {
1803 /* ERROR */
1804 fdctrl->fifo[0] = 0x80 |
1805 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1806 fdctrl_set_fifo(fdctrl, 1);
1807 }
1808 }
1809
1810 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1811 {
1812 FDrive *cur_drv;
1813
1814 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1815 cur_drv = get_cur_drv(fdctrl);
1816 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1817 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1818 cur_drv->sect, 1);
1819 } else {
1820 fd_seek(cur_drv, cur_drv->head,
1821 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
1822 }
1823 fdctrl_reset_fifo(fdctrl);
1824 /* Raise Interrupt */
1825 fdctrl->status0 |= FD_SR0_SEEK;
1826 fdctrl_raise_irq(fdctrl);
1827 }
1828
1829 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1830 {
1831 FDrive *cur_drv;
1832
1833 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1834 cur_drv = get_cur_drv(fdctrl);
1835 if (fdctrl->fifo[2] > cur_drv->track) {
1836 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1837 } else {
1838 fd_seek(cur_drv, cur_drv->head,
1839 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
1840 }
1841 fdctrl_reset_fifo(fdctrl);
1842 /* Raise Interrupt */
1843 fdctrl->status0 |= FD_SR0_SEEK;
1844 fdctrl_raise_irq(fdctrl);
1845 }
1846
1847 static const struct {
1848 uint8_t value;
1849 uint8_t mask;
1850 const char* name;
1851 int parameters;
1852 void (*handler)(FDCtrl *fdctrl, int direction);
1853 int direction;
1854 } handlers[] = {
1855 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1856 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1857 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1858 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1859 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1860 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1861 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1862 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1863 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1864 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1865 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1866 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
1867 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1868 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1869 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1870 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1871 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1872 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1873 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1874 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1875 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1876 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1877 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1878 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1879 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1880 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1881 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1882 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1883 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1884 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1885 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1886 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1887 };
1888 /* Associate command to an index in the 'handlers' array */
1889 static uint8_t command_to_handler[256];
1890
1891 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1892 {
1893 FDrive *cur_drv;
1894 int pos;
1895
1896 /* Reset mode */
1897 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1898 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1899 return;
1900 }
1901 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1902 FLOPPY_DPRINTF("error: controller not ready for writing\n");
1903 return;
1904 }
1905 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1906 /* Is it write command time ? */
1907 if (fdctrl->msr & FD_MSR_NONDMA) {
1908 /* FIFO data write */
1909 pos = fdctrl->data_pos++;
1910 pos %= FD_SECTOR_LEN;
1911 fdctrl->fifo[pos] = value;
1912 if (pos == FD_SECTOR_LEN - 1 ||
1913 fdctrl->data_pos == fdctrl->data_len) {
1914 cur_drv = get_cur_drv(fdctrl);
1915 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1916 FLOPPY_DPRINTF("error writing sector %d\n",
1917 fd_sector(cur_drv));
1918 return;
1919 }
1920 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1921 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1922 fd_sector(cur_drv));
1923 return;
1924 }
1925 }
1926 /* Switch from transfer mode to status mode
1927 * then from status mode to command mode
1928 */
1929 if (fdctrl->data_pos == fdctrl->data_len)
1930 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1931 return;
1932 }
1933 if (fdctrl->data_pos == 0) {
1934 /* Command */
1935 pos = command_to_handler[value & 0xff];
1936 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1937 fdctrl->data_len = handlers[pos].parameters + 1;
1938 fdctrl->msr |= FD_MSR_CMDBUSY;
1939 }
1940
1941 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1942 fdctrl->fifo[fdctrl->data_pos++] = value;
1943 if (fdctrl->data_pos == fdctrl->data_len) {
1944 /* We now have all parameters
1945 * and will be able to treat the command
1946 */
1947 if (fdctrl->data_state & FD_STATE_FORMAT) {
1948 fdctrl_format_sector(fdctrl);
1949 return;
1950 }
1951
1952 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1953 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1954 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1955 }
1956 }
1957
1958 static void fdctrl_result_timer(void *opaque)
1959 {
1960 FDCtrl *fdctrl = opaque;
1961 FDrive *cur_drv = get_cur_drv(fdctrl);
1962
1963 /* Pretend we are spinning.
1964 * This is needed for Coherent, which uses READ ID to check for
1965 * sector interleaving.
1966 */
1967 if (cur_drv->last_sect != 0) {
1968 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1969 }
1970 /* READ_ID can't automatically succeed! */
1971 if (fdctrl->check_media_rate &&
1972 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1973 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1974 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1975 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1976 } else {
1977 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1978 }
1979 }
1980
1981 static void fdctrl_change_cb(void *opaque, bool load)
1982 {
1983 FDrive *drive = opaque;
1984
1985 drive->media_changed = 1;
1986 fd_revalidate(drive);
1987 }
1988
1989 static const BlockDevOps fdctrl_block_ops = {
1990 .change_media_cb = fdctrl_change_cb,
1991 };
1992
1993 /* Init functions */
1994 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1995 {
1996 unsigned int i;
1997 FDrive *drive;
1998
1999 for (i = 0; i < MAX_FD; i++) {
2000 drive = &fdctrl->drives[i];
2001 drive->fdctrl = fdctrl;
2002
2003 if (drive->bs) {
2004 if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2005 error_report("fdc doesn't support drive option werror");
2006 return -1;
2007 }
2008 if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2009 error_report("fdc doesn't support drive option rerror");
2010 return -1;
2011 }
2012 }
2013
2014 fd_init(drive);
2015 fdctrl_change_cb(drive, 0);
2016 if (drive->bs) {
2017 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
2018 }
2019 }
2020 return 0;
2021 }
2022
2023 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2024 {
2025 DeviceState *dev;
2026 ISADevice *isadev;
2027
2028 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2029 if (!isadev) {
2030 return NULL;
2031 }
2032 dev = DEVICE(isadev);
2033
2034 if (fds[0]) {
2035 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
2036 }
2037 if (fds[1]) {
2038 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
2039 }
2040 qdev_init_nofail(dev);
2041
2042 return isadev;
2043 }
2044
2045 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2046 hwaddr mmio_base, DriveInfo **fds)
2047 {
2048 FDCtrl *fdctrl;
2049 DeviceState *dev;
2050 FDCtrlSysBus *sys;
2051
2052 dev = qdev_create(NULL, "sysbus-fdc");
2053 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
2054 fdctrl = &sys->state;
2055 fdctrl->dma_chann = dma_chann; /* FIXME */
2056 if (fds[0]) {
2057 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
2058 }
2059 if (fds[1]) {
2060 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
2061 }
2062 qdev_init_nofail(dev);
2063 sysbus_connect_irq(&sys->busdev, 0, irq);
2064 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
2065 }
2066
2067 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2068 DriveInfo **fds, qemu_irq *fdc_tc)
2069 {
2070 DeviceState *dev;
2071 FDCtrlSysBus *sys;
2072
2073 dev = qdev_create(NULL, "SUNW,fdtwo");
2074 if (fds[0]) {
2075 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
2076 }
2077 qdev_init_nofail(dev);
2078 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
2079 sysbus_connect_irq(&sys->busdev, 0, irq);
2080 sysbus_mmio_map(&sys->busdev, 0, io_base);
2081 *fdc_tc = qdev_get_gpio_in(dev, 0);
2082 }
2083
2084 static int fdctrl_init_common(FDCtrl *fdctrl)
2085 {
2086 int i, j;
2087 static int command_tables_inited = 0;
2088
2089 /* Fill 'command_to_handler' lookup table */
2090 if (!command_tables_inited) {
2091 command_tables_inited = 1;
2092 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2093 for (j = 0; j < sizeof(command_to_handler); j++) {
2094 if ((j & handlers[i].mask) == handlers[i].value) {
2095 command_to_handler[j] = i;
2096 }
2097 }
2098 }
2099 }
2100
2101 FLOPPY_DPRINTF("init controller\n");
2102 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2103 fdctrl->fifo_size = 512;
2104 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
2105 fdctrl_result_timer, fdctrl);
2106
2107 fdctrl->version = 0x90; /* Intel 82078 controller */
2108 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2109 fdctrl->num_floppies = MAX_FD;
2110
2111 if (fdctrl->dma_chann != -1)
2112 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2113 return fdctrl_connect_drives(fdctrl);
2114 }
2115
2116 static const MemoryRegionPortio fdc_portio_list[] = {
2117 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2118 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2119 PORTIO_END_OF_LIST(),
2120 };
2121
2122 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2123 {
2124 ISADevice *isadev = ISA_DEVICE(dev);
2125 FDCtrlISABus *isa = ISA_FDC(dev);
2126 FDCtrl *fdctrl = &isa->state;
2127 int ret;
2128
2129 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2130 "fdc");
2131
2132 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2133 fdctrl->dma_chann = isa->dma;
2134
2135 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2136 ret = fdctrl_init_common(fdctrl);
2137 if (ret < 0) {
2138 error_setg(errp, "Floppy init failed.");
2139 return;
2140 }
2141
2142 add_boot_device_path(isa->bootindexA, dev, "/floppy@0");
2143 add_boot_device_path(isa->bootindexB, dev, "/floppy@1");
2144 }
2145
2146 static int sysbus_fdc_init1(SysBusDevice *dev)
2147 {
2148 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2149 FDCtrl *fdctrl = &sys->state;
2150 int ret;
2151
2152 memory_region_init_io(&fdctrl->iomem, NULL, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
2153 sysbus_init_mmio(dev, &fdctrl->iomem);
2154 sysbus_init_irq(dev, &fdctrl->irq);
2155 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2156 fdctrl->dma_chann = -1;
2157
2158 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2159 ret = fdctrl_init_common(fdctrl);
2160
2161 return ret;
2162 }
2163
2164 static int sun4m_fdc_init1(SysBusDevice *dev)
2165 {
2166 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2167
2168 memory_region_init_io(&fdctrl->iomem, NULL, &fdctrl_mem_strict_ops, fdctrl,
2169 "fdctrl", 0x08);
2170 sysbus_init_mmio(dev, &fdctrl->iomem);
2171 sysbus_init_irq(dev, &fdctrl->irq);
2172 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2173
2174 fdctrl->sun4m = 1;
2175 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2176 return fdctrl_init_common(fdctrl);
2177 }
2178
2179 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2180 {
2181 FDCtrlISABus *isa = ISA_FDC(fdc);
2182
2183 return isa->state.drives[i].drive;
2184 }
2185
2186 static const VMStateDescription vmstate_isa_fdc ={
2187 .name = "fdc",
2188 .version_id = 2,
2189 .minimum_version_id = 2,
2190 .fields = (VMStateField []) {
2191 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2192 VMSTATE_END_OF_LIST()
2193 }
2194 };
2195
2196 static Property isa_fdc_properties[] = {
2197 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2198 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2199 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2200 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2201 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2202 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2203 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2204 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2205 0, true),
2206 DEFINE_PROP_END_OF_LIST(),
2207 };
2208
2209 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2210 {
2211 DeviceClass *dc = DEVICE_CLASS(klass);
2212
2213 dc->realize = isabus_fdc_realize;
2214 dc->fw_name = "fdc";
2215 dc->no_user = 1;
2216 dc->reset = fdctrl_external_reset_isa;
2217 dc->vmsd = &vmstate_isa_fdc;
2218 dc->props = isa_fdc_properties;
2219 }
2220
2221 static const TypeInfo isa_fdc_info = {
2222 .name = TYPE_ISA_FDC,
2223 .parent = TYPE_ISA_DEVICE,
2224 .instance_size = sizeof(FDCtrlISABus),
2225 .class_init = isabus_fdc_class_init,
2226 };
2227
2228 static const VMStateDescription vmstate_sysbus_fdc ={
2229 .name = "fdc",
2230 .version_id = 2,
2231 .minimum_version_id = 2,
2232 .fields = (VMStateField []) {
2233 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2234 VMSTATE_END_OF_LIST()
2235 }
2236 };
2237
2238 static Property sysbus_fdc_properties[] = {
2239 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2240 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2241 DEFINE_PROP_END_OF_LIST(),
2242 };
2243
2244 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2245 {
2246 DeviceClass *dc = DEVICE_CLASS(klass);
2247 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2248
2249 k->init = sysbus_fdc_init1;
2250 dc->reset = fdctrl_external_reset_sysbus;
2251 dc->vmsd = &vmstate_sysbus_fdc;
2252 dc->props = sysbus_fdc_properties;
2253 }
2254
2255 static const TypeInfo sysbus_fdc_info = {
2256 .name = "sysbus-fdc",
2257 .parent = TYPE_SYS_BUS_DEVICE,
2258 .instance_size = sizeof(FDCtrlSysBus),
2259 .class_init = sysbus_fdc_class_init,
2260 };
2261
2262 static Property sun4m_fdc_properties[] = {
2263 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2264 DEFINE_PROP_END_OF_LIST(),
2265 };
2266
2267 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2268 {
2269 DeviceClass *dc = DEVICE_CLASS(klass);
2270 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2271
2272 k->init = sun4m_fdc_init1;
2273 dc->reset = fdctrl_external_reset_sysbus;
2274 dc->vmsd = &vmstate_sysbus_fdc;
2275 dc->props = sun4m_fdc_properties;
2276 }
2277
2278 static const TypeInfo sun4m_fdc_info = {
2279 .name = "SUNW,fdtwo",
2280 .parent = TYPE_SYS_BUS_DEVICE,
2281 .instance_size = sizeof(FDCtrlSysBus),
2282 .class_init = sun4m_fdc_class_init,
2283 };
2284
2285 static void fdc_register_types(void)
2286 {
2287 type_register_static(&isa_fdc_info);
2288 type_register_static(&sysbus_fdc_info);
2289 type_register_static(&sun4m_fdc_info);
2290 }
2291
2292 type_init(fdc_register_types)
AR7 emulation for QEMU