hw/arm/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "hw/sysbus.h"
  19 #include "hw/arm/arm.h"
  20 #include "net/net.h"
  21 #include "exec/address-spaces.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/boards.h"
  24 #include "hw/block/flash.h"
  25 #include "sysemu/blockdev.h"
  26 #include "hw/loader.h"
  27 #include "hw/ssi.h"
  28
  29 #define NUM_SPI_FLASHES 4
  30 #define NUM_QSPI_FLASHES 2
  31 #define NUM_QSPI_BUSSES 2
  32
  33 #define FLASH_SIZE (64 * 1024 * 1024)
  34 #define FLASH_SECTOR_SIZE (128 * 1024)
  35
  36 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  37
  38 static const int dma_irqs[8] = {
  39     46, 47, 48, 49, 72, 73, 74, 75
  40 };
  41
  42 static struct arm_boot_info zynq_binfo = {};
  43
  44 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  45 {
  46     DeviceState *dev;
  47     SysBusDevice *s;
  48
  49     qemu_check_nic_model(nd, "cadence_gem");
  50     dev = qdev_create(NULL, "cadence_gem");
  51     qdev_set_nic_properties(dev, nd);
  52     qdev_init_nofail(dev);
  53     s = SYS_BUS_DEVICE(dev);
  54     sysbus_mmio_map(s, 0, base);
  55     sysbus_connect_irq(s, 0, irq);
  56 }
  57
  58 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
  59                                          bool is_qspi)
  60 {
  61     DeviceState *dev;
  62     SysBusDevice *busdev;
  63     SSIBus *spi;
  64     DeviceState *flash_dev;
  65     int i, j;
  66     int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
  67     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
  68
  69     dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
  70     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
  71     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
  72     qdev_prop_set_uint8(dev, "num-busses", num_busses);
  73     qdev_init_nofail(dev);
  74     busdev = SYS_BUS_DEVICE(dev);
  75     sysbus_mmio_map(busdev, 0, base_addr);
  76     if (is_qspi) {
  77         sysbus_mmio_map(busdev, 1, 0xFC000000);
  78     }
  79     sysbus_connect_irq(busdev, 0, irq);
  80
  81     for (i = 0; i < num_busses; ++i) {
  82         char bus_name[16];
  83         qemu_irq cs_line;
  84
  85         snprintf(bus_name, 16, "spi%d", i);
  86         spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
  87
  88         for (j = 0; j < num_ss; ++j) {
  89             flash_dev = ssi_create_slave(spi, "n25q128");
  90
  91             cs_line = qdev_get_gpio_in(flash_dev, 0);
  92             sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
  93         }
  94     }
  95
  96 }
  97
  98 static void zynq_init(QEMUMachineInitArgs *args)
  99 {
 100     ram_addr_t ram_size = args->ram_size;
 101     const char *cpu_model = args->cpu_model;
 102     const char *kernel_filename = args->kernel_filename;
 103     const char *kernel_cmdline = args->kernel_cmdline;
 104     const char *initrd_filename = args->initrd_filename;
 105     ARMCPU *cpu;
 106     MemoryRegion *address_space_mem = get_system_memory();
 107     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
 108     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
 109     DeviceState *dev;
 110     SysBusDevice *busdev;
 111     qemu_irq *irqp;
 112     qemu_irq pic[64];
 113     NICInfo *nd;
 114     int n;
 115     qemu_irq cpu_irq;
 116
 117     if (!cpu_model) {
 118         cpu_model = "cortex-a9";
 119     }
 120
 121     cpu = cpu_arm_init(cpu_model);
 122     if (!cpu) {
 123         fprintf(stderr, "Unable to find CPU definition\n");
 124         exit(1);
 125     }
 126     irqp = arm_pic_init_cpu(cpu);
 127     cpu_irq = irqp[ARM_PIC_CPU_IRQ];
 128
 129     /* max 2GB ram */
 130     if (ram_size > 0x80000000) {
 131         ram_size = 0x80000000;
 132     }
 133
 134     /* DDR remapped to address zero.  */
 135     memory_region_init_ram(ext_ram, NULL, "zynq.ext_ram", ram_size);
 136     vmstate_register_ram_global(ext_ram);
 137     memory_region_add_subregion(address_space_mem, 0, ext_ram);
 138
 139     /* 256K of on-chip memory */
 140     memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10);
 141     vmstate_register_ram_global(ocm_ram);
 142     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 143
 144     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 145
 146     /* AMD */
 147     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
 148                           dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
 149                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
 150                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 151                               0);
 152
 153     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 154     qdev_init_nofail(dev);
 155     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 156
 157     dev = qdev_create(NULL, "a9mpcore_priv");
 158     qdev_prop_set_uint32(dev, "num-cpu", 1);
 159     qdev_init_nofail(dev);
 160     busdev = SYS_BUS_DEVICE(dev);
 161     sysbus_mmio_map(busdev, 0, 0xF8F00000);
 162     sysbus_connect_irq(busdev, 0, cpu_irq);
 163
 164     for (n = 0; n < 64; n++) {
 165         pic[n] = qdev_get_gpio_in(dev, n);
 166     }
 167
 168     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
 169     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
 170     zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
 171
 172     sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
 173     sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
 174
 175     sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
 176     sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
 177
 178     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 179             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 180     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 181             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 182
 183     for (n = 0; n < nb_nics; n++) {
 184         nd = &nd_table[n];
 185         if (n == 0) {
 186             gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]);
 187         } else if (n == 1) {
 188             gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]);
 189         }
 190     }
 191
 192     dev = qdev_create(NULL, "generic-sdhci");
 193     qdev_init_nofail(dev);
 194     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
 195     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
 196
 197     dev = qdev_create(NULL, "generic-sdhci");
 198     qdev_init_nofail(dev);
 199     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
 200     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
 201
 202     dev = qdev_create(NULL, "pl330");
 203     qdev_prop_set_uint8(dev, "num_chnls",  8);
 204     qdev_prop_set_uint8(dev, "num_periph_req",  4);
 205     qdev_prop_set_uint8(dev, "num_events",  16);
 206
 207     qdev_prop_set_uint8(dev, "data_width",  64);
 208     qdev_prop_set_uint8(dev, "wr_cap",  8);
 209     qdev_prop_set_uint8(dev, "wr_q_dep",  16);
 210     qdev_prop_set_uint8(dev, "rd_cap",  8);
 211     qdev_prop_set_uint8(dev, "rd_q_dep",  16);
 212     qdev_prop_set_uint16(dev, "data_buffer_dep",  256);
 213
 214     qdev_init_nofail(dev);
 215     busdev = SYS_BUS_DEVICE(dev);
 216     sysbus_mmio_map(busdev, 0, 0xF8003000);
 217     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
 218     for (n = 0; n < 8; ++n) { /* event irqs */
 219         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
 220     }
 221
 222     zynq_binfo.ram_size = ram_size;
 223     zynq_binfo.kernel_filename = kernel_filename;
 224     zynq_binfo.kernel_cmdline = kernel_cmdline;
 225     zynq_binfo.initrd_filename = initrd_filename;
 226     zynq_binfo.nb_cpus = 1;
 227     zynq_binfo.board_id = 0xd32;
 228     zynq_binfo.loader_start = 0;
 229     arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo);
 230 }
 231
 232 static QEMUMachine zynq_machine = {
 233     .name = "xilinx-zynq-a9",
 234     .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
 235     .init = zynq_init,
 236     .block_default_type = IF_SCSI,
 237     .max_cpus = 1,
 238     .no_sdcard = 1,
 239     DEFAULT_MACHINE_OPTIONS,
 240 };
 241
 242 static void zynq_machine_init(void)
 243 {
 244     qemu_register_machine(&zynq_machine);
 245 }
 246
 247 machine_init(zynq_machine_init);