2 * Calxeda Highbank SoC emulation
4 * Copyright (c) 2010-2012 Calxeda
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "hw/sysbus.h"
21 #include "hw/arm/arm.h"
22 #include "hw/devices.h"
23 #include "hw/loader.h"
25 #include "sysemu/sysemu.h"
26 #include "hw/boards.h"
27 #include "sysemu/blockdev.h"
28 #include "exec/address-spaces.h"
30 #define SMP_BOOT_ADDR 0x100
31 #define SMP_BOOT_REG 0x40
32 #define GIC_BASE_ADDR 0xfff10000
38 static void hb_write_secondary(ARMCPU
*cpu
, const struct arm_boot_info
*info
)
41 uint32_t smpboot
[] = {
42 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
43 0xe210000f, /* ands r0, r0, #0x0f */
44 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
45 0xe0830200, /* add r0, r3, r0, lsl #4 */
46 0xe59f2024, /* ldr r2, privbase */
47 0xe3a01001, /* mov r1, #1 */
48 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
49 0xe3a010ff, /* mov r1, #0xff */
50 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
53 0xe5901000, /* ldr r1, [r0] */
54 0xe1110001, /* tst r1, r1 */
55 0x0afffffb, /* beq <wfi> */
56 0xe12fff11, /* bx r1 */
57 GIC_BASE_ADDR
/* privbase: gic address. */
59 for (n
= 0; n
< ARRAY_SIZE(smpboot
); n
++) {
60 smpboot
[n
] = tswap32(smpboot
[n
]);
62 rom_add_blob_fixed("smpboot", smpboot
, sizeof(smpboot
), SMP_BOOT_ADDR
);
65 static void hb_reset_secondary(ARMCPU
*cpu
, const struct arm_boot_info
*info
)
67 CPUARMState
*env
= &cpu
->env
;
69 switch (info
->nb_cpus
) {
71 stl_phys_notdirty(SMP_BOOT_REG
+ 0x30, 0);
73 stl_phys_notdirty(SMP_BOOT_REG
+ 0x20, 0);
75 stl_phys_notdirty(SMP_BOOT_REG
+ 0x10, 0);
76 env
->regs
[15] = SMP_BOOT_ADDR
;
83 #define NUM_REGS 0x200
84 static void hb_regs_write(void *opaque
, hwaddr offset
,
85 uint64_t value
, unsigned size
)
87 uint32_t *regs
= opaque
;
89 if (offset
== 0xf00) {
90 if (value
== 1 || value
== 2) {
91 qemu_system_reset_request();
92 } else if (value
== 3) {
93 qemu_system_shutdown_request();
97 regs
[offset
/4] = value
;
100 static uint64_t hb_regs_read(void *opaque
, hwaddr offset
,
103 uint32_t *regs
= opaque
;
104 uint32_t value
= regs
[offset
/4];
106 if ((offset
== 0x100) || (offset
== 0x108) || (offset
== 0x10C)) {
113 static const MemoryRegionOps hb_mem_ops
= {
114 .read
= hb_regs_read
,
115 .write
= hb_regs_write
,
116 .endianness
= DEVICE_NATIVE_ENDIAN
,
122 uint32_t regs
[NUM_REGS
];
125 static VMStateDescription vmstate_highbank_regs
= {
126 .name
= "highbank-regs",
128 .minimum_version_id
= 0,
129 .minimum_version_id_old
= 0,
130 .fields
= (VMStateField
[]) {
131 VMSTATE_UINT32_ARRAY(regs
, HighbankRegsState
, NUM_REGS
),
132 VMSTATE_END_OF_LIST(),
136 static void highbank_regs_reset(DeviceState
*dev
)
138 SysBusDevice
*sys_dev
= SYS_BUS_DEVICE(dev
);
139 HighbankRegsState
*s
= FROM_SYSBUS(HighbankRegsState
, sys_dev
);
141 s
->regs
[0x40] = 0x05F20121;
143 s
->regs
[0x42] = 0x05F30121;
144 s
->regs
[0x43] = 0x05F40121;
147 static int highbank_regs_init(SysBusDevice
*dev
)
149 HighbankRegsState
*s
= FROM_SYSBUS(HighbankRegsState
, dev
);
151 s
->iomem
= g_new(MemoryRegion
, 1);
152 memory_region_init_io(s
->iomem
, NULL
, &hb_mem_ops
, s
->regs
, "highbank_regs",
154 sysbus_init_mmio(dev
, s
->iomem
);
159 static void highbank_regs_class_init(ObjectClass
*klass
, void *data
)
161 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
162 DeviceClass
*dc
= DEVICE_CLASS(klass
);
164 sbc
->init
= highbank_regs_init
;
165 dc
->desc
= "Calxeda Highbank registers";
166 dc
->vmsd
= &vmstate_highbank_regs
;
167 dc
->reset
= highbank_regs_reset
;
170 static const TypeInfo highbank_regs_info
= {
171 .name
= "highbank-regs",
172 .parent
= TYPE_SYS_BUS_DEVICE
,
173 .instance_size
= sizeof(HighbankRegsState
),
174 .class_init
= highbank_regs_class_init
,
177 static void highbank_regs_register_types(void)
179 type_register_static(&highbank_regs_info
);
182 type_init(highbank_regs_register_types
)
184 static struct arm_boot_info highbank_binfo
;
186 /* ram_size must be set to match the upper bound of memory in the
187 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
188 * normally 0xff900000 or -m 4089. When running this board on a
189 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
190 * device tree and pass -m 2047 to QEMU.
192 static void highbank_init(QEMUMachineInitArgs
*args
)
194 ram_addr_t ram_size
= args
->ram_size
;
195 const char *cpu_model
= args
->cpu_model
;
196 const char *kernel_filename
= args
->kernel_filename
;
197 const char *kernel_cmdline
= args
->kernel_cmdline
;
198 const char *initrd_filename
= args
->initrd_filename
;
200 SysBusDevice
*busdev
;
205 MemoryRegion
*sysram
;
207 MemoryRegion
*sysmem
;
208 char *sysboot_filename
;
211 cpu_model
= "cortex-a9";
214 for (n
= 0; n
< smp_cpus
; n
++) {
216 cpu
= cpu_arm_init(cpu_model
);
218 fprintf(stderr
, "Unable to find CPU definition\n");
222 /* This will become a QOM property eventually */
223 cpu
->reset_cbar
= GIC_BASE_ADDR
;
224 irqp
= arm_pic_init_cpu(cpu
);
225 cpu_irq
[n
] = irqp
[ARM_PIC_CPU_IRQ
];
228 sysmem
= get_system_memory();
229 dram
= g_new(MemoryRegion
, 1);
230 memory_region_init_ram(dram
, NULL
, "highbank.dram", ram_size
);
231 /* SDRAM at address zero. */
232 memory_region_add_subregion(sysmem
, 0, dram
);
234 sysram
= g_new(MemoryRegion
, 1);
235 memory_region_init_ram(sysram
, NULL
, "highbank.sysram", 0x8000);
236 memory_region_add_subregion(sysmem
, 0xfff88000, sysram
);
237 if (bios_name
!= NULL
) {
238 sysboot_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
239 if (sysboot_filename
!= NULL
) {
240 uint32_t filesize
= get_image_size(sysboot_filename
);
241 if (load_image_targphys("sysram.bin", 0xfff88000, filesize
) < 0) {
242 hw_error("Unable to load %s\n", bios_name
);
245 hw_error("Unable to find %s\n", bios_name
);
249 dev
= qdev_create(NULL
, "a9mpcore_priv");
250 qdev_prop_set_uint32(dev
, "num-cpu", smp_cpus
);
251 qdev_prop_set_uint32(dev
, "num-irq", NIRQ_GIC
);
252 qdev_init_nofail(dev
);
253 busdev
= SYS_BUS_DEVICE(dev
);
254 sysbus_mmio_map(busdev
, 0, GIC_BASE_ADDR
);
255 for (n
= 0; n
< smp_cpus
; n
++) {
256 sysbus_connect_irq(busdev
, n
, cpu_irq
[n
]);
259 for (n
= 0; n
< 128; n
++) {
260 pic
[n
] = qdev_get_gpio_in(dev
, n
);
263 dev
= qdev_create(NULL
, "l2x0");
264 qdev_init_nofail(dev
);
265 busdev
= SYS_BUS_DEVICE(dev
);
266 sysbus_mmio_map(busdev
, 0, 0xfff12000);
268 dev
= qdev_create(NULL
, "sp804");
269 qdev_prop_set_uint32(dev
, "freq0", 150000000);
270 qdev_prop_set_uint32(dev
, "freq1", 150000000);
271 qdev_init_nofail(dev
);
272 busdev
= SYS_BUS_DEVICE(dev
);
273 sysbus_mmio_map(busdev
, 0, 0xfff34000);
274 sysbus_connect_irq(busdev
, 0, pic
[18]);
275 sysbus_create_simple("pl011", 0xfff36000, pic
[20]);
277 dev
= qdev_create(NULL
, "highbank-regs");
278 qdev_init_nofail(dev
);
279 busdev
= SYS_BUS_DEVICE(dev
);
280 sysbus_mmio_map(busdev
, 0, 0xfff3c000);
282 sysbus_create_simple("pl061", 0xfff30000, pic
[14]);
283 sysbus_create_simple("pl061", 0xfff31000, pic
[15]);
284 sysbus_create_simple("pl061", 0xfff32000, pic
[16]);
285 sysbus_create_simple("pl061", 0xfff33000, pic
[17]);
286 sysbus_create_simple("pl031", 0xfff35000, pic
[19]);
287 sysbus_create_simple("pl022", 0xfff39000, pic
[23]);
289 sysbus_create_simple("sysbus-ahci", 0xffe08000, pic
[83]);
291 if (nd_table
[0].used
) {
292 qemu_check_nic_model(&nd_table
[0], "xgmac");
293 dev
= qdev_create(NULL
, "xgmac");
294 qdev_set_nic_properties(dev
, &nd_table
[0]);
295 qdev_init_nofail(dev
);
296 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xfff50000);
297 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[77]);
298 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1, pic
[78]);
299 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2, pic
[79]);
301 qemu_check_nic_model(&nd_table
[1], "xgmac");
302 dev
= qdev_create(NULL
, "xgmac");
303 qdev_set_nic_properties(dev
, &nd_table
[1]);
304 qdev_init_nofail(dev
);
305 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xfff51000);
306 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[80]);
307 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 1, pic
[81]);
308 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 2, pic
[82]);
311 highbank_binfo
.ram_size
= ram_size
;
312 highbank_binfo
.kernel_filename
= kernel_filename
;
313 highbank_binfo
.kernel_cmdline
= kernel_cmdline
;
314 highbank_binfo
.initrd_filename
= initrd_filename
;
315 /* highbank requires a dtb in order to boot, and the dtb will override
316 * the board ID. The following value is ignored, so set it to -1 to be
317 * clear that the value is meaningless.
319 highbank_binfo
.board_id
= -1;
320 highbank_binfo
.nb_cpus
= smp_cpus
;
321 highbank_binfo
.loader_start
= 0;
322 highbank_binfo
.write_secondary_boot
= hb_write_secondary
;
323 highbank_binfo
.secondary_cpu_reset_hook
= hb_reset_secondary
;
324 arm_load_kernel(arm_env_get_cpu(first_cpu
), &highbank_binfo
);
327 static QEMUMachine highbank_machine
= {
329 .desc
= "Calxeda Highbank (ECX-1000)",
330 .init
= highbank_init
,
331 .block_default_type
= IF_SCSI
,
333 DEFAULT_MACHINE_OPTIONS
,
336 static void highbank_machine_init(void)
338 qemu_register_machine(&highbank_machine
);
341 machine_init(highbank_machine_init
);