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target-arm: Add v8 mmu translation support
[qemu/ar7.git] / target-arm / helper.c
blob4b6c1b63622bef4c8434626ac06aa57caa67d6ff
1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "helper.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include <zlib.h> /* For crc32 */
11
12 #ifndef CONFIG_USER_ONLY
13 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
14 int access_type, int is_user,
15 hwaddr *phys_ptr, int *prot,
16 target_ulong *page_size);
17
18 /* Definitions for the PMCCNTR and PMCR registers */
19 #define PMCRD 0x8
20 #define PMCRC 0x4
21 #define PMCRE 0x1
22 #endif
23
24 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
25 {
26 int nregs;
27
28 /* VFP data registers are always little-endian. */
29 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
30 if (reg < nregs) {
31 stfq_le_p(buf, env->vfp.regs[reg]);
32 return 8;
33 }
34 if (arm_feature(env, ARM_FEATURE_NEON)) {
35 /* Aliases for Q regs. */
36 nregs += 16;
37 if (reg < nregs) {
38 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
39 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
40 return 16;
41 }
42 }
43 switch (reg - nregs) {
44 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
45 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
46 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
47 }
48 return 0;
49 }
50
51 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
52 {
53 int nregs;
54
55 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
56 if (reg < nregs) {
57 env->vfp.regs[reg] = ldfq_le_p(buf);
58 return 8;
59 }
60 if (arm_feature(env, ARM_FEATURE_NEON)) {
61 nregs += 16;
62 if (reg < nregs) {
63 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
64 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
65 return 16;
66 }
67 }
68 switch (reg - nregs) {
69 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
70 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
72 }
73 return 0;
74 }
75
76 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
77 {
78 switch (reg) {
79 case 0 ... 31:
80 /* 128 bit FP register */
81 stfq_le_p(buf, env->vfp.regs[reg * 2]);
82 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
83 return 16;
84 case 32:
85 /* FPSR */
86 stl_p(buf, vfp_get_fpsr(env));
87 return 4;
88 case 33:
89 /* FPCR */
90 stl_p(buf, vfp_get_fpcr(env));
91 return 4;
92 default:
93 return 0;
94 }
95 }
96
97 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
98 {
99 switch (reg) {
100 case 0 ... 31:
101 /* 128 bit FP register */
102 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
103 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
104 return 16;
105 case 32:
106 /* FPSR */
107 vfp_set_fpsr(env, ldl_p(buf));
108 return 4;
109 case 33:
110 /* FPCR */
111 vfp_set_fpcr(env, ldl_p(buf));
112 return 4;
113 default:
114 return 0;
115 }
116 }
117
118 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
119 {
120 if (cpreg_field_is_64bit(ri)) {
121 return CPREG_FIELD64(env, ri);
122 } else {
123 return CPREG_FIELD32(env, ri);
124 }
125 }
126
127 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
128 uint64_t value)
129 {
130 if (cpreg_field_is_64bit(ri)) {
131 CPREG_FIELD64(env, ri) = value;
132 } else {
133 CPREG_FIELD32(env, ri) = value;
134 }
135 }
136
137 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
138 {
139 /* Raw read of a coprocessor register (as needed for migration, etc). */
140 if (ri->type & ARM_CP_CONST) {
141 return ri->resetvalue;
142 } else if (ri->raw_readfn) {
143 return ri->raw_readfn(env, ri);
144 } else if (ri->readfn) {
145 return ri->readfn(env, ri);
146 } else {
147 return raw_read(env, ri);
148 }
149 }
150
151 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
152 uint64_t v)
153 {
154 /* Raw write of a coprocessor register (as needed for migration, etc).
155 * Note that constant registers are treated as write-ignored; the
156 * caller should check for success by whether a readback gives the
157 * value written.
158 */
159 if (ri->type & ARM_CP_CONST) {
160 return;
161 } else if (ri->raw_writefn) {
162 ri->raw_writefn(env, ri, v);
163 } else if (ri->writefn) {
164 ri->writefn(env, ri, v);
165 } else {
166 raw_write(env, ri, v);
167 }
168 }
169
170 bool write_cpustate_to_list(ARMCPU *cpu)
171 {
172 /* Write the coprocessor state from cpu->env to the (index,value) list. */
173 int i;
174 bool ok = true;
175
176 for (i = 0; i < cpu->cpreg_array_len; i++) {
177 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
178 const ARMCPRegInfo *ri;
179
180 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
181 if (!ri) {
182 ok = false;
183 continue;
184 }
185 if (ri->type & ARM_CP_NO_MIGRATE) {
186 continue;
187 }
188 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
189 }
190 return ok;
191 }
192
193 bool write_list_to_cpustate(ARMCPU *cpu)
194 {
195 int i;
196 bool ok = true;
197
198 for (i = 0; i < cpu->cpreg_array_len; i++) {
199 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
200 uint64_t v = cpu->cpreg_values[i];
201 const ARMCPRegInfo *ri;
202
203 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
204 if (!ri) {
205 ok = false;
206 continue;
207 }
208 if (ri->type & ARM_CP_NO_MIGRATE) {
209 continue;
210 }
211 /* Write value and confirm it reads back as written
212 * (to catch read-only registers and partially read-only
213 * registers where the incoming migration value doesn't match)
214 */
215 write_raw_cp_reg(&cpu->env, ri, v);
216 if (read_raw_cp_reg(&cpu->env, ri) != v) {
217 ok = false;
218 }
219 }
220 return ok;
221 }
222
223 static void add_cpreg_to_list(gpointer key, gpointer opaque)
224 {
225 ARMCPU *cpu = opaque;
226 uint64_t regidx;
227 const ARMCPRegInfo *ri;
228
229 regidx = *(uint32_t *)key;
230 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
231
232 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
233 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
234 /* The value array need not be initialized at this point */
235 cpu->cpreg_array_len++;
236 }
237 }
238
239 static void count_cpreg(gpointer key, gpointer opaque)
240 {
241 ARMCPU *cpu = opaque;
242 uint64_t regidx;
243 const ARMCPRegInfo *ri;
244
245 regidx = *(uint32_t *)key;
246 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
247
248 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
249 cpu->cpreg_array_len++;
250 }
251 }
252
253 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
254 {
255 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
256 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
257
258 if (aidx > bidx) {
259 return 1;
260 }
261 if (aidx < bidx) {
262 return -1;
263 }
264 return 0;
265 }
266
267 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
268 {
269 GList **plist = udata;
270
271 *plist = g_list_prepend(*plist, key);
272 }
273
274 void init_cpreg_list(ARMCPU *cpu)
275 {
276 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
277 * Note that we require cpreg_tuples[] to be sorted by key ID.
278 */
279 GList *keys = NULL;
280 int arraylen;
281
282 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
283
284 keys = g_list_sort(keys, cpreg_key_compare);
285
286 cpu->cpreg_array_len = 0;
287
288 g_list_foreach(keys, count_cpreg, cpu);
289
290 arraylen = cpu->cpreg_array_len;
291 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
292 cpu->cpreg_values = g_new(uint64_t, arraylen);
293 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
294 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
295 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
296 cpu->cpreg_array_len = 0;
297
298 g_list_foreach(keys, add_cpreg_to_list, cpu);
299
300 assert(cpu->cpreg_array_len == arraylen);
301
302 g_list_free(keys);
303 }
304
305 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
306 {
307 ARMCPU *cpu = arm_env_get_cpu(env);
308
309 env->cp15.c3 = value;
310 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
311 }
312
313 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
314 {
315 ARMCPU *cpu = arm_env_get_cpu(env);
316
317 if (env->cp15.c13_fcse != value) {
318 /* Unlike real hardware the qemu TLB uses virtual addresses,
319 * not modified virtual addresses, so this causes a TLB flush.
320 */
321 tlb_flush(CPU(cpu), 1);
322 env->cp15.c13_fcse = value;
323 }
324 }
325
326 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
327 uint64_t value)
328 {
329 ARMCPU *cpu = arm_env_get_cpu(env);
330
331 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
332 /* For VMSA (when not using the LPAE long descriptor page table
333 * format) this register includes the ASID, so do a TLB flush.
334 * For PMSA it is purely a process ID and no action is needed.
335 */
336 tlb_flush(CPU(cpu), 1);
337 }
338 env->cp15.c13_context = value;
339 }
340
341 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
342 uint64_t value)
343 {
344 /* Invalidate all (TLBIALL) */
345 ARMCPU *cpu = arm_env_get_cpu(env);
346
347 tlb_flush(CPU(cpu), 1);
348 }
349
350 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
351 uint64_t value)
352 {
353 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
354 ARMCPU *cpu = arm_env_get_cpu(env);
355
356 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
357 }
358
359 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
360 uint64_t value)
361 {
362 /* Invalidate by ASID (TLBIASID) */
363 ARMCPU *cpu = arm_env_get_cpu(env);
364
365 tlb_flush(CPU(cpu), value == 0);
366 }
367
368 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
369 uint64_t value)
370 {
371 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
372 ARMCPU *cpu = arm_env_get_cpu(env);
373
374 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
375 }
376
377 static const ARMCPRegInfo cp_reginfo[] = {
378 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
379 * version" bits will read as a reserved value, which should cause
380 * Linux to not try to use the debug hardware.
381 */
382 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
383 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
384 /* MMU Domain access control / MPU write buffer control */
385 { .name = "DACR", .cp = 15,
386 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
387 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
388 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
389 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
390 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
391 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
392 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
393 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
394 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
395 /* ??? This covers not just the impdef TLB lockdown registers but also
396 * some v7VMSA registers relating to TEX remap, so it is overly broad.
397 */
398 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
399 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
400 /* MMU TLB control. Note that the wildcarding means we cover not just
401 * the unified TLB ops but also the dside/iside/inner-shareable variants.
402 */
403 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
404 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
405 .type = ARM_CP_NO_MIGRATE },
406 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
407 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
408 .type = ARM_CP_NO_MIGRATE },
409 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
410 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
411 .type = ARM_CP_NO_MIGRATE },
412 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
413 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
414 .type = ARM_CP_NO_MIGRATE },
415 /* Cache maintenance ops; some of this space may be overridden later. */
416 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
417 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
418 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
419 REGINFO_SENTINEL
420 };
421
422 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
423 /* Not all pre-v6 cores implemented this WFI, so this is slightly
424 * over-broad.
425 */
426 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
427 .access = PL1_W, .type = ARM_CP_WFI },
428 REGINFO_SENTINEL
429 };
430
431 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
432 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
433 * is UNPREDICTABLE; we choose to NOP as most implementations do).
434 */
435 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
436 .access = PL1_W, .type = ARM_CP_WFI },
437 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
438 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
439 * OMAPCP will override this space.
440 */
441 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
442 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
443 .resetvalue = 0 },
444 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
445 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
446 .resetvalue = 0 },
447 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
448 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
449 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
450 .resetvalue = 0 },
451 REGINFO_SENTINEL
452 };
453
454 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
455 uint64_t value)
456 {
457 if (env->cp15.c1_coproc != value) {
458 env->cp15.c1_coproc = value;
459 /* ??? Is this safe when called from within a TB? */
460 tb_flush(env);
461 }
462 }
463
464 static const ARMCPRegInfo v6_cp_reginfo[] = {
465 /* prefetch by MVA in v6, NOP in v7 */
466 { .name = "MVA_prefetch",
467 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
468 .access = PL1_W, .type = ARM_CP_NOP },
469 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
470 .access = PL0_W, .type = ARM_CP_NOP },
471 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
472 .access = PL0_W, .type = ARM_CP_NOP },
473 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
474 .access = PL0_W, .type = ARM_CP_NOP },
475 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
476 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
477 .resetvalue = 0, },
478 /* Watchpoint Fault Address Register : should actually only be present
479 * for 1136, 1176, 11MPCore.
480 */
481 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
483 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
484 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
485 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
486 .resetvalue = 0, .writefn = cpacr_write },
487 REGINFO_SENTINEL
488 };
489
490 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
491 {
492 /* Performance monitor registers user accessibility is controlled
493 * by PMUSERENR.
494 */
495 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
496 return CP_ACCESS_TRAP;
497 }
498 return CP_ACCESS_OK;
499 }
500
501 #ifndef CONFIG_USER_ONLY
502 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
503 uint64_t value)
504 {
505 /* Don't computer the number of ticks in user mode */
506 uint32_t temp_ticks;
507
508 temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
509 get_ticks_per_sec() / 1000000;
510
511 if (env->cp15.c9_pmcr & PMCRE) {
512 /* If the counter is enabled */
513 if (env->cp15.c9_pmcr & PMCRD) {
514 /* Increment once every 64 processor clock cycles */
515 env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
516 } else {
517 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
518 }
519 }
520
521 if (value & PMCRC) {
522 /* The counter has been reset */
523 env->cp15.c15_ccnt = 0;
524 }
525
526 /* only the DP, X, D and E bits are writable */
527 env->cp15.c9_pmcr &= ~0x39;
528 env->cp15.c9_pmcr |= (value & 0x39);
529
530 if (env->cp15.c9_pmcr & PMCRE) {
531 if (env->cp15.c9_pmcr & PMCRD) {
532 /* Increment once every 64 processor clock cycles */
533 temp_ticks /= 64;
534 }
535 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
536 }
537 }
538
539 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
540 {
541 uint32_t total_ticks;
542
543 if (!(env->cp15.c9_pmcr & PMCRE)) {
544 /* Counter is disabled, do not change value */
545 return env->cp15.c15_ccnt;
546 }
547
548 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
549 get_ticks_per_sec() / 1000000;
550
551 if (env->cp15.c9_pmcr & PMCRD) {
552 /* Increment once every 64 processor clock cycles */
553 total_ticks /= 64;
554 }
555 return total_ticks - env->cp15.c15_ccnt;
556 }
557
558 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
559 uint64_t value)
560 {
561 uint32_t total_ticks;
562
563 if (!(env->cp15.c9_pmcr & PMCRE)) {
564 /* Counter is disabled, set the absolute value */
565 env->cp15.c15_ccnt = value;
566 return;
567 }
568
569 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
570 get_ticks_per_sec() / 1000000;
571
572 if (env->cp15.c9_pmcr & PMCRD) {
573 /* Increment once every 64 processor clock cycles */
574 total_ticks /= 64;
575 }
576 env->cp15.c15_ccnt = total_ticks - value;
577 }
578 #endif
579
580 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
581 uint64_t value)
582 {
583 value &= (1 << 31);
584 env->cp15.c9_pmcnten |= value;
585 }
586
587 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
588 uint64_t value)
589 {
590 value &= (1 << 31);
591 env->cp15.c9_pmcnten &= ~value;
592 }
593
594 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
595 uint64_t value)
596 {
597 env->cp15.c9_pmovsr &= ~value;
598 }
599
600 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
601 uint64_t value)
602 {
603 env->cp15.c9_pmxevtyper = value & 0xff;
604 }
605
606 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
607 uint64_t value)
608 {
609 env->cp15.c9_pmuserenr = value & 1;
610 }
611
612 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
613 uint64_t value)
614 {
615 /* We have no event counters so only the C bit can be changed */
616 value &= (1 << 31);
617 env->cp15.c9_pminten |= value;
618 }
619
620 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
621 uint64_t value)
622 {
623 value &= (1 << 31);
624 env->cp15.c9_pminten &= ~value;
625 }
626
627 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
628 uint64_t value)
629 {
630 /* Note that even though the AArch64 view of this register has bits
631 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
632 * architectural requirements for bits which are RES0 only in some
633 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
634 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
635 */
636 env->cp15.c12_vbar = value & ~0x1Ful;
637 }
638
639 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
640 {
641 ARMCPU *cpu = arm_env_get_cpu(env);
642 return cpu->ccsidr[env->cp15.c0_cssel];
643 }
644
645 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
646 uint64_t value)
647 {
648 env->cp15.c0_cssel = value & 0xf;
649 }
650
651 static const ARMCPRegInfo v7_cp_reginfo[] = {
652 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
653 * debug components
654 */
655 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
656 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
657 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
658 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
659 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
660 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
661 .access = PL1_W, .type = ARM_CP_NOP },
662 /* Performance monitors are implementation defined in v7,
663 * but with an ARM recommended set of registers, which we
664 * follow (although we don't actually implement any counters)
665 *
666 * Performance registers fall into three categories:
667 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
668 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
669 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
670 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
671 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
672 */
673 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
674 .access = PL0_RW, .resetvalue = 0,
675 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
676 .writefn = pmcntenset_write,
677 .accessfn = pmreg_access,
678 .raw_writefn = raw_write },
679 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
680 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
681 .accessfn = pmreg_access,
682 .writefn = pmcntenclr_write,
683 .type = ARM_CP_NO_MIGRATE },
684 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
685 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
686 .accessfn = pmreg_access,
687 .writefn = pmovsr_write,
688 .raw_writefn = raw_write },
689 /* Unimplemented so WI. */
690 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
691 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
692 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
693 * We choose to RAZ/WI.
694 */
695 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
696 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
697 .accessfn = pmreg_access },
698 #ifndef CONFIG_USER_ONLY
699 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
700 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
701 .readfn = pmccntr_read, .writefn = pmccntr_write,
702 .accessfn = pmreg_access },
703 #endif
704 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
705 .access = PL0_RW,
706 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
707 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
708 .raw_writefn = raw_write },
709 /* Unimplemented, RAZ/WI. */
710 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
711 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
712 .accessfn = pmreg_access },
713 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
714 .access = PL0_R | PL1_RW,
715 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
716 .resetvalue = 0,
717 .writefn = pmuserenr_write, .raw_writefn = raw_write },
718 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
719 .access = PL1_RW,
720 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
721 .resetvalue = 0,
722 .writefn = pmintenset_write, .raw_writefn = raw_write },
723 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
724 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
725 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
726 .resetvalue = 0, .writefn = pmintenclr_write, },
727 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
728 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
729 .access = PL1_RW, .writefn = vbar_write,
730 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
731 .resetvalue = 0 },
732 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
733 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
734 .resetvalue = 0, },
735 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
736 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
737 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
738 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
739 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
740 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
741 .writefn = csselr_write, .resetvalue = 0 },
742 /* Auxiliary ID register: this actually has an IMPDEF value but for now
743 * just RAZ for all cores:
744 */
745 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
746 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
747 /* MAIR can just read-as-written because we don't implement caches
748 * and so don't need to care about memory attributes.
749 */
750 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
751 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
752 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
753 .resetvalue = 0 },
754 /* For non-long-descriptor page tables these are PRRR and NMRR;
755 * regardless they still act as reads-as-written for QEMU.
756 * The override is necessary because of the overly-broad TLB_LOCKDOWN
757 * definition.
758 */
759 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
760 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
761 .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
762 .resetfn = arm_cp_reset_ignore },
763 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
764 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
765 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
766 .resetfn = arm_cp_reset_ignore },
767 REGINFO_SENTINEL
768 };
769
770 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
771 uint64_t value)
772 {
773 value &= 1;
774 env->teecr = value;
775 }
776
777 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
778 {
779 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
780 return CP_ACCESS_TRAP;
781 }
782 return CP_ACCESS_OK;
783 }
784
785 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
786 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
787 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
788 .resetvalue = 0,
789 .writefn = teecr_write },
790 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
791 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
792 .accessfn = teehbr_access, .resetvalue = 0 },
793 REGINFO_SENTINEL
794 };
795
796 static const ARMCPRegInfo v6k_cp_reginfo[] = {
797 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
798 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
799 .access = PL0_RW,
800 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
801 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
802 .access = PL0_RW,
803 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
804 .resetfn = arm_cp_reset_ignore },
805 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
806 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
807 .access = PL0_R|PL1_W,
808 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
809 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
810 .access = PL0_R|PL1_W,
811 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
812 .resetfn = arm_cp_reset_ignore },
813 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
814 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
815 .access = PL1_RW,
816 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
817 REGINFO_SENTINEL
818 };
819
820 #ifndef CONFIG_USER_ONLY
821
822 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
823 {
824 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
825 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
826 return CP_ACCESS_TRAP;
827 }
828 return CP_ACCESS_OK;
829 }
830
831 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
832 {
833 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
834 if (arm_current_pl(env) == 0 &&
835 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
836 return CP_ACCESS_TRAP;
837 }
838 return CP_ACCESS_OK;
839 }
840
841 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
842 {
843 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
844 * EL0[PV]TEN is zero.
845 */
846 if (arm_current_pl(env) == 0 &&
847 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
848 return CP_ACCESS_TRAP;
849 }
850 return CP_ACCESS_OK;
851 }
852
853 static CPAccessResult gt_pct_access(CPUARMState *env,
854 const ARMCPRegInfo *ri)
855 {
856 return gt_counter_access(env, GTIMER_PHYS);
857 }
858
859 static CPAccessResult gt_vct_access(CPUARMState *env,
860 const ARMCPRegInfo *ri)
861 {
862 return gt_counter_access(env, GTIMER_VIRT);
863 }
864
865 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
866 {
867 return gt_timer_access(env, GTIMER_PHYS);
868 }
869
870 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
871 {
872 return gt_timer_access(env, GTIMER_VIRT);
873 }
874
875 static uint64_t gt_get_countervalue(CPUARMState *env)
876 {
877 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
878 }
879
880 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
881 {
882 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
883
884 if (gt->ctl & 1) {
885 /* Timer enabled: calculate and set current ISTATUS, irq, and
886 * reset timer to when ISTATUS next has to change
887 */
888 uint64_t count = gt_get_countervalue(&cpu->env);
889 /* Note that this must be unsigned 64 bit arithmetic: */
890 int istatus = count >= gt->cval;
891 uint64_t nexttick;
892
893 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
894 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
895 (istatus && !(gt->ctl & 2)));
896 if (istatus) {
897 /* Next transition is when count rolls back over to zero */
898 nexttick = UINT64_MAX;
899 } else {
900 /* Next transition is when we hit cval */
901 nexttick = gt->cval;
902 }
903 /* Note that the desired next expiry time might be beyond the
904 * signed-64-bit range of a QEMUTimer -- in this case we just
905 * set the timer for as far in the future as possible. When the
906 * timer expires we will reset the timer for any remaining period.
907 */
908 if (nexttick > INT64_MAX / GTIMER_SCALE) {
909 nexttick = INT64_MAX / GTIMER_SCALE;
910 }
911 timer_mod(cpu->gt_timer[timeridx], nexttick);
912 } else {
913 /* Timer disabled: ISTATUS and timer output always clear */
914 gt->ctl &= ~4;
915 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
916 timer_del(cpu->gt_timer[timeridx]);
917 }
918 }
919
920 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
921 {
922 ARMCPU *cpu = arm_env_get_cpu(env);
923 int timeridx = ri->opc1 & 1;
924
925 timer_del(cpu->gt_timer[timeridx]);
926 }
927
928 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
929 {
930 return gt_get_countervalue(env);
931 }
932
933 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
934 uint64_t value)
935 {
936 int timeridx = ri->opc1 & 1;
937
938 env->cp15.c14_timer[timeridx].cval = value;
939 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
940 }
941
942 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
943 {
944 int timeridx = ri->crm & 1;
945
946 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
947 gt_get_countervalue(env));
948 }
949
950 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
951 uint64_t value)
952 {
953 int timeridx = ri->crm & 1;
954
955 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
956 + sextract64(value, 0, 32);
957 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
958 }
959
960 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
961 uint64_t value)
962 {
963 ARMCPU *cpu = arm_env_get_cpu(env);
964 int timeridx = ri->crm & 1;
965 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
966
967 env->cp15.c14_timer[timeridx].ctl = value & 3;
968 if ((oldval ^ value) & 1) {
969 /* Enable toggled */
970 gt_recalc_timer(cpu, timeridx);
971 } else if ((oldval & value) & 2) {
972 /* IMASK toggled: don't need to recalculate,
973 * just set the interrupt line based on ISTATUS
974 */
975 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
976 (oldval & 4) && (value & 2));
977 }
978 }
979
980 void arm_gt_ptimer_cb(void *opaque)
981 {
982 ARMCPU *cpu = opaque;
983
984 gt_recalc_timer(cpu, GTIMER_PHYS);
985 }
986
987 void arm_gt_vtimer_cb(void *opaque)
988 {
989 ARMCPU *cpu = opaque;
990
991 gt_recalc_timer(cpu, GTIMER_VIRT);
992 }
993
994 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
995 /* Note that CNTFRQ is purely reads-as-written for the benefit
996 * of software; writing it doesn't actually change the timer frequency.
997 * Our reset value matches the fixed frequency we implement the timer at.
998 */
999 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1000 .type = ARM_CP_NO_MIGRATE,
1001 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1002 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1003 .resetfn = arm_cp_reset_ignore,
1004 },
1005 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1006 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1007 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1008 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1009 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1010 },
1011 /* overall control: mostly access permissions */
1012 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1013 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1014 .access = PL1_RW,
1015 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1016 .resetvalue = 0,
1017 },
1018 /* per-timer control */
1019 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1020 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1021 .accessfn = gt_ptimer_access,
1022 .fieldoffset = offsetoflow32(CPUARMState,
1023 cp15.c14_timer[GTIMER_PHYS].ctl),
1024 .resetfn = arm_cp_reset_ignore,
1025 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1026 },
1027 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1028 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1029 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1030 .accessfn = gt_ptimer_access,
1031 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1032 .resetvalue = 0,
1033 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1034 },
1035 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1036 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1037 .accessfn = gt_vtimer_access,
1038 .fieldoffset = offsetoflow32(CPUARMState,
1039 cp15.c14_timer[GTIMER_VIRT].ctl),
1040 .resetfn = arm_cp_reset_ignore,
1041 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1042 },
1043 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1044 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1045 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1046 .accessfn = gt_vtimer_access,
1047 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1048 .resetvalue = 0,
1049 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1050 },
1051 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1052 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1053 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1054 .accessfn = gt_ptimer_access,
1055 .readfn = gt_tval_read, .writefn = gt_tval_write,
1056 },
1057 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1058 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1059 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1060 .readfn = gt_tval_read, .writefn = gt_tval_write,
1061 },
1062 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1063 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1064 .accessfn = gt_vtimer_access,
1065 .readfn = gt_tval_read, .writefn = gt_tval_write,
1066 },
1067 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1068 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1069 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1070 .readfn = gt_tval_read, .writefn = gt_tval_write,
1071 },
1072 /* The counter itself */
1073 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1074 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1075 .accessfn = gt_pct_access,
1076 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1077 },
1078 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1079 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1080 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1081 .accessfn = gt_pct_access,
1082 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1083 },
1084 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1085 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1086 .accessfn = gt_vct_access,
1087 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1088 },
1089 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1090 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1091 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1092 .accessfn = gt_vct_access,
1093 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1094 },
1095 /* Comparison value, indicating when the timer goes off */
1096 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1097 .access = PL1_RW | PL0_R,
1098 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1099 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1100 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1101 .writefn = gt_cval_write, .raw_writefn = raw_write,
1102 },
1103 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1104 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1105 .access = PL1_RW | PL0_R,
1106 .type = ARM_CP_IO,
1107 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1108 .resetvalue = 0, .accessfn = gt_vtimer_access,
1109 .writefn = gt_cval_write, .raw_writefn = raw_write,
1110 },
1111 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1112 .access = PL1_RW | PL0_R,
1113 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1114 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1115 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1116 .writefn = gt_cval_write, .raw_writefn = raw_write,
1117 },
1118 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1119 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1120 .access = PL1_RW | PL0_R,
1121 .type = ARM_CP_IO,
1122 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1123 .resetvalue = 0, .accessfn = gt_vtimer_access,
1124 .writefn = gt_cval_write, .raw_writefn = raw_write,
1125 },
1126 REGINFO_SENTINEL
1127 };
1128
1129 #else
1130 /* In user-mode none of the generic timer registers are accessible,
1131 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1132 * so instead just don't register any of them.
1133 */
1134 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1135 REGINFO_SENTINEL
1136 };
1137
1138 #endif
1139
1140 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1141 {
1142 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1143 env->cp15.c7_par = value;
1144 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1145 env->cp15.c7_par = value & 0xfffff6ff;
1146 } else {
1147 env->cp15.c7_par = value & 0xfffff1ff;
1148 }
1149 }
1150
1151 #ifndef CONFIG_USER_ONLY
1152 /* get_phys_addr() isn't present for user-mode-only targets */
1153
1154 /* Return true if extended addresses are enabled.
1155 * This is always the case if our translation regime is 64 bit,
1156 * but depends on TTBCR.EAE for 32 bit.
1157 */
1158 static inline bool extended_addresses_enabled(CPUARMState *env)
1159 {
1160 return arm_el_is_aa64(env, 1)
1161 || ((arm_feature(env, ARM_FEATURE_LPAE)
1162 && (env->cp15.c2_control & (1U << 31))));
1163 }
1164
1165 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1166 {
1167 if (ri->opc2 & 4) {
1168 /* Other states are only available with TrustZone; in
1169 * a non-TZ implementation these registers don't exist
1170 * at all, which is an Uncategorized trap. This underdecoding
1171 * is safe because the reginfo is NO_MIGRATE.
1172 */
1173 return CP_ACCESS_TRAP_UNCATEGORIZED;
1174 }
1175 return CP_ACCESS_OK;
1176 }
1177
1178 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1179 {
1180 hwaddr phys_addr;
1181 target_ulong page_size;
1182 int prot;
1183 int ret, is_user = ri->opc2 & 2;
1184 int access_type = ri->opc2 & 1;
1185
1186 ret = get_phys_addr(env, value, access_type, is_user,
1187 &phys_addr, &prot, &page_size);
1188 if (extended_addresses_enabled(env)) {
1189 /* ret is a DFSR/IFSR value for the long descriptor
1190 * translation table format, but with WnR always clear.
1191 * Convert it to a 64-bit PAR.
1192 */
1193 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1194 if (ret == 0) {
1195 par64 |= phys_addr & ~0xfffULL;
1196 /* We don't set the ATTR or SH fields in the PAR. */
1197 } else {
1198 par64 |= 1; /* F */
1199 par64 |= (ret & 0x3f) << 1; /* FS */
1200 /* Note that S2WLK and FSTAGE are always zero, because we don't
1201 * implement virtualization and therefore there can't be a stage 2
1202 * fault.
1203 */
1204 }
1205 env->cp15.c7_par = par64;
1206 env->cp15.c7_par_hi = par64 >> 32;
1207 } else {
1208 /* ret is a DFSR/IFSR value for the short descriptor
1209 * translation table format (with WnR always clear).
1210 * Convert it to a 32-bit PAR.
1211 */
1212 if (ret == 0) {
1213 /* We do not set any attribute bits in the PAR */
1214 if (page_size == (1 << 24)
1215 && arm_feature(env, ARM_FEATURE_V7)) {
1216 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1217 } else {
1218 env->cp15.c7_par = phys_addr & 0xfffff000;
1219 }
1220 } else {
1221 env->cp15.c7_par = ((ret & (1 << 10)) >> 5) |
1222 ((ret & (1 << 12)) >> 6) |
1223 ((ret & 0xf) << 1) | 1;
1224 }
1225 env->cp15.c7_par_hi = 0;
1226 }
1227 }
1228 #endif
1229
1230 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1231 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1232 .access = PL1_RW, .resetvalue = 0,
1233 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1234 .writefn = par_write },
1235 #ifndef CONFIG_USER_ONLY
1236 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1237 .access = PL1_W, .accessfn = ats_access,
1238 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1239 #endif
1240 REGINFO_SENTINEL
1241 };
1242
1243 /* Return basic MPU access permission bits. */
1244 static uint32_t simple_mpu_ap_bits(uint32_t val)
1245 {
1246 uint32_t ret;
1247 uint32_t mask;
1248 int i;
1249 ret = 0;
1250 mask = 3;
1251 for (i = 0; i < 16; i += 2) {
1252 ret |= (val >> i) & mask;
1253 mask <<= 2;
1254 }
1255 return ret;
1256 }
1257
1258 /* Pad basic MPU access permission bits to extended format. */
1259 static uint32_t extended_mpu_ap_bits(uint32_t val)
1260 {
1261 uint32_t ret;
1262 uint32_t mask;
1263 int i;
1264 ret = 0;
1265 mask = 3;
1266 for (i = 0; i < 16; i += 2) {
1267 ret |= (val & mask) << i;
1268 mask <<= 2;
1269 }
1270 return ret;
1271 }
1272
1273 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1274 uint64_t value)
1275 {
1276 env->cp15.c5_data = extended_mpu_ap_bits(value);
1277 }
1278
1279 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1280 {
1281 return simple_mpu_ap_bits(env->cp15.c5_data);
1282 }
1283
1284 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1285 uint64_t value)
1286 {
1287 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1288 }
1289
1290 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1291 {
1292 return simple_mpu_ap_bits(env->cp15.c5_insn);
1293 }
1294
1295 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1296 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1297 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1298 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1299 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1300 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1301 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1302 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1303 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1304 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1305 .access = PL1_RW,
1306 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1307 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1308 .access = PL1_RW,
1309 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1310 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1311 .access = PL1_RW,
1312 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1313 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1314 .access = PL1_RW,
1315 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1316 /* Protection region base and size registers */
1317 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1318 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1319 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1320 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1321 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1322 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1323 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1324 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1325 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1326 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1327 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1328 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1329 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1330 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1331 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1332 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1333 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1334 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1335 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1336 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1337 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1338 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1339 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1340 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1341 REGINFO_SENTINEL
1342 };
1343
1344 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1345 uint64_t value)
1346 {
1347 int maskshift = extract32(value, 0, 3);
1348
1349 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1350 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1351 } else {
1352 value &= 7;
1353 }
1354 /* Note that we always calculate c2_mask and c2_base_mask, but
1355 * they are only used for short-descriptor tables (ie if EAE is 0);
1356 * for long-descriptor tables the TTBCR fields are used differently
1357 * and the c2_mask and c2_base_mask values are meaningless.
1358 */
1359 env->cp15.c2_control = value;
1360 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1361 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1362 }
1363
1364 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1365 uint64_t value)
1366 {
1367 ARMCPU *cpu = arm_env_get_cpu(env);
1368
1369 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1370 /* With LPAE the TTBCR could result in a change of ASID
1371 * via the TTBCR.A1 bit, so do a TLB flush.
1372 */
1373 tlb_flush(CPU(cpu), 1);
1374 }
1375 vmsa_ttbcr_raw_write(env, ri, value);
1376 }
1377
1378 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1379 {
1380 env->cp15.c2_base_mask = 0xffffc000u;
1381 env->cp15.c2_control = 0;
1382 env->cp15.c2_mask = 0;
1383 }
1384
1385 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1386 uint64_t value)
1387 {
1388 ARMCPU *cpu = arm_env_get_cpu(env);
1389
1390 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1391 tlb_flush(CPU(cpu), 1);
1392 env->cp15.c2_control = value;
1393 }
1394
1395 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1396 uint64_t value)
1397 {
1398 /* 64 bit accesses to the TTBRs can change the ASID and so we
1399 * must flush the TLB.
1400 */
1401 if (cpreg_field_is_64bit(ri)) {
1402 ARMCPU *cpu = arm_env_get_cpu(env);
1403
1404 tlb_flush(CPU(cpu), 1);
1405 }
1406 raw_write(env, ri, value);
1407 }
1408
1409 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1410 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1411 .access = PL1_RW,
1412 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1413 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1414 .access = PL1_RW,
1415 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1416 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1417 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1418 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1419 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1420 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1421 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1422 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1423 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1424 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1425 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1426 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1427 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1428 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1429 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1430 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1431 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1432 .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1433 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1434 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1435 .resetvalue = 0, },
1436 REGINFO_SENTINEL
1437 };
1438
1439 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1440 uint64_t value)
1441 {
1442 env->cp15.c15_ticonfig = value & 0xe7;
1443 /* The OS_TYPE bit in this register changes the reported CPUID! */
1444 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1445 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1446 }
1447
1448 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1449 uint64_t value)
1450 {
1451 env->cp15.c15_threadid = value & 0xffff;
1452 }
1453
1454 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1455 uint64_t value)
1456 {
1457 /* Wait-for-interrupt (deprecated) */
1458 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1459 }
1460
1461 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1462 uint64_t value)
1463 {
1464 /* On OMAP there are registers indicating the max/min index of dcache lines
1465 * containing a dirty line; cache flush operations have to reset these.
1466 */
1467 env->cp15.c15_i_max = 0x000;
1468 env->cp15.c15_i_min = 0xff0;
1469 }
1470
1471 static const ARMCPRegInfo omap_cp_reginfo[] = {
1472 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1473 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1474 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1475 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1476 .access = PL1_RW, .type = ARM_CP_NOP },
1477 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1478 .access = PL1_RW,
1479 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1480 .writefn = omap_ticonfig_write },
1481 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1482 .access = PL1_RW,
1483 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1484 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1485 .access = PL1_RW, .resetvalue = 0xff0,
1486 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1487 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1488 .access = PL1_RW,
1489 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1490 .writefn = omap_threadid_write },
1491 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1492 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1493 .type = ARM_CP_NO_MIGRATE,
1494 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1495 /* TODO: Peripheral port remap register:
1496 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1497 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1498 * when MMU is off.
1499 */
1500 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1501 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1502 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1503 .writefn = omap_cachemaint_write },
1504 { .name = "C9", .cp = 15, .crn = 9,
1505 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1506 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1507 REGINFO_SENTINEL
1508 };
1509
1510 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1511 uint64_t value)
1512 {
1513 value &= 0x3fff;
1514 if (env->cp15.c15_cpar != value) {
1515 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1516 tb_flush(env);
1517 env->cp15.c15_cpar = value;
1518 }
1519 }
1520
1521 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1522 { .name = "XSCALE_CPAR",
1523 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1524 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1525 .writefn = xscale_cpar_write, },
1526 { .name = "XSCALE_AUXCR",
1527 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1528 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1529 .resetvalue = 0, },
1530 REGINFO_SENTINEL
1531 };
1532
1533 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1534 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1535 * implementation of this implementation-defined space.
1536 * Ideally this should eventually disappear in favour of actually
1537 * implementing the correct behaviour for all cores.
1538 */
1539 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1540 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1541 .access = PL1_RW,
1542 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1543 .resetvalue = 0 },
1544 REGINFO_SENTINEL
1545 };
1546
1547 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1548 /* Cache status: RAZ because we have no cache so it's always clean */
1549 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1550 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1551 .resetvalue = 0 },
1552 REGINFO_SENTINEL
1553 };
1554
1555 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1556 /* We never have a a block transfer operation in progress */
1557 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1558 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1559 .resetvalue = 0 },
1560 /* The cache ops themselves: these all NOP for QEMU */
1561 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1562 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1563 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1564 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1565 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1566 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1567 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1568 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1569 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1570 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1571 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1572 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1573 REGINFO_SENTINEL
1574 };
1575
1576 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1577 /* The cache test-and-clean instructions always return (1 << 30)
1578 * to indicate that there are no dirty cache lines.
1579 */
1580 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1581 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1582 .resetvalue = (1 << 30) },
1583 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1584 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1585 .resetvalue = (1 << 30) },
1586 REGINFO_SENTINEL
1587 };
1588
1589 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1590 /* Ignore ReadBuffer accesses */
1591 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1592 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1593 .access = PL1_RW, .resetvalue = 0,
1594 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1595 REGINFO_SENTINEL
1596 };
1597
1598 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1599 {
1600 CPUState *cs = CPU(arm_env_get_cpu(env));
1601 uint32_t mpidr = cs->cpu_index;
1602 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1603 * in later ARM ARM versions), or any of the higher affinity level fields,
1604 * so these bits always RAZ.
1605 */
1606 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1607 mpidr |= (1U << 31);
1608 /* Cores which are uniprocessor (non-coherent)
1609 * but still implement the MP extensions set
1610 * bit 30. (For instance, A9UP.) However we do
1611 * not currently model any of those cores.
1612 */
1613 }
1614 return mpidr;
1615 }
1616
1617 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1618 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1619 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1620 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1621 REGINFO_SENTINEL
1622 };
1623
1624 static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri)
1625 {
1626 return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1627 }
1628
1629 static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri,
1630 uint64_t value)
1631 {
1632 env->cp15.c7_par_hi = value >> 32;
1633 env->cp15.c7_par = value;
1634 }
1635
1636 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1637 {
1638 env->cp15.c7_par_hi = 0;
1639 env->cp15.c7_par = 0;
1640 }
1641
1642 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1643 /* NOP AMAIR0/1: the override is because these clash with the rather
1644 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1645 */
1646 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1647 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1648 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1649 .resetvalue = 0 },
1650 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1651 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1652 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1653 .resetvalue = 0 },
1654 /* 64 bit access versions of the (dummy) debug registers */
1655 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1656 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1657 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1658 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1659 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1660 .access = PL1_RW, .type = ARM_CP_64BIT,
1661 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1662 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1663 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1664 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1665 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1666 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1667 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1668 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1669 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1670 REGINFO_SENTINEL
1671 };
1672
1673 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1674 {
1675 return vfp_get_fpcr(env);
1676 }
1677
1678 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1679 uint64_t value)
1680 {
1681 vfp_set_fpcr(env, value);
1682 }
1683
1684 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1685 {
1686 return vfp_get_fpsr(env);
1687 }
1688
1689 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1690 uint64_t value)
1691 {
1692 vfp_set_fpsr(env, value);
1693 }
1694
1695 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1696 {
1697 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1698 return CP_ACCESS_TRAP;
1699 }
1700 return CP_ACCESS_OK;
1701 }
1702
1703 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1704 uint64_t value)
1705 {
1706 env->daif = value & PSTATE_DAIF;
1707 }
1708
1709 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1710 const ARMCPRegInfo *ri)
1711 {
1712 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1713 * SCTLR_EL1.UCI is set.
1714 */
1715 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1716 return CP_ACCESS_TRAP;
1717 }
1718 return CP_ACCESS_OK;
1719 }
1720
1721 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1722 uint64_t value)
1723 {
1724 /* Invalidate by VA (AArch64 version) */
1725 ARMCPU *cpu = arm_env_get_cpu(env);
1726 uint64_t pageaddr = value << 12;
1727 tlb_flush_page(CPU(cpu), pageaddr);
1728 }
1729
1730 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1731 uint64_t value)
1732 {
1733 /* Invalidate by VA, all ASIDs (AArch64 version) */
1734 ARMCPU *cpu = arm_env_get_cpu(env);
1735 uint64_t pageaddr = value << 12;
1736 tlb_flush_page(CPU(cpu), pageaddr);
1737 }
1738
1739 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1740 uint64_t value)
1741 {
1742 /* Invalidate by ASID (AArch64 version) */
1743 ARMCPU *cpu = arm_env_get_cpu(env);
1744 int asid = extract64(value, 48, 16);
1745 tlb_flush(CPU(cpu), asid == 0);
1746 }
1747
1748 static const ARMCPRegInfo v8_cp_reginfo[] = {
1749 /* Minimal set of EL0-visible registers. This will need to be expanded
1750 * significantly for system emulation of AArch64 CPUs.
1751 */
1752 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1753 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1754 .access = PL0_RW, .type = ARM_CP_NZCV },
1755 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1756 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1757 .type = ARM_CP_NO_MIGRATE,
1758 .access = PL0_RW, .accessfn = aa64_daif_access,
1759 .fieldoffset = offsetof(CPUARMState, daif),
1760 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1761 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1762 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1763 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1764 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1765 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1766 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1767 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1768 * For system mode the DZP bit here will need to be computed, not constant.
1769 */
1770 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1771 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1772 .access = PL0_R, .type = ARM_CP_CONST,
1773 .resetvalue = 0x10 },
1774 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1775 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1776 .access = PL1_R, .type = ARM_CP_CURRENTEL },
1777 /* Cache ops: all NOPs since we don't emulate caches */
1778 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1779 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1780 .access = PL1_W, .type = ARM_CP_NOP },
1781 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1782 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1783 .access = PL1_W, .type = ARM_CP_NOP },
1784 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1785 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1786 .access = PL0_W, .type = ARM_CP_NOP,
1787 .accessfn = aa64_cacheop_access },
1788 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1789 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1790 .access = PL1_W, .type = ARM_CP_NOP },
1791 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1792 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1793 .access = PL1_W, .type = ARM_CP_NOP },
1794 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1795 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1796 .access = PL0_W, .type = ARM_CP_NOP,
1797 .accessfn = aa64_cacheop_access },
1798 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1799 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1800 .access = PL1_W, .type = ARM_CP_NOP },
1801 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1802 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1803 .access = PL0_W, .type = ARM_CP_NOP,
1804 .accessfn = aa64_cacheop_access },
1805 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1806 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1807 .access = PL0_W, .type = ARM_CP_NOP,
1808 .accessfn = aa64_cacheop_access },
1809 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1810 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1811 .access = PL1_W, .type = ARM_CP_NOP },
1812 /* TLBI operations */
1813 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1814 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1815 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1816 .writefn = tlbiall_write },
1817 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1818 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1819 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1820 .writefn = tlbi_aa64_va_write },
1821 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1822 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1823 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1824 .writefn = tlbi_aa64_asid_write },
1825 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1826 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1827 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1828 .writefn = tlbi_aa64_vaa_write },
1829 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1830 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1831 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1832 .writefn = tlbi_aa64_va_write },
1833 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1834 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1835 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1836 .writefn = tlbi_aa64_vaa_write },
1837 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1838 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1839 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1840 .writefn = tlbiall_write },
1841 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1842 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1843 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1844 .writefn = tlbi_aa64_va_write },
1845 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1846 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1847 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1848 .writefn = tlbi_aa64_asid_write },
1849 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1850 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1851 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1852 .writefn = tlbi_aa64_vaa_write },
1853 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1854 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1855 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1856 .writefn = tlbi_aa64_va_write },
1857 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1858 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1859 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1860 .writefn = tlbi_aa64_vaa_write },
1861 /* Dummy implementation of monitor debug system control register:
1862 * we don't support debug.
1863 */
1864 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
1865 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
1866 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1867 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1868 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
1869 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1870 .access = PL1_W, .type = ARM_CP_NOP },
1871 REGINFO_SENTINEL
1872 };
1873
1874 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1875 uint64_t value)
1876 {
1877 ARMCPU *cpu = arm_env_get_cpu(env);
1878
1879 env->cp15.c1_sys = value;
1880 /* ??? Lots of these bits are not implemented. */
1881 /* This may enable/disable the MMU, so do a TLB flush. */
1882 tlb_flush(CPU(cpu), 1);
1883 }
1884
1885 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1886 {
1887 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1888 * but the AArch32 CTR has its own reginfo struct)
1889 */
1890 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
1891 return CP_ACCESS_TRAP;
1892 }
1893 return CP_ACCESS_OK;
1894 }
1895
1896 static void define_aarch64_debug_regs(ARMCPU *cpu)
1897 {
1898 /* Define breakpoint and watchpoint registers. These do nothing
1899 * but read as written, for now.
1900 */
1901 int i;
1902
1903 for (i = 0; i < 16; i++) {
1904 ARMCPRegInfo dbgregs[] = {
1905 { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
1906 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
1907 .access = PL1_RW,
1908 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
1909 { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
1910 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
1911 .access = PL1_RW,
1912 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
1913 { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
1914 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
1915 .access = PL1_RW,
1916 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
1917 { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
1918 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
1919 .access = PL1_RW,
1920 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
1921 REGINFO_SENTINEL
1922 };
1923 define_arm_cp_regs(cpu, dbgregs);
1924 }
1925 }
1926
1927 void register_cp_regs_for_features(ARMCPU *cpu)
1928 {
1929 /* Register all the coprocessor registers based on feature bits */
1930 CPUARMState *env = &cpu->env;
1931 if (arm_feature(env, ARM_FEATURE_M)) {
1932 /* M profile has no coprocessor registers */
1933 return;
1934 }
1935
1936 define_arm_cp_regs(cpu, cp_reginfo);
1937 if (arm_feature(env, ARM_FEATURE_V6)) {
1938 /* The ID registers all have impdef reset values */
1939 ARMCPRegInfo v6_idregs[] = {
1940 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1941 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1942 .resetvalue = cpu->id_pfr0 },
1943 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1944 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1945 .resetvalue = cpu->id_pfr1 },
1946 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1947 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1948 .resetvalue = cpu->id_dfr0 },
1949 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1950 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1951 .resetvalue = cpu->id_afr0 },
1952 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1953 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1954 .resetvalue = cpu->id_mmfr0 },
1955 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1956 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1957 .resetvalue = cpu->id_mmfr1 },
1958 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1959 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1960 .resetvalue = cpu->id_mmfr2 },
1961 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1962 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1963 .resetvalue = cpu->id_mmfr3 },
1964 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1965 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1966 .resetvalue = cpu->id_isar0 },
1967 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1968 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1969 .resetvalue = cpu->id_isar1 },
1970 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1971 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1972 .resetvalue = cpu->id_isar2 },
1973 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1974 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1975 .resetvalue = cpu->id_isar3 },
1976 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1977 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1978 .resetvalue = cpu->id_isar4 },
1979 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1980 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1981 .resetvalue = cpu->id_isar5 },
1982 /* 6..7 are as yet unallocated and must RAZ */
1983 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1984 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1985 .resetvalue = 0 },
1986 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1987 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1988 .resetvalue = 0 },
1989 REGINFO_SENTINEL
1990 };
1991 define_arm_cp_regs(cpu, v6_idregs);
1992 define_arm_cp_regs(cpu, v6_cp_reginfo);
1993 } else {
1994 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1995 }
1996 if (arm_feature(env, ARM_FEATURE_V6K)) {
1997 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1998 }
1999 if (arm_feature(env, ARM_FEATURE_V7)) {
2000 /* v7 performance monitor control register: same implementor
2001 * field as main ID register, and we implement only the cycle
2002 * count register.
2003 */
2004 #ifndef CONFIG_USER_ONLY
2005 ARMCPRegInfo pmcr = {
2006 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2007 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2008 .type = ARM_CP_IO,
2009 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2010 .accessfn = pmreg_access, .writefn = pmcr_write,
2011 .raw_writefn = raw_write,
2012 };
2013 define_one_arm_cp_reg(cpu, &pmcr);
2014 #endif
2015 ARMCPRegInfo clidr = {
2016 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2017 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2018 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2019 };
2020 define_one_arm_cp_reg(cpu, &clidr);
2021 define_arm_cp_regs(cpu, v7_cp_reginfo);
2022 } else {
2023 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2024 }
2025 if (arm_feature(env, ARM_FEATURE_V8)) {
2026 /* AArch64 ID registers, which all have impdef reset values */
2027 ARMCPRegInfo v8_idregs[] = {
2028 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2029 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2030 .access = PL1_R, .type = ARM_CP_CONST,
2031 .resetvalue = cpu->id_aa64pfr0 },
2032 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2033 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2034 .access = PL1_R, .type = ARM_CP_CONST,
2035 .resetvalue = cpu->id_aa64pfr1},
2036 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2037 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2038 .access = PL1_R, .type = ARM_CP_CONST,
2039 .resetvalue = cpu->id_aa64dfr0 },
2040 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2041 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2042 .access = PL1_R, .type = ARM_CP_CONST,
2043 .resetvalue = cpu->id_aa64dfr1 },
2044 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2045 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2046 .access = PL1_R, .type = ARM_CP_CONST,
2047 .resetvalue = cpu->id_aa64afr0 },
2048 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2049 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2050 .access = PL1_R, .type = ARM_CP_CONST,
2051 .resetvalue = cpu->id_aa64afr1 },
2052 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2053 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2054 .access = PL1_R, .type = ARM_CP_CONST,
2055 .resetvalue = cpu->id_aa64isar0 },
2056 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2057 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2058 .access = PL1_R, .type = ARM_CP_CONST,
2059 .resetvalue = cpu->id_aa64isar1 },
2060 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2061 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2062 .access = PL1_R, .type = ARM_CP_CONST,
2063 .resetvalue = cpu->id_aa64mmfr0 },
2064 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2065 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2066 .access = PL1_R, .type = ARM_CP_CONST,
2067 .resetvalue = cpu->id_aa64mmfr1 },
2068 REGINFO_SENTINEL
2069 };
2070 define_arm_cp_regs(cpu, v8_idregs);
2071 define_arm_cp_regs(cpu, v8_cp_reginfo);
2072 define_aarch64_debug_regs(cpu);
2073 }
2074 if (arm_feature(env, ARM_FEATURE_MPU)) {
2075 /* These are the MPU registers prior to PMSAv6. Any new
2076 * PMSA core later than the ARM946 will require that we
2077 * implement the PMSAv6 or PMSAv7 registers, which are
2078 * completely different.
2079 */
2080 assert(!arm_feature(env, ARM_FEATURE_V6));
2081 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2082 } else {
2083 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2084 }
2085 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2086 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2087 }
2088 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2089 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2090 }
2091 if (arm_feature(env, ARM_FEATURE_VAPA)) {
2092 define_arm_cp_regs(cpu, vapa_cp_reginfo);
2093 }
2094 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2095 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2096 }
2097 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2098 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2099 }
2100 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2101 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2102 }
2103 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2104 define_arm_cp_regs(cpu, omap_cp_reginfo);
2105 }
2106 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2107 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2108 }
2109 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2110 define_arm_cp_regs(cpu, xscale_cp_reginfo);
2111 }
2112 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2113 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2114 }
2115 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2116 define_arm_cp_regs(cpu, lpae_cp_reginfo);
2117 }
2118 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2119 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2120 * be read-only (ie write causes UNDEF exception).
2121 */
2122 {
2123 ARMCPRegInfo id_cp_reginfo[] = {
2124 /* Note that the MIDR isn't a simple constant register because
2125 * of the TI925 behaviour where writes to another register can
2126 * cause the MIDR value to change.
2127 *
2128 * Unimplemented registers in the c15 0 0 0 space default to
2129 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2130 * and friends override accordingly.
2131 */
2132 { .name = "MIDR",
2133 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2134 .access = PL1_R, .resetvalue = cpu->midr,
2135 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2136 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2137 .type = ARM_CP_OVERRIDE },
2138 { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
2139 .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
2140 .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
2141 { .name = "CTR",
2142 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2143 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2144 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2145 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2146 .access = PL0_R, .accessfn = ctr_el0_access,
2147 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2148 { .name = "TCMTR",
2149 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2150 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2151 { .name = "TLBTR",
2152 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2153 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2154 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2155 { .name = "DUMMY",
2156 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2157 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2158 { .name = "DUMMY",
2159 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2160 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2161 { .name = "DUMMY",
2162 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2163 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2164 { .name = "DUMMY",
2165 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2166 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2167 { .name = "DUMMY",
2168 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2169 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2170 REGINFO_SENTINEL
2171 };
2172 ARMCPRegInfo crn0_wi_reginfo = {
2173 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2174 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2175 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2176 };
2177 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2178 arm_feature(env, ARM_FEATURE_STRONGARM)) {
2179 ARMCPRegInfo *r;
2180 /* Register the blanket "writes ignored" value first to cover the
2181 * whole space. Then update the specific ID registers to allow write
2182 * access, so that they ignore writes rather than causing them to
2183 * UNDEF.
2184 */
2185 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2186 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2187 r->access = PL1_RW;
2188 }
2189 }
2190 define_arm_cp_regs(cpu, id_cp_reginfo);
2191 }
2192
2193 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2194 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2195 }
2196
2197 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2198 ARMCPRegInfo auxcr = {
2199 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
2200 .access = PL1_RW, .type = ARM_CP_CONST,
2201 .resetvalue = cpu->reset_auxcr
2202 };
2203 define_one_arm_cp_reg(cpu, &auxcr);
2204 }
2205
2206 if (arm_feature(env, ARM_FEATURE_CBAR)) {
2207 ARMCPRegInfo cbar = {
2208 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2209 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2210 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
2211 };
2212 define_one_arm_cp_reg(cpu, &cbar);
2213 }
2214
2215 /* Generic registers whose values depend on the implementation */
2216 {
2217 ARMCPRegInfo sctlr = {
2218 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2219 .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2220 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2221 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2222 .raw_writefn = raw_write,
2223 };
2224 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2225 /* Normally we would always end the TB on an SCTLR write, but Linux
2226 * arch/arm/mach-pxa/sleep.S expects two instructions following
2227 * an MMU enable to execute from cache. Imitate this behaviour.
2228 */
2229 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2230 }
2231 define_one_arm_cp_reg(cpu, &sctlr);
2232 }
2233 }
2234
2235 ARMCPU *cpu_arm_init(const char *cpu_model)
2236 {
2237 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2238 }
2239
2240 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2241 {
2242 CPUState *cs = CPU(cpu);
2243 CPUARMState *env = &cpu->env;
2244
2245 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2246 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2247 aarch64_fpu_gdb_set_reg,
2248 34, "aarch64-fpu.xml", 0);
2249 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2250 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2251 51, "arm-neon.xml", 0);
2252 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2253 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2254 35, "arm-vfp3.xml", 0);
2255 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2256 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2257 19, "arm-vfp.xml", 0);
2258 }
2259 }
2260
2261 /* Sort alphabetically by type name, except for "any". */
2262 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2263 {
2264 ObjectClass *class_a = (ObjectClass *)a;
2265 ObjectClass *class_b = (ObjectClass *)b;
2266 const char *name_a, *name_b;
2267
2268 name_a = object_class_get_name(class_a);
2269 name_b = object_class_get_name(class_b);
2270 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2271 return 1;
2272 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2273 return -1;
2274 } else {
2275 return strcmp(name_a, name_b);
2276 }
2277 }
2278
2279 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2280 {
2281 ObjectClass *oc = data;
2282 CPUListState *s = user_data;
2283 const char *typename;
2284 char *name;
2285
2286 typename = object_class_get_name(oc);
2287 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2288 (*s->cpu_fprintf)(s->file, " %s\n",
2289 name);
2290 g_free(name);
2291 }
2292
2293 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2294 {
2295 CPUListState s = {
2296 .file = f,
2297 .cpu_fprintf = cpu_fprintf,
2298 };
2299 GSList *list;
2300
2301 list = object_class_get_list(TYPE_ARM_CPU, false);
2302 list = g_slist_sort(list, arm_cpu_list_compare);
2303 (*cpu_fprintf)(f, "Available CPUs:\n");
2304 g_slist_foreach(list, arm_cpu_list_entry, &s);
2305 g_slist_free(list);
2306 #ifdef CONFIG_KVM
2307 /* The 'host' CPU type is dynamically registered only if KVM is
2308 * enabled, so we have to special-case it here:
2309 */
2310 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
2311 #endif
2312 }
2313
2314 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2315 {
2316 ObjectClass *oc = data;
2317 CpuDefinitionInfoList **cpu_list = user_data;
2318 CpuDefinitionInfoList *entry;
2319 CpuDefinitionInfo *info;
2320 const char *typename;
2321
2322 typename = object_class_get_name(oc);
2323 info = g_malloc0(sizeof(*info));
2324 info->name = g_strndup(typename,
2325 strlen(typename) - strlen("-" TYPE_ARM_CPU));
2326
2327 entry = g_malloc0(sizeof(*entry));
2328 entry->value = info;
2329 entry->next = *cpu_list;
2330 *cpu_list = entry;
2331 }
2332
2333 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2334 {
2335 CpuDefinitionInfoList *cpu_list = NULL;
2336 GSList *list;
2337
2338 list = object_class_get_list(TYPE_ARM_CPU, false);
2339 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2340 g_slist_free(list);
2341
2342 return cpu_list;
2343 }
2344
2345 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2346 void *opaque, int state,
2347 int crm, int opc1, int opc2)
2348 {
2349 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2350 * add a single reginfo struct to the hash table.
2351 */
2352 uint32_t *key = g_new(uint32_t, 1);
2353 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2354 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2355 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2356 /* The AArch32 view of a shared register sees the lower 32 bits
2357 * of a 64 bit backing field. It is not migratable as the AArch64
2358 * view handles that. AArch64 also handles reset.
2359 * We assume it is a cp15 register.
2360 */
2361 r2->cp = 15;
2362 r2->type |= ARM_CP_NO_MIGRATE;
2363 r2->resetfn = arm_cp_reset_ignore;
2364 #ifdef HOST_WORDS_BIGENDIAN
2365 if (r2->fieldoffset) {
2366 r2->fieldoffset += sizeof(uint32_t);
2367 }
2368 #endif
2369 }
2370 if (state == ARM_CP_STATE_AA64) {
2371 /* To allow abbreviation of ARMCPRegInfo
2372 * definitions, we treat cp == 0 as equivalent to
2373 * the value for "standard guest-visible sysreg".
2374 */
2375 if (r->cp == 0) {
2376 r2->cp = CP_REG_ARM64_SYSREG_CP;
2377 }
2378 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2379 r2->opc0, opc1, opc2);
2380 } else {
2381 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2382 }
2383 if (opaque) {
2384 r2->opaque = opaque;
2385 }
2386 /* reginfo passed to helpers is correct for the actual access,
2387 * and is never ARM_CP_STATE_BOTH:
2388 */
2389 r2->state = state;
2390 /* Make sure reginfo passed to helpers for wildcarded regs
2391 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2392 */
2393 r2->crm = crm;
2394 r2->opc1 = opc1;
2395 r2->opc2 = opc2;
2396 /* By convention, for wildcarded registers only the first
2397 * entry is used for migration; the others are marked as
2398 * NO_MIGRATE so we don't try to transfer the register
2399 * multiple times. Special registers (ie NOP/WFI) are
2400 * never migratable.
2401 */
2402 if ((r->type & ARM_CP_SPECIAL) ||
2403 ((r->crm == CP_ANY) && crm != 0) ||
2404 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2405 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2406 r2->type |= ARM_CP_NO_MIGRATE;
2407 }
2408
2409 /* Overriding of an existing definition must be explicitly
2410 * requested.
2411 */
2412 if (!(r->type & ARM_CP_OVERRIDE)) {
2413 ARMCPRegInfo *oldreg;
2414 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2415 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2416 fprintf(stderr, "Register redefined: cp=%d %d bit "
2417 "crn=%d crm=%d opc1=%d opc2=%d, "
2418 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2419 r2->crn, r2->crm, r2->opc1, r2->opc2,
2420 oldreg->name, r2->name);
2421 g_assert_not_reached();
2422 }
2423 }
2424 g_hash_table_insert(cpu->cp_regs, key, r2);
2425 }
2426
2427
2428 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2429 const ARMCPRegInfo *r, void *opaque)
2430 {
2431 /* Define implementations of coprocessor registers.
2432 * We store these in a hashtable because typically
2433 * there are less than 150 registers in a space which
2434 * is 16*16*16*8*8 = 262144 in size.
2435 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2436 * If a register is defined twice then the second definition is
2437 * used, so this can be used to define some generic registers and
2438 * then override them with implementation specific variations.
2439 * At least one of the original and the second definition should
2440 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2441 * against accidental use.
2442 *
2443 * The state field defines whether the register is to be
2444 * visible in the AArch32 or AArch64 execution state. If the
2445 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2446 * reginfo structure for the AArch32 view, which sees the lower
2447 * 32 bits of the 64 bit register.
2448 *
2449 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2450 * be wildcarded. AArch64 registers are always considered to be 64
2451 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2452 * the register, if any.
2453 */
2454 int crm, opc1, opc2, state;
2455 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2456 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2457 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2458 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2459 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2460 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2461 /* 64 bit registers have only CRm and Opc1 fields */
2462 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2463 /* op0 only exists in the AArch64 encodings */
2464 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2465 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2466 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2467 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2468 * encodes a minimum access level for the register. We roll this
2469 * runtime check into our general permission check code, so check
2470 * here that the reginfo's specified permissions are strict enough
2471 * to encompass the generic architectural permission check.
2472 */
2473 if (r->state != ARM_CP_STATE_AA32) {
2474 int mask = 0;
2475 switch (r->opc1) {
2476 case 0: case 1: case 2:
2477 /* min_EL EL1 */
2478 mask = PL1_RW;
2479 break;
2480 case 3:
2481 /* min_EL EL0 */
2482 mask = PL0_RW;
2483 break;
2484 case 4:
2485 /* min_EL EL2 */
2486 mask = PL2_RW;
2487 break;
2488 case 5:
2489 /* unallocated encoding, so not possible */
2490 assert(false);
2491 break;
2492 case 6:
2493 /* min_EL EL3 */
2494 mask = PL3_RW;
2495 break;
2496 case 7:
2497 /* min_EL EL1, secure mode only (we don't check the latter) */
2498 mask = PL1_RW;
2499 break;
2500 default:
2501 /* broken reginfo with out-of-range opc1 */
2502 assert(false);
2503 break;
2504 }
2505 /* assert our permissions are not too lax (stricter is fine) */
2506 assert((r->access & ~mask) == 0);
2507 }
2508
2509 /* Check that the register definition has enough info to handle
2510 * reads and writes if they are permitted.
2511 */
2512 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2513 if (r->access & PL3_R) {
2514 assert(r->fieldoffset || r->readfn);
2515 }
2516 if (r->access & PL3_W) {
2517 assert(r->fieldoffset || r->writefn);
2518 }
2519 }
2520 /* Bad type field probably means missing sentinel at end of reg list */
2521 assert(cptype_valid(r->type));
2522 for (crm = crmmin; crm <= crmmax; crm++) {
2523 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2524 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2525 for (state = ARM_CP_STATE_AA32;
2526 state <= ARM_CP_STATE_AA64; state++) {
2527 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2528 continue;
2529 }
2530 add_cpreg_to_hashtable(cpu, r, opaque, state,
2531 crm, opc1, opc2);
2532 }
2533 }
2534 }
2535 }
2536 }
2537
2538 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2539 const ARMCPRegInfo *regs, void *opaque)
2540 {
2541 /* Define a whole list of registers */
2542 const ARMCPRegInfo *r;
2543 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2544 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2545 }
2546 }
2547
2548 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2549 {
2550 return g_hash_table_lookup(cpregs, &encoded_cp);
2551 }
2552
2553 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2554 uint64_t value)
2555 {
2556 /* Helper coprocessor write function for write-ignore registers */
2557 }
2558
2559 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2560 {
2561 /* Helper coprocessor write function for read-as-zero registers */
2562 return 0;
2563 }
2564
2565 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2566 {
2567 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2568 }
2569
2570 static int bad_mode_switch(CPUARMState *env, int mode)
2571 {
2572 /* Return true if it is not valid for us to switch to
2573 * this CPU mode (ie all the UNPREDICTABLE cases in
2574 * the ARM ARM CPSRWriteByInstr pseudocode).
2575 */
2576 switch (mode) {
2577 case ARM_CPU_MODE_USR:
2578 case ARM_CPU_MODE_SYS:
2579 case ARM_CPU_MODE_SVC:
2580 case ARM_CPU_MODE_ABT:
2581 case ARM_CPU_MODE_UND:
2582 case ARM_CPU_MODE_IRQ:
2583 case ARM_CPU_MODE_FIQ:
2584 return 0;
2585 default:
2586 return 1;
2587 }
2588 }
2589
2590 uint32_t cpsr_read(CPUARMState *env)
2591 {
2592 int ZF;
2593 ZF = (env->ZF == 0);
2594 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2595 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2596 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2597 | ((env->condexec_bits & 0xfc) << 8)
2598 | (env->GE << 16) | (env->daif & CPSR_AIF);
2599 }
2600
2601 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2602 {
2603 if (mask & CPSR_NZCV) {
2604 env->ZF = (~val) & CPSR_Z;
2605 env->NF = val;
2606 env->CF = (val >> 29) & 1;
2607 env->VF = (val << 3) & 0x80000000;
2608 }
2609 if (mask & CPSR_Q)
2610 env->QF = ((val & CPSR_Q) != 0);
2611 if (mask & CPSR_T)
2612 env->thumb = ((val & CPSR_T) != 0);
2613 if (mask & CPSR_IT_0_1) {
2614 env->condexec_bits &= ~3;
2615 env->condexec_bits |= (val >> 25) & 3;
2616 }
2617 if (mask & CPSR_IT_2_7) {
2618 env->condexec_bits &= 3;
2619 env->condexec_bits |= (val >> 8) & 0xfc;
2620 }
2621 if (mask & CPSR_GE) {
2622 env->GE = (val >> 16) & 0xf;
2623 }
2624
2625 env->daif &= ~(CPSR_AIF & mask);
2626 env->daif |= val & CPSR_AIF & mask;
2627
2628 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2629 if (bad_mode_switch(env, val & CPSR_M)) {
2630 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2631 * We choose to ignore the attempt and leave the CPSR M field
2632 * untouched.
2633 */
2634 mask &= ~CPSR_M;
2635 } else {
2636 switch_mode(env, val & CPSR_M);
2637 }
2638 }
2639 mask &= ~CACHED_CPSR_BITS;
2640 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2641 }
2642
2643 /* Sign/zero extend */
2644 uint32_t HELPER(sxtb16)(uint32_t x)
2645 {
2646 uint32_t res;
2647 res = (uint16_t)(int8_t)x;
2648 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2649 return res;
2650 }
2651
2652 uint32_t HELPER(uxtb16)(uint32_t x)
2653 {
2654 uint32_t res;
2655 res = (uint16_t)(uint8_t)x;
2656 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2657 return res;
2658 }
2659
2660 uint32_t HELPER(clz)(uint32_t x)
2661 {
2662 return clz32(x);
2663 }
2664
2665 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2666 {
2667 if (den == 0)
2668 return 0;
2669 if (num == INT_MIN && den == -1)
2670 return INT_MIN;
2671 return num / den;
2672 }
2673
2674 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2675 {
2676 if (den == 0)
2677 return 0;
2678 return num / den;
2679 }
2680
2681 uint32_t HELPER(rbit)(uint32_t x)
2682 {
2683 x = ((x & 0xff000000) >> 24)
2684 | ((x & 0x00ff0000) >> 8)
2685 | ((x & 0x0000ff00) << 8)
2686 | ((x & 0x000000ff) << 24);
2687 x = ((x & 0xf0f0f0f0) >> 4)
2688 | ((x & 0x0f0f0f0f) << 4);
2689 x = ((x & 0x88888888) >> 3)
2690 | ((x & 0x44444444) >> 1)
2691 | ((x & 0x22222222) << 1)
2692 | ((x & 0x11111111) << 3);
2693 return x;
2694 }
2695
2696 #if defined(CONFIG_USER_ONLY)
2697
2698 void arm_cpu_do_interrupt(CPUState *cs)
2699 {
2700 cs->exception_index = -1;
2701 }
2702
2703 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
2704 int mmu_idx)
2705 {
2706 ARMCPU *cpu = ARM_CPU(cs);
2707 CPUARMState *env = &cpu->env;
2708
2709 env->exception.vaddress = address;
2710 if (rw == 2) {
2711 cs->exception_index = EXCP_PREFETCH_ABORT;
2712 } else {
2713 cs->exception_index = EXCP_DATA_ABORT;
2714 }
2715 return 1;
2716 }
2717
2718 /* These should probably raise undefined insn exceptions. */
2719 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2720 {
2721 ARMCPU *cpu = arm_env_get_cpu(env);
2722
2723 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
2724 }
2725
2726 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2727 {
2728 ARMCPU *cpu = arm_env_get_cpu(env);
2729
2730 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
2731 return 0;
2732 }
2733
2734 void switch_mode(CPUARMState *env, int mode)
2735 {
2736 ARMCPU *cpu = arm_env_get_cpu(env);
2737
2738 if (mode != ARM_CPU_MODE_USR) {
2739 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
2740 }
2741 }
2742
2743 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2744 {
2745 ARMCPU *cpu = arm_env_get_cpu(env);
2746
2747 cpu_abort(CPU(cpu), "banked r13 write\n");
2748 }
2749
2750 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2751 {
2752 ARMCPU *cpu = arm_env_get_cpu(env);
2753
2754 cpu_abort(CPU(cpu), "banked r13 read\n");
2755 return 0;
2756 }
2757
2758 #else
2759
2760 /* Map CPU modes onto saved register banks. */
2761 int bank_number(int mode)
2762 {
2763 switch (mode) {
2764 case ARM_CPU_MODE_USR:
2765 case ARM_CPU_MODE_SYS:
2766 return 0;
2767 case ARM_CPU_MODE_SVC:
2768 return 1;
2769 case ARM_CPU_MODE_ABT:
2770 return 2;
2771 case ARM_CPU_MODE_UND:
2772 return 3;
2773 case ARM_CPU_MODE_IRQ:
2774 return 4;
2775 case ARM_CPU_MODE_FIQ:
2776 return 5;
2777 }
2778 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2779 }
2780
2781 void switch_mode(CPUARMState *env, int mode)
2782 {
2783 int old_mode;
2784 int i;
2785
2786 old_mode = env->uncached_cpsr & CPSR_M;
2787 if (mode == old_mode)
2788 return;
2789
2790 if (old_mode == ARM_CPU_MODE_FIQ) {
2791 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2792 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2793 } else if (mode == ARM_CPU_MODE_FIQ) {
2794 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2795 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2796 }
2797
2798 i = bank_number(old_mode);
2799 env->banked_r13[i] = env->regs[13];
2800 env->banked_r14[i] = env->regs[14];
2801 env->banked_spsr[i] = env->spsr;
2802
2803 i = bank_number(mode);
2804 env->regs[13] = env->banked_r13[i];
2805 env->regs[14] = env->banked_r14[i];
2806 env->spsr = env->banked_spsr[i];
2807 }
2808
2809 static void v7m_push(CPUARMState *env, uint32_t val)
2810 {
2811 CPUState *cs = CPU(arm_env_get_cpu(env));
2812
2813 env->regs[13] -= 4;
2814 stl_phys(cs->as, env->regs[13], val);
2815 }
2816
2817 static uint32_t v7m_pop(CPUARMState *env)
2818 {
2819 CPUState *cs = CPU(arm_env_get_cpu(env));
2820 uint32_t val;
2821
2822 val = ldl_phys(cs->as, env->regs[13]);
2823 env->regs[13] += 4;
2824 return val;
2825 }
2826
2827 /* Switch to V7M main or process stack pointer. */
2828 static void switch_v7m_sp(CPUARMState *env, int process)
2829 {
2830 uint32_t tmp;
2831 if (env->v7m.current_sp != process) {
2832 tmp = env->v7m.other_sp;
2833 env->v7m.other_sp = env->regs[13];
2834 env->regs[13] = tmp;
2835 env->v7m.current_sp = process;
2836 }
2837 }
2838
2839 static void do_v7m_exception_exit(CPUARMState *env)
2840 {
2841 uint32_t type;
2842 uint32_t xpsr;
2843
2844 type = env->regs[15];
2845 if (env->v7m.exception != 0)
2846 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2847
2848 /* Switch to the target stack. */
2849 switch_v7m_sp(env, (type & 4) != 0);
2850 /* Pop registers. */
2851 env->regs[0] = v7m_pop(env);
2852 env->regs[1] = v7m_pop(env);
2853 env->regs[2] = v7m_pop(env);
2854 env->regs[3] = v7m_pop(env);
2855 env->regs[12] = v7m_pop(env);
2856 env->regs[14] = v7m_pop(env);
2857 env->regs[15] = v7m_pop(env);
2858 xpsr = v7m_pop(env);
2859 xpsr_write(env, xpsr, 0xfffffdff);
2860 /* Undo stack alignment. */
2861 if (xpsr & 0x200)
2862 env->regs[13] |= 4;
2863 /* ??? The exception return type specifies Thread/Handler mode. However
2864 this is also implied by the xPSR value. Not sure what to do
2865 if there is a mismatch. */
2866 /* ??? Likewise for mismatches between the CONTROL register and the stack
2867 pointer. */
2868 }
2869
2870 /* Exception names for debug logging; note that not all of these
2871 * precisely correspond to architectural exceptions.
2872 */
2873 static const char * const excnames[] = {
2874 [EXCP_UDEF] = "Undefined Instruction",
2875 [EXCP_SWI] = "SVC",
2876 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2877 [EXCP_DATA_ABORT] = "Data Abort",
2878 [EXCP_IRQ] = "IRQ",
2879 [EXCP_FIQ] = "FIQ",
2880 [EXCP_BKPT] = "Breakpoint",
2881 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2882 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2883 [EXCP_STREX] = "QEMU intercept of STREX",
2884 };
2885
2886 static inline void arm_log_exception(int idx)
2887 {
2888 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2889 const char *exc = NULL;
2890
2891 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2892 exc = excnames[idx];
2893 }
2894 if (!exc) {
2895 exc = "unknown";
2896 }
2897 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2898 }
2899 }
2900
2901 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2902 {
2903 ARMCPU *cpu = ARM_CPU(cs);
2904 CPUARMState *env = &cpu->env;
2905 uint32_t xpsr = xpsr_read(env);
2906 uint32_t lr;
2907 uint32_t addr;
2908
2909 arm_log_exception(cs->exception_index);
2910
2911 lr = 0xfffffff1;
2912 if (env->v7m.current_sp)
2913 lr |= 4;
2914 if (env->v7m.exception == 0)
2915 lr |= 8;
2916
2917 /* For exceptions we just mark as pending on the NVIC, and let that
2918 handle it. */
2919 /* TODO: Need to escalate if the current priority is higher than the
2920 one we're raising. */
2921 switch (cs->exception_index) {
2922 case EXCP_UDEF:
2923 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2924 return;
2925 case EXCP_SWI:
2926 /* The PC already points to the next instruction. */
2927 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2928 return;
2929 case EXCP_PREFETCH_ABORT:
2930 case EXCP_DATA_ABORT:
2931 /* TODO: if we implemented the MPU registers, this is where we
2932 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
2933 */
2934 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2935 return;
2936 case EXCP_BKPT:
2937 if (semihosting_enabled) {
2938 int nr;
2939 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2940 if (nr == 0xab) {
2941 env->regs[15] += 2;
2942 env->regs[0] = do_arm_semihosting(env);
2943 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2944 return;
2945 }
2946 }
2947 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2948 return;
2949 case EXCP_IRQ:
2950 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2951 break;
2952 case EXCP_EXCEPTION_EXIT:
2953 do_v7m_exception_exit(env);
2954 return;
2955 default:
2956 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
2957 return; /* Never happens. Keep compiler happy. */
2958 }
2959
2960 /* Align stack pointer. */
2961 /* ??? Should only do this if Configuration Control Register
2962 STACKALIGN bit is set. */
2963 if (env->regs[13] & 4) {
2964 env->regs[13] -= 4;
2965 xpsr |= 0x200;
2966 }
2967 /* Switch to the handler mode. */
2968 v7m_push(env, xpsr);
2969 v7m_push(env, env->regs[15]);
2970 v7m_push(env, env->regs[14]);
2971 v7m_push(env, env->regs[12]);
2972 v7m_push(env, env->regs[3]);
2973 v7m_push(env, env->regs[2]);
2974 v7m_push(env, env->regs[1]);
2975 v7m_push(env, env->regs[0]);
2976 switch_v7m_sp(env, 0);
2977 /* Clear IT bits */
2978 env->condexec_bits = 0;
2979 env->regs[14] = lr;
2980 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
2981 env->regs[15] = addr & 0xfffffffe;
2982 env->thumb = addr & 1;
2983 }
2984
2985 /* Handle a CPU exception. */
2986 void arm_cpu_do_interrupt(CPUState *cs)
2987 {
2988 ARMCPU *cpu = ARM_CPU(cs);
2989 CPUARMState *env = &cpu->env;
2990 uint32_t addr;
2991 uint32_t mask;
2992 int new_mode;
2993 uint32_t offset;
2994
2995 assert(!IS_M(env));
2996
2997 arm_log_exception(cs->exception_index);
2998
2999 /* TODO: Vectored interrupt controller. */
3000 switch (cs->exception_index) {
3001 case EXCP_UDEF:
3002 new_mode = ARM_CPU_MODE_UND;
3003 addr = 0x04;
3004 mask = CPSR_I;
3005 if (env->thumb)
3006 offset = 2;
3007 else
3008 offset = 4;
3009 break;
3010 case EXCP_SWI:
3011 if (semihosting_enabled) {
3012 /* Check for semihosting interrupt. */
3013 if (env->thumb) {
3014 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3015 & 0xff;
3016 } else {
3017 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3018 & 0xffffff;
3019 }
3020 /* Only intercept calls from privileged modes, to provide some
3021 semblance of security. */
3022 if (((mask == 0x123456 && !env->thumb)
3023 || (mask == 0xab && env->thumb))
3024 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3025 env->regs[0] = do_arm_semihosting(env);
3026 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3027 return;
3028 }
3029 }
3030 new_mode = ARM_CPU_MODE_SVC;
3031 addr = 0x08;
3032 mask = CPSR_I;
3033 /* The PC already points to the next instruction. */
3034 offset = 0;
3035 break;
3036 case EXCP_BKPT:
3037 /* See if this is a semihosting syscall. */
3038 if (env->thumb && semihosting_enabled) {
3039 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3040 if (mask == 0xab
3041 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3042 env->regs[15] += 2;
3043 env->regs[0] = do_arm_semihosting(env);
3044 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3045 return;
3046 }
3047 }
3048 env->exception.fsr = 2;
3049 /* Fall through to prefetch abort. */
3050 case EXCP_PREFETCH_ABORT:
3051 env->cp15.c5_insn = env->exception.fsr;
3052 env->cp15.c6_insn = env->exception.vaddress;
3053 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3054 env->cp15.c5_insn, env->cp15.c6_insn);
3055 new_mode = ARM_CPU_MODE_ABT;
3056 addr = 0x0c;
3057 mask = CPSR_A | CPSR_I;
3058 offset = 4;
3059 break;
3060 case EXCP_DATA_ABORT:
3061 env->cp15.c5_data = env->exception.fsr;
3062 env->cp15.c6_data = env->exception.vaddress;
3063 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3064 env->cp15.c5_data, env->cp15.c6_data);
3065 new_mode = ARM_CPU_MODE_ABT;
3066 addr = 0x10;
3067 mask = CPSR_A | CPSR_I;
3068 offset = 8;
3069 break;
3070 case EXCP_IRQ:
3071 new_mode = ARM_CPU_MODE_IRQ;
3072 addr = 0x18;
3073 /* Disable IRQ and imprecise data aborts. */
3074 mask = CPSR_A | CPSR_I;
3075 offset = 4;
3076 break;
3077 case EXCP_FIQ:
3078 new_mode = ARM_CPU_MODE_FIQ;
3079 addr = 0x1c;
3080 /* Disable FIQ, IRQ and imprecise data aborts. */
3081 mask = CPSR_A | CPSR_I | CPSR_F;
3082 offset = 4;
3083 break;
3084 default:
3085 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3086 return; /* Never happens. Keep compiler happy. */
3087 }
3088 /* High vectors. */
3089 if (env->cp15.c1_sys & SCTLR_V) {
3090 /* when enabled, base address cannot be remapped. */
3091 addr += 0xffff0000;
3092 } else {
3093 /* ARM v7 architectures provide a vector base address register to remap
3094 * the interrupt vector table.
3095 * This register is only followed in non-monitor mode, and has a secure
3096 * and un-secure copy. Since the cpu is always in a un-secure operation
3097 * and is never in monitor mode this feature is always active.
3098 * Note: only bits 31:5 are valid.
3099 */
3100 addr += env->cp15.c12_vbar;
3101 }
3102 switch_mode (env, new_mode);
3103 env->spsr = cpsr_read(env);
3104 /* Clear IT bits. */
3105 env->condexec_bits = 0;
3106 /* Switch to the new mode, and to the correct instruction set. */
3107 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3108 env->daif |= mask;
3109 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3110 * and we should just guard the thumb mode on V4 */
3111 if (arm_feature(env, ARM_FEATURE_V4T)) {
3112 env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3113 }
3114 env->regs[14] = env->regs[15] + offset;
3115 env->regs[15] = addr;
3116 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3117 }
3118
3119 /* Check section/page access permissions.
3120 Returns the page protection flags, or zero if the access is not
3121 permitted. */
3122 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3123 int access_type, int is_user)
3124 {
3125 int prot_ro;
3126
3127 if (domain_prot == 3) {
3128 return PAGE_READ | PAGE_WRITE;
3129 }
3130
3131 if (access_type == 1)
3132 prot_ro = 0;
3133 else
3134 prot_ro = PAGE_READ;
3135
3136 switch (ap) {
3137 case 0:
3138 if (arm_feature(env, ARM_FEATURE_V7)) {
3139 return 0;
3140 }
3141 if (access_type == 1)
3142 return 0;
3143 switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3144 case SCTLR_S:
3145 return is_user ? 0 : PAGE_READ;
3146 case SCTLR_R:
3147 return PAGE_READ;
3148 default:
3149 return 0;
3150 }
3151 case 1:
3152 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3153 case 2:
3154 if (is_user)
3155 return prot_ro;
3156 else
3157 return PAGE_READ | PAGE_WRITE;
3158 case 3:
3159 return PAGE_READ | PAGE_WRITE;
3160 case 4: /* Reserved. */
3161 return 0;
3162 case 5:
3163 return is_user ? 0 : prot_ro;
3164 case 6:
3165 return prot_ro;
3166 case 7:
3167 if (!arm_feature (env, ARM_FEATURE_V6K))
3168 return 0;
3169 return prot_ro;
3170 default:
3171 abort();
3172 }
3173 }
3174
3175 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
3176 {
3177 uint32_t table;
3178
3179 if (address & env->cp15.c2_mask)
3180 table = env->cp15.ttbr1_el1 & 0xffffc000;
3181 else
3182 table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3183
3184 table |= (address >> 18) & 0x3ffc;
3185 return table;
3186 }
3187
3188 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3189 int is_user, hwaddr *phys_ptr,
3190 int *prot, target_ulong *page_size)
3191 {
3192 CPUState *cs = CPU(arm_env_get_cpu(env));
3193 int code;
3194 uint32_t table;
3195 uint32_t desc;
3196 int type;
3197 int ap;
3198 int domain;
3199 int domain_prot;
3200 hwaddr phys_addr;
3201
3202 /* Pagetable walk. */
3203 /* Lookup l1 descriptor. */
3204 table = get_level1_table_address(env, address);
3205 desc = ldl_phys(cs->as, table);
3206 type = (desc & 3);
3207 domain = (desc >> 5) & 0x0f;
3208 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3209 if (type == 0) {
3210 /* Section translation fault. */
3211 code = 5;
3212 goto do_fault;
3213 }
3214 if (domain_prot == 0 || domain_prot == 2) {
3215 if (type == 2)
3216 code = 9; /* Section domain fault. */
3217 else
3218 code = 11; /* Page domain fault. */
3219 goto do_fault;
3220 }
3221 if (type == 2) {
3222 /* 1Mb section. */
3223 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3224 ap = (desc >> 10) & 3;
3225 code = 13;
3226 *page_size = 1024 * 1024;
3227 } else {
3228 /* Lookup l2 entry. */
3229 if (type == 1) {
3230 /* Coarse pagetable. */
3231 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3232 } else {
3233 /* Fine pagetable. */
3234 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3235 }
3236 desc = ldl_phys(cs->as, table);
3237 switch (desc & 3) {
3238 case 0: /* Page translation fault. */
3239 code = 7;
3240 goto do_fault;
3241 case 1: /* 64k page. */
3242 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3243 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3244 *page_size = 0x10000;
3245 break;
3246 case 2: /* 4k page. */
3247 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3248 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3249 *page_size = 0x1000;
3250 break;
3251 case 3: /* 1k page. */
3252 if (type == 1) {
3253 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3254 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3255 } else {
3256 /* Page translation fault. */
3257 code = 7;
3258 goto do_fault;
3259 }
3260 } else {
3261 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3262 }
3263 ap = (desc >> 4) & 3;
3264 *page_size = 0x400;
3265 break;
3266 default:
3267 /* Never happens, but compiler isn't smart enough to tell. */
3268 abort();
3269 }
3270 code = 15;
3271 }
3272 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3273 if (!*prot) {
3274 /* Access permission fault. */
3275 goto do_fault;
3276 }
3277 *prot |= PAGE_EXEC;
3278 *phys_ptr = phys_addr;
3279 return 0;
3280 do_fault:
3281 return code | (domain << 4);
3282 }
3283
3284 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3285 int is_user, hwaddr *phys_ptr,
3286 int *prot, target_ulong *page_size)
3287 {
3288 CPUState *cs = CPU(arm_env_get_cpu(env));
3289 int code;
3290 uint32_t table;
3291 uint32_t desc;
3292 uint32_t xn;
3293 uint32_t pxn = 0;
3294 int type;
3295 int ap;
3296 int domain = 0;
3297 int domain_prot;
3298 hwaddr phys_addr;
3299
3300 /* Pagetable walk. */
3301 /* Lookup l1 descriptor. */
3302 table = get_level1_table_address(env, address);
3303 desc = ldl_phys(cs->as, table);
3304 type = (desc & 3);
3305 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3306 /* Section translation fault, or attempt to use the encoding
3307 * which is Reserved on implementations without PXN.
3308 */
3309 code = 5;
3310 goto do_fault;
3311 }
3312 if ((type == 1) || !(desc & (1 << 18))) {
3313 /* Page or Section. */
3314 domain = (desc >> 5) & 0x0f;
3315 }
3316 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3317 if (domain_prot == 0 || domain_prot == 2) {
3318 if (type != 1) {
3319 code = 9; /* Section domain fault. */
3320 } else {
3321 code = 11; /* Page domain fault. */
3322 }
3323 goto do_fault;
3324 }
3325 if (type != 1) {
3326 if (desc & (1 << 18)) {
3327 /* Supersection. */
3328 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3329 *page_size = 0x1000000;
3330 } else {
3331 /* Section. */
3332 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3333 *page_size = 0x100000;
3334 }
3335 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3336 xn = desc & (1 << 4);
3337 pxn = desc & 1;
3338 code = 13;
3339 } else {
3340 if (arm_feature(env, ARM_FEATURE_PXN)) {
3341 pxn = (desc >> 2) & 1;
3342 }
3343 /* Lookup l2 entry. */
3344 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3345 desc = ldl_phys(cs->as, table);
3346 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3347 switch (desc & 3) {
3348 case 0: /* Page translation fault. */
3349 code = 7;
3350 goto do_fault;
3351 case 1: /* 64k page. */
3352 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3353 xn = desc & (1 << 15);
3354 *page_size = 0x10000;
3355 break;
3356 case 2: case 3: /* 4k page. */
3357 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3358 xn = desc & 1;
3359 *page_size = 0x1000;
3360 break;
3361 default:
3362 /* Never happens, but compiler isn't smart enough to tell. */
3363 abort();
3364 }
3365 code = 15;
3366 }
3367 if (domain_prot == 3) {
3368 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3369 } else {
3370 if (pxn && !is_user) {
3371 xn = 1;
3372 }
3373 if (xn && access_type == 2)
3374 goto do_fault;
3375
3376 /* The simplified model uses AP[0] as an access control bit. */
3377 if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3378 /* Access flag fault. */
3379 code = (code == 15) ? 6 : 3;
3380 goto do_fault;
3381 }
3382 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3383 if (!*prot) {
3384 /* Access permission fault. */
3385 goto do_fault;
3386 }
3387 if (!xn) {
3388 *prot |= PAGE_EXEC;
3389 }
3390 }
3391 *phys_ptr = phys_addr;
3392 return 0;
3393 do_fault:
3394 return code | (domain << 4);
3395 }
3396
3397 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3398 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3399 */
3400 typedef enum {
3401 translation_fault = 1,
3402 access_fault = 2,
3403 permission_fault = 3,
3404 } MMUFaultType;
3405
3406 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3407 int access_type, int is_user,
3408 hwaddr *phys_ptr, int *prot,
3409 target_ulong *page_size_ptr)
3410 {
3411 CPUState *cs = CPU(arm_env_get_cpu(env));
3412 /* Read an LPAE long-descriptor translation table. */
3413 MMUFaultType fault_type = translation_fault;
3414 uint32_t level = 1;
3415 uint32_t epd;
3416 int32_t tsz;
3417 uint32_t tg;
3418 uint64_t ttbr;
3419 int ttbr_select;
3420 hwaddr descaddr, descmask;
3421 uint32_t tableattrs;
3422 target_ulong page_size;
3423 uint32_t attrs;
3424 int32_t granule_sz = 9;
3425 int32_t va_size = 32;
3426 int32_t tbi = 0;
3427
3428 if (arm_el_is_aa64(env, 1)) {
3429 va_size = 64;
3430 if (extract64(address, 55, 1))
3431 tbi = extract64(env->cp15.c2_control, 38, 1);
3432 else
3433 tbi = extract64(env->cp15.c2_control, 37, 1);
3434 tbi *= 8;
3435 }
3436
3437 /* Determine whether this address is in the region controlled by
3438 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3439 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3440 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3441 */
3442 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3443 if (arm_el_is_aa64(env, 1)) {
3444 t0sz = MIN(t0sz, 39);
3445 t0sz = MAX(t0sz, 16);
3446 }
3447 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3448 if (arm_el_is_aa64(env, 1)) {
3449 t1sz = MIN(t1sz, 39);
3450 t1sz = MAX(t1sz, 16);
3451 }
3452 if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3453 /* there is a ttbr0 region and we are in it (high bits all zero) */
3454 ttbr_select = 0;
3455 } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3456 /* there is a ttbr1 region and we are in it (high bits all one) */
3457 ttbr_select = 1;
3458 } else if (!t0sz) {
3459 /* ttbr0 region is "everything not in the ttbr1 region" */
3460 ttbr_select = 0;
3461 } else if (!t1sz) {
3462 /* ttbr1 region is "everything not in the ttbr0 region" */
3463 ttbr_select = 1;
3464 } else {
3465 /* in the gap between the two regions, this is a Translation fault */
3466 fault_type = translation_fault;
3467 goto do_fault;
3468 }
3469
3470 /* Note that QEMU ignores shareability and cacheability attributes,
3471 * so we don't need to do anything with the SH, ORGN, IRGN fields
3472 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3473 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3474 * implement any ASID-like capability so we can ignore it (instead
3475 * we will always flush the TLB any time the ASID is changed).
3476 */
3477 if (ttbr_select == 0) {
3478 ttbr = env->cp15.ttbr0_el1;
3479 epd = extract32(env->cp15.c2_control, 7, 1);
3480 tsz = t0sz;
3481
3482 tg = extract32(env->cp15.c2_control, 14, 2);
3483 if (tg == 1) { /* 64KB pages */
3484 granule_sz = 13;
3485 }
3486 if (tg == 2) { /* 16KB pages */
3487 granule_sz = 11;
3488 }
3489 } else {
3490 ttbr = env->cp15.ttbr1_el1;
3491 epd = extract32(env->cp15.c2_control, 23, 1);
3492 tsz = t1sz;
3493
3494 tg = extract32(env->cp15.c2_control, 30, 2);
3495 if (tg == 3) { /* 64KB pages */
3496 granule_sz = 13;
3497 }
3498 if (tg == 1) { /* 16KB pages */
3499 granule_sz = 11;
3500 }
3501 }
3502
3503 if (epd) {
3504 /* Translation table walk disabled => Translation fault on TLB miss */
3505 goto do_fault;
3506 }
3507
3508 /* The starting level depends on the virtual address size which can be
3509 * up to 48-bits and the translation granule size.
3510 */
3511 if ((va_size - tsz) > (granule_sz * 4 + 3)) {
3512 level = 0;
3513 } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
3514 level = 1;
3515 } else {
3516 level = 2;
3517 }
3518
3519 /* Clear the vaddr bits which aren't part of the within-region address,
3520 * so that we don't have to special case things when calculating the
3521 * first descriptor address.
3522 */
3523 if (tsz) {
3524 address &= (1ULL << (va_size - tsz)) - 1;
3525 }
3526
3527 descmask = (1ULL << (granule_sz + 3)) - 1;
3528
3529 /* Now we can extract the actual base address from the TTBR */
3530 descaddr = extract64(ttbr, 0, 48);
3531 descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
3532
3533 tableattrs = 0;
3534 for (;;) {
3535 uint64_t descriptor;
3536
3537 descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
3538 descaddr &= ~7ULL;
3539 descriptor = ldq_phys(cs->as, descaddr);
3540 if (!(descriptor & 1) ||
3541 (!(descriptor & 2) && (level == 3))) {
3542 /* Invalid, or the Reserved level 3 encoding */
3543 goto do_fault;
3544 }
3545 descaddr = descriptor & 0xfffffff000ULL;
3546
3547 if ((descriptor & 2) && (level < 3)) {
3548 /* Table entry. The top five bits are attributes which may
3549 * propagate down through lower levels of the table (and
3550 * which are all arranged so that 0 means "no effect", so
3551 * we can gather them up by ORing in the bits at each level).
3552 */
3553 tableattrs |= extract64(descriptor, 59, 5);
3554 level++;
3555 continue;
3556 }
3557 /* Block entry at level 1 or 2, or page entry at level 3.
3558 * These are basically the same thing, although the number
3559 * of bits we pull in from the vaddr varies.
3560 */
3561 page_size = (1 << ((granule_sz * (4 - level)) + 3));
3562 descaddr |= (address & (page_size - 1));
3563 /* Extract attributes from the descriptor and merge with table attrs */
3564 if (arm_feature(env, ARM_FEATURE_V8)) {
3565 attrs = extract64(descriptor, 2, 10)
3566 | (extract64(descriptor, 53, 11) << 10);
3567 } else {
3568 attrs = extract64(descriptor, 2, 10)
3569 | (extract64(descriptor, 52, 12) << 10);
3570 }
3571 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3572 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3573 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3574 * means "force PL1 access only", which means forcing AP[1] to 0.
3575 */
3576 if (extract32(tableattrs, 2, 1)) {
3577 attrs &= ~(1 << 4);
3578 }
3579 /* Since we're always in the Non-secure state, NSTable is ignored. */
3580 break;
3581 }
3582 /* Here descaddr is the final physical address, and attributes
3583 * are all in attrs.
3584 */
3585 fault_type = access_fault;
3586 if ((attrs & (1 << 8)) == 0) {
3587 /* Access flag */
3588 goto do_fault;
3589 }
3590 fault_type = permission_fault;
3591 if (is_user && !(attrs & (1 << 4))) {
3592 /* Unprivileged access not enabled */
3593 goto do_fault;
3594 }
3595 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3596 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3597 /* XN or PXN */
3598 if (access_type == 2) {
3599 goto do_fault;
3600 }
3601 *prot &= ~PAGE_EXEC;
3602 }
3603 if (attrs & (1 << 5)) {
3604 /* Write access forbidden */
3605 if (access_type == 1) {
3606 goto do_fault;
3607 }
3608 *prot &= ~PAGE_WRITE;
3609 }
3610
3611 *phys_ptr = descaddr;
3612 *page_size_ptr = page_size;
3613 return 0;
3614
3615 do_fault:
3616 /* Long-descriptor format IFSR/DFSR value */
3617 return (1 << 9) | (fault_type << 2) | level;
3618 }
3619
3620 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3621 int access_type, int is_user,
3622 hwaddr *phys_ptr, int *prot)
3623 {
3624 int n;
3625 uint32_t mask;
3626 uint32_t base;
3627
3628 *phys_ptr = address;
3629 for (n = 7; n >= 0; n--) {
3630 base = env->cp15.c6_region[n];
3631 if ((base & 1) == 0)
3632 continue;
3633 mask = 1 << ((base >> 1) & 0x1f);
3634 /* Keep this shift separate from the above to avoid an
3635 (undefined) << 32. */
3636 mask = (mask << 1) - 1;
3637 if (((base ^ address) & ~mask) == 0)
3638 break;
3639 }
3640 if (n < 0)
3641 return 2;
3642
3643 if (access_type == 2) {
3644 mask = env->cp15.c5_insn;
3645 } else {
3646 mask = env->cp15.c5_data;
3647 }
3648 mask = (mask >> (n * 4)) & 0xf;
3649 switch (mask) {
3650 case 0:
3651 return 1;
3652 case 1:
3653 if (is_user)
3654 return 1;
3655 *prot = PAGE_READ | PAGE_WRITE;
3656 break;
3657 case 2:
3658 *prot = PAGE_READ;
3659 if (!is_user)
3660 *prot |= PAGE_WRITE;
3661 break;
3662 case 3:
3663 *prot = PAGE_READ | PAGE_WRITE;
3664 break;
3665 case 5:
3666 if (is_user)
3667 return 1;
3668 *prot = PAGE_READ;
3669 break;
3670 case 6:
3671 *prot = PAGE_READ;
3672 break;
3673 default:
3674 /* Bad permission. */
3675 return 1;
3676 }
3677 *prot |= PAGE_EXEC;
3678 return 0;
3679 }
3680
3681 /* get_phys_addr - get the physical address for this virtual address
3682 *
3683 * Find the physical address corresponding to the given virtual address,
3684 * by doing a translation table walk on MMU based systems or using the
3685 * MPU state on MPU based systems.
3686 *
3687 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3688 * prot and page_size are not filled in, and the return value provides
3689 * information on why the translation aborted, in the format of a
3690 * DFSR/IFSR fault register, with the following caveats:
3691 * * we honour the short vs long DFSR format differences.
3692 * * the WnR bit is never set (the caller must do this).
3693 * * for MPU based systems we don't bother to return a full FSR format
3694 * value.
3695 *
3696 * @env: CPUARMState
3697 * @address: virtual address to get physical address for
3698 * @access_type: 0 for read, 1 for write, 2 for execute
3699 * @is_user: 0 for privileged access, 1 for user
3700 * @phys_ptr: set to the physical address corresponding to the virtual address
3701 * @prot: set to the permissions for the page containing phys_ptr
3702 * @page_size: set to the size of the page containing phys_ptr
3703 */
3704 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
3705 int access_type, int is_user,
3706 hwaddr *phys_ptr, int *prot,
3707 target_ulong *page_size)
3708 {
3709 /* Fast Context Switch Extension. */
3710 if (address < 0x02000000)
3711 address += env->cp15.c13_fcse;
3712
3713 if ((env->cp15.c1_sys & SCTLR_M) == 0) {
3714 /* MMU/MPU disabled. */
3715 *phys_ptr = address;
3716 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3717 *page_size = TARGET_PAGE_SIZE;
3718 return 0;
3719 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
3720 *page_size = TARGET_PAGE_SIZE;
3721 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3722 prot);
3723 } else if (extended_addresses_enabled(env)) {
3724 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3725 prot, page_size);
3726 } else if (env->cp15.c1_sys & SCTLR_XP) {
3727 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3728 prot, page_size);
3729 } else {
3730 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3731 prot, page_size);
3732 }
3733 }
3734
3735 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
3736 int access_type, int mmu_idx)
3737 {
3738 ARMCPU *cpu = ARM_CPU(cs);
3739 CPUARMState *env = &cpu->env;
3740 hwaddr phys_addr;
3741 target_ulong page_size;
3742 int prot;
3743 int ret, is_user;
3744 uint32_t syn;
3745 bool same_el = (arm_current_pl(env) != 0);
3746
3747 is_user = mmu_idx == MMU_USER_IDX;
3748 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3749 &page_size);
3750 if (ret == 0) {
3751 /* Map a single [sub]page. */
3752 phys_addr &= ~(hwaddr)0x3ff;
3753 address &= ~(target_ulong)0x3ff;
3754 tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
3755 return 0;
3756 }
3757
3758 /* AArch64 syndrome does not have an LPAE bit */
3759 syn = ret & ~(1 << 9);
3760
3761 /* For insn and data aborts we assume there is no instruction syndrome
3762 * information; this is always true for exceptions reported to EL1.
3763 */
3764 if (access_type == 2) {
3765 syn = syn_insn_abort(same_el, 0, 0, syn);
3766 cs->exception_index = EXCP_PREFETCH_ABORT;
3767 } else {
3768 syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
3769 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
3770 ret |= (1 << 11);
3771 }
3772 cs->exception_index = EXCP_DATA_ABORT;
3773 }
3774
3775 env->exception.syndrome = syn;
3776 env->exception.vaddress = address;
3777 env->exception.fsr = ret;
3778 return 1;
3779 }
3780
3781 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3782 {
3783 ARMCPU *cpu = ARM_CPU(cs);
3784 hwaddr phys_addr;
3785 target_ulong page_size;
3786 int prot;
3787 int ret;
3788
3789 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3790
3791 if (ret != 0) {
3792 return -1;
3793 }
3794
3795 return phys_addr;
3796 }
3797
3798 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3799 {
3800 if ((env->uncached_cpsr & CPSR_M) == mode) {
3801 env->regs[13] = val;
3802 } else {
3803 env->banked_r13[bank_number(mode)] = val;
3804 }
3805 }
3806
3807 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3808 {
3809 if ((env->uncached_cpsr & CPSR_M) == mode) {
3810 return env->regs[13];
3811 } else {
3812 return env->banked_r13[bank_number(mode)];
3813 }
3814 }
3815
3816 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3817 {
3818 ARMCPU *cpu = arm_env_get_cpu(env);
3819
3820 switch (reg) {
3821 case 0: /* APSR */
3822 return xpsr_read(env) & 0xf8000000;
3823 case 1: /* IAPSR */
3824 return xpsr_read(env) & 0xf80001ff;
3825 case 2: /* EAPSR */
3826 return xpsr_read(env) & 0xff00fc00;
3827 case 3: /* xPSR */
3828 return xpsr_read(env) & 0xff00fdff;
3829 case 5: /* IPSR */
3830 return xpsr_read(env) & 0x000001ff;
3831 case 6: /* EPSR */
3832 return xpsr_read(env) & 0x0700fc00;
3833 case 7: /* IEPSR */
3834 return xpsr_read(env) & 0x0700edff;
3835 case 8: /* MSP */
3836 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3837 case 9: /* PSP */
3838 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3839 case 16: /* PRIMASK */
3840 return (env->daif & PSTATE_I) != 0;
3841 case 17: /* BASEPRI */
3842 case 18: /* BASEPRI_MAX */
3843 return env->v7m.basepri;
3844 case 19: /* FAULTMASK */
3845 return (env->daif & PSTATE_F) != 0;
3846 case 20: /* CONTROL */
3847 return env->v7m.control;
3848 default:
3849 /* ??? For debugging only. */
3850 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
3851 return 0;
3852 }
3853 }
3854
3855 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3856 {
3857 ARMCPU *cpu = arm_env_get_cpu(env);
3858
3859 switch (reg) {
3860 case 0: /* APSR */
3861 xpsr_write(env, val, 0xf8000000);
3862 break;
3863 case 1: /* IAPSR */
3864 xpsr_write(env, val, 0xf8000000);
3865 break;
3866 case 2: /* EAPSR */
3867 xpsr_write(env, val, 0xfe00fc00);
3868 break;
3869 case 3: /* xPSR */
3870 xpsr_write(env, val, 0xfe00fc00);
3871 break;
3872 case 5: /* IPSR */
3873 /* IPSR bits are readonly. */
3874 break;
3875 case 6: /* EPSR */
3876 xpsr_write(env, val, 0x0600fc00);
3877 break;
3878 case 7: /* IEPSR */
3879 xpsr_write(env, val, 0x0600fc00);
3880 break;
3881 case 8: /* MSP */
3882 if (env->v7m.current_sp)
3883 env->v7m.other_sp = val;
3884 else
3885 env->regs[13] = val;
3886 break;
3887 case 9: /* PSP */
3888 if (env->v7m.current_sp)
3889 env->regs[13] = val;
3890 else
3891 env->v7m.other_sp = val;
3892 break;
3893 case 16: /* PRIMASK */
3894 if (val & 1) {
3895 env->daif |= PSTATE_I;
3896 } else {
3897 env->daif &= ~PSTATE_I;
3898 }
3899 break;
3900 case 17: /* BASEPRI */
3901 env->v7m.basepri = val & 0xff;
3902 break;
3903 case 18: /* BASEPRI_MAX */
3904 val &= 0xff;
3905 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3906 env->v7m.basepri = val;
3907 break;
3908 case 19: /* FAULTMASK */
3909 if (val & 1) {
3910 env->daif |= PSTATE_F;
3911 } else {
3912 env->daif &= ~PSTATE_F;
3913 }
3914 break;
3915 case 20: /* CONTROL */
3916 env->v7m.control = val & 3;
3917 switch_v7m_sp(env, (val & 2) != 0);
3918 break;
3919 default:
3920 /* ??? For debugging only. */
3921 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
3922 return;
3923 }
3924 }
3925
3926 #endif
3927
3928 /* Note that signed overflow is undefined in C. The following routines are
3929 careful to use unsigned types where modulo arithmetic is required.
3930 Failure to do so _will_ break on newer gcc. */
3931
3932 /* Signed saturating arithmetic. */
3933
3934 /* Perform 16-bit signed saturating addition. */
3935 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3936 {
3937 uint16_t res;
3938
3939 res = a + b;
3940 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3941 if (a & 0x8000)
3942 res = 0x8000;
3943 else
3944 res = 0x7fff;
3945 }
3946 return res;
3947 }
3948
3949 /* Perform 8-bit signed saturating addition. */
3950 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3951 {
3952 uint8_t res;
3953
3954 res = a + b;
3955 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3956 if (a & 0x80)
3957 res = 0x80;
3958 else
3959 res = 0x7f;
3960 }
3961 return res;
3962 }
3963
3964 /* Perform 16-bit signed saturating subtraction. */
3965 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3966 {
3967 uint16_t res;
3968
3969 res = a - b;
3970 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3971 if (a & 0x8000)
3972 res = 0x8000;
3973 else
3974 res = 0x7fff;
3975 }
3976 return res;
3977 }
3978
3979 /* Perform 8-bit signed saturating subtraction. */
3980 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3981 {
3982 uint8_t res;
3983
3984 res = a - b;
3985 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3986 if (a & 0x80)
3987 res = 0x80;
3988 else
3989 res = 0x7f;
3990 }
3991 return res;
3992 }
3993
3994 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3995 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3996 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3997 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3998 #define PFX q
3999
4000 #include "op_addsub.h"
4001
4002 /* Unsigned saturating arithmetic. */
4003 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4004 {
4005 uint16_t res;
4006 res = a + b;
4007 if (res < a)
4008 res = 0xffff;
4009 return res;
4010 }
4011
4012 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4013 {
4014 if (a > b)
4015 return a - b;
4016 else
4017 return 0;
4018 }
4019
4020 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4021 {
4022 uint8_t res;
4023 res = a + b;
4024 if (res < a)
4025 res = 0xff;
4026 return res;
4027 }
4028
4029 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4030 {
4031 if (a > b)
4032 return a - b;
4033 else
4034 return 0;
4035 }
4036
4037 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4038 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4039 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
4040 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
4041 #define PFX uq
4042
4043 #include "op_addsub.h"
4044
4045 /* Signed modulo arithmetic. */
4046 #define SARITH16(a, b, n, op) do { \
4047 int32_t sum; \
4048 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4049 RESULT(sum, n, 16); \
4050 if (sum >= 0) \
4051 ge |= 3 << (n * 2); \
4052 } while(0)
4053
4054 #define SARITH8(a, b, n, op) do { \
4055 int32_t sum; \
4056 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4057 RESULT(sum, n, 8); \
4058 if (sum >= 0) \
4059 ge |= 1 << n; \
4060 } while(0)
4061
4062
4063 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4064 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4065 #define ADD8(a, b, n) SARITH8(a, b, n, +)
4066 #define SUB8(a, b, n) SARITH8(a, b, n, -)
4067 #define PFX s
4068 #define ARITH_GE
4069
4070 #include "op_addsub.h"
4071
4072 /* Unsigned modulo arithmetic. */
4073 #define ADD16(a, b, n) do { \
4074 uint32_t sum; \
4075 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4076 RESULT(sum, n, 16); \
4077 if ((sum >> 16) == 1) \
4078 ge |= 3 << (n * 2); \
4079 } while(0)
4080
4081 #define ADD8(a, b, n) do { \
4082 uint32_t sum; \
4083 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4084 RESULT(sum, n, 8); \
4085 if ((sum >> 8) == 1) \
4086 ge |= 1 << n; \
4087 } while(0)
4088
4089 #define SUB16(a, b, n) do { \
4090 uint32_t sum; \
4091 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4092 RESULT(sum, n, 16); \
4093 if ((sum >> 16) == 0) \
4094 ge |= 3 << (n * 2); \
4095 } while(0)
4096
4097 #define SUB8(a, b, n) do { \
4098 uint32_t sum; \
4099 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4100 RESULT(sum, n, 8); \
4101 if ((sum >> 8) == 0) \
4102 ge |= 1 << n; \
4103 } while(0)
4104
4105 #define PFX u
4106 #define ARITH_GE
4107
4108 #include "op_addsub.h"
4109
4110 /* Halved signed arithmetic. */
4111 #define ADD16(a, b, n) \
4112 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4113 #define SUB16(a, b, n) \
4114 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4115 #define ADD8(a, b, n) \
4116 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4117 #define SUB8(a, b, n) \
4118 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4119 #define PFX sh
4120
4121 #include "op_addsub.h"
4122
4123 /* Halved unsigned arithmetic. */
4124 #define ADD16(a, b, n) \
4125 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4126 #define SUB16(a, b, n) \
4127 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4128 #define ADD8(a, b, n) \
4129 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4130 #define SUB8(a, b, n) \
4131 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4132 #define PFX uh
4133
4134 #include "op_addsub.h"
4135
4136 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4137 {
4138 if (a > b)
4139 return a - b;
4140 else
4141 return b - a;
4142 }
4143
4144 /* Unsigned sum of absolute byte differences. */
4145 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4146 {
4147 uint32_t sum;
4148 sum = do_usad(a, b);
4149 sum += do_usad(a >> 8, b >> 8);
4150 sum += do_usad(a >> 16, b >>16);
4151 sum += do_usad(a >> 24, b >> 24);
4152 return sum;
4153 }
4154
4155 /* For ARMv6 SEL instruction. */
4156 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4157 {
4158 uint32_t mask;
4159
4160 mask = 0;
4161 if (flags & 1)
4162 mask |= 0xff;
4163 if (flags & 2)
4164 mask |= 0xff00;
4165 if (flags & 4)
4166 mask |= 0xff0000;
4167 if (flags & 8)
4168 mask |= 0xff000000;
4169 return (a & mask) | (b & ~mask);
4170 }
4171
4172 /* VFP support. We follow the convention used for VFP instructions:
4173 Single precision routines have a "s" suffix, double precision a
4174 "d" suffix. */
4175
4176 /* Convert host exception flags to vfp form. */
4177 static inline int vfp_exceptbits_from_host(int host_bits)
4178 {
4179 int target_bits = 0;
4180
4181 if (host_bits & float_flag_invalid)
4182 target_bits |= 1;
4183 if (host_bits & float_flag_divbyzero)
4184 target_bits |= 2;
4185 if (host_bits & float_flag_overflow)
4186 target_bits |= 4;
4187 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4188 target_bits |= 8;
4189 if (host_bits & float_flag_inexact)
4190 target_bits |= 0x10;
4191 if (host_bits & float_flag_input_denormal)
4192 target_bits |= 0x80;
4193 return target_bits;
4194 }
4195
4196 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4197 {
4198 int i;
4199 uint32_t fpscr;
4200
4201 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4202 | (env->vfp.vec_len << 16)
4203 | (env->vfp.vec_stride << 20);
4204 i = get_float_exception_flags(&env->vfp.fp_status);
4205 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4206 fpscr |= vfp_exceptbits_from_host(i);
4207 return fpscr;
4208 }
4209
4210 uint32_t vfp_get_fpscr(CPUARMState *env)
4211 {
4212 return HELPER(vfp_get_fpscr)(env);
4213 }
4214
4215 /* Convert vfp exception flags to target form. */
4216 static inline int vfp_exceptbits_to_host(int target_bits)
4217 {
4218 int host_bits = 0;
4219
4220 if (target_bits & 1)
4221 host_bits |= float_flag_invalid;
4222 if (target_bits & 2)
4223 host_bits |= float_flag_divbyzero;
4224 if (target_bits & 4)
4225 host_bits |= float_flag_overflow;
4226 if (target_bits & 8)
4227 host_bits |= float_flag_underflow;
4228 if (target_bits & 0x10)
4229 host_bits |= float_flag_inexact;
4230 if (target_bits & 0x80)
4231 host_bits |= float_flag_input_denormal;
4232 return host_bits;
4233 }
4234
4235 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4236 {
4237 int i;
4238 uint32_t changed;
4239
4240 changed = env->vfp.xregs[ARM_VFP_FPSCR];
4241 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4242 env->vfp.vec_len = (val >> 16) & 7;
4243 env->vfp.vec_stride = (val >> 20) & 3;
4244
4245 changed ^= val;
4246 if (changed & (3 << 22)) {
4247 i = (val >> 22) & 3;
4248 switch (i) {
4249 case FPROUNDING_TIEEVEN:
4250 i = float_round_nearest_even;
4251 break;
4252 case FPROUNDING_POSINF:
4253 i = float_round_up;
4254 break;
4255 case FPROUNDING_NEGINF:
4256 i = float_round_down;
4257 break;
4258 case FPROUNDING_ZERO:
4259 i = float_round_to_zero;
4260 break;
4261 }
4262 set_float_rounding_mode(i, &env->vfp.fp_status);
4263 }
4264 if (changed & (1 << 24)) {
4265 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4266 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4267 }
4268 if (changed & (1 << 25))
4269 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4270
4271 i = vfp_exceptbits_to_host(val);
4272 set_float_exception_flags(i, &env->vfp.fp_status);
4273 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4274 }
4275
4276 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4277 {
4278 HELPER(vfp_set_fpscr)(env, val);
4279 }
4280
4281 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4282
4283 #define VFP_BINOP(name) \
4284 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4285 { \
4286 float_status *fpst = fpstp; \
4287 return float32_ ## name(a, b, fpst); \
4288 } \
4289 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4290 { \
4291 float_status *fpst = fpstp; \
4292 return float64_ ## name(a, b, fpst); \
4293 }
4294 VFP_BINOP(add)
4295 VFP_BINOP(sub)
4296 VFP_BINOP(mul)
4297 VFP_BINOP(div)
4298 VFP_BINOP(min)
4299 VFP_BINOP(max)
4300 VFP_BINOP(minnum)
4301 VFP_BINOP(maxnum)
4302 #undef VFP_BINOP
4303
4304 float32 VFP_HELPER(neg, s)(float32 a)
4305 {
4306 return float32_chs(a);
4307 }
4308
4309 float64 VFP_HELPER(neg, d)(float64 a)
4310 {
4311 return float64_chs(a);
4312 }
4313
4314 float32 VFP_HELPER(abs, s)(float32 a)
4315 {
4316 return float32_abs(a);
4317 }
4318
4319 float64 VFP_HELPER(abs, d)(float64 a)
4320 {
4321 return float64_abs(a);
4322 }
4323
4324 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4325 {
4326 return float32_sqrt(a, &env->vfp.fp_status);
4327 }
4328
4329 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4330 {
4331 return float64_sqrt(a, &env->vfp.fp_status);
4332 }
4333
4334 /* XXX: check quiet/signaling case */
4335 #define DO_VFP_cmp(p, type) \
4336 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4337 { \
4338 uint32_t flags; \
4339 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4340 case 0: flags = 0x6; break; \
4341 case -1: flags = 0x8; break; \
4342 case 1: flags = 0x2; break; \
4343 default: case 2: flags = 0x3; break; \
4344 } \
4345 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4346 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4347 } \
4348 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4349 { \
4350 uint32_t flags; \
4351 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4352 case 0: flags = 0x6; break; \
4353 case -1: flags = 0x8; break; \
4354 case 1: flags = 0x2; break; \
4355 default: case 2: flags = 0x3; break; \
4356 } \
4357 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4358 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4359 }
4360 DO_VFP_cmp(s, float32)
4361 DO_VFP_cmp(d, float64)
4362 #undef DO_VFP_cmp
4363
4364 /* Integer to float and float to integer conversions */
4365
4366 #define CONV_ITOF(name, fsz, sign) \
4367 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4368 { \
4369 float_status *fpst = fpstp; \
4370 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4371 }
4372
4373 #define CONV_FTOI(name, fsz, sign, round) \
4374 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4375 { \
4376 float_status *fpst = fpstp; \
4377 if (float##fsz##_is_any_nan(x)) { \
4378 float_raise(float_flag_invalid, fpst); \
4379 return 0; \
4380 } \
4381 return float##fsz##_to_##sign##int32##round(x, fpst); \
4382 }
4383
4384 #define FLOAT_CONVS(name, p, fsz, sign) \
4385 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4386 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4387 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4388
4389 FLOAT_CONVS(si, s, 32, )
4390 FLOAT_CONVS(si, d, 64, )
4391 FLOAT_CONVS(ui, s, 32, u)
4392 FLOAT_CONVS(ui, d, 64, u)
4393
4394 #undef CONV_ITOF
4395 #undef CONV_FTOI
4396 #undef FLOAT_CONVS
4397
4398 /* floating point conversion */
4399 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4400 {
4401 float64 r = float32_to_float64(x, &env->vfp.fp_status);
4402 /* ARM requires that S<->D conversion of any kind of NaN generates
4403 * a quiet NaN by forcing the most significant frac bit to 1.
4404 */
4405 return float64_maybe_silence_nan(r);
4406 }
4407
4408 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4409 {
4410 float32 r = float64_to_float32(x, &env->vfp.fp_status);
4411 /* ARM requires that S<->D conversion of any kind of NaN generates
4412 * a quiet NaN by forcing the most significant frac bit to 1.
4413 */
4414 return float32_maybe_silence_nan(r);
4415 }
4416
4417 /* VFP3 fixed point conversion. */
4418 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4419 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4420 void *fpstp) \
4421 { \
4422 float_status *fpst = fpstp; \
4423 float##fsz tmp; \
4424 tmp = itype##_to_##float##fsz(x, fpst); \
4425 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4426 }
4427
4428 /* Notice that we want only input-denormal exception flags from the
4429 * scalbn operation: the other possible flags (overflow+inexact if
4430 * we overflow to infinity, output-denormal) aren't correct for the
4431 * complete scale-and-convert operation.
4432 */
4433 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4434 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4435 uint32_t shift, \
4436 void *fpstp) \
4437 { \
4438 float_status *fpst = fpstp; \
4439 int old_exc_flags = get_float_exception_flags(fpst); \
4440 float##fsz tmp; \
4441 if (float##fsz##_is_any_nan(x)) { \
4442 float_raise(float_flag_invalid, fpst); \
4443 return 0; \
4444 } \
4445 tmp = float##fsz##_scalbn(x, shift, fpst); \
4446 old_exc_flags |= get_float_exception_flags(fpst) \
4447 & float_flag_input_denormal; \
4448 set_float_exception_flags(old_exc_flags, fpst); \
4449 return float##fsz##_to_##itype##round(tmp, fpst); \
4450 }
4451
4452 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4453 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4454 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4455 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4456
4457 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4458 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4459 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4460
4461 VFP_CONV_FIX(sh, d, 64, 64, int16)
4462 VFP_CONV_FIX(sl, d, 64, 64, int32)
4463 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4464 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4465 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4466 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4467 VFP_CONV_FIX(sh, s, 32, 32, int16)
4468 VFP_CONV_FIX(sl, s, 32, 32, int32)
4469 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4470 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4471 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4472 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4473 #undef VFP_CONV_FIX
4474 #undef VFP_CONV_FIX_FLOAT
4475 #undef VFP_CONV_FLOAT_FIX_ROUND
4476
4477 /* Set the current fp rounding mode and return the old one.
4478 * The argument is a softfloat float_round_ value.
4479 */
4480 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4481 {
4482 float_status *fp_status = &env->vfp.fp_status;
4483
4484 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4485 set_float_rounding_mode(rmode, fp_status);
4486
4487 return prev_rmode;
4488 }
4489
4490 /* Set the current fp rounding mode in the standard fp status and return
4491 * the old one. This is for NEON instructions that need to change the
4492 * rounding mode but wish to use the standard FPSCR values for everything
4493 * else. Always set the rounding mode back to the correct value after
4494 * modifying it.
4495 * The argument is a softfloat float_round_ value.
4496 */
4497 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4498 {
4499 float_status *fp_status = &env->vfp.standard_fp_status;
4500
4501 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4502 set_float_rounding_mode(rmode, fp_status);
4503
4504 return prev_rmode;
4505 }
4506
4507 /* Half precision conversions. */
4508 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4509 {
4510 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4511 float32 r = float16_to_float32(make_float16(a), ieee, s);
4512 if (ieee) {
4513 return float32_maybe_silence_nan(r);
4514 }
4515 return r;
4516 }
4517
4518 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4519 {
4520 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4521 float16 r = float32_to_float16(a, ieee, s);
4522 if (ieee) {
4523 r = float16_maybe_silence_nan(r);
4524 }
4525 return float16_val(r);
4526 }
4527
4528 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4529 {
4530 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4531 }
4532
4533 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4534 {
4535 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4536 }
4537
4538 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4539 {
4540 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4541 }
4542
4543 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4544 {
4545 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4546 }
4547
4548 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4549 {
4550 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4551 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4552 if (ieee) {
4553 return float64_maybe_silence_nan(r);
4554 }
4555 return r;
4556 }
4557
4558 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4559 {
4560 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4561 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4562 if (ieee) {
4563 r = float16_maybe_silence_nan(r);
4564 }
4565 return float16_val(r);
4566 }
4567
4568 #define float32_two make_float32(0x40000000)
4569 #define float32_three make_float32(0x40400000)
4570 #define float32_one_point_five make_float32(0x3fc00000)
4571
4572 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4573 {
4574 float_status *s = &env->vfp.standard_fp_status;
4575 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4576 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4577 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4578 float_raise(float_flag_input_denormal, s);
4579 }
4580 return float32_two;
4581 }
4582 return float32_sub(float32_two, float32_mul(a, b, s), s);
4583 }
4584
4585 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4586 {
4587 float_status *s = &env->vfp.standard_fp_status;
4588 float32 product;
4589 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4590 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4591 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4592 float_raise(float_flag_input_denormal, s);
4593 }
4594 return float32_one_point_five;
4595 }
4596 product = float32_mul(a, b, s);
4597 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4598 }
4599
4600 /* NEON helpers. */
4601
4602 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4603 * int->float conversions at run-time. */
4604 #define float64_256 make_float64(0x4070000000000000LL)
4605 #define float64_512 make_float64(0x4080000000000000LL)
4606 #define float32_maxnorm make_float32(0x7f7fffff)
4607 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
4608
4609 /* Reciprocal functions
4610 *
4611 * The algorithm that must be used to calculate the estimate
4612 * is specified by the ARM ARM, see FPRecipEstimate()
4613 */
4614
4615 static float64 recip_estimate(float64 a, float_status *real_fp_status)
4616 {
4617 /* These calculations mustn't set any fp exception flags,
4618 * so we use a local copy of the fp_status.
4619 */
4620 float_status dummy_status = *real_fp_status;
4621 float_status *s = &dummy_status;
4622 /* q = (int)(a * 512.0) */
4623 float64 q = float64_mul(float64_512, a, s);
4624 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4625
4626 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4627 q = int64_to_float64(q_int, s);
4628 q = float64_add(q, float64_half, s);
4629 q = float64_div(q, float64_512, s);
4630 q = float64_div(float64_one, q, s);
4631
4632 /* s = (int)(256.0 * r + 0.5) */
4633 q = float64_mul(q, float64_256, s);
4634 q = float64_add(q, float64_half, s);
4635 q_int = float64_to_int64_round_to_zero(q, s);
4636
4637 /* return (double)s / 256.0 */
4638 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4639 }
4640
4641 /* Common wrapper to call recip_estimate */
4642 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
4643 {
4644 uint64_t val64 = float64_val(num);
4645 uint64_t frac = extract64(val64, 0, 52);
4646 int64_t exp = extract64(val64, 52, 11);
4647 uint64_t sbit;
4648 float64 scaled, estimate;
4649
4650 /* Generate the scaled number for the estimate function */
4651 if (exp == 0) {
4652 if (extract64(frac, 51, 1) == 0) {
4653 exp = -1;
4654 frac = extract64(frac, 0, 50) << 2;
4655 } else {
4656 frac = extract64(frac, 0, 51) << 1;
4657 }
4658 }
4659
4660 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
4661 scaled = make_float64((0x3feULL << 52)
4662 | extract64(frac, 44, 8) << 44);
4663
4664 estimate = recip_estimate(scaled, fpst);
4665
4666 /* Build new result */
4667 val64 = float64_val(estimate);
4668 sbit = 0x8000000000000000ULL & val64;
4669 exp = off - exp;
4670 frac = extract64(val64, 0, 52);
4671
4672 if (exp == 0) {
4673 frac = 1ULL << 51 | extract64(frac, 1, 51);
4674 } else if (exp == -1) {
4675 frac = 1ULL << 50 | extract64(frac, 2, 50);
4676 exp = 0;
4677 }
4678
4679 return make_float64(sbit | (exp << 52) | frac);
4680 }
4681
4682 static bool round_to_inf(float_status *fpst, bool sign_bit)
4683 {
4684 switch (fpst->float_rounding_mode) {
4685 case float_round_nearest_even: /* Round to Nearest */
4686 return true;
4687 case float_round_up: /* Round to +Inf */
4688 return !sign_bit;
4689 case float_round_down: /* Round to -Inf */
4690 return sign_bit;
4691 case float_round_to_zero: /* Round to Zero */
4692 return false;
4693 }
4694
4695 g_assert_not_reached();
4696 }
4697
4698 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
4699 {
4700 float_status *fpst = fpstp;
4701 float32 f32 = float32_squash_input_denormal(input, fpst);
4702 uint32_t f32_val = float32_val(f32);
4703 uint32_t f32_sbit = 0x80000000ULL & f32_val;
4704 int32_t f32_exp = extract32(f32_val, 23, 8);
4705 uint32_t f32_frac = extract32(f32_val, 0, 23);
4706 float64 f64, r64;
4707 uint64_t r64_val;
4708 int64_t r64_exp;
4709 uint64_t r64_frac;
4710
4711 if (float32_is_any_nan(f32)) {
4712 float32 nan = f32;
4713 if (float32_is_signaling_nan(f32)) {
4714 float_raise(float_flag_invalid, fpst);
4715 nan = float32_maybe_silence_nan(f32);
4716 }
4717 if (fpst->default_nan_mode) {
4718 nan = float32_default_nan;
4719 }
4720 return nan;
4721 } else if (float32_is_infinity(f32)) {
4722 return float32_set_sign(float32_zero, float32_is_neg(f32));
4723 } else if (float32_is_zero(f32)) {
4724 float_raise(float_flag_divbyzero, fpst);
4725 return float32_set_sign(float32_infinity, float32_is_neg(f32));
4726 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
4727 /* Abs(value) < 2.0^-128 */
4728 float_raise(float_flag_overflow | float_flag_inexact, fpst);
4729 if (round_to_inf(fpst, f32_sbit)) {
4730 return float32_set_sign(float32_infinity, float32_is_neg(f32));
4731 } else {
4732 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
4733 }
4734 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
4735 float_raise(float_flag_underflow, fpst);
4736 return float32_set_sign(float32_zero, float32_is_neg(f32));
4737 }
4738
4739
4740 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
4741 r64 = call_recip_estimate(f64, 253, fpst);
4742 r64_val = float64_val(r64);
4743 r64_exp = extract64(r64_val, 52, 11);
4744 r64_frac = extract64(r64_val, 0, 52);
4745
4746 /* result = sign : result_exp<7:0> : fraction<51:29>; */
4747 return make_float32(f32_sbit |
4748 (r64_exp & 0xff) << 23 |
4749 extract64(r64_frac, 29, 24));
4750 }
4751
4752 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
4753 {
4754 float_status *fpst = fpstp;
4755 float64 f64 = float64_squash_input_denormal(input, fpst);
4756 uint64_t f64_val = float64_val(f64);
4757 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
4758 int64_t f64_exp = extract64(f64_val, 52, 11);
4759 float64 r64;
4760 uint64_t r64_val;
4761 int64_t r64_exp;
4762 uint64_t r64_frac;
4763
4764 /* Deal with any special cases */
4765 if (float64_is_any_nan(f64)) {
4766 float64 nan = f64;
4767 if (float64_is_signaling_nan(f64)) {
4768 float_raise(float_flag_invalid, fpst);
4769 nan = float64_maybe_silence_nan(f64);
4770 }
4771 if (fpst->default_nan_mode) {
4772 nan = float64_default_nan;
4773 }
4774 return nan;
4775 } else if (float64_is_infinity(f64)) {
4776 return float64_set_sign(float64_zero, float64_is_neg(f64));
4777 } else if (float64_is_zero(f64)) {
4778 float_raise(float_flag_divbyzero, fpst);
4779 return float64_set_sign(float64_infinity, float64_is_neg(f64));
4780 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
4781 /* Abs(value) < 2.0^-1024 */
4782 float_raise(float_flag_overflow | float_flag_inexact, fpst);
4783 if (round_to_inf(fpst, f64_sbit)) {
4784 return float64_set_sign(float64_infinity, float64_is_neg(f64));
4785 } else {
4786 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
4787 }
4788 } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
4789 float_raise(float_flag_underflow, fpst);
4790 return float64_set_sign(float64_zero, float64_is_neg(f64));
4791 }
4792
4793 r64 = call_recip_estimate(f64, 2045, fpst);
4794 r64_val = float64_val(r64);
4795 r64_exp = extract64(r64_val, 52, 11);
4796 r64_frac = extract64(r64_val, 0, 52);
4797
4798 /* result = sign : result_exp<10:0> : fraction<51:0> */
4799 return make_float64(f64_sbit |
4800 ((r64_exp & 0x7ff) << 52) |
4801 r64_frac);
4802 }
4803
4804 /* The algorithm that must be used to calculate the estimate
4805 * is specified by the ARM ARM.
4806 */
4807 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
4808 {
4809 /* These calculations mustn't set any fp exception flags,
4810 * so we use a local copy of the fp_status.
4811 */
4812 float_status dummy_status = *real_fp_status;
4813 float_status *s = &dummy_status;
4814 float64 q;
4815 int64_t q_int;
4816
4817 if (float64_lt(a, float64_half, s)) {
4818 /* range 0.25 <= a < 0.5 */
4819
4820 /* a in units of 1/512 rounded down */
4821 /* q0 = (int)(a * 512.0); */
4822 q = float64_mul(float64_512, a, s);
4823 q_int = float64_to_int64_round_to_zero(q, s);
4824
4825 /* reciprocal root r */
4826 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4827 q = int64_to_float64(q_int, s);
4828 q = float64_add(q, float64_half, s);
4829 q = float64_div(q, float64_512, s);
4830 q = float64_sqrt(q, s);
4831 q = float64_div(float64_one, q, s);
4832 } else {
4833 /* range 0.5 <= a < 1.0 */
4834
4835 /* a in units of 1/256 rounded down */
4836 /* q1 = (int)(a * 256.0); */
4837 q = float64_mul(float64_256, a, s);
4838 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4839
4840 /* reciprocal root r */
4841 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4842 q = int64_to_float64(q_int, s);
4843 q = float64_add(q, float64_half, s);
4844 q = float64_div(q, float64_256, s);
4845 q = float64_sqrt(q, s);
4846 q = float64_div(float64_one, q, s);
4847 }
4848 /* r in units of 1/256 rounded to nearest */
4849 /* s = (int)(256.0 * r + 0.5); */
4850
4851 q = float64_mul(q, float64_256,s );
4852 q = float64_add(q, float64_half, s);
4853 q_int = float64_to_int64_round_to_zero(q, s);
4854
4855 /* return (double)s / 256.0;*/
4856 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4857 }
4858
4859 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
4860 {
4861 float_status *s = fpstp;
4862 float32 f32 = float32_squash_input_denormal(input, s);
4863 uint32_t val = float32_val(f32);
4864 uint32_t f32_sbit = 0x80000000 & val;
4865 int32_t f32_exp = extract32(val, 23, 8);
4866 uint32_t f32_frac = extract32(val, 0, 23);
4867 uint64_t f64_frac;
4868 uint64_t val64;
4869 int result_exp;
4870 float64 f64;
4871
4872 if (float32_is_any_nan(f32)) {
4873 float32 nan = f32;
4874 if (float32_is_signaling_nan(f32)) {
4875 float_raise(float_flag_invalid, s);
4876 nan = float32_maybe_silence_nan(f32);
4877 }
4878 if (s->default_nan_mode) {
4879 nan = float32_default_nan;
4880 }
4881 return nan;
4882 } else if (float32_is_zero(f32)) {
4883 float_raise(float_flag_divbyzero, s);
4884 return float32_set_sign(float32_infinity, float32_is_neg(f32));
4885 } else if (float32_is_neg(f32)) {
4886 float_raise(float_flag_invalid, s);
4887 return float32_default_nan;
4888 } else if (float32_is_infinity(f32)) {
4889 return float32_zero;
4890 }
4891
4892 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
4893 * preserving the parity of the exponent. */
4894
4895 f64_frac = ((uint64_t) f32_frac) << 29;
4896 if (f32_exp == 0) {
4897 while (extract64(f64_frac, 51, 1) == 0) {
4898 f64_frac = f64_frac << 1;
4899 f32_exp = f32_exp-1;
4900 }
4901 f64_frac = extract64(f64_frac, 0, 51) << 1;
4902 }
4903
4904 if (extract64(f32_exp, 0, 1) == 0) {
4905 f64 = make_float64(((uint64_t) f32_sbit) << 32
4906 | (0x3feULL << 52)
4907 | f64_frac);
4908 } else {
4909 f64 = make_float64(((uint64_t) f32_sbit) << 32
4910 | (0x3fdULL << 52)
4911 | f64_frac);
4912 }
4913
4914 result_exp = (380 - f32_exp) / 2;
4915
4916 f64 = recip_sqrt_estimate(f64, s);
4917
4918 val64 = float64_val(f64);
4919
4920 val = ((result_exp & 0xff) << 23)
4921 | ((val64 >> 29) & 0x7fffff);
4922 return make_float32(val);
4923 }
4924
4925 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
4926 {
4927 float_status *s = fpstp;
4928 float64 f64 = float64_squash_input_denormal(input, s);
4929 uint64_t val = float64_val(f64);
4930 uint64_t f64_sbit = 0x8000000000000000ULL & val;
4931 int64_t f64_exp = extract64(val, 52, 11);
4932 uint64_t f64_frac = extract64(val, 0, 52);
4933 int64_t result_exp;
4934 uint64_t result_frac;
4935
4936 if (float64_is_any_nan(f64)) {
4937 float64 nan = f64;
4938 if (float64_is_signaling_nan(f64)) {
4939 float_raise(float_flag_invalid, s);
4940 nan = float64_maybe_silence_nan(f64);
4941 }
4942 if (s->default_nan_mode) {
4943 nan = float64_default_nan;
4944 }
4945 return nan;
4946 } else if (float64_is_zero(f64)) {
4947 float_raise(float_flag_divbyzero, s);
4948 return float64_set_sign(float64_infinity, float64_is_neg(f64));
4949 } else if (float64_is_neg(f64)) {
4950 float_raise(float_flag_invalid, s);
4951 return float64_default_nan;
4952 } else if (float64_is_infinity(f64)) {
4953 return float64_zero;
4954 }
4955
4956 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
4957 * preserving the parity of the exponent. */
4958
4959 if (f64_exp == 0) {
4960 while (extract64(f64_frac, 51, 1) == 0) {
4961 f64_frac = f64_frac << 1;
4962 f64_exp = f64_exp - 1;
4963 }
4964 f64_frac = extract64(f64_frac, 0, 51) << 1;
4965 }
4966
4967 if (extract64(f64_exp, 0, 1) == 0) {
4968 f64 = make_float64(f64_sbit
4969 | (0x3feULL << 52)
4970 | f64_frac);
4971 } else {
4972 f64 = make_float64(f64_sbit
4973 | (0x3fdULL << 52)
4974 | f64_frac);
4975 }
4976
4977 result_exp = (3068 - f64_exp) / 2;
4978
4979 f64 = recip_sqrt_estimate(f64, s);
4980
4981 result_frac = extract64(float64_val(f64), 0, 52);
4982
4983 return make_float64(f64_sbit |
4984 ((result_exp & 0x7ff) << 52) |
4985 result_frac);
4986 }
4987
4988 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
4989 {
4990 float_status *s = fpstp;
4991 float64 f64;
4992
4993 if ((a & 0x80000000) == 0) {
4994 return 0xffffffff;
4995 }
4996
4997 f64 = make_float64((0x3feULL << 52)
4998 | ((int64_t)(a & 0x7fffffff) << 21));
4999
5000 f64 = recip_estimate(f64, s);
5001
5002 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5003 }
5004
5005 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5006 {
5007 float_status *fpst = fpstp;
5008 float64 f64;
5009
5010 if ((a & 0xc0000000) == 0) {
5011 return 0xffffffff;
5012 }
5013
5014 if (a & 0x80000000) {
5015 f64 = make_float64((0x3feULL << 52)
5016 | ((uint64_t)(a & 0x7fffffff) << 21));
5017 } else { /* bits 31-30 == '01' */
5018 f64 = make_float64((0x3fdULL << 52)
5019 | ((uint64_t)(a & 0x3fffffff) << 22));
5020 }
5021
5022 f64 = recip_sqrt_estimate(f64, fpst);
5023
5024 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5025 }
5026
5027 /* VFPv4 fused multiply-accumulate */
5028 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5029 {
5030 float_status *fpst = fpstp;
5031 return float32_muladd(a, b, c, 0, fpst);
5032 }
5033
5034 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5035 {
5036 float_status *fpst = fpstp;
5037 return float64_muladd(a, b, c, 0, fpst);
5038 }
5039
5040 /* ARMv8 round to integral */
5041 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5042 {
5043 return float32_round_to_int(x, fp_status);
5044 }
5045
5046 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5047 {
5048 return float64_round_to_int(x, fp_status);
5049 }
5050
5051 float32 HELPER(rints)(float32 x, void *fp_status)
5052 {
5053 int old_flags = get_float_exception_flags(fp_status), new_flags;
5054 float32 ret;
5055
5056 ret = float32_round_to_int(x, fp_status);
5057
5058 /* Suppress any inexact exceptions the conversion produced */
5059 if (!(old_flags & float_flag_inexact)) {
5060 new_flags = get_float_exception_flags(fp_status);
5061 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5062 }
5063
5064 return ret;
5065 }
5066
5067 float64 HELPER(rintd)(float64 x, void *fp_status)
5068 {
5069 int old_flags = get_float_exception_flags(fp_status), new_flags;
5070 float64 ret;
5071
5072 ret = float64_round_to_int(x, fp_status);
5073
5074 new_flags = get_float_exception_flags(fp_status);
5075
5076 /* Suppress any inexact exceptions the conversion produced */
5077 if (!(old_flags & float_flag_inexact)) {
5078 new_flags = get_float_exception_flags(fp_status);
5079 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5080 }
5081
5082 return ret;
5083 }
5084
5085 /* Convert ARM rounding mode to softfloat */
5086 int arm_rmode_to_sf(int rmode)
5087 {
5088 switch (rmode) {
5089 case FPROUNDING_TIEAWAY:
5090 rmode = float_round_ties_away;
5091 break;
5092 case FPROUNDING_ODD:
5093 /* FIXME: add support for TIEAWAY and ODD */
5094 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5095 rmode);
5096 case FPROUNDING_TIEEVEN:
5097 default:
5098 rmode = float_round_nearest_even;
5099 break;
5100 case FPROUNDING_POSINF:
5101 rmode = float_round_up;
5102 break;
5103 case FPROUNDING_NEGINF:
5104 rmode = float_round_down;
5105 break;
5106 case FPROUNDING_ZERO:
5107 rmode = float_round_to_zero;
5108 break;
5109 }
5110 return rmode;
5111 }
5112
5113 static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
5114 {
5115 memset(buf, 0, 4);
5116
5117 if (bytes == 1) {
5118 buf[0] = val & 0xff;
5119 } else if (bytes == 2) {
5120 buf[0] = val & 0xff;
5121 buf[1] = (val >> 8) & 0xff;
5122 } else {
5123 buf[0] = val & 0xff;
5124 buf[1] = (val >> 8) & 0xff;
5125 buf[2] = (val >> 16) & 0xff;
5126 buf[3] = (val >> 24) & 0xff;
5127 }
5128 }
5129
5130 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5131 {
5132 uint8_t buf[4];
5133
5134 crc_init_buffer(buf, val, bytes);
5135
5136 /* zlib crc32 converts the accumulator and output to one's complement. */
5137 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5138 }
5139
5140 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5141 {
5142 uint8_t buf[4];
5143
5144 crc_init_buffer(buf, val, bytes);
5145
5146 /* Linux crc32c converts the output to one's complement. */
5147 return crc32c(acc, buf, bytes) ^ 0xffffffff;
5148 }
AR7 emulation for QEMU