2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "disas/disas.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31 #include "sysemu/kvm.h"
33 #include "trace-tcg.h"
36 #define MIPS_DEBUG_DISAS 0
37 //#define MIPS_DEBUG_SIGN_EXTENSIONS
39 /* MIPS major opcodes */
40 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
43 /* indirect opcode tables */
44 OPC_SPECIAL
= (0x00 << 26),
45 OPC_REGIMM
= (0x01 << 26),
46 OPC_CP0
= (0x10 << 26),
47 OPC_CP1
= (0x11 << 26),
48 OPC_CP2
= (0x12 << 26),
49 OPC_CP3
= (0x13 << 26),
50 OPC_SPECIAL2
= (0x1C << 26),
51 OPC_SPECIAL3
= (0x1F << 26),
52 /* arithmetic with immediate */
53 OPC_ADDI
= (0x08 << 26),
54 OPC_ADDIU
= (0x09 << 26),
55 OPC_SLTI
= (0x0A << 26),
56 OPC_SLTIU
= (0x0B << 26),
57 /* logic with immediate */
58 OPC_ANDI
= (0x0C << 26),
59 OPC_ORI
= (0x0D << 26),
60 OPC_XORI
= (0x0E << 26),
61 OPC_LUI
= (0x0F << 26),
62 /* arithmetic with immediate */
63 OPC_DADDI
= (0x18 << 26),
64 OPC_DADDIU
= (0x19 << 26),
65 /* Jump and branches */
67 OPC_JAL
= (0x03 << 26),
68 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
69 OPC_BEQL
= (0x14 << 26),
70 OPC_BNE
= (0x05 << 26),
71 OPC_BNEL
= (0x15 << 26),
72 OPC_BLEZ
= (0x06 << 26),
73 OPC_BLEZL
= (0x16 << 26),
74 OPC_BGTZ
= (0x07 << 26),
75 OPC_BGTZL
= (0x17 << 26),
76 OPC_JALX
= (0x1D << 26),
77 OPC_DAUI
= (0x1D << 26),
79 OPC_LDL
= (0x1A << 26),
80 OPC_LDR
= (0x1B << 26),
81 OPC_LB
= (0x20 << 26),
82 OPC_LH
= (0x21 << 26),
83 OPC_LWL
= (0x22 << 26),
84 OPC_LW
= (0x23 << 26),
85 OPC_LWPC
= OPC_LW
| 0x5,
86 OPC_LBU
= (0x24 << 26),
87 OPC_LHU
= (0x25 << 26),
88 OPC_LWR
= (0x26 << 26),
89 OPC_LWU
= (0x27 << 26),
90 OPC_SB
= (0x28 << 26),
91 OPC_SH
= (0x29 << 26),
92 OPC_SWL
= (0x2A << 26),
93 OPC_SW
= (0x2B << 26),
94 OPC_SDL
= (0x2C << 26),
95 OPC_SDR
= (0x2D << 26),
96 OPC_SWR
= (0x2E << 26),
97 OPC_LL
= (0x30 << 26),
98 OPC_LLD
= (0x34 << 26),
99 OPC_LD
= (0x37 << 26),
100 OPC_LDPC
= OPC_LD
| 0x5,
101 OPC_SC
= (0x38 << 26),
102 OPC_SCD
= (0x3C << 26),
103 OPC_SD
= (0x3F << 26),
104 /* Floating point load/store */
105 OPC_LWC1
= (0x31 << 26),
106 OPC_LWC2
= (0x32 << 26),
107 OPC_LDC1
= (0x35 << 26),
108 OPC_LDC2
= (0x36 << 26),
109 OPC_SWC1
= (0x39 << 26),
110 OPC_SWC2
= (0x3A << 26),
111 OPC_SDC1
= (0x3D << 26),
112 OPC_SDC2
= (0x3E << 26),
113 /* Compact Branches */
114 OPC_BLEZALC
= (0x06 << 26),
115 OPC_BGEZALC
= (0x06 << 26),
116 OPC_BGEUC
= (0x06 << 26),
117 OPC_BGTZALC
= (0x07 << 26),
118 OPC_BLTZALC
= (0x07 << 26),
119 OPC_BLTUC
= (0x07 << 26),
120 OPC_BOVC
= (0x08 << 26),
121 OPC_BEQZALC
= (0x08 << 26),
122 OPC_BEQC
= (0x08 << 26),
123 OPC_BLEZC
= (0x16 << 26),
124 OPC_BGEZC
= (0x16 << 26),
125 OPC_BGEC
= (0x16 << 26),
126 OPC_BGTZC
= (0x17 << 26),
127 OPC_BLTZC
= (0x17 << 26),
128 OPC_BLTC
= (0x17 << 26),
129 OPC_BNVC
= (0x18 << 26),
130 OPC_BNEZALC
= (0x18 << 26),
131 OPC_BNEC
= (0x18 << 26),
132 OPC_BC
= (0x32 << 26),
133 OPC_BEQZC
= (0x36 << 26),
134 OPC_JIC
= (0x36 << 26),
135 OPC_BALC
= (0x3A << 26),
136 OPC_BNEZC
= (0x3E << 26),
137 OPC_JIALC
= (0x3E << 26),
138 /* MDMX ASE specific */
139 OPC_MDMX
= (0x1E << 26),
140 /* MSA ASE, same as MDMX */
142 /* Cache and prefetch */
143 OPC_CACHE
= (0x2F << 26),
144 OPC_PREF
= (0x33 << 26),
145 /* PC-relative address computation / loads */
146 OPC_PCREL
= (0x3B << 26),
149 /* PC-relative address computation / loads */
150 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
151 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
153 /* Instructions determined by bits 19 and 20 */
154 OPC_ADDIUPC
= OPC_PCREL
| (0 << 19),
155 R6_OPC_LWPC
= OPC_PCREL
| (1 << 19),
156 OPC_LWUPC
= OPC_PCREL
| (2 << 19),
158 /* Instructions determined by bits 16 ... 20 */
159 OPC_AUIPC
= OPC_PCREL
| (0x1e << 16),
160 OPC_ALUIPC
= OPC_PCREL
| (0x1f << 16),
163 R6_OPC_LDPC
= OPC_PCREL
| (6 << 18),
166 /* MIPS special opcodes */
167 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
171 OPC_SLL
= 0x00 | OPC_SPECIAL
,
172 /* NOP is SLL r0, r0, 0 */
173 /* SSNOP is SLL r0, r0, 1 */
174 /* EHB is SLL r0, r0, 3 */
175 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
176 OPC_ROTR
= OPC_SRL
| (1 << 21),
177 OPC_SRA
= 0x03 | OPC_SPECIAL
,
178 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
179 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
180 OPC_ROTRV
= OPC_SRLV
| (1 << 6),
181 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
182 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
183 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
184 OPC_DROTRV
= OPC_DSRLV
| (1 << 6),
185 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
186 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
187 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
188 OPC_DROTR
= OPC_DSRL
| (1 << 21),
189 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
190 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
191 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
192 OPC_DROTR32
= OPC_DSRL32
| (1 << 21),
193 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
194 /* Multiplication / division */
195 OPC_MULT
= 0x18 | OPC_SPECIAL
,
196 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
197 OPC_DIV
= 0x1A | OPC_SPECIAL
,
198 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
199 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
200 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
201 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
202 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
204 /* 2 registers arithmetic / logic */
205 OPC_ADD
= 0x20 | OPC_SPECIAL
,
206 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
207 OPC_SUB
= 0x22 | OPC_SPECIAL
,
208 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
209 OPC_AND
= 0x24 | OPC_SPECIAL
,
210 OPC_OR
= 0x25 | OPC_SPECIAL
,
211 OPC_XOR
= 0x26 | OPC_SPECIAL
,
212 OPC_NOR
= 0x27 | OPC_SPECIAL
,
213 OPC_SLT
= 0x2A | OPC_SPECIAL
,
214 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
215 OPC_DADD
= 0x2C | OPC_SPECIAL
,
216 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
217 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
218 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
220 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
221 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
223 OPC_TGE
= 0x30 | OPC_SPECIAL
,
224 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
225 OPC_TLT
= 0x32 | OPC_SPECIAL
,
226 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
227 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
228 OPC_TNE
= 0x36 | OPC_SPECIAL
,
229 /* HI / LO registers load & stores */
230 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
231 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
232 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
233 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
234 /* Conditional moves */
235 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
236 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
238 OPC_SELEQZ
= 0x35 | OPC_SPECIAL
,
239 OPC_SELNEZ
= 0x37 | OPC_SPECIAL
,
241 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
244 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
245 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
246 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
247 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
248 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
250 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
251 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
252 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
253 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
256 /* R6 Multiply and Divide instructions have the same Opcode
257 and function field as legacy OPC_MULT[U]/OPC_DIV[U] */
258 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
261 R6_OPC_MUL
= OPC_MULT
| (2 << 6),
262 R6_OPC_MUH
= OPC_MULT
| (3 << 6),
263 R6_OPC_MULU
= OPC_MULTU
| (2 << 6),
264 R6_OPC_MUHU
= OPC_MULTU
| (3 << 6),
265 R6_OPC_DIV
= OPC_DIV
| (2 << 6),
266 R6_OPC_MOD
= OPC_DIV
| (3 << 6),
267 R6_OPC_DIVU
= OPC_DIVU
| (2 << 6),
268 R6_OPC_MODU
= OPC_DIVU
| (3 << 6),
270 R6_OPC_DMUL
= OPC_DMULT
| (2 << 6),
271 R6_OPC_DMUH
= OPC_DMULT
| (3 << 6),
272 R6_OPC_DMULU
= OPC_DMULTU
| (2 << 6),
273 R6_OPC_DMUHU
= OPC_DMULTU
| (3 << 6),
274 R6_OPC_DDIV
= OPC_DDIV
| (2 << 6),
275 R6_OPC_DMOD
= OPC_DDIV
| (3 << 6),
276 R6_OPC_DDIVU
= OPC_DDIVU
| (2 << 6),
277 R6_OPC_DMODU
= OPC_DDIVU
| (3 << 6),
279 R6_OPC_CLZ
= 0x10 | OPC_SPECIAL
,
280 R6_OPC_CLO
= 0x11 | OPC_SPECIAL
,
281 R6_OPC_DCLZ
= 0x12 | OPC_SPECIAL
,
282 R6_OPC_DCLO
= 0x13 | OPC_SPECIAL
,
283 R6_OPC_SDBBP
= 0x0e | OPC_SPECIAL
,
285 OPC_LSA
= 0x05 | OPC_SPECIAL
,
286 OPC_DLSA
= 0x15 | OPC_SPECIAL
,
289 /* Multiplication variants of the vr54xx. */
290 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
293 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
294 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
295 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
296 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
297 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
298 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
299 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
300 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
301 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
302 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
303 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
304 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
305 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
306 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
309 /* REGIMM (rt field) opcodes */
310 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
313 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
314 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
315 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
316 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
317 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
318 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
319 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
320 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
321 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
322 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
323 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
324 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
325 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
326 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
327 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
329 OPC_DAHI
= (0x06 << 16) | OPC_REGIMM
,
330 OPC_DATI
= (0x1e << 16) | OPC_REGIMM
,
333 /* Special2 opcodes */
334 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
337 /* Multiply & xxx operations */
338 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
339 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
340 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
341 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
342 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
344 OPC_MULT_G_2F
= 0x10 | OPC_SPECIAL2
,
345 OPC_DMULT_G_2F
= 0x11 | OPC_SPECIAL2
,
346 OPC_MULTU_G_2F
= 0x12 | OPC_SPECIAL2
,
347 OPC_DMULTU_G_2F
= 0x13 | OPC_SPECIAL2
,
348 OPC_DIV_G_2F
= 0x14 | OPC_SPECIAL2
,
349 OPC_DDIV_G_2F
= 0x15 | OPC_SPECIAL2
,
350 OPC_DIVU_G_2F
= 0x16 | OPC_SPECIAL2
,
351 OPC_DDIVU_G_2F
= 0x17 | OPC_SPECIAL2
,
352 OPC_MOD_G_2F
= 0x1c | OPC_SPECIAL2
,
353 OPC_DMOD_G_2F
= 0x1d | OPC_SPECIAL2
,
354 OPC_MODU_G_2F
= 0x1e | OPC_SPECIAL2
,
355 OPC_DMODU_G_2F
= 0x1f | OPC_SPECIAL2
,
357 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
358 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
359 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
360 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
362 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
365 /* Special3 opcodes */
366 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
369 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
370 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
371 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
372 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
373 OPC_INS
= 0x04 | OPC_SPECIAL3
,
374 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
375 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
376 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
377 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
378 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
379 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
380 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
381 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
384 OPC_MULT_G_2E
= 0x18 | OPC_SPECIAL3
,
385 OPC_MULTU_G_2E
= 0x19 | OPC_SPECIAL3
,
386 OPC_DIV_G_2E
= 0x1A | OPC_SPECIAL3
,
387 OPC_DIVU_G_2E
= 0x1B | OPC_SPECIAL3
,
388 OPC_DMULT_G_2E
= 0x1C | OPC_SPECIAL3
,
389 OPC_DMULTU_G_2E
= 0x1D | OPC_SPECIAL3
,
390 OPC_DDIV_G_2E
= 0x1E | OPC_SPECIAL3
,
391 OPC_DDIVU_G_2E
= 0x1F | OPC_SPECIAL3
,
392 OPC_MOD_G_2E
= 0x22 | OPC_SPECIAL3
,
393 OPC_MODU_G_2E
= 0x23 | OPC_SPECIAL3
,
394 OPC_DMOD_G_2E
= 0x26 | OPC_SPECIAL3
,
395 OPC_DMODU_G_2E
= 0x27 | OPC_SPECIAL3
,
398 OPC_LX_DSP
= 0x0A | OPC_SPECIAL3
,
399 /* MIPS DSP Arithmetic */
400 OPC_ADDU_QB_DSP
= 0x10 | OPC_SPECIAL3
,
401 OPC_ADDU_OB_DSP
= 0x14 | OPC_SPECIAL3
,
402 OPC_ABSQ_S_PH_DSP
= 0x12 | OPC_SPECIAL3
,
403 OPC_ABSQ_S_QH_DSP
= 0x16 | OPC_SPECIAL3
,
404 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
405 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
406 OPC_CMPU_EQ_QB_DSP
= 0x11 | OPC_SPECIAL3
,
407 OPC_CMPU_EQ_OB_DSP
= 0x15 | OPC_SPECIAL3
,
408 /* MIPS DSP GPR-Based Shift Sub-class */
409 OPC_SHLL_QB_DSP
= 0x13 | OPC_SPECIAL3
,
410 OPC_SHLL_OB_DSP
= 0x17 | OPC_SPECIAL3
,
411 /* MIPS DSP Multiply Sub-class insns */
412 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
413 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
414 OPC_DPA_W_PH_DSP
= 0x30 | OPC_SPECIAL3
,
415 OPC_DPAQ_W_QH_DSP
= 0x34 | OPC_SPECIAL3
,
416 /* DSP Bit/Manipulation Sub-class */
417 OPC_INSV_DSP
= 0x0C | OPC_SPECIAL3
,
418 OPC_DINSV_DSP
= 0x0D | OPC_SPECIAL3
,
419 /* MIPS DSP Append Sub-class */
420 OPC_APPEND_DSP
= 0x31 | OPC_SPECIAL3
,
421 OPC_DAPPEND_DSP
= 0x35 | OPC_SPECIAL3
,
422 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
423 OPC_EXTR_W_DSP
= 0x38 | OPC_SPECIAL3
,
424 OPC_DEXTR_W_DSP
= 0x3C | OPC_SPECIAL3
,
427 R6_OPC_PREF
= 0x35 | OPC_SPECIAL3
,
428 R6_OPC_CACHE
= 0x25 | OPC_SPECIAL3
,
429 R6_OPC_LL
= 0x36 | OPC_SPECIAL3
,
430 R6_OPC_SC
= 0x26 | OPC_SPECIAL3
,
431 R6_OPC_LLD
= 0x37 | OPC_SPECIAL3
,
432 R6_OPC_SCD
= 0x27 | OPC_SPECIAL3
,
436 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
439 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
440 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
441 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
442 OPC_ALIGN
= (0x08 << 6) | OPC_BSHFL
, /* 010.bp */
443 OPC_ALIGN_END
= (0x0B << 6) | OPC_BSHFL
, /* 010.00 to 010.11 */
444 OPC_BITSWAP
= (0x00 << 6) | OPC_BSHFL
/* 00000 */
448 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
451 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
452 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
453 OPC_DALIGN
= (0x08 << 6) | OPC_DBSHFL
, /* 01.bp */
454 OPC_DALIGN_END
= (0x0F << 6) | OPC_DBSHFL
, /* 01.000 to 01.111 */
455 OPC_DBITSWAP
= (0x00 << 6) | OPC_DBSHFL
, /* 00000 */
458 /* MIPS DSP REGIMM opcodes */
460 OPC_BPOSGE32
= (0x1C << 16) | OPC_REGIMM
,
461 OPC_BPOSGE64
= (0x1D << 16) | OPC_REGIMM
,
464 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
467 OPC_LBUX
= (0x06 << 6) | OPC_LX_DSP
,
468 OPC_LHX
= (0x04 << 6) | OPC_LX_DSP
,
469 OPC_LWX
= (0x00 << 6) | OPC_LX_DSP
,
470 OPC_LDX
= (0x08 << 6) | OPC_LX_DSP
,
473 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
475 /* MIPS DSP Arithmetic Sub-class */
476 OPC_ADDQ_PH
= (0x0A << 6) | OPC_ADDU_QB_DSP
,
477 OPC_ADDQ_S_PH
= (0x0E << 6) | OPC_ADDU_QB_DSP
,
478 OPC_ADDQ_S_W
= (0x16 << 6) | OPC_ADDU_QB_DSP
,
479 OPC_ADDU_QB
= (0x00 << 6) | OPC_ADDU_QB_DSP
,
480 OPC_ADDU_S_QB
= (0x04 << 6) | OPC_ADDU_QB_DSP
,
481 OPC_ADDU_PH
= (0x08 << 6) | OPC_ADDU_QB_DSP
,
482 OPC_ADDU_S_PH
= (0x0C << 6) | OPC_ADDU_QB_DSP
,
483 OPC_SUBQ_PH
= (0x0B << 6) | OPC_ADDU_QB_DSP
,
484 OPC_SUBQ_S_PH
= (0x0F << 6) | OPC_ADDU_QB_DSP
,
485 OPC_SUBQ_S_W
= (0x17 << 6) | OPC_ADDU_QB_DSP
,
486 OPC_SUBU_QB
= (0x01 << 6) | OPC_ADDU_QB_DSP
,
487 OPC_SUBU_S_QB
= (0x05 << 6) | OPC_ADDU_QB_DSP
,
488 OPC_SUBU_PH
= (0x09 << 6) | OPC_ADDU_QB_DSP
,
489 OPC_SUBU_S_PH
= (0x0D << 6) | OPC_ADDU_QB_DSP
,
490 OPC_ADDSC
= (0x10 << 6) | OPC_ADDU_QB_DSP
,
491 OPC_ADDWC
= (0x11 << 6) | OPC_ADDU_QB_DSP
,
492 OPC_MODSUB
= (0x12 << 6) | OPC_ADDU_QB_DSP
,
493 OPC_RADDU_W_QB
= (0x14 << 6) | OPC_ADDU_QB_DSP
,
494 /* MIPS DSP Multiply Sub-class insns */
495 OPC_MULEU_S_PH_QBL
= (0x06 << 6) | OPC_ADDU_QB_DSP
,
496 OPC_MULEU_S_PH_QBR
= (0x07 << 6) | OPC_ADDU_QB_DSP
,
497 OPC_MULQ_RS_PH
= (0x1F << 6) | OPC_ADDU_QB_DSP
,
498 OPC_MULEQ_S_W_PHL
= (0x1C << 6) | OPC_ADDU_QB_DSP
,
499 OPC_MULEQ_S_W_PHR
= (0x1D << 6) | OPC_ADDU_QB_DSP
,
500 OPC_MULQ_S_PH
= (0x1E << 6) | OPC_ADDU_QB_DSP
,
503 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
504 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
506 /* MIPS DSP Arithmetic Sub-class */
507 OPC_ADDUH_QB
= (0x00 << 6) | OPC_ADDUH_QB_DSP
,
508 OPC_ADDUH_R_QB
= (0x02 << 6) | OPC_ADDUH_QB_DSP
,
509 OPC_ADDQH_PH
= (0x08 << 6) | OPC_ADDUH_QB_DSP
,
510 OPC_ADDQH_R_PH
= (0x0A << 6) | OPC_ADDUH_QB_DSP
,
511 OPC_ADDQH_W
= (0x10 << 6) | OPC_ADDUH_QB_DSP
,
512 OPC_ADDQH_R_W
= (0x12 << 6) | OPC_ADDUH_QB_DSP
,
513 OPC_SUBUH_QB
= (0x01 << 6) | OPC_ADDUH_QB_DSP
,
514 OPC_SUBUH_R_QB
= (0x03 << 6) | OPC_ADDUH_QB_DSP
,
515 OPC_SUBQH_PH
= (0x09 << 6) | OPC_ADDUH_QB_DSP
,
516 OPC_SUBQH_R_PH
= (0x0B << 6) | OPC_ADDUH_QB_DSP
,
517 OPC_SUBQH_W
= (0x11 << 6) | OPC_ADDUH_QB_DSP
,
518 OPC_SUBQH_R_W
= (0x13 << 6) | OPC_ADDUH_QB_DSP
,
519 /* MIPS DSP Multiply Sub-class insns */
520 OPC_MUL_PH
= (0x0C << 6) | OPC_ADDUH_QB_DSP
,
521 OPC_MUL_S_PH
= (0x0E << 6) | OPC_ADDUH_QB_DSP
,
522 OPC_MULQ_S_W
= (0x16 << 6) | OPC_ADDUH_QB_DSP
,
523 OPC_MULQ_RS_W
= (0x17 << 6) | OPC_ADDUH_QB_DSP
,
526 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
528 /* MIPS DSP Arithmetic Sub-class */
529 OPC_ABSQ_S_QB
= (0x01 << 6) | OPC_ABSQ_S_PH_DSP
,
530 OPC_ABSQ_S_PH
= (0x09 << 6) | OPC_ABSQ_S_PH_DSP
,
531 OPC_ABSQ_S_W
= (0x11 << 6) | OPC_ABSQ_S_PH_DSP
,
532 OPC_PRECEQ_W_PHL
= (0x0C << 6) | OPC_ABSQ_S_PH_DSP
,
533 OPC_PRECEQ_W_PHR
= (0x0D << 6) | OPC_ABSQ_S_PH_DSP
,
534 OPC_PRECEQU_PH_QBL
= (0x04 << 6) | OPC_ABSQ_S_PH_DSP
,
535 OPC_PRECEQU_PH_QBR
= (0x05 << 6) | OPC_ABSQ_S_PH_DSP
,
536 OPC_PRECEQU_PH_QBLA
= (0x06 << 6) | OPC_ABSQ_S_PH_DSP
,
537 OPC_PRECEQU_PH_QBRA
= (0x07 << 6) | OPC_ABSQ_S_PH_DSP
,
538 OPC_PRECEU_PH_QBL
= (0x1C << 6) | OPC_ABSQ_S_PH_DSP
,
539 OPC_PRECEU_PH_QBR
= (0x1D << 6) | OPC_ABSQ_S_PH_DSP
,
540 OPC_PRECEU_PH_QBLA
= (0x1E << 6) | OPC_ABSQ_S_PH_DSP
,
541 OPC_PRECEU_PH_QBRA
= (0x1F << 6) | OPC_ABSQ_S_PH_DSP
,
542 /* DSP Bit/Manipulation Sub-class */
543 OPC_BITREV
= (0x1B << 6) | OPC_ABSQ_S_PH_DSP
,
544 OPC_REPL_QB
= (0x02 << 6) | OPC_ABSQ_S_PH_DSP
,
545 OPC_REPLV_QB
= (0x03 << 6) | OPC_ABSQ_S_PH_DSP
,
546 OPC_REPL_PH
= (0x0A << 6) | OPC_ABSQ_S_PH_DSP
,
547 OPC_REPLV_PH
= (0x0B << 6) | OPC_ABSQ_S_PH_DSP
,
550 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
552 /* MIPS DSP Arithmetic Sub-class */
553 OPC_PRECR_QB_PH
= (0x0D << 6) | OPC_CMPU_EQ_QB_DSP
,
554 OPC_PRECRQ_QB_PH
= (0x0C << 6) | OPC_CMPU_EQ_QB_DSP
,
555 OPC_PRECR_SRA_PH_W
= (0x1E << 6) | OPC_CMPU_EQ_QB_DSP
,
556 OPC_PRECR_SRA_R_PH_W
= (0x1F << 6) | OPC_CMPU_EQ_QB_DSP
,
557 OPC_PRECRQ_PH_W
= (0x14 << 6) | OPC_CMPU_EQ_QB_DSP
,
558 OPC_PRECRQ_RS_PH_W
= (0x15 << 6) | OPC_CMPU_EQ_QB_DSP
,
559 OPC_PRECRQU_S_QB_PH
= (0x0F << 6) | OPC_CMPU_EQ_QB_DSP
,
560 /* DSP Compare-Pick Sub-class */
561 OPC_CMPU_EQ_QB
= (0x00 << 6) | OPC_CMPU_EQ_QB_DSP
,
562 OPC_CMPU_LT_QB
= (0x01 << 6) | OPC_CMPU_EQ_QB_DSP
,
563 OPC_CMPU_LE_QB
= (0x02 << 6) | OPC_CMPU_EQ_QB_DSP
,
564 OPC_CMPGU_EQ_QB
= (0x04 << 6) | OPC_CMPU_EQ_QB_DSP
,
565 OPC_CMPGU_LT_QB
= (0x05 << 6) | OPC_CMPU_EQ_QB_DSP
,
566 OPC_CMPGU_LE_QB
= (0x06 << 6) | OPC_CMPU_EQ_QB_DSP
,
567 OPC_CMPGDU_EQ_QB
= (0x18 << 6) | OPC_CMPU_EQ_QB_DSP
,
568 OPC_CMPGDU_LT_QB
= (0x19 << 6) | OPC_CMPU_EQ_QB_DSP
,
569 OPC_CMPGDU_LE_QB
= (0x1A << 6) | OPC_CMPU_EQ_QB_DSP
,
570 OPC_CMP_EQ_PH
= (0x08 << 6) | OPC_CMPU_EQ_QB_DSP
,
571 OPC_CMP_LT_PH
= (0x09 << 6) | OPC_CMPU_EQ_QB_DSP
,
572 OPC_CMP_LE_PH
= (0x0A << 6) | OPC_CMPU_EQ_QB_DSP
,
573 OPC_PICK_QB
= (0x03 << 6) | OPC_CMPU_EQ_QB_DSP
,
574 OPC_PICK_PH
= (0x0B << 6) | OPC_CMPU_EQ_QB_DSP
,
575 OPC_PACKRL_PH
= (0x0E << 6) | OPC_CMPU_EQ_QB_DSP
,
578 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
580 /* MIPS DSP GPR-Based Shift Sub-class */
581 OPC_SHLL_QB
= (0x00 << 6) | OPC_SHLL_QB_DSP
,
582 OPC_SHLLV_QB
= (0x02 << 6) | OPC_SHLL_QB_DSP
,
583 OPC_SHLL_PH
= (0x08 << 6) | OPC_SHLL_QB_DSP
,
584 OPC_SHLLV_PH
= (0x0A << 6) | OPC_SHLL_QB_DSP
,
585 OPC_SHLL_S_PH
= (0x0C << 6) | OPC_SHLL_QB_DSP
,
586 OPC_SHLLV_S_PH
= (0x0E << 6) | OPC_SHLL_QB_DSP
,
587 OPC_SHLL_S_W
= (0x14 << 6) | OPC_SHLL_QB_DSP
,
588 OPC_SHLLV_S_W
= (0x16 << 6) | OPC_SHLL_QB_DSP
,
589 OPC_SHRL_QB
= (0x01 << 6) | OPC_SHLL_QB_DSP
,
590 OPC_SHRLV_QB
= (0x03 << 6) | OPC_SHLL_QB_DSP
,
591 OPC_SHRL_PH
= (0x19 << 6) | OPC_SHLL_QB_DSP
,
592 OPC_SHRLV_PH
= (0x1B << 6) | OPC_SHLL_QB_DSP
,
593 OPC_SHRA_QB
= (0x04 << 6) | OPC_SHLL_QB_DSP
,
594 OPC_SHRA_R_QB
= (0x05 << 6) | OPC_SHLL_QB_DSP
,
595 OPC_SHRAV_QB
= (0x06 << 6) | OPC_SHLL_QB_DSP
,
596 OPC_SHRAV_R_QB
= (0x07 << 6) | OPC_SHLL_QB_DSP
,
597 OPC_SHRA_PH
= (0x09 << 6) | OPC_SHLL_QB_DSP
,
598 OPC_SHRAV_PH
= (0x0B << 6) | OPC_SHLL_QB_DSP
,
599 OPC_SHRA_R_PH
= (0x0D << 6) | OPC_SHLL_QB_DSP
,
600 OPC_SHRAV_R_PH
= (0x0F << 6) | OPC_SHLL_QB_DSP
,
601 OPC_SHRA_R_W
= (0x15 << 6) | OPC_SHLL_QB_DSP
,
602 OPC_SHRAV_R_W
= (0x17 << 6) | OPC_SHLL_QB_DSP
,
605 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
607 /* MIPS DSP Multiply Sub-class insns */
608 OPC_DPAU_H_QBL
= (0x03 << 6) | OPC_DPA_W_PH_DSP
,
609 OPC_DPAU_H_QBR
= (0x07 << 6) | OPC_DPA_W_PH_DSP
,
610 OPC_DPSU_H_QBL
= (0x0B << 6) | OPC_DPA_W_PH_DSP
,
611 OPC_DPSU_H_QBR
= (0x0F << 6) | OPC_DPA_W_PH_DSP
,
612 OPC_DPA_W_PH
= (0x00 << 6) | OPC_DPA_W_PH_DSP
,
613 OPC_DPAX_W_PH
= (0x08 << 6) | OPC_DPA_W_PH_DSP
,
614 OPC_DPAQ_S_W_PH
= (0x04 << 6) | OPC_DPA_W_PH_DSP
,
615 OPC_DPAQX_S_W_PH
= (0x18 << 6) | OPC_DPA_W_PH_DSP
,
616 OPC_DPAQX_SA_W_PH
= (0x1A << 6) | OPC_DPA_W_PH_DSP
,
617 OPC_DPS_W_PH
= (0x01 << 6) | OPC_DPA_W_PH_DSP
,
618 OPC_DPSX_W_PH
= (0x09 << 6) | OPC_DPA_W_PH_DSP
,
619 OPC_DPSQ_S_W_PH
= (0x05 << 6) | OPC_DPA_W_PH_DSP
,
620 OPC_DPSQX_S_W_PH
= (0x19 << 6) | OPC_DPA_W_PH_DSP
,
621 OPC_DPSQX_SA_W_PH
= (0x1B << 6) | OPC_DPA_W_PH_DSP
,
622 OPC_MULSAQ_S_W_PH
= (0x06 << 6) | OPC_DPA_W_PH_DSP
,
623 OPC_DPAQ_SA_L_W
= (0x0C << 6) | OPC_DPA_W_PH_DSP
,
624 OPC_DPSQ_SA_L_W
= (0x0D << 6) | OPC_DPA_W_PH_DSP
,
625 OPC_MAQ_S_W_PHL
= (0x14 << 6) | OPC_DPA_W_PH_DSP
,
626 OPC_MAQ_S_W_PHR
= (0x16 << 6) | OPC_DPA_W_PH_DSP
,
627 OPC_MAQ_SA_W_PHL
= (0x10 << 6) | OPC_DPA_W_PH_DSP
,
628 OPC_MAQ_SA_W_PHR
= (0x12 << 6) | OPC_DPA_W_PH_DSP
,
629 OPC_MULSA_W_PH
= (0x02 << 6) | OPC_DPA_W_PH_DSP
,
632 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
634 /* DSP Bit/Manipulation Sub-class */
635 OPC_INSV
= (0x00 << 6) | OPC_INSV_DSP
,
638 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
640 /* MIPS DSP Append Sub-class */
641 OPC_APPEND
= (0x00 << 6) | OPC_APPEND_DSP
,
642 OPC_PREPEND
= (0x01 << 6) | OPC_APPEND_DSP
,
643 OPC_BALIGN
= (0x10 << 6) | OPC_APPEND_DSP
,
646 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
648 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
649 OPC_EXTR_W
= (0x00 << 6) | OPC_EXTR_W_DSP
,
650 OPC_EXTR_R_W
= (0x04 << 6) | OPC_EXTR_W_DSP
,
651 OPC_EXTR_RS_W
= (0x06 << 6) | OPC_EXTR_W_DSP
,
652 OPC_EXTR_S_H
= (0x0E << 6) | OPC_EXTR_W_DSP
,
653 OPC_EXTRV_S_H
= (0x0F << 6) | OPC_EXTR_W_DSP
,
654 OPC_EXTRV_W
= (0x01 << 6) | OPC_EXTR_W_DSP
,
655 OPC_EXTRV_R_W
= (0x05 << 6) | OPC_EXTR_W_DSP
,
656 OPC_EXTRV_RS_W
= (0x07 << 6) | OPC_EXTR_W_DSP
,
657 OPC_EXTP
= (0x02 << 6) | OPC_EXTR_W_DSP
,
658 OPC_EXTPV
= (0x03 << 6) | OPC_EXTR_W_DSP
,
659 OPC_EXTPDP
= (0x0A << 6) | OPC_EXTR_W_DSP
,
660 OPC_EXTPDPV
= (0x0B << 6) | OPC_EXTR_W_DSP
,
661 OPC_SHILO
= (0x1A << 6) | OPC_EXTR_W_DSP
,
662 OPC_SHILOV
= (0x1B << 6) | OPC_EXTR_W_DSP
,
663 OPC_MTHLIP
= (0x1F << 6) | OPC_EXTR_W_DSP
,
664 OPC_WRDSP
= (0x13 << 6) | OPC_EXTR_W_DSP
,
665 OPC_RDDSP
= (0x12 << 6) | OPC_EXTR_W_DSP
,
668 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
670 /* MIPS DSP Arithmetic Sub-class */
671 OPC_PRECEQ_L_PWL
= (0x14 << 6) | OPC_ABSQ_S_QH_DSP
,
672 OPC_PRECEQ_L_PWR
= (0x15 << 6) | OPC_ABSQ_S_QH_DSP
,
673 OPC_PRECEQ_PW_QHL
= (0x0C << 6) | OPC_ABSQ_S_QH_DSP
,
674 OPC_PRECEQ_PW_QHR
= (0x0D << 6) | OPC_ABSQ_S_QH_DSP
,
675 OPC_PRECEQ_PW_QHLA
= (0x0E << 6) | OPC_ABSQ_S_QH_DSP
,
676 OPC_PRECEQ_PW_QHRA
= (0x0F << 6) | OPC_ABSQ_S_QH_DSP
,
677 OPC_PRECEQU_QH_OBL
= (0x04 << 6) | OPC_ABSQ_S_QH_DSP
,
678 OPC_PRECEQU_QH_OBR
= (0x05 << 6) | OPC_ABSQ_S_QH_DSP
,
679 OPC_PRECEQU_QH_OBLA
= (0x06 << 6) | OPC_ABSQ_S_QH_DSP
,
680 OPC_PRECEQU_QH_OBRA
= (0x07 << 6) | OPC_ABSQ_S_QH_DSP
,
681 OPC_PRECEU_QH_OBL
= (0x1C << 6) | OPC_ABSQ_S_QH_DSP
,
682 OPC_PRECEU_QH_OBR
= (0x1D << 6) | OPC_ABSQ_S_QH_DSP
,
683 OPC_PRECEU_QH_OBLA
= (0x1E << 6) | OPC_ABSQ_S_QH_DSP
,
684 OPC_PRECEU_QH_OBRA
= (0x1F << 6) | OPC_ABSQ_S_QH_DSP
,
685 OPC_ABSQ_S_OB
= (0x01 << 6) | OPC_ABSQ_S_QH_DSP
,
686 OPC_ABSQ_S_PW
= (0x11 << 6) | OPC_ABSQ_S_QH_DSP
,
687 OPC_ABSQ_S_QH
= (0x09 << 6) | OPC_ABSQ_S_QH_DSP
,
688 /* DSP Bit/Manipulation Sub-class */
689 OPC_REPL_OB
= (0x02 << 6) | OPC_ABSQ_S_QH_DSP
,
690 OPC_REPL_PW
= (0x12 << 6) | OPC_ABSQ_S_QH_DSP
,
691 OPC_REPL_QH
= (0x0A << 6) | OPC_ABSQ_S_QH_DSP
,
692 OPC_REPLV_OB
= (0x03 << 6) | OPC_ABSQ_S_QH_DSP
,
693 OPC_REPLV_PW
= (0x13 << 6) | OPC_ABSQ_S_QH_DSP
,
694 OPC_REPLV_QH
= (0x0B << 6) | OPC_ABSQ_S_QH_DSP
,
697 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
699 /* MIPS DSP Multiply Sub-class insns */
700 OPC_MULEQ_S_PW_QHL
= (0x1C << 6) | OPC_ADDU_OB_DSP
,
701 OPC_MULEQ_S_PW_QHR
= (0x1D << 6) | OPC_ADDU_OB_DSP
,
702 OPC_MULEU_S_QH_OBL
= (0x06 << 6) | OPC_ADDU_OB_DSP
,
703 OPC_MULEU_S_QH_OBR
= (0x07 << 6) | OPC_ADDU_OB_DSP
,
704 OPC_MULQ_RS_QH
= (0x1F << 6) | OPC_ADDU_OB_DSP
,
705 /* MIPS DSP Arithmetic Sub-class */
706 OPC_RADDU_L_OB
= (0x14 << 6) | OPC_ADDU_OB_DSP
,
707 OPC_SUBQ_PW
= (0x13 << 6) | OPC_ADDU_OB_DSP
,
708 OPC_SUBQ_S_PW
= (0x17 << 6) | OPC_ADDU_OB_DSP
,
709 OPC_SUBQ_QH
= (0x0B << 6) | OPC_ADDU_OB_DSP
,
710 OPC_SUBQ_S_QH
= (0x0F << 6) | OPC_ADDU_OB_DSP
,
711 OPC_SUBU_OB
= (0x01 << 6) | OPC_ADDU_OB_DSP
,
712 OPC_SUBU_S_OB
= (0x05 << 6) | OPC_ADDU_OB_DSP
,
713 OPC_SUBU_QH
= (0x09 << 6) | OPC_ADDU_OB_DSP
,
714 OPC_SUBU_S_QH
= (0x0D << 6) | OPC_ADDU_OB_DSP
,
715 OPC_SUBUH_OB
= (0x19 << 6) | OPC_ADDU_OB_DSP
,
716 OPC_SUBUH_R_OB
= (0x1B << 6) | OPC_ADDU_OB_DSP
,
717 OPC_ADDQ_PW
= (0x12 << 6) | OPC_ADDU_OB_DSP
,
718 OPC_ADDQ_S_PW
= (0x16 << 6) | OPC_ADDU_OB_DSP
,
719 OPC_ADDQ_QH
= (0x0A << 6) | OPC_ADDU_OB_DSP
,
720 OPC_ADDQ_S_QH
= (0x0E << 6) | OPC_ADDU_OB_DSP
,
721 OPC_ADDU_OB
= (0x00 << 6) | OPC_ADDU_OB_DSP
,
722 OPC_ADDU_S_OB
= (0x04 << 6) | OPC_ADDU_OB_DSP
,
723 OPC_ADDU_QH
= (0x08 << 6) | OPC_ADDU_OB_DSP
,
724 OPC_ADDU_S_QH
= (0x0C << 6) | OPC_ADDU_OB_DSP
,
725 OPC_ADDUH_OB
= (0x18 << 6) | OPC_ADDU_OB_DSP
,
726 OPC_ADDUH_R_OB
= (0x1A << 6) | OPC_ADDU_OB_DSP
,
729 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
731 /* DSP Compare-Pick Sub-class */
732 OPC_CMP_EQ_PW
= (0x10 << 6) | OPC_CMPU_EQ_OB_DSP
,
733 OPC_CMP_LT_PW
= (0x11 << 6) | OPC_CMPU_EQ_OB_DSP
,
734 OPC_CMP_LE_PW
= (0x12 << 6) | OPC_CMPU_EQ_OB_DSP
,
735 OPC_CMP_EQ_QH
= (0x08 << 6) | OPC_CMPU_EQ_OB_DSP
,
736 OPC_CMP_LT_QH
= (0x09 << 6) | OPC_CMPU_EQ_OB_DSP
,
737 OPC_CMP_LE_QH
= (0x0A << 6) | OPC_CMPU_EQ_OB_DSP
,
738 OPC_CMPGDU_EQ_OB
= (0x18 << 6) | OPC_CMPU_EQ_OB_DSP
,
739 OPC_CMPGDU_LT_OB
= (0x19 << 6) | OPC_CMPU_EQ_OB_DSP
,
740 OPC_CMPGDU_LE_OB
= (0x1A << 6) | OPC_CMPU_EQ_OB_DSP
,
741 OPC_CMPGU_EQ_OB
= (0x04 << 6) | OPC_CMPU_EQ_OB_DSP
,
742 OPC_CMPGU_LT_OB
= (0x05 << 6) | OPC_CMPU_EQ_OB_DSP
,
743 OPC_CMPGU_LE_OB
= (0x06 << 6) | OPC_CMPU_EQ_OB_DSP
,
744 OPC_CMPU_EQ_OB
= (0x00 << 6) | OPC_CMPU_EQ_OB_DSP
,
745 OPC_CMPU_LT_OB
= (0x01 << 6) | OPC_CMPU_EQ_OB_DSP
,
746 OPC_CMPU_LE_OB
= (0x02 << 6) | OPC_CMPU_EQ_OB_DSP
,
747 OPC_PACKRL_PW
= (0x0E << 6) | OPC_CMPU_EQ_OB_DSP
,
748 OPC_PICK_OB
= (0x03 << 6) | OPC_CMPU_EQ_OB_DSP
,
749 OPC_PICK_PW
= (0x13 << 6) | OPC_CMPU_EQ_OB_DSP
,
750 OPC_PICK_QH
= (0x0B << 6) | OPC_CMPU_EQ_OB_DSP
,
751 /* MIPS DSP Arithmetic Sub-class */
752 OPC_PRECR_OB_QH
= (0x0D << 6) | OPC_CMPU_EQ_OB_DSP
,
753 OPC_PRECR_SRA_QH_PW
= (0x1E << 6) | OPC_CMPU_EQ_OB_DSP
,
754 OPC_PRECR_SRA_R_QH_PW
= (0x1F << 6) | OPC_CMPU_EQ_OB_DSP
,
755 OPC_PRECRQ_OB_QH
= (0x0C << 6) | OPC_CMPU_EQ_OB_DSP
,
756 OPC_PRECRQ_PW_L
= (0x1C << 6) | OPC_CMPU_EQ_OB_DSP
,
757 OPC_PRECRQ_QH_PW
= (0x14 << 6) | OPC_CMPU_EQ_OB_DSP
,
758 OPC_PRECRQ_RS_QH_PW
= (0x15 << 6) | OPC_CMPU_EQ_OB_DSP
,
759 OPC_PRECRQU_S_OB_QH
= (0x0F << 6) | OPC_CMPU_EQ_OB_DSP
,
762 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
764 /* DSP Append Sub-class */
765 OPC_DAPPEND
= (0x00 << 6) | OPC_DAPPEND_DSP
,
766 OPC_PREPENDD
= (0x03 << 6) | OPC_DAPPEND_DSP
,
767 OPC_PREPENDW
= (0x01 << 6) | OPC_DAPPEND_DSP
,
768 OPC_DBALIGN
= (0x10 << 6) | OPC_DAPPEND_DSP
,
771 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
773 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
774 OPC_DMTHLIP
= (0x1F << 6) | OPC_DEXTR_W_DSP
,
775 OPC_DSHILO
= (0x1A << 6) | OPC_DEXTR_W_DSP
,
776 OPC_DEXTP
= (0x02 << 6) | OPC_DEXTR_W_DSP
,
777 OPC_DEXTPDP
= (0x0A << 6) | OPC_DEXTR_W_DSP
,
778 OPC_DEXTPDPV
= (0x0B << 6) | OPC_DEXTR_W_DSP
,
779 OPC_DEXTPV
= (0x03 << 6) | OPC_DEXTR_W_DSP
,
780 OPC_DEXTR_L
= (0x10 << 6) | OPC_DEXTR_W_DSP
,
781 OPC_DEXTR_R_L
= (0x14 << 6) | OPC_DEXTR_W_DSP
,
782 OPC_DEXTR_RS_L
= (0x16 << 6) | OPC_DEXTR_W_DSP
,
783 OPC_DEXTR_W
= (0x00 << 6) | OPC_DEXTR_W_DSP
,
784 OPC_DEXTR_R_W
= (0x04 << 6) | OPC_DEXTR_W_DSP
,
785 OPC_DEXTR_RS_W
= (0x06 << 6) | OPC_DEXTR_W_DSP
,
786 OPC_DEXTR_S_H
= (0x0E << 6) | OPC_DEXTR_W_DSP
,
787 OPC_DEXTRV_L
= (0x11 << 6) | OPC_DEXTR_W_DSP
,
788 OPC_DEXTRV_R_L
= (0x15 << 6) | OPC_DEXTR_W_DSP
,
789 OPC_DEXTRV_RS_L
= (0x17 << 6) | OPC_DEXTR_W_DSP
,
790 OPC_DEXTRV_S_H
= (0x0F << 6) | OPC_DEXTR_W_DSP
,
791 OPC_DEXTRV_W
= (0x01 << 6) | OPC_DEXTR_W_DSP
,
792 OPC_DEXTRV_R_W
= (0x05 << 6) | OPC_DEXTR_W_DSP
,
793 OPC_DEXTRV_RS_W
= (0x07 << 6) | OPC_DEXTR_W_DSP
,
794 OPC_DSHILOV
= (0x1B << 6) | OPC_DEXTR_W_DSP
,
797 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
799 /* DSP Bit/Manipulation Sub-class */
800 OPC_DINSV
= (0x00 << 6) | OPC_DINSV_DSP
,
803 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
805 /* MIPS DSP Multiply Sub-class insns */
806 OPC_DMADD
= (0x19 << 6) | OPC_DPAQ_W_QH_DSP
,
807 OPC_DMADDU
= (0x1D << 6) | OPC_DPAQ_W_QH_DSP
,
808 OPC_DMSUB
= (0x1B << 6) | OPC_DPAQ_W_QH_DSP
,
809 OPC_DMSUBU
= (0x1F << 6) | OPC_DPAQ_W_QH_DSP
,
810 OPC_DPA_W_QH
= (0x00 << 6) | OPC_DPAQ_W_QH_DSP
,
811 OPC_DPAQ_S_W_QH
= (0x04 << 6) | OPC_DPAQ_W_QH_DSP
,
812 OPC_DPAQ_SA_L_PW
= (0x0C << 6) | OPC_DPAQ_W_QH_DSP
,
813 OPC_DPAU_H_OBL
= (0x03 << 6) | OPC_DPAQ_W_QH_DSP
,
814 OPC_DPAU_H_OBR
= (0x07 << 6) | OPC_DPAQ_W_QH_DSP
,
815 OPC_DPS_W_QH
= (0x01 << 6) | OPC_DPAQ_W_QH_DSP
,
816 OPC_DPSQ_S_W_QH
= (0x05 << 6) | OPC_DPAQ_W_QH_DSP
,
817 OPC_DPSQ_SA_L_PW
= (0x0D << 6) | OPC_DPAQ_W_QH_DSP
,
818 OPC_DPSU_H_OBL
= (0x0B << 6) | OPC_DPAQ_W_QH_DSP
,
819 OPC_DPSU_H_OBR
= (0x0F << 6) | OPC_DPAQ_W_QH_DSP
,
820 OPC_MAQ_S_L_PWL
= (0x1C << 6) | OPC_DPAQ_W_QH_DSP
,
821 OPC_MAQ_S_L_PWR
= (0x1E << 6) | OPC_DPAQ_W_QH_DSP
,
822 OPC_MAQ_S_W_QHLL
= (0x14 << 6) | OPC_DPAQ_W_QH_DSP
,
823 OPC_MAQ_SA_W_QHLL
= (0x10 << 6) | OPC_DPAQ_W_QH_DSP
,
824 OPC_MAQ_S_W_QHLR
= (0x15 << 6) | OPC_DPAQ_W_QH_DSP
,
825 OPC_MAQ_SA_W_QHLR
= (0x11 << 6) | OPC_DPAQ_W_QH_DSP
,
826 OPC_MAQ_S_W_QHRL
= (0x16 << 6) | OPC_DPAQ_W_QH_DSP
,
827 OPC_MAQ_SA_W_QHRL
= (0x12 << 6) | OPC_DPAQ_W_QH_DSP
,
828 OPC_MAQ_S_W_QHRR
= (0x17 << 6) | OPC_DPAQ_W_QH_DSP
,
829 OPC_MAQ_SA_W_QHRR
= (0x13 << 6) | OPC_DPAQ_W_QH_DSP
,
830 OPC_MULSAQ_S_L_PW
= (0x0E << 6) | OPC_DPAQ_W_QH_DSP
,
831 OPC_MULSAQ_S_W_QH
= (0x06 << 6) | OPC_DPAQ_W_QH_DSP
,
834 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
836 /* MIPS DSP GPR-Based Shift Sub-class */
837 OPC_SHLL_PW
= (0x10 << 6) | OPC_SHLL_OB_DSP
,
838 OPC_SHLL_S_PW
= (0x14 << 6) | OPC_SHLL_OB_DSP
,
839 OPC_SHLLV_OB
= (0x02 << 6) | OPC_SHLL_OB_DSP
,
840 OPC_SHLLV_PW
= (0x12 << 6) | OPC_SHLL_OB_DSP
,
841 OPC_SHLLV_S_PW
= (0x16 << 6) | OPC_SHLL_OB_DSP
,
842 OPC_SHLLV_QH
= (0x0A << 6) | OPC_SHLL_OB_DSP
,
843 OPC_SHLLV_S_QH
= (0x0E << 6) | OPC_SHLL_OB_DSP
,
844 OPC_SHRA_PW
= (0x11 << 6) | OPC_SHLL_OB_DSP
,
845 OPC_SHRA_R_PW
= (0x15 << 6) | OPC_SHLL_OB_DSP
,
846 OPC_SHRAV_OB
= (0x06 << 6) | OPC_SHLL_OB_DSP
,
847 OPC_SHRAV_R_OB
= (0x07 << 6) | OPC_SHLL_OB_DSP
,
848 OPC_SHRAV_PW
= (0x13 << 6) | OPC_SHLL_OB_DSP
,
849 OPC_SHRAV_R_PW
= (0x17 << 6) | OPC_SHLL_OB_DSP
,
850 OPC_SHRAV_QH
= (0x0B << 6) | OPC_SHLL_OB_DSP
,
851 OPC_SHRAV_R_QH
= (0x0F << 6) | OPC_SHLL_OB_DSP
,
852 OPC_SHRLV_OB
= (0x03 << 6) | OPC_SHLL_OB_DSP
,
853 OPC_SHRLV_QH
= (0x1B << 6) | OPC_SHLL_OB_DSP
,
854 OPC_SHLL_OB
= (0x00 << 6) | OPC_SHLL_OB_DSP
,
855 OPC_SHLL_QH
= (0x08 << 6) | OPC_SHLL_OB_DSP
,
856 OPC_SHLL_S_QH
= (0x0C << 6) | OPC_SHLL_OB_DSP
,
857 OPC_SHRA_OB
= (0x04 << 6) | OPC_SHLL_OB_DSP
,
858 OPC_SHRA_R_OB
= (0x05 << 6) | OPC_SHLL_OB_DSP
,
859 OPC_SHRA_QH
= (0x09 << 6) | OPC_SHLL_OB_DSP
,
860 OPC_SHRA_R_QH
= (0x0D << 6) | OPC_SHLL_OB_DSP
,
861 OPC_SHRL_OB
= (0x01 << 6) | OPC_SHLL_OB_DSP
,
862 OPC_SHRL_QH
= (0x19 << 6) | OPC_SHLL_OB_DSP
,
865 /* Coprocessor 0 (rs field) */
866 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
869 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
870 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
871 OPC_MFHC0
= (0x02 << 21) | OPC_CP0
,
872 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
873 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
874 OPC_MTHC0
= (0x06 << 21) | OPC_CP0
,
875 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
876 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
877 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
878 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
879 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
880 OPC_C0
= (0x10 << 21) | OPC_CP0
,
881 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
882 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
886 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
889 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
890 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
891 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
892 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
893 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
894 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
897 /* Coprocessor 0 (with rs == C0) */
898 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
901 OPC_TLBR
= 0x01 | OPC_C0
,
902 OPC_TLBWI
= 0x02 | OPC_C0
,
903 OPC_TLBINV
= 0x03 | OPC_C0
,
904 OPC_TLBINVF
= 0x04 | OPC_C0
,
905 OPC_TLBWR
= 0x06 | OPC_C0
,
906 OPC_TLBP
= 0x08 | OPC_C0
,
907 OPC_RFE
= 0x10 | OPC_C0
,
908 OPC_ERET
= 0x18 | OPC_C0
,
909 OPC_DERET
= 0x1F | OPC_C0
,
910 OPC_WAIT
= 0x20 | OPC_C0
,
913 /* Coprocessor 1 (rs field) */
914 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
916 /* Values for the fmt field in FP instructions */
918 /* 0 - 15 are reserved */
919 FMT_S
= 16, /* single fp */
920 FMT_D
= 17, /* double fp */
921 FMT_E
= 18, /* extended fp */
922 FMT_Q
= 19, /* quad fp */
923 FMT_W
= 20, /* 32-bit fixed */
924 FMT_L
= 21, /* 64-bit fixed */
925 FMT_PS
= 22, /* paired single fp */
926 /* 23 - 31 are reserved */
930 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
931 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
932 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
933 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
934 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
935 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
936 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
937 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
938 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
939 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
940 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
941 OPC_BZ_V
= (0x0B << 21) | OPC_CP1
,
942 OPC_BNZ_V
= (0x0F << 21) | OPC_CP1
,
943 OPC_S_FMT
= (FMT_S
<< 21) | OPC_CP1
,
944 OPC_D_FMT
= (FMT_D
<< 21) | OPC_CP1
,
945 OPC_E_FMT
= (FMT_E
<< 21) | OPC_CP1
,
946 OPC_Q_FMT
= (FMT_Q
<< 21) | OPC_CP1
,
947 OPC_W_FMT
= (FMT_W
<< 21) | OPC_CP1
,
948 OPC_L_FMT
= (FMT_L
<< 21) | OPC_CP1
,
949 OPC_PS_FMT
= (FMT_PS
<< 21) | OPC_CP1
,
950 OPC_BC1EQZ
= (0x09 << 21) | OPC_CP1
,
951 OPC_BC1NEZ
= (0x0D << 21) | OPC_CP1
,
952 OPC_BZ_B
= (0x18 << 21) | OPC_CP1
,
953 OPC_BZ_H
= (0x19 << 21) | OPC_CP1
,
954 OPC_BZ_W
= (0x1A << 21) | OPC_CP1
,
955 OPC_BZ_D
= (0x1B << 21) | OPC_CP1
,
956 OPC_BNZ_B
= (0x1C << 21) | OPC_CP1
,
957 OPC_BNZ_H
= (0x1D << 21) | OPC_CP1
,
958 OPC_BNZ_W
= (0x1E << 21) | OPC_CP1
,
959 OPC_BNZ_D
= (0x1F << 21) | OPC_CP1
,
962 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
963 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
966 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
967 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
968 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
969 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
973 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
974 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
978 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
979 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
982 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
985 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
986 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
987 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
988 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
989 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
990 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
991 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
992 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
993 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
994 OPC_BC2EQZ
= (0x09 << 21) | OPC_CP2
,
995 OPC_BC2NEZ
= (0x0D << 21) | OPC_CP2
,
998 #define MASK_LMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1001 OPC_PADDSH
= (24 << 21) | (0x00) | OPC_CP2
,
1002 OPC_PADDUSH
= (25 << 21) | (0x00) | OPC_CP2
,
1003 OPC_PADDH
= (26 << 21) | (0x00) | OPC_CP2
,
1004 OPC_PADDW
= (27 << 21) | (0x00) | OPC_CP2
,
1005 OPC_PADDSB
= (28 << 21) | (0x00) | OPC_CP2
,
1006 OPC_PADDUSB
= (29 << 21) | (0x00) | OPC_CP2
,
1007 OPC_PADDB
= (30 << 21) | (0x00) | OPC_CP2
,
1008 OPC_PADDD
= (31 << 21) | (0x00) | OPC_CP2
,
1010 OPC_PSUBSH
= (24 << 21) | (0x01) | OPC_CP2
,
1011 OPC_PSUBUSH
= (25 << 21) | (0x01) | OPC_CP2
,
1012 OPC_PSUBH
= (26 << 21) | (0x01) | OPC_CP2
,
1013 OPC_PSUBW
= (27 << 21) | (0x01) | OPC_CP2
,
1014 OPC_PSUBSB
= (28 << 21) | (0x01) | OPC_CP2
,
1015 OPC_PSUBUSB
= (29 << 21) | (0x01) | OPC_CP2
,
1016 OPC_PSUBB
= (30 << 21) | (0x01) | OPC_CP2
,
1017 OPC_PSUBD
= (31 << 21) | (0x01) | OPC_CP2
,
1019 OPC_PSHUFH
= (24 << 21) | (0x02) | OPC_CP2
,
1020 OPC_PACKSSWH
= (25 << 21) | (0x02) | OPC_CP2
,
1021 OPC_PACKSSHB
= (26 << 21) | (0x02) | OPC_CP2
,
1022 OPC_PACKUSHB
= (27 << 21) | (0x02) | OPC_CP2
,
1023 OPC_XOR_CP2
= (28 << 21) | (0x02) | OPC_CP2
,
1024 OPC_NOR_CP2
= (29 << 21) | (0x02) | OPC_CP2
,
1025 OPC_AND_CP2
= (30 << 21) | (0x02) | OPC_CP2
,
1026 OPC_PANDN
= (31 << 21) | (0x02) | OPC_CP2
,
1028 OPC_PUNPCKLHW
= (24 << 21) | (0x03) | OPC_CP2
,
1029 OPC_PUNPCKHHW
= (25 << 21) | (0x03) | OPC_CP2
,
1030 OPC_PUNPCKLBH
= (26 << 21) | (0x03) | OPC_CP2
,
1031 OPC_PUNPCKHBH
= (27 << 21) | (0x03) | OPC_CP2
,
1032 OPC_PINSRH_0
= (28 << 21) | (0x03) | OPC_CP2
,
1033 OPC_PINSRH_1
= (29 << 21) | (0x03) | OPC_CP2
,
1034 OPC_PINSRH_2
= (30 << 21) | (0x03) | OPC_CP2
,
1035 OPC_PINSRH_3
= (31 << 21) | (0x03) | OPC_CP2
,
1037 OPC_PAVGH
= (24 << 21) | (0x08) | OPC_CP2
,
1038 OPC_PAVGB
= (25 << 21) | (0x08) | OPC_CP2
,
1039 OPC_PMAXSH
= (26 << 21) | (0x08) | OPC_CP2
,
1040 OPC_PMINSH
= (27 << 21) | (0x08) | OPC_CP2
,
1041 OPC_PMAXUB
= (28 << 21) | (0x08) | OPC_CP2
,
1042 OPC_PMINUB
= (29 << 21) | (0x08) | OPC_CP2
,
1044 OPC_PCMPEQW
= (24 << 21) | (0x09) | OPC_CP2
,
1045 OPC_PCMPGTW
= (25 << 21) | (0x09) | OPC_CP2
,
1046 OPC_PCMPEQH
= (26 << 21) | (0x09) | OPC_CP2
,
1047 OPC_PCMPGTH
= (27 << 21) | (0x09) | OPC_CP2
,
1048 OPC_PCMPEQB
= (28 << 21) | (0x09) | OPC_CP2
,
1049 OPC_PCMPGTB
= (29 << 21) | (0x09) | OPC_CP2
,
1051 OPC_PSLLW
= (24 << 21) | (0x0A) | OPC_CP2
,
1052 OPC_PSLLH
= (25 << 21) | (0x0A) | OPC_CP2
,
1053 OPC_PMULLH
= (26 << 21) | (0x0A) | OPC_CP2
,
1054 OPC_PMULHH
= (27 << 21) | (0x0A) | OPC_CP2
,
1055 OPC_PMULUW
= (28 << 21) | (0x0A) | OPC_CP2
,
1056 OPC_PMULHUH
= (29 << 21) | (0x0A) | OPC_CP2
,
1058 OPC_PSRLW
= (24 << 21) | (0x0B) | OPC_CP2
,
1059 OPC_PSRLH
= (25 << 21) | (0x0B) | OPC_CP2
,
1060 OPC_PSRAW
= (26 << 21) | (0x0B) | OPC_CP2
,
1061 OPC_PSRAH
= (27 << 21) | (0x0B) | OPC_CP2
,
1062 OPC_PUNPCKLWD
= (28 << 21) | (0x0B) | OPC_CP2
,
1063 OPC_PUNPCKHWD
= (29 << 21) | (0x0B) | OPC_CP2
,
1065 OPC_ADDU_CP2
= (24 << 21) | (0x0C) | OPC_CP2
,
1066 OPC_OR_CP2
= (25 << 21) | (0x0C) | OPC_CP2
,
1067 OPC_ADD_CP2
= (26 << 21) | (0x0C) | OPC_CP2
,
1068 OPC_DADD_CP2
= (27 << 21) | (0x0C) | OPC_CP2
,
1069 OPC_SEQU_CP2
= (28 << 21) | (0x0C) | OPC_CP2
,
1070 OPC_SEQ_CP2
= (29 << 21) | (0x0C) | OPC_CP2
,
1072 OPC_SUBU_CP2
= (24 << 21) | (0x0D) | OPC_CP2
,
1073 OPC_PASUBUB
= (25 << 21) | (0x0D) | OPC_CP2
,
1074 OPC_SUB_CP2
= (26 << 21) | (0x0D) | OPC_CP2
,
1075 OPC_DSUB_CP2
= (27 << 21) | (0x0D) | OPC_CP2
,
1076 OPC_SLTU_CP2
= (28 << 21) | (0x0D) | OPC_CP2
,
1077 OPC_SLT_CP2
= (29 << 21) | (0x0D) | OPC_CP2
,
1079 OPC_SLL_CP2
= (24 << 21) | (0x0E) | OPC_CP2
,
1080 OPC_DSLL_CP2
= (25 << 21) | (0x0E) | OPC_CP2
,
1081 OPC_PEXTRH
= (26 << 21) | (0x0E) | OPC_CP2
,
1082 OPC_PMADDHW
= (27 << 21) | (0x0E) | OPC_CP2
,
1083 OPC_SLEU_CP2
= (28 << 21) | (0x0E) | OPC_CP2
,
1084 OPC_SLE_CP2
= (29 << 21) | (0x0E) | OPC_CP2
,
1086 OPC_SRL_CP2
= (24 << 21) | (0x0F) | OPC_CP2
,
1087 OPC_DSRL_CP2
= (25 << 21) | (0x0F) | OPC_CP2
,
1088 OPC_SRA_CP2
= (26 << 21) | (0x0F) | OPC_CP2
,
1089 OPC_DSRA_CP2
= (27 << 21) | (0x0F) | OPC_CP2
,
1090 OPC_BIADD
= (28 << 21) | (0x0F) | OPC_CP2
,
1091 OPC_PMOVMSKB
= (29 << 21) | (0x0F) | OPC_CP2
,
1095 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
1098 OPC_LWXC1
= 0x00 | OPC_CP3
,
1099 OPC_LDXC1
= 0x01 | OPC_CP3
,
1100 OPC_LUXC1
= 0x05 | OPC_CP3
,
1101 OPC_SWXC1
= 0x08 | OPC_CP3
,
1102 OPC_SDXC1
= 0x09 | OPC_CP3
,
1103 OPC_SUXC1
= 0x0D | OPC_CP3
,
1104 OPC_PREFX
= 0x0F | OPC_CP3
,
1105 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
1106 OPC_MADD_S
= 0x20 | OPC_CP3
,
1107 OPC_MADD_D
= 0x21 | OPC_CP3
,
1108 OPC_MADD_PS
= 0x26 | OPC_CP3
,
1109 OPC_MSUB_S
= 0x28 | OPC_CP3
,
1110 OPC_MSUB_D
= 0x29 | OPC_CP3
,
1111 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
1112 OPC_NMADD_S
= 0x30 | OPC_CP3
,
1113 OPC_NMADD_D
= 0x31 | OPC_CP3
,
1114 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
1115 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
1116 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
1117 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
1121 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1123 OPC_MSA_I8_00
= 0x00 | OPC_MSA
,
1124 OPC_MSA_I8_01
= 0x01 | OPC_MSA
,
1125 OPC_MSA_I8_02
= 0x02 | OPC_MSA
,
1126 OPC_MSA_I5_06
= 0x06 | OPC_MSA
,
1127 OPC_MSA_I5_07
= 0x07 | OPC_MSA
,
1128 OPC_MSA_BIT_09
= 0x09 | OPC_MSA
,
1129 OPC_MSA_BIT_0A
= 0x0A | OPC_MSA
,
1130 OPC_MSA_3R_0D
= 0x0D | OPC_MSA
,
1131 OPC_MSA_3R_0E
= 0x0E | OPC_MSA
,
1132 OPC_MSA_3R_0F
= 0x0F | OPC_MSA
,
1133 OPC_MSA_3R_10
= 0x10 | OPC_MSA
,
1134 OPC_MSA_3R_11
= 0x11 | OPC_MSA
,
1135 OPC_MSA_3R_12
= 0x12 | OPC_MSA
,
1136 OPC_MSA_3R_13
= 0x13 | OPC_MSA
,
1137 OPC_MSA_3R_14
= 0x14 | OPC_MSA
,
1138 OPC_MSA_3R_15
= 0x15 | OPC_MSA
,
1139 OPC_MSA_ELM
= 0x19 | OPC_MSA
,
1140 OPC_MSA_3RF_1A
= 0x1A | OPC_MSA
,
1141 OPC_MSA_3RF_1B
= 0x1B | OPC_MSA
,
1142 OPC_MSA_3RF_1C
= 0x1C | OPC_MSA
,
1143 OPC_MSA_VEC
= 0x1E | OPC_MSA
,
1145 /* MI10 instruction */
1146 OPC_LD_B
= (0x20) | OPC_MSA
,
1147 OPC_LD_H
= (0x21) | OPC_MSA
,
1148 OPC_LD_W
= (0x22) | OPC_MSA
,
1149 OPC_LD_D
= (0x23) | OPC_MSA
,
1150 OPC_ST_B
= (0x24) | OPC_MSA
,
1151 OPC_ST_H
= (0x25) | OPC_MSA
,
1152 OPC_ST_W
= (0x26) | OPC_MSA
,
1153 OPC_ST_D
= (0x27) | OPC_MSA
,
1157 /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
1158 OPC_ADDVI_df
= (0x0 << 23) | OPC_MSA_I5_06
,
1159 OPC_CEQI_df
= (0x0 << 23) | OPC_MSA_I5_07
,
1160 OPC_SUBVI_df
= (0x1 << 23) | OPC_MSA_I5_06
,
1161 OPC_MAXI_S_df
= (0x2 << 23) | OPC_MSA_I5_06
,
1162 OPC_CLTI_S_df
= (0x2 << 23) | OPC_MSA_I5_07
,
1163 OPC_MAXI_U_df
= (0x3 << 23) | OPC_MSA_I5_06
,
1164 OPC_CLTI_U_df
= (0x3 << 23) | OPC_MSA_I5_07
,
1165 OPC_MINI_S_df
= (0x4 << 23) | OPC_MSA_I5_06
,
1166 OPC_CLEI_S_df
= (0x4 << 23) | OPC_MSA_I5_07
,
1167 OPC_MINI_U_df
= (0x5 << 23) | OPC_MSA_I5_06
,
1168 OPC_CLEI_U_df
= (0x5 << 23) | OPC_MSA_I5_07
,
1169 OPC_LDI_df
= (0x6 << 23) | OPC_MSA_I5_07
,
1171 /* I8 instruction */
1172 OPC_ANDI_B
= (0x0 << 24) | OPC_MSA_I8_00
,
1173 OPC_BMNZI_B
= (0x0 << 24) | OPC_MSA_I8_01
,
1174 OPC_SHF_B
= (0x0 << 24) | OPC_MSA_I8_02
,
1175 OPC_ORI_B
= (0x1 << 24) | OPC_MSA_I8_00
,
1176 OPC_BMZI_B
= (0x1 << 24) | OPC_MSA_I8_01
,
1177 OPC_SHF_H
= (0x1 << 24) | OPC_MSA_I8_02
,
1178 OPC_NORI_B
= (0x2 << 24) | OPC_MSA_I8_00
,
1179 OPC_BSELI_B
= (0x2 << 24) | OPC_MSA_I8_01
,
1180 OPC_SHF_W
= (0x2 << 24) | OPC_MSA_I8_02
,
1181 OPC_XORI_B
= (0x3 << 24) | OPC_MSA_I8_00
,
1183 /* VEC/2R/2RF instruction */
1184 OPC_AND_V
= (0x00 << 21) | OPC_MSA_VEC
,
1185 OPC_OR_V
= (0x01 << 21) | OPC_MSA_VEC
,
1186 OPC_NOR_V
= (0x02 << 21) | OPC_MSA_VEC
,
1187 OPC_XOR_V
= (0x03 << 21) | OPC_MSA_VEC
,
1188 OPC_BMNZ_V
= (0x04 << 21) | OPC_MSA_VEC
,
1189 OPC_BMZ_V
= (0x05 << 21) | OPC_MSA_VEC
,
1190 OPC_BSEL_V
= (0x06 << 21) | OPC_MSA_VEC
,
1192 OPC_MSA_2R
= (0x18 << 21) | OPC_MSA_VEC
,
1193 OPC_MSA_2RF
= (0x19 << 21) | OPC_MSA_VEC
,
1195 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
1196 OPC_FILL_df
= (0x00 << 18) | OPC_MSA_2R
,
1197 OPC_PCNT_df
= (0x01 << 18) | OPC_MSA_2R
,
1198 OPC_NLOC_df
= (0x02 << 18) | OPC_MSA_2R
,
1199 OPC_NLZC_df
= (0x03 << 18) | OPC_MSA_2R
,
1201 /* 2RF instruction df(bit 16) = _w, _d */
1202 OPC_FCLASS_df
= (0x00 << 17) | OPC_MSA_2RF
,
1203 OPC_FTRUNC_S_df
= (0x01 << 17) | OPC_MSA_2RF
,
1204 OPC_FTRUNC_U_df
= (0x02 << 17) | OPC_MSA_2RF
,
1205 OPC_FSQRT_df
= (0x03 << 17) | OPC_MSA_2RF
,
1206 OPC_FRSQRT_df
= (0x04 << 17) | OPC_MSA_2RF
,
1207 OPC_FRCP_df
= (0x05 << 17) | OPC_MSA_2RF
,
1208 OPC_FRINT_df
= (0x06 << 17) | OPC_MSA_2RF
,
1209 OPC_FLOG2_df
= (0x07 << 17) | OPC_MSA_2RF
,
1210 OPC_FEXUPL_df
= (0x08 << 17) | OPC_MSA_2RF
,
1211 OPC_FEXUPR_df
= (0x09 << 17) | OPC_MSA_2RF
,
1212 OPC_FFQL_df
= (0x0A << 17) | OPC_MSA_2RF
,
1213 OPC_FFQR_df
= (0x0B << 17) | OPC_MSA_2RF
,
1214 OPC_FTINT_S_df
= (0x0C << 17) | OPC_MSA_2RF
,
1215 OPC_FTINT_U_df
= (0x0D << 17) | OPC_MSA_2RF
,
1216 OPC_FFINT_S_df
= (0x0E << 17) | OPC_MSA_2RF
,
1217 OPC_FFINT_U_df
= (0x0F << 17) | OPC_MSA_2RF
,
1219 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
1220 OPC_SLL_df
= (0x0 << 23) | OPC_MSA_3R_0D
,
1221 OPC_ADDV_df
= (0x0 << 23) | OPC_MSA_3R_0E
,
1222 OPC_CEQ_df
= (0x0 << 23) | OPC_MSA_3R_0F
,
1223 OPC_ADD_A_df
= (0x0 << 23) | OPC_MSA_3R_10
,
1224 OPC_SUBS_S_df
= (0x0 << 23) | OPC_MSA_3R_11
,
1225 OPC_MULV_df
= (0x0 << 23) | OPC_MSA_3R_12
,
1226 OPC_DOTP_S_df
= (0x0 << 23) | OPC_MSA_3R_13
,
1227 OPC_SLD_df
= (0x0 << 23) | OPC_MSA_3R_14
,
1228 OPC_VSHF_df
= (0x0 << 23) | OPC_MSA_3R_15
,
1229 OPC_SRA_df
= (0x1 << 23) | OPC_MSA_3R_0D
,
1230 OPC_SUBV_df
= (0x1 << 23) | OPC_MSA_3R_0E
,
1231 OPC_ADDS_A_df
= (0x1 << 23) | OPC_MSA_3R_10
,
1232 OPC_SUBS_U_df
= (0x1 << 23) | OPC_MSA_3R_11
,
1233 OPC_MADDV_df
= (0x1 << 23) | OPC_MSA_3R_12
,
1234 OPC_DOTP_U_df
= (0x1 << 23) | OPC_MSA_3R_13
,
1235 OPC_SPLAT_df
= (0x1 << 23) | OPC_MSA_3R_14
,
1236 OPC_SRAR_df
= (0x1 << 23) | OPC_MSA_3R_15
,
1237 OPC_SRL_df
= (0x2 << 23) | OPC_MSA_3R_0D
,
1238 OPC_MAX_S_df
= (0x2 << 23) | OPC_MSA_3R_0E
,
1239 OPC_CLT_S_df
= (0x2 << 23) | OPC_MSA_3R_0F
,
1240 OPC_ADDS_S_df
= (0x2 << 23) | OPC_MSA_3R_10
,
1241 OPC_SUBSUS_U_df
= (0x2 << 23) | OPC_MSA_3R_11
,
1242 OPC_MSUBV_df
= (0x2 << 23) | OPC_MSA_3R_12
,
1243 OPC_DPADD_S_df
= (0x2 << 23) | OPC_MSA_3R_13
,
1244 OPC_PCKEV_df
= (0x2 << 23) | OPC_MSA_3R_14
,
1245 OPC_SRLR_df
= (0x2 << 23) | OPC_MSA_3R_15
,
1246 OPC_BCLR_df
= (0x3 << 23) | OPC_MSA_3R_0D
,
1247 OPC_MAX_U_df
= (0x3 << 23) | OPC_MSA_3R_0E
,
1248 OPC_CLT_U_df
= (0x3 << 23) | OPC_MSA_3R_0F
,
1249 OPC_ADDS_U_df
= (0x3 << 23) | OPC_MSA_3R_10
,
1250 OPC_SUBSUU_S_df
= (0x3 << 23) | OPC_MSA_3R_11
,
1251 OPC_DPADD_U_df
= (0x3 << 23) | OPC_MSA_3R_13
,
1252 OPC_PCKOD_df
= (0x3 << 23) | OPC_MSA_3R_14
,
1253 OPC_BSET_df
= (0x4 << 23) | OPC_MSA_3R_0D
,
1254 OPC_MIN_S_df
= (0x4 << 23) | OPC_MSA_3R_0E
,
1255 OPC_CLE_S_df
= (0x4 << 23) | OPC_MSA_3R_0F
,
1256 OPC_AVE_S_df
= (0x4 << 23) | OPC_MSA_3R_10
,
1257 OPC_ASUB_S_df
= (0x4 << 23) | OPC_MSA_3R_11
,
1258 OPC_DIV_S_df
= (0x4 << 23) | OPC_MSA_3R_12
,
1259 OPC_DPSUB_S_df
= (0x4 << 23) | OPC_MSA_3R_13
,
1260 OPC_ILVL_df
= (0x4 << 23) | OPC_MSA_3R_14
,
1261 OPC_HADD_S_df
= (0x4 << 23) | OPC_MSA_3R_15
,
1262 OPC_BNEG_df
= (0x5 << 23) | OPC_MSA_3R_0D
,
1263 OPC_MIN_U_df
= (0x5 << 23) | OPC_MSA_3R_0E
,
1264 OPC_CLE_U_df
= (0x5 << 23) | OPC_MSA_3R_0F
,
1265 OPC_AVE_U_df
= (0x5 << 23) | OPC_MSA_3R_10
,
1266 OPC_ASUB_U_df
= (0x5 << 23) | OPC_MSA_3R_11
,
1267 OPC_DIV_U_df
= (0x5 << 23) | OPC_MSA_3R_12
,
1268 OPC_DPSUB_U_df
= (0x5 << 23) | OPC_MSA_3R_13
,
1269 OPC_ILVR_df
= (0x5 << 23) | OPC_MSA_3R_14
,
1270 OPC_HADD_U_df
= (0x5 << 23) | OPC_MSA_3R_15
,
1271 OPC_BINSL_df
= (0x6 << 23) | OPC_MSA_3R_0D
,
1272 OPC_MAX_A_df
= (0x6 << 23) | OPC_MSA_3R_0E
,
1273 OPC_AVER_S_df
= (0x6 << 23) | OPC_MSA_3R_10
,
1274 OPC_MOD_S_df
= (0x6 << 23) | OPC_MSA_3R_12
,
1275 OPC_ILVEV_df
= (0x6 << 23) | OPC_MSA_3R_14
,
1276 OPC_HSUB_S_df
= (0x6 << 23) | OPC_MSA_3R_15
,
1277 OPC_BINSR_df
= (0x7 << 23) | OPC_MSA_3R_0D
,
1278 OPC_MIN_A_df
= (0x7 << 23) | OPC_MSA_3R_0E
,
1279 OPC_AVER_U_df
= (0x7 << 23) | OPC_MSA_3R_10
,
1280 OPC_MOD_U_df
= (0x7 << 23) | OPC_MSA_3R_12
,
1281 OPC_ILVOD_df
= (0x7 << 23) | OPC_MSA_3R_14
,
1282 OPC_HSUB_U_df
= (0x7 << 23) | OPC_MSA_3R_15
,
1284 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
1285 OPC_SLDI_df
= (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1286 OPC_CTCMSA
= (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
1287 OPC_SPLATI_df
= (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1288 OPC_CFCMSA
= (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
1289 OPC_COPY_S_df
= (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1290 OPC_MOVE_V
= (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM
,
1291 OPC_COPY_U_df
= (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1292 OPC_INSERT_df
= (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1293 OPC_INSVE_df
= (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM
,
1295 /* 3RF instruction _df(bit 21) = _w, _d */
1296 OPC_FCAF_df
= (0x0 << 22) | OPC_MSA_3RF_1A
,
1297 OPC_FADD_df
= (0x0 << 22) | OPC_MSA_3RF_1B
,
1298 OPC_FCUN_df
= (0x1 << 22) | OPC_MSA_3RF_1A
,
1299 OPC_FSUB_df
= (0x1 << 22) | OPC_MSA_3RF_1B
,
1300 OPC_FCOR_df
= (0x1 << 22) | OPC_MSA_3RF_1C
,
1301 OPC_FCEQ_df
= (0x2 << 22) | OPC_MSA_3RF_1A
,
1302 OPC_FMUL_df
= (0x2 << 22) | OPC_MSA_3RF_1B
,
1303 OPC_FCUNE_df
= (0x2 << 22) | OPC_MSA_3RF_1C
,
1304 OPC_FCUEQ_df
= (0x3 << 22) | OPC_MSA_3RF_1A
,
1305 OPC_FDIV_df
= (0x3 << 22) | OPC_MSA_3RF_1B
,
1306 OPC_FCNE_df
= (0x3 << 22) | OPC_MSA_3RF_1C
,
1307 OPC_FCLT_df
= (0x4 << 22) | OPC_MSA_3RF_1A
,
1308 OPC_FMADD_df
= (0x4 << 22) | OPC_MSA_3RF_1B
,
1309 OPC_MUL_Q_df
= (0x4 << 22) | OPC_MSA_3RF_1C
,
1310 OPC_FCULT_df
= (0x5 << 22) | OPC_MSA_3RF_1A
,
1311 OPC_FMSUB_df
= (0x5 << 22) | OPC_MSA_3RF_1B
,
1312 OPC_MADD_Q_df
= (0x5 << 22) | OPC_MSA_3RF_1C
,
1313 OPC_FCLE_df
= (0x6 << 22) | OPC_MSA_3RF_1A
,
1314 OPC_MSUB_Q_df
= (0x6 << 22) | OPC_MSA_3RF_1C
,
1315 OPC_FCULE_df
= (0x7 << 22) | OPC_MSA_3RF_1A
,
1316 OPC_FEXP2_df
= (0x7 << 22) | OPC_MSA_3RF_1B
,
1317 OPC_FSAF_df
= (0x8 << 22) | OPC_MSA_3RF_1A
,
1318 OPC_FEXDO_df
= (0x8 << 22) | OPC_MSA_3RF_1B
,
1319 OPC_FSUN_df
= (0x9 << 22) | OPC_MSA_3RF_1A
,
1320 OPC_FSOR_df
= (0x9 << 22) | OPC_MSA_3RF_1C
,
1321 OPC_FSEQ_df
= (0xA << 22) | OPC_MSA_3RF_1A
,
1322 OPC_FTQ_df
= (0xA << 22) | OPC_MSA_3RF_1B
,
1323 OPC_FSUNE_df
= (0xA << 22) | OPC_MSA_3RF_1C
,
1324 OPC_FSUEQ_df
= (0xB << 22) | OPC_MSA_3RF_1A
,
1325 OPC_FSNE_df
= (0xB << 22) | OPC_MSA_3RF_1C
,
1326 OPC_FSLT_df
= (0xC << 22) | OPC_MSA_3RF_1A
,
1327 OPC_FMIN_df
= (0xC << 22) | OPC_MSA_3RF_1B
,
1328 OPC_MULR_Q_df
= (0xC << 22) | OPC_MSA_3RF_1C
,
1329 OPC_FSULT_df
= (0xD << 22) | OPC_MSA_3RF_1A
,
1330 OPC_FMIN_A_df
= (0xD << 22) | OPC_MSA_3RF_1B
,
1331 OPC_MADDR_Q_df
= (0xD << 22) | OPC_MSA_3RF_1C
,
1332 OPC_FSLE_df
= (0xE << 22) | OPC_MSA_3RF_1A
,
1333 OPC_FMAX_df
= (0xE << 22) | OPC_MSA_3RF_1B
,
1334 OPC_MSUBR_Q_df
= (0xE << 22) | OPC_MSA_3RF_1C
,
1335 OPC_FSULE_df
= (0xF << 22) | OPC_MSA_3RF_1A
,
1336 OPC_FMAX_A_df
= (0xF << 22) | OPC_MSA_3RF_1B
,
1338 /* BIT instruction df(bits 22..16) = _B _H _W _D */
1339 OPC_SLLI_df
= (0x0 << 23) | OPC_MSA_BIT_09
,
1340 OPC_SAT_S_df
= (0x0 << 23) | OPC_MSA_BIT_0A
,
1341 OPC_SRAI_df
= (0x1 << 23) | OPC_MSA_BIT_09
,
1342 OPC_SAT_U_df
= (0x1 << 23) | OPC_MSA_BIT_0A
,
1343 OPC_SRLI_df
= (0x2 << 23) | OPC_MSA_BIT_09
,
1344 OPC_SRARI_df
= (0x2 << 23) | OPC_MSA_BIT_0A
,
1345 OPC_BCLRI_df
= (0x3 << 23) | OPC_MSA_BIT_09
,
1346 OPC_SRLRI_df
= (0x3 << 23) | OPC_MSA_BIT_0A
,
1347 OPC_BSETI_df
= (0x4 << 23) | OPC_MSA_BIT_09
,
1348 OPC_BNEGI_df
= (0x5 << 23) | OPC_MSA_BIT_09
,
1349 OPC_BINSLI_df
= (0x6 << 23) | OPC_MSA_BIT_09
,
1350 OPC_BINSRI_df
= (0x7 << 23) | OPC_MSA_BIT_09
,
1353 /* global register indices */
1354 static TCGv_ptr cpu_env
;
1355 static TCGv cpu_gpr
[32], cpu_PC
;
1356 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
];
1357 static TCGv cpu_dspctrl
, btarget
, bcond
;
1358 static TCGv_i32 hflags
;
1359 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
1360 static TCGv_i64 fpu_f64
[32];
1361 static TCGv_i64 msa_wr_d
[64];
1363 static uint32_t gen_opc_hflags
[OPC_BUF_SIZE
];
1364 static target_ulong gen_opc_btarget
[OPC_BUF_SIZE
];
1366 #include "exec/gen-icount.h"
1368 #define gen_helper_0e0i(name, arg) do { \
1369 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
1370 gen_helper_##name(cpu_env, helper_tmp); \
1371 tcg_temp_free_i32(helper_tmp); \
1374 #define gen_helper_0e1i(name, arg1, arg2) do { \
1375 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1376 gen_helper_##name(cpu_env, arg1, helper_tmp); \
1377 tcg_temp_free_i32(helper_tmp); \
1380 #define gen_helper_1e0i(name, ret, arg1) do { \
1381 TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
1382 gen_helper_##name(ret, cpu_env, helper_tmp); \
1383 tcg_temp_free_i32(helper_tmp); \
1386 #define gen_helper_1e1i(name, ret, arg1, arg2) do { \
1387 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1388 gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
1389 tcg_temp_free_i32(helper_tmp); \
1392 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
1393 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1394 gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
1395 tcg_temp_free_i32(helper_tmp); \
1398 #define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
1399 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1400 gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
1401 tcg_temp_free_i32(helper_tmp); \
1404 #define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
1405 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
1406 gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
1407 tcg_temp_free_i32(helper_tmp); \
1410 typedef struct DisasContext
{
1411 struct TranslationBlock
*tb
;
1412 target_ulong pc
, saved_pc
;
1414 int singlestep_enabled
;
1416 int32_t CP0_Config1
;
1417 /* Routine used to access memory */
1419 TCGMemOp default_tcg_memop_mask
;
1420 uint32_t hflags
, saved_hflags
;
1422 target_ulong btarget
;
1431 int CP0_LLAddr_shift
;
1435 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
1436 * exception condition */
1437 BS_STOP
= 1, /* We want to stop translation for any reason */
1438 BS_BRANCH
= 2, /* We reached a branch condition */
1439 BS_EXCP
= 3, /* We reached an exception condition */
1442 static const char * const regnames
[] = {
1443 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
1449 static const char * const regnames_HI
[] = {
1450 "HI0", "HI1", "HI2", "HI3",
1453 static const char * const regnames_LO
[] = {
1454 "LO0", "LO1", "LO2", "LO3",
1457 static const char * const fregnames
[] = {
1458 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1459 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1460 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1461 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1464 static const char * const msaregnames
[] = {
1465 "w0.d0", "w0.d1", "w1.d0", "w1.d1",
1466 "w2.d0", "w2.d1", "w3.d0", "w3.d1",
1467 "w4.d0", "w4.d1", "w5.d0", "w5.d1",
1468 "w6.d0", "w6.d1", "w7.d0", "w7.d1",
1469 "w8.d0", "w8.d1", "w9.d0", "w9.d1",
1470 "w10.d0", "w10.d1", "w11.d0", "w11.d1",
1471 "w12.d0", "w12.d1", "w13.d0", "w13.d1",
1472 "w14.d0", "w14.d1", "w15.d0", "w15.d1",
1473 "w16.d0", "w16.d1", "w17.d0", "w17.d1",
1474 "w18.d0", "w18.d1", "w19.d0", "w19.d1",
1475 "w20.d0", "w20.d1", "w21.d0", "w21.d1",
1476 "w22.d0", "w22.d1", "w23.d0", "w23.d1",
1477 "w24.d0", "w24.d1", "w25.d0", "w25.d1",
1478 "w26.d0", "w26.d1", "w27.d0", "w27.d1",
1479 "w28.d0", "w28.d1", "w29.d0", "w29.d1",
1480 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
1483 #define MIPS_DEBUG(fmt, ...) \
1485 if (MIPS_DEBUG_DISAS) { \
1486 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
1487 TARGET_FMT_lx ": %08x " fmt "\n", \
1488 ctx->pc, ctx->opcode , ## __VA_ARGS__); \
1492 #define LOG_DISAS(...) \
1494 if (MIPS_DEBUG_DISAS) { \
1495 qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
1499 #define MIPS_INVAL(op) \
1500 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
1501 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F))
1503 /* General purpose registers moves. */
1504 static inline void gen_load_gpr (TCGv t
, int reg
)
1507 tcg_gen_movi_tl(t
, 0);
1509 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
1512 static inline void gen_store_gpr (TCGv t
, int reg
)
1515 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
1518 /* Moves to/from shadow registers. */
1519 static inline void gen_load_srsgpr (int from
, int to
)
1521 TCGv t0
= tcg_temp_new();
1524 tcg_gen_movi_tl(t0
, 0);
1526 TCGv_i32 t2
= tcg_temp_new_i32();
1527 TCGv_ptr addr
= tcg_temp_new_ptr();
1529 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
1530 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
1531 tcg_gen_andi_i32(t2
, t2
, 0xf);
1532 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
1533 tcg_gen_ext_i32_ptr(addr
, t2
);
1534 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
1536 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
1537 tcg_temp_free_ptr(addr
);
1538 tcg_temp_free_i32(t2
);
1540 gen_store_gpr(t0
, to
);
1544 static inline void gen_store_srsgpr (int from
, int to
)
1547 TCGv t0
= tcg_temp_new();
1548 TCGv_i32 t2
= tcg_temp_new_i32();
1549 TCGv_ptr addr
= tcg_temp_new_ptr();
1551 gen_load_gpr(t0
, from
);
1552 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
1553 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
1554 tcg_gen_andi_i32(t2
, t2
, 0xf);
1555 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
1556 tcg_gen_ext_i32_ptr(addr
, t2
);
1557 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
1559 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
1560 tcg_temp_free_ptr(addr
);
1561 tcg_temp_free_i32(t2
);
1567 static inline void gen_save_pc(target_ulong pc
)
1569 tcg_gen_movi_tl(cpu_PC
, pc
);
1572 static inline void save_cpu_state(DisasContext
*ctx
, int do_save_pc
)
1574 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
1575 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
1576 gen_save_pc(ctx
->pc
);
1577 ctx
->saved_pc
= ctx
->pc
;
1579 if (ctx
->hflags
!= ctx
->saved_hflags
) {
1580 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
1581 ctx
->saved_hflags
= ctx
->hflags
;
1582 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
1588 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
1594 static inline void restore_cpu_state(CPUMIPSState
*env
, DisasContext
*ctx
)
1596 ctx
->saved_hflags
= ctx
->hflags
;
1597 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
1603 ctx
->btarget
= env
->btarget
;
1608 static inline void generate_exception_err(DisasContext
*ctx
, int excp
, int err
)
1610 TCGv_i32 texcp
= tcg_const_i32(excp
);
1611 TCGv_i32 terr
= tcg_const_i32(err
);
1612 save_cpu_state(ctx
, 1);
1613 gen_helper_raise_exception_err(cpu_env
, texcp
, terr
);
1614 tcg_temp_free_i32(terr
);
1615 tcg_temp_free_i32(texcp
);
1618 static inline void generate_exception(DisasContext
*ctx
, int excp
)
1620 save_cpu_state(ctx
, 1);
1621 gen_helper_0e0i(raise_exception
, excp
);
1624 /* Floating point register moves. */
1625 static void gen_load_fpr32(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
1627 if (ctx
->hflags
& MIPS_HFLAG_FRE
) {
1628 generate_exception(ctx
, EXCP_RI
);
1630 tcg_gen_trunc_i64_i32(t
, fpu_f64
[reg
]);
1633 static void gen_store_fpr32(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
1636 if (ctx
->hflags
& MIPS_HFLAG_FRE
) {
1637 generate_exception(ctx
, EXCP_RI
);
1639 t64
= tcg_temp_new_i64();
1640 tcg_gen_extu_i32_i64(t64
, t
);
1641 tcg_gen_deposit_i64(fpu_f64
[reg
], fpu_f64
[reg
], t64
, 0, 32);
1642 tcg_temp_free_i64(t64
);
1645 static void gen_load_fpr32h(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
1647 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
1648 TCGv_i64 t64
= tcg_temp_new_i64();
1649 tcg_gen_shri_i64(t64
, fpu_f64
[reg
], 32);
1650 tcg_gen_trunc_i64_i32(t
, t64
);
1651 tcg_temp_free_i64(t64
);
1653 gen_load_fpr32(ctx
, t
, reg
| 1);
1657 static void gen_store_fpr32h(DisasContext
*ctx
, TCGv_i32 t
, int reg
)
1659 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
1660 TCGv_i64 t64
= tcg_temp_new_i64();
1661 tcg_gen_extu_i32_i64(t64
, t
);
1662 tcg_gen_deposit_i64(fpu_f64
[reg
], fpu_f64
[reg
], t64
, 32, 32);
1663 tcg_temp_free_i64(t64
);
1665 gen_store_fpr32(ctx
, t
, reg
| 1);
1669 static void gen_load_fpr64(DisasContext
*ctx
, TCGv_i64 t
, int reg
)
1671 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
1672 tcg_gen_mov_i64(t
, fpu_f64
[reg
]);
1674 tcg_gen_concat32_i64(t
, fpu_f64
[reg
& ~1], fpu_f64
[reg
| 1]);
1678 static void gen_store_fpr64(DisasContext
*ctx
, TCGv_i64 t
, int reg
)
1680 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
1681 tcg_gen_mov_i64(fpu_f64
[reg
], t
);
1684 tcg_gen_deposit_i64(fpu_f64
[reg
& ~1], fpu_f64
[reg
& ~1], t
, 0, 32);
1685 t0
= tcg_temp_new_i64();
1686 tcg_gen_shri_i64(t0
, t
, 32);
1687 tcg_gen_deposit_i64(fpu_f64
[reg
| 1], fpu_f64
[reg
| 1], t0
, 0, 32);
1688 tcg_temp_free_i64(t0
);
1692 static inline int get_fp_bit (int cc
)
1700 /* Addresses computation */
1701 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg0
, TCGv arg1
)
1703 tcg_gen_add_tl(ret
, arg0
, arg1
);
1705 #if defined(TARGET_MIPS64)
1706 if (ctx
->hflags
& MIPS_HFLAG_AWRAP
) {
1707 tcg_gen_ext32s_i64(ret
, ret
);
1712 /* Addresses computation (translation time) */
1713 static target_long
addr_add(DisasContext
*ctx
, target_long base
,
1716 target_long sum
= base
+ offset
;
1718 #if defined(TARGET_MIPS64)
1719 if (ctx
->hflags
& MIPS_HFLAG_AWRAP
) {
1726 static inline void check_cp0_enabled(DisasContext
*ctx
)
1728 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
1729 generate_exception_err(ctx
, EXCP_CpU
, 0);
1732 static inline void check_cp1_enabled(DisasContext
*ctx
)
1734 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
1735 generate_exception_err(ctx
, EXCP_CpU
, 1);
1738 /* Verify that the processor is running with COP1X instructions enabled.
1739 This is associated with the nabla symbol in the MIPS32 and MIPS64
1742 static inline void check_cop1x(DisasContext
*ctx
)
1744 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
1745 generate_exception(ctx
, EXCP_RI
);
1748 /* Verify that the processor is running with 64-bit floating-point
1749 operations enabled. */
1751 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
1753 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
1754 generate_exception(ctx
, EXCP_RI
);
1758 * Verify if floating point register is valid; an operation is not defined
1759 * if bit 0 of any register specification is set and the FR bit in the
1760 * Status register equals zero, since the register numbers specify an
1761 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1762 * in the Status register equals one, both even and odd register numbers
1763 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1765 * Multiple 64 bit wide registers can be checked by calling
1766 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1768 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
1770 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
1771 generate_exception(ctx
, EXCP_RI
);
1774 /* Verify that the processor is running with DSP instructions enabled.
1775 This is enabled by CP0 Status register MX(24) bit.
1778 static inline void check_dsp(DisasContext
*ctx
)
1780 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_DSP
))) {
1781 if (ctx
->insn_flags
& ASE_DSP
) {
1782 generate_exception(ctx
, EXCP_DSPDIS
);
1784 generate_exception(ctx
, EXCP_RI
);
1789 static inline void check_dspr2(DisasContext
*ctx
)
1791 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_DSPR2
))) {
1792 if (ctx
->insn_flags
& ASE_DSP
) {
1793 generate_exception(ctx
, EXCP_DSPDIS
);
1795 generate_exception(ctx
, EXCP_RI
);
1800 /* This code generates a "reserved instruction" exception if the
1801 CPU does not support the instruction set corresponding to flags. */
1802 static inline void check_insn(DisasContext
*ctx
, int flags
)
1804 if (unlikely(!(ctx
->insn_flags
& flags
))) {
1805 generate_exception(ctx
, EXCP_RI
);
1809 /* This code generates a "reserved instruction" exception if the
1810 CPU has corresponding flag set which indicates that the instruction
1811 has been removed. */
1812 static inline void check_insn_opc_removed(DisasContext
*ctx
, int flags
)
1814 if (unlikely(ctx
->insn_flags
& flags
)) {
1815 generate_exception(ctx
, EXCP_RI
);
1819 #ifdef TARGET_MIPS64
1820 /* This code generates a "reserved instruction" exception if 64-bit
1821 instructions are not enabled. */
1822 static inline void check_mips_64(DisasContext
*ctx
)
1824 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
1825 generate_exception(ctx
, EXCP_RI
);
1829 #ifndef CONFIG_USER_ONLY
1830 static inline void check_mvh(DisasContext
*ctx
)
1832 if (unlikely(!ctx
->mvh
)) {
1833 generate_exception(ctx
, EXCP_RI
);
1838 /* Define small wrappers for gen_load_fpr* so that we have a uniform
1839 calling interface for 32 and 64-bit FPRs. No sense in changing
1840 all callers for gen_load_fpr32 when we need the CTX parameter for
1842 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
1843 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
1844 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
1845 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
1846 int ft, int fs, int cc) \
1848 TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
1849 TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
1852 check_cp1_64bitmode(ctx); \
1858 check_cp1_registers(ctx, fs | ft); \
1866 gen_ldcmp_fpr##bits (ctx, fp0, fs); \
1867 gen_ldcmp_fpr##bits (ctx, fp1, ft); \
1869 case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
1870 case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
1871 case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
1872 case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
1873 case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
1874 case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
1875 case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
1876 case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
1877 case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
1878 case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
1879 case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
1880 case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
1881 case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
1882 case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
1883 case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
1884 case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
1887 tcg_temp_free_i##bits (fp0); \
1888 tcg_temp_free_i##bits (fp1); \
1891 FOP_CONDS(, 0, d
, FMT_D
, 64)
1892 FOP_CONDS(abs
, 1, d
, FMT_D
, 64)
1893 FOP_CONDS(, 0, s
, FMT_S
, 32)
1894 FOP_CONDS(abs
, 1, s
, FMT_S
, 32)
1895 FOP_CONDS(, 0, ps
, FMT_PS
, 64)
1896 FOP_CONDS(abs
, 1, ps
, FMT_PS
, 64)
1899 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
1900 static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
1901 int ft, int fs, int fd) \
1903 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
1904 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
1905 if (ifmt == FMT_D) { \
1906 check_cp1_registers(ctx, fs | ft | fd); \
1908 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
1909 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
1912 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
1915 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
1918 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
1921 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
1924 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
1927 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
1930 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
1933 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
1936 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
1939 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
1942 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
1945 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
1948 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
1951 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
1954 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
1957 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
1960 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
1963 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
1966 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
1969 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
1972 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
1975 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
1981 tcg_temp_free_i ## bits (fp0); \
1982 tcg_temp_free_i ## bits (fp1); \
1985 FOP_CONDNS(d
, FMT_D
, 64, gen_store_fpr64(ctx
, fp0
, fd
))
1986 FOP_CONDNS(s
, FMT_S
, 32, gen_store_fpr32(ctx
, fp0
, fd
))
1988 #undef gen_ldcmp_fpr32
1989 #undef gen_ldcmp_fpr64
1991 /* load/store instructions. */
1992 #ifdef CONFIG_USER_ONLY
1993 #define OP_LD_ATOMIC(insn,fname) \
1994 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
1996 TCGv t0 = tcg_temp_new(); \
1997 tcg_gen_mov_tl(t0, arg1); \
1998 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
1999 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2000 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
2001 tcg_temp_free(t0); \
2004 #define OP_LD_ATOMIC(insn,fname) \
2005 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
2007 gen_helper_1e1i(insn, ret, arg1, ctx->mem_idx); \
2010 OP_LD_ATOMIC(ll
,ld32s
);
2011 #if defined(TARGET_MIPS64)
2012 OP_LD_ATOMIC(lld
,ld64
);
2016 #ifdef CONFIG_USER_ONLY
2017 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
2018 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
2020 TCGv t0 = tcg_temp_new(); \
2021 TCGLabel *l1 = gen_new_label(); \
2022 TCGLabel *l2 = gen_new_label(); \
2024 tcg_gen_andi_tl(t0, arg2, almask); \
2025 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
2026 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \
2027 generate_exception(ctx, EXCP_AdES); \
2028 gen_set_label(l1); \
2029 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2030 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
2031 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
2032 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
2033 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
2034 gen_helper_0e0i(raise_exception, EXCP_SC); \
2035 gen_set_label(l2); \
2036 tcg_gen_movi_tl(t0, 0); \
2037 gen_store_gpr(t0, rt); \
2038 tcg_temp_free(t0); \
2041 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
2042 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
2044 TCGv t0 = tcg_temp_new(); \
2045 gen_helper_1e2i(insn, t0, arg1, arg2, ctx->mem_idx); \
2046 gen_store_gpr(t0, rt); \
2047 tcg_temp_free(t0); \
2050 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
2051 #if defined(TARGET_MIPS64)
2052 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
2056 static void gen_base_offset_addr (DisasContext
*ctx
, TCGv addr
,
2057 int base
, int16_t offset
)
2060 tcg_gen_movi_tl(addr
, offset
);
2061 } else if (offset
== 0) {
2062 gen_load_gpr(addr
, base
);
2064 tcg_gen_movi_tl(addr
, offset
);
2065 gen_op_addr_add(ctx
, addr
, cpu_gpr
[base
], addr
);
2069 static target_ulong
pc_relative_pc (DisasContext
*ctx
)
2071 target_ulong pc
= ctx
->pc
;
2073 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2074 int branch_bytes
= ctx
->hflags
& MIPS_HFLAG_BDS16
? 2 : 4;
2079 pc
&= ~(target_ulong
)3;
2084 static void gen_ld(DisasContext
*ctx
, uint32_t opc
,
2085 int rt
, int base
, int16_t offset
)
2087 const char *opn
= "ld";
2090 if (rt
== 0 && ctx
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)) {
2091 /* Loongson CPU uses a load to zero register for prefetch.
2092 We emulate it as a NOP. On other CPU we must perform the
2093 actual memory access. */
2098 t0
= tcg_temp_new();
2099 gen_base_offset_addr(ctx
, t0
, base
, offset
);
2102 #if defined(TARGET_MIPS64)
2104 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEUL
|
2105 ctx
->default_tcg_memop_mask
);
2106 gen_store_gpr(t0
, rt
);
2110 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEQ
|
2111 ctx
->default_tcg_memop_mask
);
2112 gen_store_gpr(t0
, rt
);
2117 save_cpu_state(ctx
, 1);
2118 op_ld_lld(t0
, t0
, ctx
);
2119 gen_store_gpr(t0
, rt
);
2123 t1
= tcg_temp_new();
2124 tcg_gen_andi_tl(t1
, t0
, 7);
2125 #ifndef TARGET_WORDS_BIGENDIAN
2126 tcg_gen_xori_tl(t1
, t1
, 7);
2128 tcg_gen_shli_tl(t1
, t1
, 3);
2129 tcg_gen_andi_tl(t0
, t0
, ~7);
2130 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEQ
);
2131 tcg_gen_shl_tl(t0
, t0
, t1
);
2132 tcg_gen_xori_tl(t1
, t1
, 63);
2133 t2
= tcg_const_tl(0x7fffffffffffffffull
);
2134 tcg_gen_shr_tl(t2
, t2
, t1
);
2135 gen_load_gpr(t1
, rt
);
2136 tcg_gen_and_tl(t1
, t1
, t2
);
2138 tcg_gen_or_tl(t0
, t0
, t1
);
2140 gen_store_gpr(t0
, rt
);
2144 t1
= tcg_temp_new();
2145 tcg_gen_andi_tl(t1
, t0
, 7);
2146 #ifdef TARGET_WORDS_BIGENDIAN
2147 tcg_gen_xori_tl(t1
, t1
, 7);
2149 tcg_gen_shli_tl(t1
, t1
, 3);
2150 tcg_gen_andi_tl(t0
, t0
, ~7);
2151 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEQ
);
2152 tcg_gen_shr_tl(t0
, t0
, t1
);
2153 tcg_gen_xori_tl(t1
, t1
, 63);
2154 t2
= tcg_const_tl(0xfffffffffffffffeull
);
2155 tcg_gen_shl_tl(t2
, t2
, t1
);
2156 gen_load_gpr(t1
, rt
);
2157 tcg_gen_and_tl(t1
, t1
, t2
);
2159 tcg_gen_or_tl(t0
, t0
, t1
);
2161 gen_store_gpr(t0
, rt
);
2165 t1
= tcg_const_tl(pc_relative_pc(ctx
));
2166 gen_op_addr_add(ctx
, t0
, t0
, t1
);
2168 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEQ
);
2169 gen_store_gpr(t0
, rt
);
2174 t1
= tcg_const_tl(pc_relative_pc(ctx
));
2175 gen_op_addr_add(ctx
, t0
, t0
, t1
);
2177 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESL
);
2178 gen_store_gpr(t0
, rt
);
2182 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESL
|
2183 ctx
->default_tcg_memop_mask
);
2184 gen_store_gpr(t0
, rt
);
2188 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESW
|
2189 ctx
->default_tcg_memop_mask
);
2190 gen_store_gpr(t0
, rt
);
2194 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEUW
|
2195 ctx
->default_tcg_memop_mask
);
2196 gen_store_gpr(t0
, rt
);
2200 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_SB
);
2201 gen_store_gpr(t0
, rt
);
2205 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_UB
);
2206 gen_store_gpr(t0
, rt
);
2210 t1
= tcg_temp_new();
2211 tcg_gen_andi_tl(t1
, t0
, 3);
2212 #ifndef TARGET_WORDS_BIGENDIAN
2213 tcg_gen_xori_tl(t1
, t1
, 3);
2215 tcg_gen_shli_tl(t1
, t1
, 3);
2216 tcg_gen_andi_tl(t0
, t0
, ~3);
2217 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEUL
);
2218 tcg_gen_shl_tl(t0
, t0
, t1
);
2219 tcg_gen_xori_tl(t1
, t1
, 31);
2220 t2
= tcg_const_tl(0x7fffffffull
);
2221 tcg_gen_shr_tl(t2
, t2
, t1
);
2222 gen_load_gpr(t1
, rt
);
2223 tcg_gen_and_tl(t1
, t1
, t2
);
2225 tcg_gen_or_tl(t0
, t0
, t1
);
2227 tcg_gen_ext32s_tl(t0
, t0
);
2228 gen_store_gpr(t0
, rt
);
2232 t1
= tcg_temp_new();
2233 tcg_gen_andi_tl(t1
, t0
, 3);
2234 #ifdef TARGET_WORDS_BIGENDIAN
2235 tcg_gen_xori_tl(t1
, t1
, 3);
2237 tcg_gen_shli_tl(t1
, t1
, 3);
2238 tcg_gen_andi_tl(t0
, t0
, ~3);
2239 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEUL
);
2240 tcg_gen_shr_tl(t0
, t0
, t1
);
2241 tcg_gen_xori_tl(t1
, t1
, 31);
2242 t2
= tcg_const_tl(0xfffffffeull
);
2243 tcg_gen_shl_tl(t2
, t2
, t1
);
2244 gen_load_gpr(t1
, rt
);
2245 tcg_gen_and_tl(t1
, t1
, t2
);
2247 tcg_gen_or_tl(t0
, t0
, t1
);
2249 tcg_gen_ext32s_tl(t0
, t0
);
2250 gen_store_gpr(t0
, rt
);
2255 save_cpu_state(ctx
, 1);
2256 op_ld_ll(t0
, t0
, ctx
);
2257 gen_store_gpr(t0
, rt
);
2261 (void)opn
; /* avoid a compiler warning */
2262 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
2267 static void gen_st (DisasContext
*ctx
, uint32_t opc
, int rt
,
2268 int base
, int16_t offset
)
2270 const char *opn
= "st";
2271 TCGv t0
= tcg_temp_new();
2272 TCGv t1
= tcg_temp_new();
2274 gen_base_offset_addr(ctx
, t0
, base
, offset
);
2275 gen_load_gpr(t1
, rt
);
2277 #if defined(TARGET_MIPS64)
2279 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
|
2280 ctx
->default_tcg_memop_mask
);
2284 save_cpu_state(ctx
, 1);
2285 gen_helper_0e2i(sdl
, t1
, t0
, ctx
->mem_idx
);
2289 save_cpu_state(ctx
, 1);
2290 gen_helper_0e2i(sdr
, t1
, t0
, ctx
->mem_idx
);
2295 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
|
2296 ctx
->default_tcg_memop_mask
);
2300 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUW
|
2301 ctx
->default_tcg_memop_mask
);
2305 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_8
);
2309 save_cpu_state(ctx
, 1);
2310 gen_helper_0e2i(swl
, t1
, t0
, ctx
->mem_idx
);
2314 save_cpu_state(ctx
, 1);
2315 gen_helper_0e2i(swr
, t1
, t0
, ctx
->mem_idx
);
2319 (void)opn
; /* avoid a compiler warning */
2320 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
2326 /* Store conditional */
2327 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
2328 int base
, int16_t offset
)
2330 const char *opn
= "st_cond";
2333 #ifdef CONFIG_USER_ONLY
2334 t0
= tcg_temp_local_new();
2335 t1
= tcg_temp_local_new();
2337 t0
= tcg_temp_new();
2338 t1
= tcg_temp_new();
2340 gen_base_offset_addr(ctx
, t0
, base
, offset
);
2341 gen_load_gpr(t1
, rt
);
2343 #if defined(TARGET_MIPS64)
2346 save_cpu_state(ctx
, 1);
2347 op_st_scd(t1
, t0
, rt
, ctx
);
2353 save_cpu_state(ctx
, 1);
2354 op_st_sc(t1
, t0
, rt
, ctx
);
2358 (void)opn
; /* avoid a compiler warning */
2359 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
2364 /* Load and store */
2365 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
2366 int base
, int16_t offset
)
2368 const char *opn
= "flt_ldst";
2369 TCGv t0
= tcg_temp_new();
2371 gen_base_offset_addr(ctx
, t0
, base
, offset
);
2372 /* Don't do NOP if destination is zero: we must perform the actual
2377 TCGv_i32 fp0
= tcg_temp_new_i32();
2378 tcg_gen_qemu_ld_i32(fp0
, t0
, ctx
->mem_idx
, MO_TESL
|
2379 ctx
->default_tcg_memop_mask
);
2380 gen_store_fpr32(ctx
, fp0
, ft
);
2381 tcg_temp_free_i32(fp0
);
2387 TCGv_i32 fp0
= tcg_temp_new_i32();
2388 gen_load_fpr32(ctx
, fp0
, ft
);
2389 tcg_gen_qemu_st_i32(fp0
, t0
, ctx
->mem_idx
, MO_TEUL
|
2390 ctx
->default_tcg_memop_mask
);
2391 tcg_temp_free_i32(fp0
);
2397 TCGv_i64 fp0
= tcg_temp_new_i64();
2398 tcg_gen_qemu_ld_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
|
2399 ctx
->default_tcg_memop_mask
);
2400 gen_store_fpr64(ctx
, fp0
, ft
);
2401 tcg_temp_free_i64(fp0
);
2407 TCGv_i64 fp0
= tcg_temp_new_i64();
2408 gen_load_fpr64(ctx
, fp0
, ft
);
2409 tcg_gen_qemu_st_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
|
2410 ctx
->default_tcg_memop_mask
);
2411 tcg_temp_free_i64(fp0
);
2417 generate_exception(ctx
, EXCP_RI
);
2420 (void)opn
; /* avoid a compiler warning */
2421 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
2426 static void gen_cop1_ldst(DisasContext
*ctx
, uint32_t op
, int rt
,
2427 int rs
, int16_t imm
)
2429 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
2430 check_cp1_enabled(ctx
);
2434 check_insn(ctx
, ISA_MIPS2
);
2437 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
2440 generate_exception_err(ctx
, EXCP_CpU
, 1);
2444 /* Arithmetic with immediate operand */
2445 static void gen_arith_imm(DisasContext
*ctx
, uint32_t opc
,
2446 int rt
, int rs
, int16_t imm
)
2448 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
2449 const char *opn
= "imm arith";
2451 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
2452 /* If no destination, treat it as a NOP.
2453 For addi, we must generate the overflow exception when needed. */
2460 TCGv t0
= tcg_temp_local_new();
2461 TCGv t1
= tcg_temp_new();
2462 TCGv t2
= tcg_temp_new();
2463 TCGLabel
*l1
= gen_new_label();
2465 gen_load_gpr(t1
, rs
);
2466 tcg_gen_addi_tl(t0
, t1
, uimm
);
2467 tcg_gen_ext32s_tl(t0
, t0
);
2469 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
2470 tcg_gen_xori_tl(t2
, t0
, uimm
);
2471 tcg_gen_and_tl(t1
, t1
, t2
);
2473 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
2475 /* operands of same sign, result different sign */
2476 generate_exception(ctx
, EXCP_OVERFLOW
);
2478 tcg_gen_ext32s_tl(t0
, t0
);
2479 gen_store_gpr(t0
, rt
);
2486 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
2487 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
2489 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
2493 #if defined(TARGET_MIPS64)
2496 TCGv t0
= tcg_temp_local_new();
2497 TCGv t1
= tcg_temp_new();
2498 TCGv t2
= tcg_temp_new();
2499 TCGLabel
*l1
= gen_new_label();
2501 gen_load_gpr(t1
, rs
);
2502 tcg_gen_addi_tl(t0
, t1
, uimm
);
2504 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
2505 tcg_gen_xori_tl(t2
, t0
, uimm
);
2506 tcg_gen_and_tl(t1
, t1
, t2
);
2508 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
2510 /* operands of same sign, result different sign */
2511 generate_exception(ctx
, EXCP_OVERFLOW
);
2513 gen_store_gpr(t0
, rt
);
2520 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
2522 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
2528 (void)opn
; /* avoid a compiler warning */
2529 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
2532 /* Logic with immediate operand */
2533 static void gen_logic_imm(DisasContext
*ctx
, uint32_t opc
,
2534 int rt
, int rs
, int16_t imm
)
2539 /* If no destination, treat it as a NOP. */
2543 uimm
= (uint16_t)imm
;
2546 if (likely(rs
!= 0))
2547 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
2549 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
2550 MIPS_DEBUG("andi %s, %s, " TARGET_FMT_lx
, regnames
[rt
],
2551 regnames
[rs
], uimm
);
2555 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
2557 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
2558 MIPS_DEBUG("ori %s, %s, " TARGET_FMT_lx
, regnames
[rt
],
2559 regnames
[rs
], uimm
);
2562 if (likely(rs
!= 0))
2563 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
2565 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
2566 MIPS_DEBUG("xori %s, %s, " TARGET_FMT_lx
, regnames
[rt
],
2567 regnames
[rs
], uimm
);
2570 if (rs
!= 0 && (ctx
->insn_flags
& ISA_MIPS32R6
)) {
2572 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], imm
<< 16);
2573 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
2574 MIPS_DEBUG("aui %s, %s, %04x", regnames
[rt
], regnames
[rs
], imm
);
2576 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
2577 MIPS_DEBUG("lui %s, " TARGET_FMT_lx
, regnames
[rt
], uimm
);
2582 MIPS_DEBUG("Unknown logical immediate opcode %08x", opc
);
2587 /* Set on less than with immediate operand */
2588 static void gen_slt_imm(DisasContext
*ctx
, uint32_t opc
,
2589 int rt
, int rs
, int16_t imm
)
2591 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
2592 const char *opn
= "imm arith";
2596 /* If no destination, treat it as a NOP. */
2600 t0
= tcg_temp_new();
2601 gen_load_gpr(t0
, rs
);
2604 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr
[rt
], t0
, uimm
);
2608 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr
[rt
], t0
, uimm
);
2612 (void)opn
; /* avoid a compiler warning */
2613 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
2617 /* Shifts with immediate operand */
2618 static void gen_shift_imm(DisasContext
*ctx
, uint32_t opc
,
2619 int rt
, int rs
, int16_t imm
)
2621 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
2622 const char *opn
= "imm shift";
2626 /* If no destination, treat it as a NOP. */
2631 t0
= tcg_temp_new();
2632 gen_load_gpr(t0
, rs
);
2635 tcg_gen_shli_tl(t0
, t0
, uimm
);
2636 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
2640 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
2645 tcg_gen_ext32u_tl(t0
, t0
);
2646 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
2648 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
2654 TCGv_i32 t1
= tcg_temp_new_i32();
2656 tcg_gen_trunc_tl_i32(t1
, t0
);
2657 tcg_gen_rotri_i32(t1
, t1
, uimm
);
2658 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
2659 tcg_temp_free_i32(t1
);
2661 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
2665 #if defined(TARGET_MIPS64)
2667 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
2671 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
2675 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
2680 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
2682 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
2687 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
2691 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
2695 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
2699 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
2704 (void)opn
; /* avoid a compiler warning */
2705 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
2710 static void gen_arith(DisasContext
*ctx
, uint32_t opc
,
2711 int rd
, int rs
, int rt
)
2713 const char *opn
= "arith";
2715 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
2716 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
2717 /* If no destination, treat it as a NOP.
2718 For add & sub, we must generate the overflow exception when needed. */
2726 TCGv t0
= tcg_temp_local_new();
2727 TCGv t1
= tcg_temp_new();
2728 TCGv t2
= tcg_temp_new();
2729 TCGLabel
*l1
= gen_new_label();
2731 gen_load_gpr(t1
, rs
);
2732 gen_load_gpr(t2
, rt
);
2733 tcg_gen_add_tl(t0
, t1
, t2
);
2734 tcg_gen_ext32s_tl(t0
, t0
);
2735 tcg_gen_xor_tl(t1
, t1
, t2
);
2736 tcg_gen_xor_tl(t2
, t0
, t2
);
2737 tcg_gen_andc_tl(t1
, t2
, t1
);
2739 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
2741 /* operands of same sign, result different sign */
2742 generate_exception(ctx
, EXCP_OVERFLOW
);
2744 gen_store_gpr(t0
, rd
);
2750 if (rs
!= 0 && rt
!= 0) {
2751 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2752 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2753 } else if (rs
== 0 && rt
!= 0) {
2754 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2755 } else if (rs
!= 0 && rt
== 0) {
2756 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2758 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2764 TCGv t0
= tcg_temp_local_new();
2765 TCGv t1
= tcg_temp_new();
2766 TCGv t2
= tcg_temp_new();
2767 TCGLabel
*l1
= gen_new_label();
2769 gen_load_gpr(t1
, rs
);
2770 gen_load_gpr(t2
, rt
);
2771 tcg_gen_sub_tl(t0
, t1
, t2
);
2772 tcg_gen_ext32s_tl(t0
, t0
);
2773 tcg_gen_xor_tl(t2
, t1
, t2
);
2774 tcg_gen_xor_tl(t1
, t0
, t1
);
2775 tcg_gen_and_tl(t1
, t1
, t2
);
2777 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
2779 /* operands of different sign, first operand and result different sign */
2780 generate_exception(ctx
, EXCP_OVERFLOW
);
2782 gen_store_gpr(t0
, rd
);
2788 if (rs
!= 0 && rt
!= 0) {
2789 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2790 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2791 } else if (rs
== 0 && rt
!= 0) {
2792 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2793 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2794 } else if (rs
!= 0 && rt
== 0) {
2795 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2797 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2801 #if defined(TARGET_MIPS64)
2804 TCGv t0
= tcg_temp_local_new();
2805 TCGv t1
= tcg_temp_new();
2806 TCGv t2
= tcg_temp_new();
2807 TCGLabel
*l1
= gen_new_label();
2809 gen_load_gpr(t1
, rs
);
2810 gen_load_gpr(t2
, rt
);
2811 tcg_gen_add_tl(t0
, t1
, t2
);
2812 tcg_gen_xor_tl(t1
, t1
, t2
);
2813 tcg_gen_xor_tl(t2
, t0
, t2
);
2814 tcg_gen_andc_tl(t1
, t2
, t1
);
2816 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
2818 /* operands of same sign, result different sign */
2819 generate_exception(ctx
, EXCP_OVERFLOW
);
2821 gen_store_gpr(t0
, rd
);
2827 if (rs
!= 0 && rt
!= 0) {
2828 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2829 } else if (rs
== 0 && rt
!= 0) {
2830 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2831 } else if (rs
!= 0 && rt
== 0) {
2832 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2834 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2840 TCGv t0
= tcg_temp_local_new();
2841 TCGv t1
= tcg_temp_new();
2842 TCGv t2
= tcg_temp_new();
2843 TCGLabel
*l1
= gen_new_label();
2845 gen_load_gpr(t1
, rs
);
2846 gen_load_gpr(t2
, rt
);
2847 tcg_gen_sub_tl(t0
, t1
, t2
);
2848 tcg_gen_xor_tl(t2
, t1
, t2
);
2849 tcg_gen_xor_tl(t1
, t0
, t1
);
2850 tcg_gen_and_tl(t1
, t1
, t2
);
2852 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
2854 /* operands of different sign, first operand and result different sign */
2855 generate_exception(ctx
, EXCP_OVERFLOW
);
2857 gen_store_gpr(t0
, rd
);
2863 if (rs
!= 0 && rt
!= 0) {
2864 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2865 } else if (rs
== 0 && rt
!= 0) {
2866 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2867 } else if (rs
!= 0 && rt
== 0) {
2868 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2870 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2876 if (likely(rs
!= 0 && rt
!= 0)) {
2877 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2878 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2880 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2885 (void)opn
; /* avoid a compiler warning */
2886 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2889 /* Conditional move */
2890 static void gen_cond_move(DisasContext
*ctx
, uint32_t opc
,
2891 int rd
, int rs
, int rt
)
2893 const char *opn
= "cond move";
2897 /* If no destination, treat it as a NOP. */
2902 t0
= tcg_temp_new();
2903 gen_load_gpr(t0
, rt
);
2904 t1
= tcg_const_tl(0);
2905 t2
= tcg_temp_new();
2906 gen_load_gpr(t2
, rs
);
2909 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rd
], t0
, t1
, t2
, cpu_gpr
[rd
]);
2913 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr
[rd
], t0
, t1
, t2
, cpu_gpr
[rd
]);
2917 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rd
], t0
, t1
, t2
, t1
);
2921 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr
[rd
], t0
, t1
, t2
, t1
);
2929 (void)opn
; /* avoid a compiler warning */
2930 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2934 static void gen_logic(DisasContext
*ctx
, uint32_t opc
,
2935 int rd
, int rs
, int rt
)
2937 const char *opn
= "logic";
2940 /* If no destination, treat it as a NOP. */
2947 if (likely(rs
!= 0 && rt
!= 0)) {
2948 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2950 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2955 if (rs
!= 0 && rt
!= 0) {
2956 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2957 } else if (rs
== 0 && rt
!= 0) {
2958 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2959 } else if (rs
!= 0 && rt
== 0) {
2960 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2962 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
2967 if (likely(rs
!= 0 && rt
!= 0)) {
2968 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2969 } else if (rs
== 0 && rt
!= 0) {
2970 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2971 } else if (rs
!= 0 && rt
== 0) {
2972 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2974 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2979 if (likely(rs
!= 0 && rt
!= 0)) {
2980 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
2981 } else if (rs
== 0 && rt
!= 0) {
2982 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
2983 } else if (rs
!= 0 && rt
== 0) {
2984 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
2986 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2991 (void)opn
; /* avoid a compiler warning */
2992 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2995 /* Set on lower than */
2996 static void gen_slt(DisasContext
*ctx
, uint32_t opc
,
2997 int rd
, int rs
, int rt
)
2999 const char *opn
= "slt";
3003 /* If no destination, treat it as a NOP. */
3008 t0
= tcg_temp_new();
3009 t1
= tcg_temp_new();
3010 gen_load_gpr(t0
, rs
);
3011 gen_load_gpr(t1
, rt
);
3014 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr
[rd
], t0
, t1
);
3018 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr
[rd
], t0
, t1
);
3022 (void)opn
; /* avoid a compiler warning */
3023 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
3029 static void gen_shift(DisasContext
*ctx
, uint32_t opc
,
3030 int rd
, int rs
, int rt
)
3032 const char *opn
= "shifts";
3036 /* If no destination, treat it as a NOP.
3037 For add & sub, we must generate the overflow exception when needed. */
3042 t0
= tcg_temp_new();
3043 t1
= tcg_temp_new();
3044 gen_load_gpr(t0
, rs
);
3045 gen_load_gpr(t1
, rt
);
3048 tcg_gen_andi_tl(t0
, t0
, 0x1f);
3049 tcg_gen_shl_tl(t0
, t1
, t0
);
3050 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
3054 tcg_gen_andi_tl(t0
, t0
, 0x1f);
3055 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
3059 tcg_gen_ext32u_tl(t1
, t1
);
3060 tcg_gen_andi_tl(t0
, t0
, 0x1f);
3061 tcg_gen_shr_tl(t0
, t1
, t0
);
3062 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
3067 TCGv_i32 t2
= tcg_temp_new_i32();
3068 TCGv_i32 t3
= tcg_temp_new_i32();
3070 tcg_gen_trunc_tl_i32(t2
, t0
);
3071 tcg_gen_trunc_tl_i32(t3
, t1
);
3072 tcg_gen_andi_i32(t2
, t2
, 0x1f);
3073 tcg_gen_rotr_i32(t2
, t3
, t2
);
3074 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
3075 tcg_temp_free_i32(t2
);
3076 tcg_temp_free_i32(t3
);
3080 #if defined(TARGET_MIPS64)
3082 tcg_gen_andi_tl(t0
, t0
, 0x3f);
3083 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
3087 tcg_gen_andi_tl(t0
, t0
, 0x3f);
3088 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
3092 tcg_gen_andi_tl(t0
, t0
, 0x3f);
3093 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
3097 tcg_gen_andi_tl(t0
, t0
, 0x3f);
3098 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
3103 (void)opn
; /* avoid a compiler warning */
3104 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
3109 /* Arithmetic on HI/LO registers */
3110 static void gen_HILO(DisasContext
*ctx
, uint32_t opc
, int acc
, int reg
)
3112 const char *opn
= "hilo";
3114 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
3126 #if defined(TARGET_MIPS64)
3128 tcg_gen_ext32s_tl(cpu_gpr
[reg
], cpu_HI
[acc
]);
3132 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[acc
]);
3137 #if defined(TARGET_MIPS64)
3139 tcg_gen_ext32s_tl(cpu_gpr
[reg
], cpu_LO
[acc
]);
3143 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[acc
]);
3149 #if defined(TARGET_MIPS64)
3151 tcg_gen_ext32s_tl(cpu_HI
[acc
], cpu_gpr
[reg
]);
3155 tcg_gen_mov_tl(cpu_HI
[acc
], cpu_gpr
[reg
]);
3158 tcg_gen_movi_tl(cpu_HI
[acc
], 0);
3164 #if defined(TARGET_MIPS64)
3166 tcg_gen_ext32s_tl(cpu_LO
[acc
], cpu_gpr
[reg
]);
3170 tcg_gen_mov_tl(cpu_LO
[acc
], cpu_gpr
[reg
]);
3173 tcg_gen_movi_tl(cpu_LO
[acc
], 0);
3178 (void)opn
; /* avoid a compiler warning */
3179 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
3182 static inline void gen_r6_ld(target_long addr
, int reg
, int memidx
,
3185 TCGv t0
= tcg_const_tl(addr
);
3186 tcg_gen_qemu_ld_tl(t0
, t0
, memidx
, memop
);
3187 gen_store_gpr(t0
, reg
);
3191 static inline void gen_pcrel(DisasContext
*ctx
, int rs
, int16_t imm
)
3196 switch (MASK_OPC_PCREL_TOP2BITS(ctx
->opcode
)) {
3199 offset
= sextract32(ctx
->opcode
<< 2, 0, 21);
3200 addr
= addr_add(ctx
, ctx
->pc
, offset
);
3201 tcg_gen_movi_tl(cpu_gpr
[rs
], addr
);
3205 offset
= sextract32(ctx
->opcode
<< 2, 0, 21);
3206 addr
= addr_add(ctx
, ctx
->pc
, offset
);
3207 gen_r6_ld(addr
, rs
, ctx
->mem_idx
, MO_TESL
);
3209 #if defined(TARGET_MIPS64)
3212 offset
= sextract32(ctx
->opcode
<< 2, 0, 21);
3213 addr
= addr_add(ctx
, ctx
->pc
, offset
);
3214 gen_r6_ld(addr
, rs
, ctx
->mem_idx
, MO_TEUL
);
3218 switch (MASK_OPC_PCREL_TOP5BITS(ctx
->opcode
)) {
3222 addr
= addr_add(ctx
, ctx
->pc
, offset
);
3223 tcg_gen_movi_tl(cpu_gpr
[rs
], addr
);
3229 addr
= ~0xFFFF & addr_add(ctx
, ctx
->pc
, offset
);
3230 tcg_gen_movi_tl(cpu_gpr
[rs
], addr
);
3233 #if defined(TARGET_MIPS64)
3234 case R6_OPC_LDPC
: /* bits 16 and 17 are part of immediate */
3235 case R6_OPC_LDPC
+ (1 << 16):
3236 case R6_OPC_LDPC
+ (2 << 16):
3237 case R6_OPC_LDPC
+ (3 << 16):
3239 offset
= sextract32(ctx
->opcode
<< 3, 0, 21);
3240 addr
= addr_add(ctx
, (ctx
->pc
& ~0x7), offset
);
3241 gen_r6_ld(addr
, rs
, ctx
->mem_idx
, MO_TEQ
);
3245 MIPS_INVAL("OPC_PCREL");
3246 generate_exception(ctx
, EXCP_RI
);
3253 static void gen_r6_muldiv(DisasContext
*ctx
, int opc
, int rd
, int rs
, int rt
)
3255 const char *opn
= "r6 mul/div";
3264 t0
= tcg_temp_new();
3265 t1
= tcg_temp_new();
3267 gen_load_gpr(t0
, rs
);
3268 gen_load_gpr(t1
, rt
);
3273 TCGv t2
= tcg_temp_new();
3274 TCGv t3
= tcg_temp_new();
3275 tcg_gen_ext32s_tl(t0
, t0
);
3276 tcg_gen_ext32s_tl(t1
, t1
);
3277 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
3278 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
3279 tcg_gen_and_tl(t2
, t2
, t3
);
3280 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
3281 tcg_gen_or_tl(t2
, t2
, t3
);
3282 tcg_gen_movi_tl(t3
, 0);
3283 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
3284 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
3285 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3293 TCGv t2
= tcg_temp_new();
3294 TCGv t3
= tcg_temp_new();
3295 tcg_gen_ext32s_tl(t0
, t0
);
3296 tcg_gen_ext32s_tl(t1
, t1
);
3297 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
3298 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
3299 tcg_gen_and_tl(t2
, t2
, t3
);
3300 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
3301 tcg_gen_or_tl(t2
, t2
, t3
);
3302 tcg_gen_movi_tl(t3
, 0);
3303 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
3304 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
3305 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3313 TCGv t2
= tcg_const_tl(0);
3314 TCGv t3
= tcg_const_tl(1);
3315 tcg_gen_ext32u_tl(t0
, t0
);
3316 tcg_gen_ext32u_tl(t1
, t1
);
3317 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
3318 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
3319 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3327 TCGv t2
= tcg_const_tl(0);
3328 TCGv t3
= tcg_const_tl(1);
3329 tcg_gen_ext32u_tl(t0
, t0
);
3330 tcg_gen_ext32u_tl(t1
, t1
);
3331 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
3332 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
3333 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3341 TCGv_i32 t2
= tcg_temp_new_i32();
3342 TCGv_i32 t3
= tcg_temp_new_i32();
3343 tcg_gen_trunc_tl_i32(t2
, t0
);
3344 tcg_gen_trunc_tl_i32(t3
, t1
);
3345 tcg_gen_mul_i32(t2
, t2
, t3
);
3346 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
3347 tcg_temp_free_i32(t2
);
3348 tcg_temp_free_i32(t3
);
3354 TCGv_i32 t2
= tcg_temp_new_i32();
3355 TCGv_i32 t3
= tcg_temp_new_i32();
3356 tcg_gen_trunc_tl_i32(t2
, t0
);
3357 tcg_gen_trunc_tl_i32(t3
, t1
);
3358 tcg_gen_muls2_i32(t2
, t3
, t2
, t3
);
3359 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t3
);
3360 tcg_temp_free_i32(t2
);
3361 tcg_temp_free_i32(t3
);
3367 TCGv_i32 t2
= tcg_temp_new_i32();
3368 TCGv_i32 t3
= tcg_temp_new_i32();
3369 tcg_gen_trunc_tl_i32(t2
, t0
);
3370 tcg_gen_trunc_tl_i32(t3
, t1
);
3371 tcg_gen_mul_i32(t2
, t2
, t3
);
3372 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
3373 tcg_temp_free_i32(t2
);
3374 tcg_temp_free_i32(t3
);
3380 TCGv_i32 t2
= tcg_temp_new_i32();
3381 TCGv_i32 t3
= tcg_temp_new_i32();
3382 tcg_gen_trunc_tl_i32(t2
, t0
);
3383 tcg_gen_trunc_tl_i32(t3
, t1
);
3384 tcg_gen_mulu2_i32(t2
, t3
, t2
, t3
);
3385 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t3
);
3386 tcg_temp_free_i32(t2
);
3387 tcg_temp_free_i32(t3
);
3391 #if defined(TARGET_MIPS64)
3394 TCGv t2
= tcg_temp_new();
3395 TCGv t3
= tcg_temp_new();
3396 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, -1LL << 63);
3397 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1LL);
3398 tcg_gen_and_tl(t2
, t2
, t3
);
3399 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
3400 tcg_gen_or_tl(t2
, t2
, t3
);
3401 tcg_gen_movi_tl(t3
, 0);
3402 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
3403 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
3411 TCGv t2
= tcg_temp_new();
3412 TCGv t3
= tcg_temp_new();
3413 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, -1LL << 63);
3414 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1LL);
3415 tcg_gen_and_tl(t2
, t2
, t3
);
3416 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
3417 tcg_gen_or_tl(t2
, t2
, t3
);
3418 tcg_gen_movi_tl(t3
, 0);
3419 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
3420 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
3428 TCGv t2
= tcg_const_tl(0);
3429 TCGv t3
= tcg_const_tl(1);
3430 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
3431 tcg_gen_divu_i64(cpu_gpr
[rd
], t0
, t1
);
3439 TCGv t2
= tcg_const_tl(0);
3440 TCGv t3
= tcg_const_tl(1);
3441 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
3442 tcg_gen_remu_i64(cpu_gpr
[rd
], t0
, t1
);
3449 tcg_gen_mul_i64(cpu_gpr
[rd
], t0
, t1
);
3454 TCGv t2
= tcg_temp_new();
3455 tcg_gen_muls2_i64(t2
, cpu_gpr
[rd
], t0
, t1
);
3461 tcg_gen_mul_i64(cpu_gpr
[rd
], t0
, t1
);
3466 TCGv t2
= tcg_temp_new();
3467 tcg_gen_mulu2_i64(t2
, cpu_gpr
[rd
], t0
, t1
);
3475 generate_exception(ctx
, EXCP_RI
);
3478 (void)opn
; /* avoid a compiler warning */
3479 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
3485 static void gen_muldiv(DisasContext
*ctx
, uint32_t opc
,
3486 int acc
, int rs
, int rt
)
3488 const char *opn
= "mul/div";
3491 t0
= tcg_temp_new();
3492 t1
= tcg_temp_new();
3494 gen_load_gpr(t0
, rs
);
3495 gen_load_gpr(t1
, rt
);
3504 TCGv t2
= tcg_temp_new();
3505 TCGv t3
= tcg_temp_new();
3506 tcg_gen_ext32s_tl(t0
, t0
);
3507 tcg_gen_ext32s_tl(t1
, t1
);
3508 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
3509 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1);
3510 tcg_gen_and_tl(t2
, t2
, t3
);
3511 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
3512 tcg_gen_or_tl(t2
, t2
, t3
);
3513 tcg_gen_movi_tl(t3
, 0);
3514 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
3515 tcg_gen_div_tl(cpu_LO
[acc
], t0
, t1
);
3516 tcg_gen_rem_tl(cpu_HI
[acc
], t0
, t1
);
3517 tcg_gen_ext32s_tl(cpu_LO
[acc
], cpu_LO
[acc
]);
3518 tcg_gen_ext32s_tl(cpu_HI
[acc
], cpu_HI
[acc
]);
3526 TCGv t2
= tcg_const_tl(0);
3527 TCGv t3
= tcg_const_tl(1);
3528 tcg_gen_ext32u_tl(t0
, t0
);
3529 tcg_gen_ext32u_tl(t1
, t1
);
3530 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
3531 tcg_gen_divu_tl(cpu_LO
[acc
], t0
, t1
);
3532 tcg_gen_remu_tl(cpu_HI
[acc
], t0
, t1
);
3533 tcg_gen_ext32s_tl(cpu_LO
[acc
], cpu_LO
[acc
]);
3534 tcg_gen_ext32s_tl(cpu_HI
[acc
], cpu_HI
[acc
]);
3542 TCGv_i32 t2
= tcg_temp_new_i32();
3543 TCGv_i32 t3
= tcg_temp_new_i32();
3544 tcg_gen_trunc_tl_i32(t2
, t0
);
3545 tcg_gen_trunc_tl_i32(t3
, t1
);
3546 tcg_gen_muls2_i32(t2
, t3
, t2
, t3
);
3547 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
3548 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
3549 tcg_temp_free_i32(t2
);
3550 tcg_temp_free_i32(t3
);
3556 TCGv_i32 t2
= tcg_temp_new_i32();
3557 TCGv_i32 t3
= tcg_temp_new_i32();
3558 tcg_gen_trunc_tl_i32(t2
, t0
);
3559 tcg_gen_trunc_tl_i32(t3
, t1
);
3560 tcg_gen_mulu2_i32(t2
, t3
, t2
, t3
);
3561 tcg_gen_ext_i32_tl(cpu_LO
[acc
], t2
);
3562 tcg_gen_ext_i32_tl(cpu_HI
[acc
], t3
);
3563 tcg_temp_free_i32(t2
);
3564 tcg_temp_free_i32(t3
);
3568 #if defined(TARGET_MIPS64)
3571 TCGv t2
= tcg_temp_new();
3572 TCGv t3
= tcg_temp_new();
3573 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, t0
, -1LL << 63);
3574 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, -1LL);
3575 tcg_gen_and_tl(t2
, t2
, t3
);
3576 tcg_gen_setcondi_tl(TCG_COND_EQ
, t3
, t1
, 0);
3577 tcg_gen_or_tl(t2
, t2
, t3
);
3578 tcg_gen_movi_tl(t3
, 0);
3579 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
3580 tcg_gen_div_tl(cpu_LO
[acc
], t0
, t1
);
3581 tcg_gen_rem_tl(cpu_HI
[acc
], t0
, t1
);
3589 TCGv t2
= tcg_const_tl(0);
3590 TCGv t3
= tcg_const_tl(1);
3591 tcg_gen_movcond_tl(TCG_COND_EQ
, t1
, t1
, t2
, t3
, t1
);
3592 tcg_gen_divu_i64(cpu_LO
[acc
], t0
, t1
);
3593 tcg_gen_remu_i64(cpu_HI
[acc
], t0
, t1
);
3600 tcg_gen_muls2_i64(cpu_LO
[acc
], cpu_HI
[acc
], t0
, t1
);
3604 tcg_gen_mulu2_i64(cpu_LO
[acc
], cpu_HI
[acc
], t0
, t1
);
3610 TCGv_i64 t2
= tcg_temp_new_i64();
3611 TCGv_i64 t3
= tcg_temp_new_i64();
3613 tcg_gen_ext_tl_i64(t2
, t0
);
3614 tcg_gen_ext_tl_i64(t3
, t1
);
3615 tcg_gen_mul_i64(t2
, t2
, t3
);
3616 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
3617 tcg_gen_add_i64(t2
, t2
, t3
);
3618 tcg_temp_free_i64(t3
);
3619 tcg_gen_trunc_i64_tl(t0
, t2
);
3620 tcg_gen_shri_i64(t2
, t2
, 32);
3621 tcg_gen_trunc_i64_tl(t1
, t2
);
3622 tcg_temp_free_i64(t2
);
3623 tcg_gen_ext32s_tl(cpu_LO
[acc
], t0
);
3624 tcg_gen_ext32s_tl(cpu_HI
[acc
], t1
);
3630 TCGv_i64 t2
= tcg_temp_new_i64();
3631 TCGv_i64 t3
= tcg_temp_new_i64();
3633 tcg_gen_ext32u_tl(t0
, t0
);
3634 tcg_gen_ext32u_tl(t1
, t1
);
3635 tcg_gen_extu_tl_i64(t2
, t0
);
3636 tcg_gen_extu_tl_i64(t3
, t1
);
3637 tcg_gen_mul_i64(t2
, t2
, t3
);
3638 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
3639 tcg_gen_add_i64(t2
, t2
, t3
);
3640 tcg_temp_free_i64(t3
);
3641 tcg_gen_trunc_i64_tl(t0
, t2
);
3642 tcg_gen_shri_i64(t2
, t2
, 32);
3643 tcg_gen_trunc_i64_tl(t1
, t2
);
3644 tcg_temp_free_i64(t2
);
3645 tcg_gen_ext32s_tl(cpu_LO
[acc
], t0
);
3646 tcg_gen_ext32s_tl(cpu_HI
[acc
], t1
);
3652 TCGv_i64 t2
= tcg_temp_new_i64();
3653 TCGv_i64 t3
= tcg_temp_new_i64();
3655 tcg_gen_ext_tl_i64(t2
, t0
);
3656 tcg_gen_ext_tl_i64(t3
, t1
);
3657 tcg_gen_mul_i64(t2
, t2
, t3
);
3658 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
3659 tcg_gen_sub_i64(t2
, t3
, t2
);
3660 tcg_temp_free_i64(t3
);
3661 tcg_gen_trunc_i64_tl(t0
, t2
);
3662 tcg_gen_shri_i64(t2
, t2
, 32);
3663 tcg_gen_trunc_i64_tl(t1
, t2
);
3664 tcg_temp_free_i64(t2
);
3665 tcg_gen_ext32s_tl(cpu_LO
[acc
], t0
);
3666 tcg_gen_ext32s_tl(cpu_HI
[acc
], t1
);
3672 TCGv_i64 t2
= tcg_temp_new_i64();
3673 TCGv_i64 t3
= tcg_temp_new_i64();
3675 tcg_gen_ext32u_tl(t0
, t0
);
3676 tcg_gen_ext32u_tl(t1
, t1
);
3677 tcg_gen_extu_tl_i64(t2
, t0
);
3678 tcg_gen_extu_tl_i64(t3
, t1
);
3679 tcg_gen_mul_i64(t2
, t2
, t3
);
3680 tcg_gen_concat_tl_i64(t3
, cpu_LO
[acc
], cpu_HI
[acc
]);
3681 tcg_gen_sub_i64(t2
, t3
, t2
);
3682 tcg_temp_free_i64(t3
);
3683 tcg_gen_trunc_i64_tl(t0
, t2
);
3684 tcg_gen_shri_i64(t2
, t2
, 32);
3685 tcg_gen_trunc_i64_tl(t1
, t2
);
3686 tcg_temp_free_i64(t2
);
3687 tcg_gen_ext32s_tl(cpu_LO
[acc
], t0
);
3688 tcg_gen_ext32s_tl(cpu_HI
[acc
], t1
);
3694 generate_exception(ctx
, EXCP_RI
);
3697 (void)opn
; /* avoid a compiler warning */
3698 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
3704 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
3705 int rd
, int rs
, int rt
)
3707 const char *opn
= "mul vr54xx";
3708 TCGv t0
= tcg_temp_new();
3709 TCGv t1
= tcg_temp_new();
3711 gen_load_gpr(t0
, rs
);
3712 gen_load_gpr(t1
, rt
);
3715 case OPC_VR54XX_MULS
:
3716 gen_helper_muls(t0
, cpu_env
, t0
, t1
);
3719 case OPC_VR54XX_MULSU
:
3720 gen_helper_mulsu(t0
, cpu_env
, t0
, t1
);
3723 case OPC_VR54XX_MACC
:
3724 gen_helper_macc(t0
, cpu_env
, t0
, t1
);
3727 case OPC_VR54XX_MACCU
:
3728 gen_helper_maccu(t0
, cpu_env
, t0
, t1
);
3731 case OPC_VR54XX_MSAC
:
3732 gen_helper_msac(t0
, cpu_env
, t0
, t1
);
3735 case OPC_VR54XX_MSACU
:
3736 gen_helper_msacu(t0
, cpu_env
, t0
, t1
);
3739 case OPC_VR54XX_MULHI
:
3740 gen_helper_mulhi(t0
, cpu_env
, t0
, t1
);
3743 case OPC_VR54XX_MULHIU
:
3744 gen_helper_mulhiu(t0
, cpu_env
, t0
, t1
);
3747 case OPC_VR54XX_MULSHI
:
3748 gen_helper_mulshi(t0
, cpu_env
, t0
, t1
);
3751 case OPC_VR54XX_MULSHIU
:
3752 gen_helper_mulshiu(t0
, cpu_env
, t0
, t1
);
3755 case OPC_VR54XX_MACCHI
:
3756 gen_helper_macchi(t0
, cpu_env
, t0
, t1
);
3759 case OPC_VR54XX_MACCHIU
:
3760 gen_helper_macchiu(t0
, cpu_env
, t0
, t1
);
3763 case OPC_VR54XX_MSACHI
:
3764 gen_helper_msachi(t0
, cpu_env
, t0
, t1
);
3767 case OPC_VR54XX_MSACHIU
:
3768 gen_helper_msachiu(t0
, cpu_env
, t0
, t1
);
3772 MIPS_INVAL("mul vr54xx");
3773 generate_exception(ctx
, EXCP_RI
);
3776 gen_store_gpr(t0
, rd
);
3777 (void)opn
; /* avoid a compiler warning */
3778 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
3785 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
3788 const char *opn
= "CLx";
3796 t0
= tcg_temp_new();
3797 gen_load_gpr(t0
, rs
);
3801 gen_helper_clo(cpu_gpr
[rd
], t0
);
3806 gen_helper_clz(cpu_gpr
[rd
], t0
);
3809 #if defined(TARGET_MIPS64)
3812 gen_helper_dclo(cpu_gpr
[rd
], t0
);
3817 gen_helper_dclz(cpu_gpr
[rd
], t0
);
3822 (void)opn
; /* avoid a compiler warning */
3823 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
3827 /* Godson integer instructions */
3828 static void gen_loongson_integer(DisasContext
*ctx
, uint32_t opc
,
3829 int rd
, int rs
, int rt
)
3831 const char *opn
= "loongson";
3843 case OPC_MULTU_G_2E
:
3844 case OPC_MULTU_G_2F
:
3845 #if defined(TARGET_MIPS64)
3846 case OPC_DMULT_G_2E
:
3847 case OPC_DMULT_G_2F
:
3848 case OPC_DMULTU_G_2E
:
3849 case OPC_DMULTU_G_2F
:
3851 t0
= tcg_temp_new();
3852 t1
= tcg_temp_new();
3855 t0
= tcg_temp_local_new();
3856 t1
= tcg_temp_local_new();
3860 gen_load_gpr(t0
, rs
);
3861 gen_load_gpr(t1
, rt
);
3866 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
3867 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3870 case OPC_MULTU_G_2E
:
3871 case OPC_MULTU_G_2F
:
3872 tcg_gen_ext32u_tl(t0
, t0
);
3873 tcg_gen_ext32u_tl(t1
, t1
);
3874 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
3875 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3881 TCGLabel
*l1
= gen_new_label();
3882 TCGLabel
*l2
= gen_new_label();
3883 TCGLabel
*l3
= gen_new_label();
3884 tcg_gen_ext32s_tl(t0
, t0
);
3885 tcg_gen_ext32s_tl(t1
, t1
);
3886 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
3887 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
3890 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
3891 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
3892 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
3895 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
3896 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3904 TCGLabel
*l1
= gen_new_label();
3905 TCGLabel
*l2
= gen_new_label();
3906 tcg_gen_ext32u_tl(t0
, t0
);
3907 tcg_gen_ext32u_tl(t1
, t1
);
3908 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
3909 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
3912 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
3913 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3921 TCGLabel
*l1
= gen_new_label();
3922 TCGLabel
*l2
= gen_new_label();
3923 TCGLabel
*l3
= gen_new_label();
3924 tcg_gen_ext32u_tl(t0
, t0
);
3925 tcg_gen_ext32u_tl(t1
, t1
);
3926 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
3927 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
3928 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
3930 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
3933 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
3934 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3942 TCGLabel
*l1
= gen_new_label();
3943 TCGLabel
*l2
= gen_new_label();
3944 tcg_gen_ext32u_tl(t0
, t0
);
3945 tcg_gen_ext32u_tl(t1
, t1
);
3946 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
3947 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
3950 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
3951 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
3956 #if defined(TARGET_MIPS64)
3957 case OPC_DMULT_G_2E
:
3958 case OPC_DMULT_G_2F
:
3959 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
3962 case OPC_DMULTU_G_2E
:
3963 case OPC_DMULTU_G_2F
:
3964 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
3970 TCGLabel
*l1
= gen_new_label();
3971 TCGLabel
*l2
= gen_new_label();
3972 TCGLabel
*l3
= gen_new_label();
3973 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
3974 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
3977 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
3978 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
3979 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
3982 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
3987 case OPC_DDIVU_G_2E
:
3988 case OPC_DDIVU_G_2F
:
3990 TCGLabel
*l1
= gen_new_label();
3991 TCGLabel
*l2
= gen_new_label();
3992 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
3993 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
3996 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
4004 TCGLabel
*l1
= gen_new_label();
4005 TCGLabel
*l2
= gen_new_label();
4006 TCGLabel
*l3
= gen_new_label();
4007 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4008 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
4009 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
4011 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4014 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
4019 case OPC_DMODU_G_2E
:
4020 case OPC_DMODU_G_2F
:
4022 TCGLabel
*l1
= gen_new_label();
4023 TCGLabel
*l2
= gen_new_label();
4024 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
4025 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
4028 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
4036 (void)opn
; /* avoid a compiler warning */
4037 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
4042 /* Loongson multimedia instructions */
4043 static void gen_loongson_multimedia(DisasContext
*ctx
, int rd
, int rs
, int rt
)
4045 const char *opn
= "loongson_cp2";
4046 uint32_t opc
, shift_max
;
4049 opc
= MASK_LMI(ctx
->opcode
);
4055 t0
= tcg_temp_local_new_i64();
4056 t1
= tcg_temp_local_new_i64();
4059 t0
= tcg_temp_new_i64();
4060 t1
= tcg_temp_new_i64();
4064 gen_load_fpr64(ctx
, t0
, rs
);
4065 gen_load_fpr64(ctx
, t1
, rt
);
4067 #define LMI_HELPER(UP, LO) \
4068 case OPC_##UP: gen_helper_##LO(t0, t0, t1); opn = #LO; break
4069 #define LMI_HELPER_1(UP, LO) \
4070 case OPC_##UP: gen_helper_##LO(t0, t0); opn = #LO; break
4071 #define LMI_DIRECT(UP, LO, OP) \
4072 case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); opn = #LO; break
4075 LMI_HELPER(PADDSH
, paddsh
);
4076 LMI_HELPER(PADDUSH
, paddush
);
4077 LMI_HELPER(PADDH
, paddh
);
4078 LMI_HELPER(PADDW
, paddw
);
4079 LMI_HELPER(PADDSB
, paddsb
);
4080 LMI_HELPER(PADDUSB
, paddusb
);
4081 LMI_HELPER(PADDB
, paddb
);
4083 LMI_HELPER(PSUBSH
, psubsh
);
4084 LMI_HELPER(PSUBUSH
, psubush
);
4085 LMI_HELPER(PSUBH
, psubh
);
4086 LMI_HELPER(PSUBW
, psubw
);
4087 LMI_HELPER(PSUBSB
, psubsb
);
4088 LMI_HELPER(PSUBUSB
, psubusb
);
4089 LMI_HELPER(PSUBB
, psubb
);
4091 LMI_HELPER(PSHUFH
, pshufh
);
4092 LMI_HELPER(PACKSSWH
, packsswh
);
4093 LMI_HELPER(PACKSSHB
, packsshb
);
4094 LMI_HELPER(PACKUSHB
, packushb
);
4096 LMI_HELPER(PUNPCKLHW
, punpcklhw
);
4097 LMI_HELPER(PUNPCKHHW
, punpckhhw
);
4098 LMI_HELPER(PUNPCKLBH
, punpcklbh
);
4099 LMI_HELPER(PUNPCKHBH
, punpckhbh
);
4100 LMI_HELPER(PUNPCKLWD
, punpcklwd
);
4101 LMI_HELPER(PUNPCKHWD
, punpckhwd
);
4103 LMI_HELPER(PAVGH
, pavgh
);
4104 LMI_HELPER(PAVGB
, pavgb
);
4105 LMI_HELPER(PMAXSH
, pmaxsh
);
4106 LMI_HELPER(PMINSH
, pminsh
);
4107 LMI_HELPER(PMAXUB
, pmaxub
);
4108 LMI_HELPER(PMINUB
, pminub
);
4110 LMI_HELPER(PCMPEQW
, pcmpeqw
);
4111 LMI_HELPER(PCMPGTW
, pcmpgtw
);
4112 LMI_HELPER(PCMPEQH
, pcmpeqh
);
4113 LMI_HELPER(PCMPGTH
, pcmpgth
);
4114 LMI_HELPER(PCMPEQB
, pcmpeqb
);
4115 LMI_HELPER(PCMPGTB
, pcmpgtb
);
4117 LMI_HELPER(PSLLW
, psllw
);
4118 LMI_HELPER(PSLLH
, psllh
);
4119 LMI_HELPER(PSRLW
, psrlw
);
4120 LMI_HELPER(PSRLH
, psrlh
);
4121 LMI_HELPER(PSRAW
, psraw
);
4122 LMI_HELPER(PSRAH
, psrah
);
4124 LMI_HELPER(PMULLH
, pmullh
);
4125 LMI_HELPER(PMULHH
, pmulhh
);
4126 LMI_HELPER(PMULHUH
, pmulhuh
);
4127 LMI_HELPER(PMADDHW
, pmaddhw
);
4129 LMI_HELPER(PASUBUB
, pasubub
);
4130 LMI_HELPER_1(BIADD
, biadd
);
4131 LMI_HELPER_1(PMOVMSKB
, pmovmskb
);
4133 LMI_DIRECT(PADDD
, paddd
, add
);
4134 LMI_DIRECT(PSUBD
, psubd
, sub
);
4135 LMI_DIRECT(XOR_CP2
, xor, xor);
4136 LMI_DIRECT(NOR_CP2
, nor
, nor
);
4137 LMI_DIRECT(AND_CP2
, and, and);
4138 LMI_DIRECT(PANDN
, pandn
, andc
);
4139 LMI_DIRECT(OR
, or, or);
4142 tcg_gen_deposit_i64(t0
, t0
, t1
, 0, 16);
4146 tcg_gen_deposit_i64(t0
, t0
, t1
, 16, 16);
4150 tcg_gen_deposit_i64(t0
, t0
, t1
, 32, 16);
4154 tcg_gen_deposit_i64(t0
, t0
, t1
, 48, 16);
4159 tcg_gen_andi_i64(t1
, t1
, 3);
4160 tcg_gen_shli_i64(t1
, t1
, 4);
4161 tcg_gen_shr_i64(t0
, t0
, t1
);
4162 tcg_gen_ext16u_i64(t0
, t0
);
4167 tcg_gen_add_i64(t0
, t0
, t1
);
4168 tcg_gen_ext32s_i64(t0
, t0
);
4172 tcg_gen_sub_i64(t0
, t0
, t1
);
4173 tcg_gen_ext32s_i64(t0
, t0
);
4202 /* Make sure shift count isn't TCG undefined behaviour. */
4203 tcg_gen_andi_i64(t1
, t1
, shift_max
- 1);
4208 tcg_gen_shl_i64(t0
, t0
, t1
);
4212 /* Since SRA is UndefinedResult without sign-extended inputs,
4213 we can treat SRA and DSRA the same. */
4214 tcg_gen_sar_i64(t0
, t0
, t1
);
4217 /* We want to shift in zeros for SRL; zero-extend first. */
4218 tcg_gen_ext32u_i64(t0
, t0
);
4221 tcg_gen_shr_i64(t0
, t0
, t1
);
4225 if (shift_max
== 32) {
4226 tcg_gen_ext32s_i64(t0
, t0
);
4229 /* Shifts larger than MAX produce zero. */
4230 tcg_gen_setcondi_i64(TCG_COND_LTU
, t1
, t1
, shift_max
);
4231 tcg_gen_neg_i64(t1
, t1
);
4232 tcg_gen_and_i64(t0
, t0
, t1
);
4238 TCGv_i64 t2
= tcg_temp_new_i64();
4239 TCGLabel
*lab
= gen_new_label();
4241 tcg_gen_mov_i64(t2
, t0
);
4242 tcg_gen_add_i64(t0
, t1
, t2
);
4243 if (opc
== OPC_ADD_CP2
) {
4244 tcg_gen_ext32s_i64(t0
, t0
);
4246 tcg_gen_xor_i64(t1
, t1
, t2
);
4247 tcg_gen_xor_i64(t2
, t2
, t0
);
4248 tcg_gen_andc_i64(t1
, t2
, t1
);
4249 tcg_temp_free_i64(t2
);
4250 tcg_gen_brcondi_i64(TCG_COND_GE
, t1
, 0, lab
);
4251 generate_exception(ctx
, EXCP_OVERFLOW
);
4254 opn
= (opc
== OPC_ADD_CP2
? "add" : "dadd");
4261 TCGv_i64 t2
= tcg_temp_new_i64();
4262 TCGLabel
*lab
= gen_new_label();
4264 tcg_gen_mov_i64(t2
, t0
);
4265 tcg_gen_sub_i64(t0
, t1
, t2
);
4266 if (opc
== OPC_SUB_CP2
) {
4267 tcg_gen_ext32s_i64(t0
, t0
);
4269 tcg_gen_xor_i64(t1
, t1
, t2
);
4270 tcg_gen_xor_i64(t2
, t2
, t0
);
4271 tcg_gen_and_i64(t1
, t1
, t2
);
4272 tcg_temp_free_i64(t2
);
4273 tcg_gen_brcondi_i64(TCG_COND_GE
, t1
, 0, lab
);
4274 generate_exception(ctx
, EXCP_OVERFLOW
);
4277 opn
= (opc
== OPC_SUB_CP2
? "sub" : "dsub");
4282 tcg_gen_ext32u_i64(t0
, t0
);
4283 tcg_gen_ext32u_i64(t1
, t1
);
4284 tcg_gen_mul_i64(t0
, t0
, t1
);
4294 /* ??? Document is unclear: Set FCC[CC]. Does that mean the
4295 FD field is the CC field? */
4298 generate_exception(ctx
, EXCP_RI
);
4305 gen_store_fpr64(ctx
, t0
, rd
);
4307 (void)opn
; /* avoid a compiler warning */
4308 MIPS_DEBUG("%s %s, %s, %s", opn
,
4309 fregnames
[rd
], fregnames
[rs
], fregnames
[rt
]);
4310 tcg_temp_free_i64(t0
);
4311 tcg_temp_free_i64(t1
);
4315 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
4316 int rs
, int rt
, int16_t imm
)
4319 TCGv t0
= tcg_temp_new();
4320 TCGv t1
= tcg_temp_new();
4323 /* Load needed operands */
4331 /* Compare two registers */
4333 gen_load_gpr(t0
, rs
);
4334 gen_load_gpr(t1
, rt
);
4344 /* Compare register to immediate */
4345 if (rs
!= 0 || imm
!= 0) {
4346 gen_load_gpr(t0
, rs
);
4347 tcg_gen_movi_tl(t1
, (int32_t)imm
);
4354 case OPC_TEQ
: /* rs == rs */
4355 case OPC_TEQI
: /* r0 == 0 */
4356 case OPC_TGE
: /* rs >= rs */
4357 case OPC_TGEI
: /* r0 >= 0 */
4358 case OPC_TGEU
: /* rs >= rs unsigned */
4359 case OPC_TGEIU
: /* r0 >= 0 unsigned */
4361 generate_exception(ctx
, EXCP_TRAP
);
4363 case OPC_TLT
: /* rs < rs */
4364 case OPC_TLTI
: /* r0 < 0 */
4365 case OPC_TLTU
: /* rs < rs unsigned */
4366 case OPC_TLTIU
: /* r0 < 0 unsigned */
4367 case OPC_TNE
: /* rs != rs */
4368 case OPC_TNEI
: /* r0 != 0 */
4369 /* Never trap: treat as NOP. */
4373 TCGLabel
*l1
= gen_new_label();
4378 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
4382 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
4386 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
4390 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4394 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
4398 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
4401 generate_exception(ctx
, EXCP_TRAP
);
4408 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
4410 TranslationBlock
*tb
;
4412 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
4413 likely(!ctx
->singlestep_enabled
)) {
4416 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
4419 if (ctx
->singlestep_enabled
) {
4420 save_cpu_state(ctx
, 0);
4421 gen_helper_0e0i(raise_exception
, EXCP_DEBUG
);
4427 /* Branches (before delay slot) */
4428 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
4430 int rs
, int rt
, int32_t offset
,
4433 target_ulong btgt
= -1;
4435 int bcond_compute
= 0;
4436 TCGv t0
= tcg_temp_new();
4437 TCGv t1
= tcg_temp_new();
4439 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
4440 #ifdef MIPS_DEBUG_DISAS
4441 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
4442 TARGET_FMT_lx
"\n", ctx
->pc
);
4444 generate_exception(ctx
, EXCP_RI
);
4448 /* Load needed operands */
4454 /* Compare two registers */
4456 gen_load_gpr(t0
, rs
);
4457 gen_load_gpr(t1
, rt
);
4460 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
4474 /* Compare to zero */
4476 gen_load_gpr(t0
, rs
);
4479 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
4482 #if defined(TARGET_MIPS64)
4484 tcg_gen_andi_tl(t0
, cpu_dspctrl
, 0x7F);
4486 tcg_gen_andi_tl(t0
, cpu_dspctrl
, 0x3F);
4489 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
4494 /* Jump to immediate */
4495 btgt
= ((ctx
->pc
+ insn_bytes
) & (int32_t)0xF0000000) | (uint32_t)offset
;
4499 /* Jump to register */
4500 if (offset
!= 0 && offset
!= 16) {
4501 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
4502 others are reserved. */
4503 MIPS_INVAL("jump hint");
4504 generate_exception(ctx
, EXCP_RI
);
4507 gen_load_gpr(btarget
, rs
);
4510 MIPS_INVAL("branch/jump");
4511 generate_exception(ctx
, EXCP_RI
);
4514 if (bcond_compute
== 0) {
4515 /* No condition to be computed */
4517 case OPC_BEQ
: /* rx == rx */
4518 case OPC_BEQL
: /* rx == rx likely */
4519 case OPC_BGEZ
: /* 0 >= 0 */
4520 case OPC_BGEZL
: /* 0 >= 0 likely */
4521 case OPC_BLEZ
: /* 0 <= 0 */
4522 case OPC_BLEZL
: /* 0 <= 0 likely */
4524 ctx
->hflags
|= MIPS_HFLAG_B
;
4525 MIPS_DEBUG("balways");
4527 case OPC_BGEZAL
: /* 0 >= 0 */
4528 case OPC_BGEZALL
: /* 0 >= 0 likely */
4529 /* Always take and link */
4531 ctx
->hflags
|= MIPS_HFLAG_B
;
4532 MIPS_DEBUG("balways and link");
4534 case OPC_BNE
: /* rx != rx */
4535 case OPC_BGTZ
: /* 0 > 0 */
4536 case OPC_BLTZ
: /* 0 < 0 */
4538 MIPS_DEBUG("bnever (NOP)");
4540 case OPC_BLTZAL
: /* 0 < 0 */
4541 /* Handle as an unconditional branch to get correct delay
4544 btgt
= ctx
->pc
+ insn_bytes
+ delayslot_size
;
4545 ctx
->hflags
|= MIPS_HFLAG_B
;
4546 MIPS_DEBUG("bnever and link");
4548 case OPC_BLTZALL
: /* 0 < 0 likely */
4549 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
4550 /* Skip the instruction in the delay slot */
4551 MIPS_DEBUG("bnever, link and skip");
4554 case OPC_BNEL
: /* rx != rx likely */
4555 case OPC_BGTZL
: /* 0 > 0 likely */
4556 case OPC_BLTZL
: /* 0 < 0 likely */
4557 /* Skip the instruction in the delay slot */
4558 MIPS_DEBUG("bnever and skip");
4562 ctx
->hflags
|= MIPS_HFLAG_B
;
4563 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
4566 ctx
->hflags
|= MIPS_HFLAG_BX
;
4570 ctx
->hflags
|= MIPS_HFLAG_B
;
4571 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
4574 ctx
->hflags
|= MIPS_HFLAG_BR
;
4575 MIPS_DEBUG("jr %s", regnames
[rs
]);
4579 ctx
->hflags
|= MIPS_HFLAG_BR
;
4580 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
4583 MIPS_INVAL("branch/jump");
4584 generate_exception(ctx
, EXCP_RI
);
4590 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
4591 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
4592 regnames
[rs
], regnames
[rt
], btgt
);
4595 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
4596 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
4597 regnames
[rs
], regnames
[rt
], btgt
);
4600 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
4601 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
4602 regnames
[rs
], regnames
[rt
], btgt
);
4605 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
4606 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
4607 regnames
[rs
], regnames
[rt
], btgt
);
4610 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
4611 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4614 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
4615 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4618 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
4619 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4623 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
4625 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4628 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
4629 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4632 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
4633 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4636 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
4637 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4640 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
4641 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4644 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
4645 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4648 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
4649 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4652 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 32);
4653 MIPS_DEBUG("bposge32 " TARGET_FMT_lx
, btgt
);
4655 #if defined(TARGET_MIPS64)
4657 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 64);
4658 MIPS_DEBUG("bposge64 " TARGET_FMT_lx
, btgt
);
4662 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
4664 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4666 ctx
->hflags
|= MIPS_HFLAG_BC
;
4669 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
4671 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
4673 ctx
->hflags
|= MIPS_HFLAG_BL
;
4676 MIPS_INVAL("conditional branch/jump");
4677 generate_exception(ctx
, EXCP_RI
);
4681 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
4682 blink
, ctx
->hflags
, btgt
);
4684 ctx
->btarget
= btgt
;
4686 switch (delayslot_size
) {
4688 ctx
->hflags
|= MIPS_HFLAG_BDS16
;
4691 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
4696 int post_delay
= insn_bytes
+ delayslot_size
;
4697 int lowbit
= !!(ctx
->hflags
& MIPS_HFLAG_M16
);
4699 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ post_delay
+ lowbit
);
4703 if (insn_bytes
== 2)
4704 ctx
->hflags
|= MIPS_HFLAG_B16
;
4709 /* special3 bitfield operations */
4710 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
4711 int rs
, int lsb
, int msb
)
4713 TCGv t0
= tcg_temp_new();
4714 TCGv t1
= tcg_temp_new();
4716 gen_load_gpr(t1
, rs
);
4721 tcg_gen_shri_tl(t0
, t1
, lsb
);
4723 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
4725 tcg_gen_ext32s_tl(t0
, t0
);
4728 #if defined(TARGET_MIPS64)
4730 tcg_gen_shri_tl(t0
, t1
, lsb
);
4732 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
4736 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
4737 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
4740 tcg_gen_shri_tl(t0
, t1
, lsb
);
4741 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
4747 gen_load_gpr(t0
, rt
);
4748 tcg_gen_deposit_tl(t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
4749 tcg_gen_ext32s_tl(t0
, t0
);
4751 #if defined(TARGET_MIPS64)
4753 gen_load_gpr(t0
, rt
);
4754 tcg_gen_deposit_tl(t0
, t0
, t1
, lsb
, msb
+ 32 - lsb
+ 1);
4757 gen_load_gpr(t0
, rt
);
4758 tcg_gen_deposit_tl(t0
, t0
, t1
, lsb
+ 32, msb
- lsb
+ 1);
4761 gen_load_gpr(t0
, rt
);
4762 tcg_gen_deposit_tl(t0
, t0
, t1
, lsb
, msb
- lsb
+ 1);
4767 MIPS_INVAL("bitops");
4768 generate_exception(ctx
, EXCP_RI
);
4773 gen_store_gpr(t0
, rt
);
4778 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
4783 /* If no destination, treat it as a NOP. */
4788 t0
= tcg_temp_new();
4789 gen_load_gpr(t0
, rt
);
4793 TCGv t1
= tcg_temp_new();
4795 tcg_gen_shri_tl(t1
, t0
, 8);
4796 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
4797 tcg_gen_shli_tl(t0
, t0
, 8);
4798 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
4799 tcg_gen_or_tl(t0
, t0
, t1
);
4801 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
4805 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
4808 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
4810 #if defined(TARGET_MIPS64)
4813 TCGv t1
= tcg_temp_new();
4815 tcg_gen_shri_tl(t1
, t0
, 8);
4816 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
4817 tcg_gen_shli_tl(t0
, t0
, 8);
4818 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
4819 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
4825 TCGv t1
= tcg_temp_new();
4827 tcg_gen_shri_tl(t1
, t0
, 16);
4828 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
4829 tcg_gen_shli_tl(t0
, t0
, 16);
4830 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
4831 tcg_gen_or_tl(t0
, t0
, t1
);
4832 tcg_gen_shri_tl(t1
, t0
, 32);
4833 tcg_gen_shli_tl(t0
, t0
, 32);
4834 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
4840 MIPS_INVAL("bsfhl");
4841 generate_exception(ctx
, EXCP_RI
);
4848 #ifndef CONFIG_USER_ONLY
4849 /* CP0 (MMU and control) */
4850 static inline void gen_move_low32(TCGv ret
, TCGv_i64 arg
)
4852 #if defined(TARGET_MIPS64)
4853 tcg_gen_ext32s_tl(ret
, arg
);
4855 tcg_gen_trunc_i64_tl(ret
, arg
);
4859 static inline void gen_mthc0_entrylo(TCGv arg
, target_ulong off
)
4861 TCGv_i64 t0
= tcg_temp_new_i64();
4862 TCGv_i64 t1
= tcg_temp_new_i64();
4864 tcg_gen_ext_tl_i64(t0
, arg
);
4865 tcg_gen_ld_i64(t1
, cpu_env
, off
);
4866 #if defined(TARGET_MIPS64)
4867 tcg_gen_deposit_i64(t1
, t1
, t0
, 30, 32);
4869 tcg_gen_concat32_i64(t1
, t1
, t0
);
4871 tcg_gen_st_i64(t1
, cpu_env
, off
);
4872 tcg_temp_free_i64(t1
);
4873 tcg_temp_free_i64(t0
);
4876 static inline void gen_mthc0_store64(TCGv arg
, target_ulong off
)
4878 TCGv_i64 t0
= tcg_temp_new_i64();
4879 TCGv_i64 t1
= tcg_temp_new_i64();
4881 tcg_gen_ext_tl_i64(t0
, arg
);
4882 tcg_gen_ld_i64(t1
, cpu_env
, off
);
4883 tcg_gen_concat32_i64(t1
, t1
, t0
);
4884 tcg_gen_st_i64(t1
, cpu_env
, off
);
4885 tcg_temp_free_i64(t1
);
4886 tcg_temp_free_i64(t0
);
4889 static inline void gen_mfhc0_entrylo(TCGv arg
, target_ulong off
)
4891 TCGv_i64 t0
= tcg_temp_new_i64();
4893 tcg_gen_ld_i64(t0
, cpu_env
, off
);
4894 #if defined(TARGET_MIPS64)
4895 tcg_gen_shri_i64(t0
, t0
, 30);
4897 tcg_gen_shri_i64(t0
, t0
, 32);
4899 gen_move_low32(arg
, t0
);
4900 tcg_temp_free_i64(t0
);
4903 static inline void gen_mfhc0_load64(TCGv arg
, target_ulong off
, int shift
)
4905 TCGv_i64 t0
= tcg_temp_new_i64();
4907 tcg_gen_ld_i64(t0
, cpu_env
, off
);
4908 tcg_gen_shri_i64(t0
, t0
, 32 + shift
);
4909 gen_move_low32(arg
, t0
);
4910 tcg_temp_free_i64(t0
);
4913 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
4915 TCGv_i32 t0
= tcg_temp_new_i32();
4917 tcg_gen_ld_i32(t0
, cpu_env
, off
);
4918 tcg_gen_ext_i32_tl(arg
, t0
);
4919 tcg_temp_free_i32(t0
);
4922 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
4924 tcg_gen_ld_tl(arg
, cpu_env
, off
);
4925 tcg_gen_ext32s_tl(arg
, arg
);
4928 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
4930 TCGv_i32 t0
= tcg_temp_new_i32();
4932 tcg_gen_trunc_tl_i32(t0
, arg
);
4933 tcg_gen_st_i32(t0
, cpu_env
, off
);
4934 tcg_temp_free_i32(t0
);
4937 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
4939 tcg_gen_ext32s_tl(arg
, arg
);
4940 tcg_gen_st_tl(arg
, cpu_env
, off
);
4943 static void gen_mfhc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4945 const char *rn
= "invalid";
4947 if (!(ctx
->hflags
& MIPS_HFLAG_ELPA
)) {
4948 goto mfhc0_read_zero
;
4955 gen_mfhc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo0
));
4959 goto mfhc0_read_zero
;
4965 gen_mfhc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo1
));
4969 goto mfhc0_read_zero
;
4975 gen_mfhc0_load64(arg
, offsetof(CPUMIPSState
, lladdr
),
4976 ctx
->CP0_LLAddr_shift
);
4980 goto mfhc0_read_zero
;
4989 gen_mfhc0_load64(arg
, offsetof(CPUMIPSState
, CP0_TagLo
), 0);
4993 goto mfhc0_read_zero
;
4997 goto mfhc0_read_zero
;
5000 (void)rn
; /* avoid a compiler warning */
5001 LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5005 LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5006 tcg_gen_movi_tl(arg
, 0);
5009 static void gen_mthc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
5011 const char *rn
= "invalid";
5012 uint64_t mask
= ctx
->PAMask
>> 36;
5014 if (!(ctx
->hflags
& MIPS_HFLAG_ELPA
)) {
5022 tcg_gen_andi_tl(arg
, arg
, mask
);
5023 gen_mthc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo0
));
5033 tcg_gen_andi_tl(arg
, arg
, mask
);
5034 gen_mthc0_entrylo(arg
, offsetof(CPUMIPSState
, CP0_EntryLo1
));
5044 /* LLAddr is read-only (the only exception is bit 0 if LLB is
5045 supported); the CP0_LLAddr_rw_bitmask does not seem to be
5046 relevant for modern MIPS cores supporting MTHC0, therefore
5047 treating MTHC0 to LLAddr as NOP. */
5060 tcg_gen_andi_tl(arg
, arg
, mask
);
5061 gen_mthc0_store64(arg
, offsetof(CPUMIPSState
, CP0_TagLo
));
5072 (void)rn
; /* avoid a compiler warning */
5074 LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5077 static inline void gen_mfc0_unimplemented(DisasContext
*ctx
, TCGv arg
)
5079 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
5080 tcg_gen_movi_tl(arg
, 0);
5082 tcg_gen_movi_tl(arg
, ~0);
5086 #define CP0_CHECK(c) \
5089 goto cp0_unimplemented; \
5093 static void gen_mfc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
5095 const char *rn
= "invalid";
5098 check_insn(ctx
, ISA_MIPS32
);
5104 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Index
));
5108 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5109 gen_helper_mfc0_mvpcontrol(arg
, cpu_env
);
5113 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5114 gen_helper_mfc0_mvpconf0(arg
, cpu_env
);
5118 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5119 gen_helper_mfc0_mvpconf1(arg
, cpu_env
);
5123 goto cp0_unimplemented
;
5129 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
5130 gen_helper_mfc0_random(arg
, cpu_env
);
5134 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5135 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEControl
));
5139 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5140 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf0
));
5144 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5145 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf1
));
5149 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5150 gen_mfc0_load64(arg
, offsetof(CPUMIPSState
, CP0_YQMask
));
5154 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5155 gen_mfc0_load64(arg
, offsetof(CPUMIPSState
, CP0_VPESchedule
));
5159 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5160 gen_mfc0_load64(arg
, offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
5161 rn
= "VPEScheFBack";
5164 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5165 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEOpt
));
5169 goto cp0_unimplemented
;
5176 TCGv_i64 tmp
= tcg_temp_new_i64();
5177 tcg_gen_ld_i64(tmp
, cpu_env
,
5178 offsetof(CPUMIPSState
, CP0_EntryLo0
));
5179 #if defined(TARGET_MIPS64)
5181 /* Move RI/XI fields to bits 31:30 */
5182 tcg_gen_shri_tl(arg
, tmp
, CP0EnLo_XI
);
5183 tcg_gen_deposit_tl(tmp
, tmp
, arg
, 30, 2);
5186 gen_move_low32(arg
, tmp
);
5187 tcg_temp_free_i64(tmp
);
5192 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5193 gen_helper_mfc0_tcstatus(arg
, cpu_env
);
5197 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5198 gen_helper_mfc0_tcbind(arg
, cpu_env
);
5202 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5203 gen_helper_mfc0_tcrestart(arg
, cpu_env
);
5207 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5208 gen_helper_mfc0_tchalt(arg
, cpu_env
);
5212 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5213 gen_helper_mfc0_tccontext(arg
, cpu_env
);
5217 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5218 gen_helper_mfc0_tcschedule(arg
, cpu_env
);
5222 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5223 gen_helper_mfc0_tcschefback(arg
, cpu_env
);
5227 goto cp0_unimplemented
;
5234 TCGv_i64 tmp
= tcg_temp_new_i64();
5235 tcg_gen_ld_i64(tmp
, cpu_env
,
5236 offsetof(CPUMIPSState
, CP0_EntryLo1
));
5237 #if defined(TARGET_MIPS64)
5239 /* Move RI/XI fields to bits 31:30 */
5240 tcg_gen_shri_tl(arg
, tmp
, CP0EnLo_XI
);
5241 tcg_gen_deposit_tl(tmp
, tmp
, arg
, 30, 2);
5244 gen_move_low32(arg
, tmp
);
5245 tcg_temp_free_i64(tmp
);
5250 goto cp0_unimplemented
;
5256 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_Context
));
5257 tcg_gen_ext32s_tl(arg
, arg
);
5261 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
5262 rn
= "ContextConfig";
5263 goto cp0_unimplemented
;
5266 CP0_CHECK(ctx
->ulri
);
5267 tcg_gen_ld32s_tl(arg
, cpu_env
,
5268 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
5272 goto cp0_unimplemented
;
5278 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageMask
));
5282 check_insn(ctx
, ISA_MIPS32R2
);
5283 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageGrain
));
5287 goto cp0_unimplemented
;
5293 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Wired
));
5297 check_insn(ctx
, ISA_MIPS32R2
);
5298 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf0
));
5302 check_insn(ctx
, ISA_MIPS32R2
);
5303 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf1
));
5307 check_insn(ctx
, ISA_MIPS32R2
);
5308 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf2
));
5312 check_insn(ctx
, ISA_MIPS32R2
);
5313 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf3
));
5317 check_insn(ctx
, ISA_MIPS32R2
);
5318 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf4
));
5322 goto cp0_unimplemented
;
5328 check_insn(ctx
, ISA_MIPS32R2
);
5329 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_HWREna
));
5333 goto cp0_unimplemented
;
5339 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_BadVAddr
));
5340 tcg_gen_ext32s_tl(arg
, arg
);
5345 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstr
));
5350 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstrP
));
5354 goto cp0_unimplemented
;
5360 /* Mark as an IO operation because we read the time. */
5361 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
5364 gen_helper_mfc0_count(arg
, cpu_env
);
5365 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
5368 /* Break the TB to be able to take timer interrupts immediately
5369 after reading count. */
5370 ctx
->bstate
= BS_STOP
;
5373 /* 6,7 are implementation dependent */
5375 goto cp0_unimplemented
;
5381 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryHi
));
5382 tcg_gen_ext32s_tl(arg
, arg
);
5386 goto cp0_unimplemented
;
5392 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Compare
));
5395 /* 6,7 are implementation dependent */
5397 goto cp0_unimplemented
;
5403 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Status
));
5407 check_insn(ctx
, ISA_MIPS32R2
);
5408 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_IntCtl
));
5412 check_insn(ctx
, ISA_MIPS32R2
);
5413 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
5417 check_insn(ctx
, ISA_MIPS32R2
);
5418 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
5422 goto cp0_unimplemented
;
5428 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Cause
));
5432 goto cp0_unimplemented
;
5438 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
5439 tcg_gen_ext32s_tl(arg
, arg
);
5443 goto cp0_unimplemented
;
5449 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PRid
));
5453 check_insn(ctx
, ISA_MIPS32R2
);
5454 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_EBase
));
5458 goto cp0_unimplemented
;
5464 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config0
));
5468 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config1
));
5472 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config2
));
5476 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config3
));
5480 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config4
));
5484 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config5
));
5487 /* 6,7 are implementation dependent */
5489 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config6
));
5493 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config7
));
5497 goto cp0_unimplemented
;
5503 gen_helper_mfc0_lladdr(arg
, cpu_env
);
5507 goto cp0_unimplemented
;
5513 gen_helper_1e0i(mfc0_watchlo
, arg
, sel
);
5517 goto cp0_unimplemented
;
5523 gen_helper_1e0i(mfc0_watchhi
, arg
, sel
);
5527 goto cp0_unimplemented
;
5533 #if defined(TARGET_MIPS64)
5534 check_insn(ctx
, ISA_MIPS3
);
5535 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_XContext
));
5536 tcg_gen_ext32s_tl(arg
, arg
);
5541 goto cp0_unimplemented
;
5545 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5546 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
5549 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Framemask
));
5553 goto cp0_unimplemented
;
5557 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
5558 rn
= "'Diagnostic"; /* implementation dependent */
5563 gen_helper_mfc0_debug(arg
, cpu_env
); /* EJTAG support */
5567 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
5568 rn
= "TraceControl";
5571 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
5572 rn
= "TraceControl2";
5575 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
5576 rn
= "UserTraceData";
5579 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
5583 goto cp0_unimplemented
;
5590 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
5591 tcg_gen_ext32s_tl(arg
, arg
);
5595 goto cp0_unimplemented
;
5601 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Performance0
));
5602 rn
= "Performance0";
5605 // gen_helper_mfc0_performance1(arg);
5606 rn
= "Performance1";
5609 // gen_helper_mfc0_performance2(arg);
5610 rn
= "Performance2";
5613 // gen_helper_mfc0_performance3(arg);
5614 rn
= "Performance3";
5617 // gen_helper_mfc0_performance4(arg);
5618 rn
= "Performance4";
5621 // gen_helper_mfc0_performance5(arg);
5622 rn
= "Performance5";
5625 // gen_helper_mfc0_performance6(arg);
5626 rn
= "Performance6";
5629 // gen_helper_mfc0_performance7(arg);
5630 rn
= "Performance7";
5633 goto cp0_unimplemented
;
5637 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
5643 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
5647 goto cp0_unimplemented
;
5657 TCGv_i64 tmp
= tcg_temp_new_i64();
5658 tcg_gen_ld_i64(tmp
, cpu_env
, offsetof(CPUMIPSState
, CP0_TagLo
));
5659 gen_move_low32(arg
, tmp
);
5660 tcg_temp_free_i64(tmp
);
5668 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataLo
));
5672 goto cp0_unimplemented
;
5681 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_TagHi
));
5688 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataHi
));
5692 goto cp0_unimplemented
;
5698 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
5699 tcg_gen_ext32s_tl(arg
, arg
);
5703 goto cp0_unimplemented
;
5710 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
5714 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
5715 tcg_gen_ld_tl(arg
, cpu_env
,
5716 offsetof(CPUMIPSState
, CP0_KScratch
[sel
-2]));
5717 tcg_gen_ext32s_tl(arg
, arg
);
5721 goto cp0_unimplemented
;
5725 goto cp0_unimplemented
;
5727 (void)rn
; /* avoid a compiler warning */
5728 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5732 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5733 gen_mfc0_unimplemented(ctx
, arg
);
5736 static void gen_mtc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
5738 const char *rn
= "invalid";
5741 check_insn(ctx
, ISA_MIPS32
);
5743 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
5751 gen_helper_mtc0_index(cpu_env
, arg
);
5755 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5756 gen_helper_mtc0_mvpcontrol(cpu_env
, arg
);
5760 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5765 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5770 goto cp0_unimplemented
;
5780 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5781 gen_helper_mtc0_vpecontrol(cpu_env
, arg
);
5785 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5786 gen_helper_mtc0_vpeconf0(cpu_env
, arg
);
5790 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5791 gen_helper_mtc0_vpeconf1(cpu_env
, arg
);
5795 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5796 gen_helper_mtc0_yqmask(cpu_env
, arg
);
5800 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5801 gen_mtc0_store64(arg
, offsetof(CPUMIPSState
, CP0_VPESchedule
));
5805 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5806 gen_mtc0_store64(arg
, offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
5807 rn
= "VPEScheFBack";
5810 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5811 gen_helper_mtc0_vpeopt(cpu_env
, arg
);
5815 goto cp0_unimplemented
;
5821 gen_helper_mtc0_entrylo0(cpu_env
, arg
);
5825 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5826 gen_helper_mtc0_tcstatus(cpu_env
, arg
);
5830 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5831 gen_helper_mtc0_tcbind(cpu_env
, arg
);
5835 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5836 gen_helper_mtc0_tcrestart(cpu_env
, arg
);
5840 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5841 gen_helper_mtc0_tchalt(cpu_env
, arg
);
5845 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5846 gen_helper_mtc0_tccontext(cpu_env
, arg
);
5850 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5851 gen_helper_mtc0_tcschedule(cpu_env
, arg
);
5855 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
5856 gen_helper_mtc0_tcschefback(cpu_env
, arg
);
5860 goto cp0_unimplemented
;
5866 gen_helper_mtc0_entrylo1(cpu_env
, arg
);
5870 goto cp0_unimplemented
;
5876 gen_helper_mtc0_context(cpu_env
, arg
);
5880 // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
5881 rn
= "ContextConfig";
5882 goto cp0_unimplemented
;
5885 CP0_CHECK(ctx
->ulri
);
5886 tcg_gen_st_tl(arg
, cpu_env
,
5887 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
5891 goto cp0_unimplemented
;
5897 gen_helper_mtc0_pagemask(cpu_env
, arg
);
5901 check_insn(ctx
, ISA_MIPS32R2
);
5902 gen_helper_mtc0_pagegrain(cpu_env
, arg
);
5904 ctx
->bstate
= BS_STOP
;
5907 goto cp0_unimplemented
;
5913 gen_helper_mtc0_wired(cpu_env
, arg
);
5917 check_insn(ctx
, ISA_MIPS32R2
);
5918 gen_helper_mtc0_srsconf0(cpu_env
, arg
);
5922 check_insn(ctx
, ISA_MIPS32R2
);
5923 gen_helper_mtc0_srsconf1(cpu_env
, arg
);
5927 check_insn(ctx
, ISA_MIPS32R2
);
5928 gen_helper_mtc0_srsconf2(cpu_env
, arg
);
5932 check_insn(ctx
, ISA_MIPS32R2
);
5933 gen_helper_mtc0_srsconf3(cpu_env
, arg
);
5937 check_insn(ctx
, ISA_MIPS32R2
);
5938 gen_helper_mtc0_srsconf4(cpu_env
, arg
);
5942 goto cp0_unimplemented
;
5948 check_insn(ctx
, ISA_MIPS32R2
);
5949 gen_helper_mtc0_hwrena(cpu_env
, arg
);
5950 ctx
->bstate
= BS_STOP
;
5954 goto cp0_unimplemented
;
5972 goto cp0_unimplemented
;
5978 gen_helper_mtc0_count(cpu_env
, arg
);
5981 /* 6,7 are implementation dependent */
5983 goto cp0_unimplemented
;
5989 gen_helper_mtc0_entryhi(cpu_env
, arg
);
5993 goto cp0_unimplemented
;
5999 gen_helper_mtc0_compare(cpu_env
, arg
);
6002 /* 6,7 are implementation dependent */
6004 goto cp0_unimplemented
;
6010 save_cpu_state(ctx
, 1);
6011 gen_helper_mtc0_status(cpu_env
, arg
);
6012 /* BS_STOP isn't good enough here, hflags may have changed. */
6013 gen_save_pc(ctx
->pc
+ 4);
6014 ctx
->bstate
= BS_EXCP
;
6018 check_insn(ctx
, ISA_MIPS32R2
);
6019 gen_helper_mtc0_intctl(cpu_env
, arg
);
6020 /* Stop translation as we may have switched the execution mode */
6021 ctx
->bstate
= BS_STOP
;
6025 check_insn(ctx
, ISA_MIPS32R2
);
6026 gen_helper_mtc0_srsctl(cpu_env
, arg
);
6027 /* Stop translation as we may have switched the execution mode */
6028 ctx
->bstate
= BS_STOP
;
6032 check_insn(ctx
, ISA_MIPS32R2
);
6033 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
6034 /* Stop translation as we may have switched the execution mode */
6035 ctx
->bstate
= BS_STOP
;
6039 goto cp0_unimplemented
;
6045 save_cpu_state(ctx
, 1);
6046 gen_helper_mtc0_cause(cpu_env
, arg
);
6050 goto cp0_unimplemented
;
6056 gen_mtc0_store64(arg
, offsetof(CPUMIPSState
, CP0_EPC
));
6060 goto cp0_unimplemented
;
6070 check_insn(ctx
, ISA_MIPS32R2
);
6071 gen_helper_mtc0_ebase(cpu_env
, arg
);
6075 goto cp0_unimplemented
;
6081 gen_helper_mtc0_config0(cpu_env
, arg
);
6083 /* Stop translation as we may have switched the execution mode */
6084 ctx
->bstate
= BS_STOP
;
6087 /* ignored, read only */
6091 gen_helper_mtc0_config2(cpu_env
, arg
);
6093 /* Stop translation as we may have switched the execution mode */
6094 ctx
->bstate
= BS_STOP
;
6097 gen_helper_mtc0_config3(cpu_env
, arg
);
6099 /* Stop translation as we may have switched the execution mode */
6100 ctx
->bstate
= BS_STOP
;
6103 gen_helper_mtc0_config4(cpu_env
, arg
);
6105 ctx
->bstate
= BS_STOP
;
6108 gen_helper_mtc0_config5(cpu_env
, arg
);
6110 /* Stop translation as we may have switched the execution mode */
6111 ctx
->bstate
= BS_STOP
;
6113 /* 6,7 are implementation dependent */
6123 rn
= "Invalid config selector";
6124 goto cp0_unimplemented
;
6130 gen_helper_mtc0_lladdr(cpu_env
, arg
);
6134 goto cp0_unimplemented
;
6140 gen_helper_0e1i(mtc0_watchlo
, arg
, sel
);
6144 goto cp0_unimplemented
;
6150 gen_helper_0e1i(mtc0_watchhi
, arg
, sel
);
6154 goto cp0_unimplemented
;
6160 #if defined(TARGET_MIPS64)
6161 check_insn(ctx
, ISA_MIPS3
);
6162 gen_helper_mtc0_xcontext(cpu_env
, arg
);
6167 goto cp0_unimplemented
;
6171 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6172 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
6175 gen_helper_mtc0_framemask(cpu_env
, arg
);
6179 goto cp0_unimplemented
;
6184 rn
= "Diagnostic"; /* implementation dependent */
6189 gen_helper_mtc0_debug(cpu_env
, arg
); /* EJTAG support */
6190 /* BS_STOP isn't good enough here, hflags may have changed. */
6191 gen_save_pc(ctx
->pc
+ 4);
6192 ctx
->bstate
= BS_EXCP
;
6196 // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
6197 rn
= "TraceControl";
6198 /* Stop translation as we may have switched the execution mode */
6199 ctx
->bstate
= BS_STOP
;
6202 // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
6203 rn
= "TraceControl2";
6204 /* Stop translation as we may have switched the execution mode */
6205 ctx
->bstate
= BS_STOP
;
6208 /* Stop translation as we may have switched the execution mode */
6209 ctx
->bstate
= BS_STOP
;
6210 // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
6211 rn
= "UserTraceData";
6212 /* Stop translation as we may have switched the execution mode */
6213 ctx
->bstate
= BS_STOP
;
6216 // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
6217 /* Stop translation as we may have switched the execution mode */
6218 ctx
->bstate
= BS_STOP
;
6222 goto cp0_unimplemented
;
6229 gen_mtc0_store64(arg
, offsetof(CPUMIPSState
, CP0_DEPC
));
6233 goto cp0_unimplemented
;
6239 gen_helper_mtc0_performance0(cpu_env
, arg
);
6240 rn
= "Performance0";
6243 // gen_helper_mtc0_performance1(arg);
6244 rn
= "Performance1";
6247 // gen_helper_mtc0_performance2(arg);
6248 rn
= "Performance2";
6251 // gen_helper_mtc0_performance3(arg);
6252 rn
= "Performance3";
6255 // gen_helper_mtc0_performance4(arg);
6256 rn
= "Performance4";
6259 // gen_helper_mtc0_performance5(arg);
6260 rn
= "Performance5";
6263 // gen_helper_mtc0_performance6(arg);
6264 rn
= "Performance6";
6267 // gen_helper_mtc0_performance7(arg);
6268 rn
= "Performance7";
6271 goto cp0_unimplemented
;
6285 goto cp0_unimplemented
;
6294 gen_helper_mtc0_taglo(cpu_env
, arg
);
6301 gen_helper_mtc0_datalo(cpu_env
, arg
);
6305 goto cp0_unimplemented
;
6314 gen_helper_mtc0_taghi(cpu_env
, arg
);
6321 gen_helper_mtc0_datahi(cpu_env
, arg
);
6326 goto cp0_unimplemented
;
6332 gen_mtc0_store64(arg
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
6336 goto cp0_unimplemented
;
6343 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
6347 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
6348 tcg_gen_st_tl(arg
, cpu_env
,
6349 offsetof(CPUMIPSState
, CP0_KScratch
[sel
-2]));
6353 goto cp0_unimplemented
;
6355 /* Stop translation as we may have switched the execution mode */
6356 ctx
->bstate
= BS_STOP
;
6359 goto cp0_unimplemented
;
6361 (void)rn
; /* avoid a compiler warning */
6362 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
6363 /* For simplicity assume that all writes can cause interrupts. */
6364 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
6366 ctx
->bstate
= BS_STOP
;
6371 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
6374 #if defined(TARGET_MIPS64)
6375 static void gen_dmfc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
6377 const char *rn
= "invalid";
6380 check_insn(ctx
, ISA_MIPS64
);
6386 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Index
));
6390 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6391 gen_helper_mfc0_mvpcontrol(arg
, cpu_env
);
6395 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6396 gen_helper_mfc0_mvpconf0(arg
, cpu_env
);
6400 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6401 gen_helper_mfc0_mvpconf1(arg
, cpu_env
);
6405 goto cp0_unimplemented
;
6411 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
6412 gen_helper_mfc0_random(arg
, cpu_env
);
6416 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6417 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEControl
));
6421 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6422 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf0
));
6426 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6427 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEConf1
));
6431 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6432 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_YQMask
));
6436 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6437 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_VPESchedule
));
6441 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6442 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
6443 rn
= "VPEScheFBack";
6446 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6447 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_VPEOpt
));
6451 goto cp0_unimplemented
;
6457 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryLo0
));
6461 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6462 gen_helper_mfc0_tcstatus(arg
, cpu_env
);
6466 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6467 gen_helper_mfc0_tcbind(arg
, cpu_env
);
6471 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6472 gen_helper_dmfc0_tcrestart(arg
, cpu_env
);
6476 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6477 gen_helper_dmfc0_tchalt(arg
, cpu_env
);
6481 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6482 gen_helper_dmfc0_tccontext(arg
, cpu_env
);
6486 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6487 gen_helper_dmfc0_tcschedule(arg
, cpu_env
);
6491 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6492 gen_helper_dmfc0_tcschefback(arg
, cpu_env
);
6496 goto cp0_unimplemented
;
6502 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryLo1
));
6506 goto cp0_unimplemented
;
6512 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_Context
));
6516 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
6517 rn
= "ContextConfig";
6518 goto cp0_unimplemented
;
6521 CP0_CHECK(ctx
->ulri
);
6522 tcg_gen_ld_tl(arg
, cpu_env
,
6523 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
6527 goto cp0_unimplemented
;
6533 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageMask
));
6537 check_insn(ctx
, ISA_MIPS32R2
);
6538 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PageGrain
));
6542 goto cp0_unimplemented
;
6548 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Wired
));
6552 check_insn(ctx
, ISA_MIPS32R2
);
6553 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf0
));
6557 check_insn(ctx
, ISA_MIPS32R2
);
6558 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf1
));
6562 check_insn(ctx
, ISA_MIPS32R2
);
6563 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf2
));
6567 check_insn(ctx
, ISA_MIPS32R2
);
6568 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf3
));
6572 check_insn(ctx
, ISA_MIPS32R2
);
6573 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSConf4
));
6577 goto cp0_unimplemented
;
6583 check_insn(ctx
, ISA_MIPS32R2
);
6584 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_HWREna
));
6588 goto cp0_unimplemented
;
6594 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_BadVAddr
));
6599 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstr
));
6604 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_BadInstrP
));
6608 goto cp0_unimplemented
;
6614 /* Mark as an IO operation because we read the time. */
6615 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
6618 gen_helper_mfc0_count(arg
, cpu_env
);
6619 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
6622 /* Break the TB to be able to take timer interrupts immediately
6623 after reading count. */
6624 ctx
->bstate
= BS_STOP
;
6627 /* 6,7 are implementation dependent */
6629 goto cp0_unimplemented
;
6635 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EntryHi
));
6639 goto cp0_unimplemented
;
6645 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Compare
));
6648 /* 6,7 are implementation dependent */
6650 goto cp0_unimplemented
;
6656 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Status
));
6660 check_insn(ctx
, ISA_MIPS32R2
);
6661 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_IntCtl
));
6665 check_insn(ctx
, ISA_MIPS32R2
);
6666 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSCtl
));
6670 check_insn(ctx
, ISA_MIPS32R2
);
6671 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
6675 goto cp0_unimplemented
;
6681 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Cause
));
6685 goto cp0_unimplemented
;
6691 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
6695 goto cp0_unimplemented
;
6701 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_PRid
));
6705 check_insn(ctx
, ISA_MIPS32R2
);
6706 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_EBase
));
6710 goto cp0_unimplemented
;
6716 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config0
));
6720 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config1
));
6724 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config2
));
6728 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config3
));
6732 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config4
));
6736 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config5
));
6739 /* 6,7 are implementation dependent */
6741 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config6
));
6745 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Config7
));
6749 goto cp0_unimplemented
;
6755 gen_helper_dmfc0_lladdr(arg
, cpu_env
);
6759 goto cp0_unimplemented
;
6765 gen_helper_1e0i(dmfc0_watchlo
, arg
, sel
);
6769 goto cp0_unimplemented
;
6775 gen_helper_1e0i(mfc0_watchhi
, arg
, sel
);
6779 goto cp0_unimplemented
;
6785 check_insn(ctx
, ISA_MIPS3
);
6786 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_XContext
));
6790 goto cp0_unimplemented
;
6794 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6795 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
6798 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Framemask
));
6802 goto cp0_unimplemented
;
6806 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
6807 rn
= "'Diagnostic"; /* implementation dependent */
6812 gen_helper_mfc0_debug(arg
, cpu_env
); /* EJTAG support */
6816 // gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
6817 rn
= "TraceControl";
6820 // gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
6821 rn
= "TraceControl2";
6824 // gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
6825 rn
= "UserTraceData";
6828 // gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
6832 goto cp0_unimplemented
;
6839 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
6843 goto cp0_unimplemented
;
6849 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_Performance0
));
6850 rn
= "Performance0";
6853 // gen_helper_dmfc0_performance1(arg);
6854 rn
= "Performance1";
6857 // gen_helper_dmfc0_performance2(arg);
6858 rn
= "Performance2";
6861 // gen_helper_dmfc0_performance3(arg);
6862 rn
= "Performance3";
6865 // gen_helper_dmfc0_performance4(arg);
6866 rn
= "Performance4";
6869 // gen_helper_dmfc0_performance5(arg);
6870 rn
= "Performance5";
6873 // gen_helper_dmfc0_performance6(arg);
6874 rn
= "Performance6";
6877 // gen_helper_dmfc0_performance7(arg);
6878 rn
= "Performance7";
6881 goto cp0_unimplemented
;
6885 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
6892 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
6896 goto cp0_unimplemented
;
6905 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_TagLo
));
6912 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataLo
));
6916 goto cp0_unimplemented
;
6925 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_TagHi
));
6932 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DataHi
));
6936 goto cp0_unimplemented
;
6942 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
6946 goto cp0_unimplemented
;
6953 gen_mfc0_load32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
6957 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
6958 tcg_gen_ld_tl(arg
, cpu_env
,
6959 offsetof(CPUMIPSState
, CP0_KScratch
[sel
-2]));
6963 goto cp0_unimplemented
;
6967 goto cp0_unimplemented
;
6969 (void)rn
; /* avoid a compiler warning */
6970 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
6974 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
6975 gen_mfc0_unimplemented(ctx
, arg
);
6978 static void gen_dmtc0(DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
6980 const char *rn
= "invalid";
6983 check_insn(ctx
, ISA_MIPS64
);
6985 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
6993 gen_helper_mtc0_index(cpu_env
, arg
);
6997 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
6998 gen_helper_mtc0_mvpcontrol(cpu_env
, arg
);
7002 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7007 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7012 goto cp0_unimplemented
;
7022 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7023 gen_helper_mtc0_vpecontrol(cpu_env
, arg
);
7027 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7028 gen_helper_mtc0_vpeconf0(cpu_env
, arg
);
7032 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7033 gen_helper_mtc0_vpeconf1(cpu_env
, arg
);
7037 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7038 gen_helper_mtc0_yqmask(cpu_env
, arg
);
7042 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7043 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_VPESchedule
));
7047 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7048 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_VPEScheFBack
));
7049 rn
= "VPEScheFBack";
7052 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7053 gen_helper_mtc0_vpeopt(cpu_env
, arg
);
7057 goto cp0_unimplemented
;
7063 gen_helper_dmtc0_entrylo0(cpu_env
, arg
);
7067 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7068 gen_helper_mtc0_tcstatus(cpu_env
, arg
);
7072 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7073 gen_helper_mtc0_tcbind(cpu_env
, arg
);
7077 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7078 gen_helper_mtc0_tcrestart(cpu_env
, arg
);
7082 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7083 gen_helper_mtc0_tchalt(cpu_env
, arg
);
7087 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7088 gen_helper_mtc0_tccontext(cpu_env
, arg
);
7092 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7093 gen_helper_mtc0_tcschedule(cpu_env
, arg
);
7097 CP0_CHECK(ctx
->insn_flags
& ASE_MT
);
7098 gen_helper_mtc0_tcschefback(cpu_env
, arg
);
7102 goto cp0_unimplemented
;
7108 gen_helper_dmtc0_entrylo1(cpu_env
, arg
);
7112 goto cp0_unimplemented
;
7118 gen_helper_mtc0_context(cpu_env
, arg
);
7122 // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
7123 rn
= "ContextConfig";
7124 goto cp0_unimplemented
;
7127 CP0_CHECK(ctx
->ulri
);
7128 tcg_gen_st_tl(arg
, cpu_env
,
7129 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
7133 goto cp0_unimplemented
;
7139 gen_helper_mtc0_pagemask(cpu_env
, arg
);
7143 check_insn(ctx
, ISA_MIPS32R2
);
7144 gen_helper_mtc0_pagegrain(cpu_env
, arg
);
7148 goto cp0_unimplemented
;
7154 gen_helper_mtc0_wired(cpu_env
, arg
);
7158 check_insn(ctx
, ISA_MIPS32R2
);
7159 gen_helper_mtc0_srsconf0(cpu_env
, arg
);
7163 check_insn(ctx
, ISA_MIPS32R2
);
7164 gen_helper_mtc0_srsconf1(cpu_env
, arg
);
7168 check_insn(ctx
, ISA_MIPS32R2
);
7169 gen_helper_mtc0_srsconf2(cpu_env
, arg
);
7173 check_insn(ctx
, ISA_MIPS32R2
);
7174 gen_helper_mtc0_srsconf3(cpu_env
, arg
);
7178 check_insn(ctx
, ISA_MIPS32R2
);
7179 gen_helper_mtc0_srsconf4(cpu_env
, arg
);
7183 goto cp0_unimplemented
;
7189 check_insn(ctx
, ISA_MIPS32R2
);
7190 gen_helper_mtc0_hwrena(cpu_env
, arg
);
7191 ctx
->bstate
= BS_STOP
;
7195 goto cp0_unimplemented
;
7213 goto cp0_unimplemented
;
7219 gen_helper_mtc0_count(cpu_env
, arg
);
7222 /* 6,7 are implementation dependent */
7224 goto cp0_unimplemented
;
7226 /* Stop translation as we may have switched the execution mode */
7227 ctx
->bstate
= BS_STOP
;
7232 gen_helper_mtc0_entryhi(cpu_env
, arg
);
7236 goto cp0_unimplemented
;
7242 gen_helper_mtc0_compare(cpu_env
, arg
);
7245 /* 6,7 are implementation dependent */
7247 goto cp0_unimplemented
;
7249 /* Stop translation as we may have switched the execution mode */
7250 ctx
->bstate
= BS_STOP
;
7255 save_cpu_state(ctx
, 1);
7256 gen_helper_mtc0_status(cpu_env
, arg
);
7257 /* BS_STOP isn't good enough here, hflags may have changed. */
7258 gen_save_pc(ctx
->pc
+ 4);
7259 ctx
->bstate
= BS_EXCP
;
7263 check_insn(ctx
, ISA_MIPS32R2
);
7264 gen_helper_mtc0_intctl(cpu_env
, arg
);
7265 /* Stop translation as we may have switched the execution mode */
7266 ctx
->bstate
= BS_STOP
;
7270 check_insn(ctx
, ISA_MIPS32R2
);
7271 gen_helper_mtc0_srsctl(cpu_env
, arg
);
7272 /* Stop translation as we may have switched the execution mode */
7273 ctx
->bstate
= BS_STOP
;
7277 check_insn(ctx
, ISA_MIPS32R2
);
7278 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_SRSMap
));
7279 /* Stop translation as we may have switched the execution mode */
7280 ctx
->bstate
= BS_STOP
;
7284 goto cp0_unimplemented
;
7290 save_cpu_state(ctx
, 1);
7291 /* Mark as an IO operation because we may trigger a software
7293 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
7296 gen_helper_mtc0_cause(cpu_env
, arg
);
7297 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
7300 /* Stop translation as we may have triggered an intetrupt */
7301 ctx
->bstate
= BS_STOP
;
7305 goto cp0_unimplemented
;
7311 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_EPC
));
7315 goto cp0_unimplemented
;
7325 check_insn(ctx
, ISA_MIPS32R2
);
7326 gen_helper_mtc0_ebase(cpu_env
, arg
);
7330 goto cp0_unimplemented
;
7336 gen_helper_mtc0_config0(cpu_env
, arg
);
7338 /* Stop translation as we may have switched the execution mode */
7339 ctx
->bstate
= BS_STOP
;
7342 /* ignored, read only */
7346 gen_helper_mtc0_config2(cpu_env
, arg
);
7348 /* Stop translation as we may have switched the execution mode */
7349 ctx
->bstate
= BS_STOP
;
7352 gen_helper_mtc0_config3(cpu_env
, arg
);
7354 /* Stop translation as we may have switched the execution mode */
7355 ctx
->bstate
= BS_STOP
;
7358 /* currently ignored */
7362 gen_helper_mtc0_config5(cpu_env
, arg
);
7364 /* Stop translation as we may have switched the execution mode */
7365 ctx
->bstate
= BS_STOP
;
7367 /* 6,7 are implementation dependent */
7369 rn
= "Invalid config selector";
7370 goto cp0_unimplemented
;
7376 gen_helper_mtc0_lladdr(cpu_env
, arg
);
7380 goto cp0_unimplemented
;
7386 gen_helper_0e1i(mtc0_watchlo
, arg
, sel
);
7390 goto cp0_unimplemented
;
7396 gen_helper_0e1i(mtc0_watchhi
, arg
, sel
);
7400 goto cp0_unimplemented
;
7406 check_insn(ctx
, ISA_MIPS3
);
7407 gen_helper_mtc0_xcontext(cpu_env
, arg
);
7411 goto cp0_unimplemented
;
7415 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7416 CP0_CHECK(!(ctx
->insn_flags
& ISA_MIPS32R6
));
7419 gen_helper_mtc0_framemask(cpu_env
, arg
);
7423 goto cp0_unimplemented
;
7428 rn
= "Diagnostic"; /* implementation dependent */
7433 gen_helper_mtc0_debug(cpu_env
, arg
); /* EJTAG support */
7434 /* BS_STOP isn't good enough here, hflags may have changed. */
7435 gen_save_pc(ctx
->pc
+ 4);
7436 ctx
->bstate
= BS_EXCP
;
7440 // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
7441 /* Stop translation as we may have switched the execution mode */
7442 ctx
->bstate
= BS_STOP
;
7443 rn
= "TraceControl";
7446 // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
7447 /* Stop translation as we may have switched the execution mode */
7448 ctx
->bstate
= BS_STOP
;
7449 rn
= "TraceControl2";
7452 // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
7453 /* Stop translation as we may have switched the execution mode */
7454 ctx
->bstate
= BS_STOP
;
7455 rn
= "UserTraceData";
7458 // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
7459 /* Stop translation as we may have switched the execution mode */
7460 ctx
->bstate
= BS_STOP
;
7464 goto cp0_unimplemented
;
7471 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_DEPC
));
7475 goto cp0_unimplemented
;
7481 gen_helper_mtc0_performance0(cpu_env
, arg
);
7482 rn
= "Performance0";
7485 // gen_helper_mtc0_performance1(cpu_env, arg);
7486 rn
= "Performance1";
7489 // gen_helper_mtc0_performance2(cpu_env, arg);
7490 rn
= "Performance2";
7493 // gen_helper_mtc0_performance3(cpu_env, arg);
7494 rn
= "Performance3";
7497 // gen_helper_mtc0_performance4(cpu_env, arg);
7498 rn
= "Performance4";
7501 // gen_helper_mtc0_performance5(cpu_env, arg);
7502 rn
= "Performance5";
7505 // gen_helper_mtc0_performance6(cpu_env, arg);
7506 rn
= "Performance6";
7509 // gen_helper_mtc0_performance7(cpu_env, arg);
7510 rn
= "Performance7";
7513 goto cp0_unimplemented
;
7527 goto cp0_unimplemented
;
7536 gen_helper_mtc0_taglo(cpu_env
, arg
);
7543 gen_helper_mtc0_datalo(cpu_env
, arg
);
7547 goto cp0_unimplemented
;
7556 gen_helper_mtc0_taghi(cpu_env
, arg
);
7563 gen_helper_mtc0_datahi(cpu_env
, arg
);
7568 goto cp0_unimplemented
;
7574 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUMIPSState
, CP0_ErrorEPC
));
7578 goto cp0_unimplemented
;
7585 gen_mtc0_store32(arg
, offsetof(CPUMIPSState
, CP0_DESAVE
));
7589 CP0_CHECK(ctx
->kscrexist
& (1 << sel
));
7590 tcg_gen_st_tl(arg
, cpu_env
,
7591 offsetof(CPUMIPSState
, CP0_KScratch
[sel
-2]));
7595 goto cp0_unimplemented
;
7597 /* Stop translation as we may have switched the execution mode */
7598 ctx
->bstate
= BS_STOP
;
7601 goto cp0_unimplemented
;
7603 (void)rn
; /* avoid a compiler warning */
7604 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
7605 /* For simplicity assume that all writes can cause interrupts. */
7606 if (ctx
->tb
->cflags
& CF_USE_ICOUNT
) {
7608 ctx
->bstate
= BS_STOP
;
7613 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
7615 #endif /* TARGET_MIPS64 */
7617 static void gen_mftr(CPUMIPSState
*env
, DisasContext
*ctx
, int rt
, int rd
,
7618 int u
, int sel
, int h
)
7620 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
7621 TCGv t0
= tcg_temp_local_new();
7623 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
7624 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
7625 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
7626 tcg_gen_movi_tl(t0
, -1);
7627 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
7628 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
7629 tcg_gen_movi_tl(t0
, -1);
7635 gen_helper_mftc0_vpecontrol(t0
, cpu_env
);
7638 gen_helper_mftc0_vpeconf0(t0
, cpu_env
);
7648 gen_helper_mftc0_tcstatus(t0
, cpu_env
);
7651 gen_helper_mftc0_tcbind(t0
, cpu_env
);
7654 gen_helper_mftc0_tcrestart(t0
, cpu_env
);
7657 gen_helper_mftc0_tchalt(t0
, cpu_env
);
7660 gen_helper_mftc0_tccontext(t0
, cpu_env
);
7663 gen_helper_mftc0_tcschedule(t0
, cpu_env
);
7666 gen_helper_mftc0_tcschefback(t0
, cpu_env
);
7669 gen_mfc0(ctx
, t0
, rt
, sel
);
7676 gen_helper_mftc0_entryhi(t0
, cpu_env
);
7679 gen_mfc0(ctx
, t0
, rt
, sel
);
7685 gen_helper_mftc0_status(t0
, cpu_env
);
7688 gen_mfc0(ctx
, t0
, rt
, sel
);
7694 gen_helper_mftc0_cause(t0
, cpu_env
);
7704 gen_helper_mftc0_epc(t0
, cpu_env
);
7714 gen_helper_mftc0_ebase(t0
, cpu_env
);
7724 gen_helper_mftc0_configx(t0
, cpu_env
, tcg_const_tl(sel
));
7734 gen_helper_mftc0_debug(t0
, cpu_env
);
7737 gen_mfc0(ctx
, t0
, rt
, sel
);
7742 gen_mfc0(ctx
, t0
, rt
, sel
);
7744 } else switch (sel
) {
7745 /* GPR registers. */
7747 gen_helper_1e0i(mftgpr
, t0
, rt
);
7749 /* Auxiliary CPU registers */
7753 gen_helper_1e0i(mftlo
, t0
, 0);
7756 gen_helper_1e0i(mfthi
, t0
, 0);
7759 gen_helper_1e0i(mftacx
, t0
, 0);
7762 gen_helper_1e0i(mftlo
, t0
, 1);
7765 gen_helper_1e0i(mfthi
, t0
, 1);
7768 gen_helper_1e0i(mftacx
, t0
, 1);
7771 gen_helper_1e0i(mftlo
, t0
, 2);
7774 gen_helper_1e0i(mfthi
, t0
, 2);
7777 gen_helper_1e0i(mftacx
, t0
, 2);
7780 gen_helper_1e0i(mftlo
, t0
, 3);
7783 gen_helper_1e0i(mfthi
, t0
, 3);
7786 gen_helper_1e0i(mftacx
, t0
, 3);
7789 gen_helper_mftdsp(t0
, cpu_env
);
7795 /* Floating point (COP1). */
7797 /* XXX: For now we support only a single FPU context. */
7799 TCGv_i32 fp0
= tcg_temp_new_i32();
7801 gen_load_fpr32(ctx
, fp0
, rt
);
7802 tcg_gen_ext_i32_tl(t0
, fp0
);
7803 tcg_temp_free_i32(fp0
);
7805 TCGv_i32 fp0
= tcg_temp_new_i32();
7807 gen_load_fpr32h(ctx
, fp0
, rt
);
7808 tcg_gen_ext_i32_tl(t0
, fp0
);
7809 tcg_temp_free_i32(fp0
);
7813 /* XXX: For now we support only a single FPU context. */
7814 gen_helper_1e0i(cfc1
, t0
, rt
);
7816 /* COP2: Not implemented. */
7823 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
7824 gen_store_gpr(t0
, rd
);
7830 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
7831 generate_exception(ctx
, EXCP_RI
);
7834 static void gen_mttr(CPUMIPSState
*env
, DisasContext
*ctx
, int rd
, int rt
,
7835 int u
, int sel
, int h
)
7837 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
7838 TCGv t0
= tcg_temp_local_new();
7840 gen_load_gpr(t0
, rt
);
7841 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
7842 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
7843 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
7845 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
7846 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
7853 gen_helper_mttc0_vpecontrol(cpu_env
, t0
);
7856 gen_helper_mttc0_vpeconf0(cpu_env
, t0
);
7866 gen_helper_mttc0_tcstatus(cpu_env
, t0
);
7869 gen_helper_mttc0_tcbind(cpu_env
, t0
);
7872 gen_helper_mttc0_tcrestart(cpu_env
, t0
);
7875 gen_helper_mttc0_tchalt(cpu_env
, t0
);
7878 gen_helper_mttc0_tccontext(cpu_env
, t0
);
7881 gen_helper_mttc0_tcschedule(cpu_env
, t0
);
7884 gen_helper_mttc0_tcschefback(cpu_env
, t0
);
7887 gen_mtc0(ctx
, t0
, rd
, sel
);
7894 gen_helper_mttc0_entryhi(cpu_env
, t0
);
7897 gen_mtc0(ctx
, t0
, rd
, sel
);
7903 gen_helper_mttc0_status(cpu_env
, t0
);
7906 gen_mtc0(ctx
, t0
, rd
, sel
);
7912 gen_helper_mttc0_cause(cpu_env
, t0
);
7922 gen_helper_mttc0_ebase(cpu_env
, t0
);
7932 gen_helper_mttc0_debug(cpu_env
, t0
);
7935 gen_mtc0(ctx
, t0
, rd
, sel
);
7940 gen_mtc0(ctx
, t0
, rd
, sel
);
7942 } else switch (sel
) {
7943 /* GPR registers. */
7945 gen_helper_0e1i(mttgpr
, t0
, rd
);
7947 /* Auxiliary CPU registers */
7951 gen_helper_0e1i(mttlo
, t0
, 0);
7954 gen_helper_0e1i(mtthi
, t0
, 0);
7957 gen_helper_0e1i(mttacx
, t0
, 0);
7960 gen_helper_0e1i(mttlo
, t0
, 1);
7963 gen_helper_0e1i(mtthi
, t0
, 1);
7966 gen_helper_0e1i(mttacx
, t0
, 1);
7969 gen_helper_0e1i(mttlo
, t0
, 2);
7972 gen_helper_0e1i(mtthi
, t0
, 2);
7975 gen_helper_0e1i(mttacx
, t0
, 2);
7978 gen_helper_0e1i(mttlo
, t0
, 3);
7981 gen_helper_0e1i(mtthi
, t0
, 3);
7984 gen_helper_0e1i(mttacx
, t0
, 3);
7987 gen_helper_mttdsp(cpu_env
, t0
);
7993 /* Floating point (COP1). */
7995 /* XXX: For now we support only a single FPU context. */
7997 TCGv_i32 fp0
= tcg_temp_new_i32();
7999 tcg_gen_trunc_tl_i32(fp0
, t0
);
8000 gen_store_fpr32(ctx
, fp0
, rd
);
8001 tcg_temp_free_i32(fp0
);
8003 TCGv_i32 fp0
= tcg_temp_new_i32();
8005 tcg_gen_trunc_tl_i32(fp0
, t0
);
8006 gen_store_fpr32h(ctx
, fp0
, rd
);
8007 tcg_temp_free_i32(fp0
);
8011 /* XXX: For now we support only a single FPU context. */
8012 save_cpu_state(ctx
, 1);
8014 TCGv_i32 fs_tmp
= tcg_const_i32(rd
);
8016 gen_helper_0e2i(ctc1
, t0
, fs_tmp
, rt
);
8017 tcg_temp_free_i32(fs_tmp
);
8019 /* Stop translation as we may have changed hflags */
8020 ctx
->bstate
= BS_STOP
;
8022 /* COP2: Not implemented. */
8029 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
8035 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
8036 generate_exception(ctx
, EXCP_RI
);
8039 static void gen_cp0 (CPUMIPSState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
8041 const char *opn
= "ldst";
8043 check_cp0_enabled(ctx
);
8050 gen_mfc0(ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
8055 TCGv t0
= tcg_temp_new();
8057 gen_load_gpr(t0
, rt
);
8058 gen_mtc0(ctx
, t0
, rd
, ctx
->opcode
& 0x7);
8063 #if defined(TARGET_MIPS64)
8065 check_insn(ctx
, ISA_MIPS3
);
8070 gen_dmfc0(ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
8074 check_insn(ctx
, ISA_MIPS3
);
8076 TCGv t0
= tcg_temp_new();
8078 gen_load_gpr(t0
, rt
);
8079 gen_dmtc0(ctx
, t0
, rd
, ctx
->opcode
& 0x7);
8091 gen_mfhc0(ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
8097 TCGv t0
= tcg_temp_new();
8098 gen_load_gpr(t0
, rt
);
8099 gen_mthc0(ctx
, t0
, rd
, ctx
->opcode
& 0x7);
8105 check_insn(ctx
, ASE_MT
);
8110 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
8111 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
8115 check_insn(ctx
, ASE_MT
);
8116 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
8117 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
8122 if (!env
->tlb
->helper_tlbwi
)
8124 gen_helper_tlbwi(cpu_env
);
8129 if (!env
->tlb
->helper_tlbinv
) {
8132 gen_helper_tlbinv(cpu_env
);
8133 } /* treat as nop if TLBINV not supported */
8138 if (!env
->tlb
->helper_tlbinvf
) {
8141 gen_helper_tlbinvf(cpu_env
);
8142 } /* treat as nop if TLBINV not supported */
8146 if (!env
->tlb
->helper_tlbwr
)
8148 gen_helper_tlbwr(cpu_env
);
8152 if (!env
->tlb
->helper_tlbp
)
8154 gen_helper_tlbp(cpu_env
);
8158 if (!env
->tlb
->helper_tlbr
)
8160 gen_helper_tlbr(cpu_env
);
8162 case OPC_ERET
: /* OPC_ERETNC */
8163 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
8164 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8165 MIPS_DEBUG("CTI in delay / forbidden slot");
8168 int bit_shift
= (ctx
->hflags
& MIPS_HFLAG_M16
) ? 16 : 6;
8169 if (ctx
->opcode
& (1 << bit_shift
)) {
8172 check_insn(ctx
, ISA_MIPS32R5
);
8173 gen_helper_eretnc(cpu_env
);
8177 check_insn(ctx
, ISA_MIPS2
);
8178 gen_helper_eret(cpu_env
);
8180 ctx
->bstate
= BS_EXCP
;
8185 check_insn(ctx
, ISA_MIPS32
);
8186 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
8187 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8188 MIPS_DEBUG("CTI in delay / forbidden slot");
8191 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
8193 generate_exception(ctx
, EXCP_RI
);
8195 gen_helper_deret(cpu_env
);
8196 ctx
->bstate
= BS_EXCP
;
8201 check_insn(ctx
, ISA_MIPS3
| ISA_MIPS32
);
8202 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
8203 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8204 MIPS_DEBUG("CTI in delay / forbidden slot");
8207 /* If we get an exception, we want to restart at next instruction */
8209 save_cpu_state(ctx
, 1);
8211 gen_helper_wait(cpu_env
);
8212 ctx
->bstate
= BS_EXCP
;
8217 generate_exception(ctx
, EXCP_RI
);
8220 (void)opn
; /* avoid a compiler warning */
8221 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
8223 #endif /* !CONFIG_USER_ONLY */
8225 /* CP1 Branches (before delay slot) */
8226 static void gen_compute_branch1(DisasContext
*ctx
, uint32_t op
,
8227 int32_t cc
, int32_t offset
)
8229 target_ulong btarget
;
8230 const char *opn
= "cp1 cond branch";
8231 TCGv_i32 t0
= tcg_temp_new_i32();
8233 if ((ctx
->insn_flags
& ISA_MIPS32R6
) && (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8234 MIPS_DEBUG("CTI in delay / forbidden slot");
8235 generate_exception(ctx
, EXCP_RI
);
8240 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
);
8242 btarget
= ctx
->pc
+ 4 + offset
;
8246 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8247 tcg_gen_not_i32(t0
, t0
);
8248 tcg_gen_andi_i32(t0
, t0
, 1);
8249 tcg_gen_extu_i32_tl(bcond
, t0
);
8253 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8254 tcg_gen_not_i32(t0
, t0
);
8255 tcg_gen_andi_i32(t0
, t0
, 1);
8256 tcg_gen_extu_i32_tl(bcond
, t0
);
8260 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8261 tcg_gen_andi_i32(t0
, t0
, 1);
8262 tcg_gen_extu_i32_tl(bcond
, t0
);
8266 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8267 tcg_gen_andi_i32(t0
, t0
, 1);
8268 tcg_gen_extu_i32_tl(bcond
, t0
);
8271 ctx
->hflags
|= MIPS_HFLAG_BL
;
8275 TCGv_i32 t1
= tcg_temp_new_i32();
8276 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8277 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
8278 tcg_gen_nand_i32(t0
, t0
, t1
);
8279 tcg_temp_free_i32(t1
);
8280 tcg_gen_andi_i32(t0
, t0
, 1);
8281 tcg_gen_extu_i32_tl(bcond
, t0
);
8287 TCGv_i32 t1
= tcg_temp_new_i32();
8288 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8289 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
8290 tcg_gen_or_i32(t0
, t0
, t1
);
8291 tcg_temp_free_i32(t1
);
8292 tcg_gen_andi_i32(t0
, t0
, 1);
8293 tcg_gen_extu_i32_tl(bcond
, t0
);
8299 TCGv_i32 t1
= tcg_temp_new_i32();
8300 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8301 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
8302 tcg_gen_and_i32(t0
, t0
, t1
);
8303 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
8304 tcg_gen_and_i32(t0
, t0
, t1
);
8305 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
8306 tcg_gen_nand_i32(t0
, t0
, t1
);
8307 tcg_temp_free_i32(t1
);
8308 tcg_gen_andi_i32(t0
, t0
, 1);
8309 tcg_gen_extu_i32_tl(bcond
, t0
);
8315 TCGv_i32 t1
= tcg_temp_new_i32();
8316 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
8317 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
8318 tcg_gen_or_i32(t0
, t0
, t1
);
8319 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
8320 tcg_gen_or_i32(t0
, t0
, t1
);
8321 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
8322 tcg_gen_or_i32(t0
, t0
, t1
);
8323 tcg_temp_free_i32(t1
);
8324 tcg_gen_andi_i32(t0
, t0
, 1);
8325 tcg_gen_extu_i32_tl(bcond
, t0
);
8329 ctx
->hflags
|= MIPS_HFLAG_BC
;
8333 generate_exception (ctx
, EXCP_RI
);
8336 (void)opn
; /* avoid a compiler warning */
8337 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
8338 ctx
->hflags
, btarget
);
8339 ctx
->btarget
= btarget
;
8340 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
8342 tcg_temp_free_i32(t0
);
8345 /* R6 CP1 Branches */
8346 static void gen_compute_branch1_r6(DisasContext
*ctx
, uint32_t op
,
8347 int32_t ft
, int32_t offset
)
8349 target_ulong btarget
;
8350 const char *opn
= "cp1 cond branch";
8351 TCGv_i64 t0
= tcg_temp_new_i64();
8353 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8354 #ifdef MIPS_DEBUG_DISAS
8355 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
8358 generate_exception(ctx
, EXCP_RI
);
8362 gen_load_fpr64(ctx
, t0
, ft
);
8363 tcg_gen_andi_i64(t0
, t0
, 1);
8365 btarget
= addr_add(ctx
, ctx
->pc
+ 4, offset
);
8369 tcg_gen_xori_i64(t0
, t0
, 1);
8371 ctx
->hflags
|= MIPS_HFLAG_BC
;
8374 /* t0 already set */
8376 ctx
->hflags
|= MIPS_HFLAG_BC
;
8380 generate_exception(ctx
, EXCP_RI
);
8384 tcg_gen_trunc_i64_tl(bcond
, t0
);
8386 (void)opn
; /* avoid a compiler warning */
8387 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
8388 ctx
->hflags
, btarget
);
8389 ctx
->btarget
= btarget
;
8390 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
8393 tcg_temp_free_i64(t0
);
8396 /* Coprocessor 1 (FPU) */
8398 #define FOP(func, fmt) (((fmt) << 21) | (func))
8401 OPC_ADD_S
= FOP(0, FMT_S
),
8402 OPC_SUB_S
= FOP(1, FMT_S
),
8403 OPC_MUL_S
= FOP(2, FMT_S
),
8404 OPC_DIV_S
= FOP(3, FMT_S
),
8405 OPC_SQRT_S
= FOP(4, FMT_S
),
8406 OPC_ABS_S
= FOP(5, FMT_S
),
8407 OPC_MOV_S
= FOP(6, FMT_S
),
8408 OPC_NEG_S
= FOP(7, FMT_S
),
8409 OPC_ROUND_L_S
= FOP(8, FMT_S
),
8410 OPC_TRUNC_L_S
= FOP(9, FMT_S
),
8411 OPC_CEIL_L_S
= FOP(10, FMT_S
),
8412 OPC_FLOOR_L_S
= FOP(11, FMT_S
),
8413 OPC_ROUND_W_S
= FOP(12, FMT_S
),
8414 OPC_TRUNC_W_S
= FOP(13, FMT_S
),
8415 OPC_CEIL_W_S
= FOP(14, FMT_S
),
8416 OPC_FLOOR_W_S
= FOP(15, FMT_S
),
8417 OPC_SEL_S
= FOP(16, FMT_S
),
8418 OPC_MOVCF_S
= FOP(17, FMT_S
),
8419 OPC_MOVZ_S
= FOP(18, FMT_S
),
8420 OPC_MOVN_S
= FOP(19, FMT_S
),
8421 OPC_SELEQZ_S
= FOP(20, FMT_S
),
8422 OPC_RECIP_S
= FOP(21, FMT_S
),
8423 OPC_RSQRT_S
= FOP(22, FMT_S
),
8424 OPC_SELNEZ_S
= FOP(23, FMT_S
),
8425 OPC_MADDF_S
= FOP(24, FMT_S
),
8426 OPC_MSUBF_S
= FOP(25, FMT_S
),
8427 OPC_RINT_S
= FOP(26, FMT_S
),
8428 OPC_CLASS_S
= FOP(27, FMT_S
),
8429 OPC_MIN_S
= FOP(28, FMT_S
),
8430 OPC_RECIP2_S
= FOP(28, FMT_S
),
8431 OPC_MINA_S
= FOP(29, FMT_S
),
8432 OPC_RECIP1_S
= FOP(29, FMT_S
),
8433 OPC_MAX_S
= FOP(30, FMT_S
),
8434 OPC_RSQRT1_S
= FOP(30, FMT_S
),
8435 OPC_MAXA_S
= FOP(31, FMT_S
),
8436 OPC_RSQRT2_S
= FOP(31, FMT_S
),
8437 OPC_CVT_D_S
= FOP(33, FMT_S
),
8438 OPC_CVT_W_S
= FOP(36, FMT_S
),
8439 OPC_CVT_L_S
= FOP(37, FMT_S
),
8440 OPC_CVT_PS_S
= FOP(38, FMT_S
),
8441 OPC_CMP_F_S
= FOP (48, FMT_S
),
8442 OPC_CMP_UN_S
= FOP (49, FMT_S
),
8443 OPC_CMP_EQ_S
= FOP (50, FMT_S
),
8444 OPC_CMP_UEQ_S
= FOP (51, FMT_S
),
8445 OPC_CMP_OLT_S
= FOP (52, FMT_S
),
8446 OPC_CMP_ULT_S
= FOP (53, FMT_S
),
8447 OPC_CMP_OLE_S
= FOP (54, FMT_S
),
8448 OPC_CMP_ULE_S
= FOP (55, FMT_S
),
8449 OPC_CMP_SF_S
= FOP (56, FMT_S
),
8450 OPC_CMP_NGLE_S
= FOP (57, FMT_S
),
8451 OPC_CMP_SEQ_S
= FOP (58, FMT_S
),
8452 OPC_CMP_NGL_S
= FOP (59, FMT_S
),
8453 OPC_CMP_LT_S
= FOP (60, FMT_S
),
8454 OPC_CMP_NGE_S
= FOP (61, FMT_S
),
8455 OPC_CMP_LE_S
= FOP (62, FMT_S
),
8456 OPC_CMP_NGT_S
= FOP (63, FMT_S
),
8458 OPC_ADD_D
= FOP(0, FMT_D
),
8459 OPC_SUB_D
= FOP(1, FMT_D
),
8460 OPC_MUL_D
= FOP(2, FMT_D
),
8461 OPC_DIV_D
= FOP(3, FMT_D
),
8462 OPC_SQRT_D
= FOP(4, FMT_D
),
8463 OPC_ABS_D
= FOP(5, FMT_D
),
8464 OPC_MOV_D
= FOP(6, FMT_D
),
8465 OPC_NEG_D
= FOP(7, FMT_D
),
8466 OPC_ROUND_L_D
= FOP(8, FMT_D
),
8467 OPC_TRUNC_L_D
= FOP(9, FMT_D
),
8468 OPC_CEIL_L_D
= FOP(10, FMT_D
),
8469 OPC_FLOOR_L_D
= FOP(11, FMT_D
),
8470 OPC_ROUND_W_D
= FOP(12, FMT_D
),
8471 OPC_TRUNC_W_D
= FOP(13, FMT_D
),
8472 OPC_CEIL_W_D
= FOP(14, FMT_D
),
8473 OPC_FLOOR_W_D
= FOP(15, FMT_D
),
8474 OPC_SEL_D
= FOP(16, FMT_D
),
8475 OPC_MOVCF_D
= FOP(17, FMT_D
),
8476 OPC_MOVZ_D
= FOP(18, FMT_D
),
8477 OPC_MOVN_D
= FOP(19, FMT_D
),
8478 OPC_SELEQZ_D
= FOP(20, FMT_D
),
8479 OPC_RECIP_D
= FOP(21, FMT_D
),
8480 OPC_RSQRT_D
= FOP(22, FMT_D
),
8481 OPC_SELNEZ_D
= FOP(23, FMT_D
),
8482 OPC_MADDF_D
= FOP(24, FMT_D
),
8483 OPC_MSUBF_D
= FOP(25, FMT_D
),
8484 OPC_RINT_D
= FOP(26, FMT_D
),
8485 OPC_CLASS_D
= FOP(27, FMT_D
),
8486 OPC_MIN_D
= FOP(28, FMT_D
),
8487 OPC_RECIP2_D
= FOP(28, FMT_D
),
8488 OPC_MINA_D
= FOP(29, FMT_D
),
8489 OPC_RECIP1_D
= FOP(29, FMT_D
),
8490 OPC_MAX_D
= FOP(30, FMT_D
),
8491 OPC_RSQRT1_D
= FOP(30, FMT_D
),
8492 OPC_MAXA_D
= FOP(31, FMT_D
),
8493 OPC_RSQRT2_D
= FOP(31, FMT_D
),
8494 OPC_CVT_S_D
= FOP(32, FMT_D
),
8495 OPC_CVT_W_D
= FOP(36, FMT_D
),
8496 OPC_CVT_L_D
= FOP(37, FMT_D
),
8497 OPC_CMP_F_D
= FOP (48, FMT_D
),
8498 OPC_CMP_UN_D
= FOP (49, FMT_D
),
8499 OPC_CMP_EQ_D
= FOP (50, FMT_D
),
8500 OPC_CMP_UEQ_D
= FOP (51, FMT_D
),
8501 OPC_CMP_OLT_D
= FOP (52, FMT_D
),
8502 OPC_CMP_ULT_D
= FOP (53, FMT_D
),
8503 OPC_CMP_OLE_D
= FOP (54, FMT_D
),
8504 OPC_CMP_ULE_D
= FOP (55, FMT_D
),
8505 OPC_CMP_SF_D
= FOP (56, FMT_D
),
8506 OPC_CMP_NGLE_D
= FOP (57, FMT_D
),
8507 OPC_CMP_SEQ_D
= FOP (58, FMT_D
),
8508 OPC_CMP_NGL_D
= FOP (59, FMT_D
),
8509 OPC_CMP_LT_D
= FOP (60, FMT_D
),
8510 OPC_CMP_NGE_D
= FOP (61, FMT_D
),
8511 OPC_CMP_LE_D
= FOP (62, FMT_D
),
8512 OPC_CMP_NGT_D
= FOP (63, FMT_D
),
8514 OPC_CVT_S_W
= FOP(32, FMT_W
),
8515 OPC_CVT_D_W
= FOP(33, FMT_W
),
8516 OPC_CVT_S_L
= FOP(32, FMT_L
),
8517 OPC_CVT_D_L
= FOP(33, FMT_L
),
8518 OPC_CVT_PS_PW
= FOP(38, FMT_W
),
8520 OPC_ADD_PS
= FOP(0, FMT_PS
),
8521 OPC_SUB_PS
= FOP(1, FMT_PS
),
8522 OPC_MUL_PS
= FOP(2, FMT_PS
),
8523 OPC_DIV_PS
= FOP(3, FMT_PS
),
8524 OPC_ABS_PS
= FOP(5, FMT_PS
),
8525 OPC_MOV_PS
= FOP(6, FMT_PS
),
8526 OPC_NEG_PS
= FOP(7, FMT_PS
),
8527 OPC_MOVCF_PS
= FOP(17, FMT_PS
),
8528 OPC_MOVZ_PS
= FOP(18, FMT_PS
),
8529 OPC_MOVN_PS
= FOP(19, FMT_PS
),
8530 OPC_ADDR_PS
= FOP(24, FMT_PS
),
8531 OPC_MULR_PS
= FOP(26, FMT_PS
),
8532 OPC_RECIP2_PS
= FOP(28, FMT_PS
),
8533 OPC_RECIP1_PS
= FOP(29, FMT_PS
),
8534 OPC_RSQRT1_PS
= FOP(30, FMT_PS
),
8535 OPC_RSQRT2_PS
= FOP(31, FMT_PS
),
8537 OPC_CVT_S_PU
= FOP(32, FMT_PS
),
8538 OPC_CVT_PW_PS
= FOP(36, FMT_PS
),
8539 OPC_CVT_S_PL
= FOP(40, FMT_PS
),
8540 OPC_PLL_PS
= FOP(44, FMT_PS
),
8541 OPC_PLU_PS
= FOP(45, FMT_PS
),
8542 OPC_PUL_PS
= FOP(46, FMT_PS
),
8543 OPC_PUU_PS
= FOP(47, FMT_PS
),
8544 OPC_CMP_F_PS
= FOP (48, FMT_PS
),
8545 OPC_CMP_UN_PS
= FOP (49, FMT_PS
),
8546 OPC_CMP_EQ_PS
= FOP (50, FMT_PS
),
8547 OPC_CMP_UEQ_PS
= FOP (51, FMT_PS
),
8548 OPC_CMP_OLT_PS
= FOP (52, FMT_PS
),
8549 OPC_CMP_ULT_PS
= FOP (53, FMT_PS
),
8550 OPC_CMP_OLE_PS
= FOP (54, FMT_PS
),
8551 OPC_CMP_ULE_PS
= FOP (55, FMT_PS
),
8552 OPC_CMP_SF_PS
= FOP (56, FMT_PS
),
8553 OPC_CMP_NGLE_PS
= FOP (57, FMT_PS
),
8554 OPC_CMP_SEQ_PS
= FOP (58, FMT_PS
),
8555 OPC_CMP_NGL_PS
= FOP (59, FMT_PS
),
8556 OPC_CMP_LT_PS
= FOP (60, FMT_PS
),
8557 OPC_CMP_NGE_PS
= FOP (61, FMT_PS
),
8558 OPC_CMP_LE_PS
= FOP (62, FMT_PS
),
8559 OPC_CMP_NGT_PS
= FOP (63, FMT_PS
),
8563 R6_OPC_CMP_AF_S
= FOP(0, FMT_W
),
8564 R6_OPC_CMP_UN_S
= FOP(1, FMT_W
),
8565 R6_OPC_CMP_EQ_S
= FOP(2, FMT_W
),
8566 R6_OPC_CMP_UEQ_S
= FOP(3, FMT_W
),
8567 R6_OPC_CMP_LT_S
= FOP(4, FMT_W
),
8568 R6_OPC_CMP_ULT_S
= FOP(5, FMT_W
),
8569 R6_OPC_CMP_LE_S
= FOP(6, FMT_W
),
8570 R6_OPC_CMP_ULE_S
= FOP(7, FMT_W
),
8571 R6_OPC_CMP_SAF_S
= FOP(8, FMT_W
),
8572 R6_OPC_CMP_SUN_S
= FOP(9, FMT_W
),
8573 R6_OPC_CMP_SEQ_S
= FOP(10, FMT_W
),
8574 R6_OPC_CMP_SEUQ_S
= FOP(11, FMT_W
),
8575 R6_OPC_CMP_SLT_S
= FOP(12, FMT_W
),
8576 R6_OPC_CMP_SULT_S
= FOP(13, FMT_W
),
8577 R6_OPC_CMP_SLE_S
= FOP(14, FMT_W
),
8578 R6_OPC_CMP_SULE_S
= FOP(15, FMT_W
),
8579 R6_OPC_CMP_OR_S
= FOP(17, FMT_W
),
8580 R6_OPC_CMP_UNE_S
= FOP(18, FMT_W
),
8581 R6_OPC_CMP_NE_S
= FOP(19, FMT_W
),
8582 R6_OPC_CMP_SOR_S
= FOP(25, FMT_W
),
8583 R6_OPC_CMP_SUNE_S
= FOP(26, FMT_W
),
8584 R6_OPC_CMP_SNE_S
= FOP(27, FMT_W
),
8586 R6_OPC_CMP_AF_D
= FOP(0, FMT_L
),
8587 R6_OPC_CMP_UN_D
= FOP(1, FMT_L
),
8588 R6_OPC_CMP_EQ_D
= FOP(2, FMT_L
),
8589 R6_OPC_CMP_UEQ_D
= FOP(3, FMT_L
),
8590 R6_OPC_CMP_LT_D
= FOP(4, FMT_L
),
8591 R6_OPC_CMP_ULT_D
= FOP(5, FMT_L
),
8592 R6_OPC_CMP_LE_D
= FOP(6, FMT_L
),
8593 R6_OPC_CMP_ULE_D
= FOP(7, FMT_L
),
8594 R6_OPC_CMP_SAF_D
= FOP(8, FMT_L
),
8595 R6_OPC_CMP_SUN_D
= FOP(9, FMT_L
),
8596 R6_OPC_CMP_SEQ_D
= FOP(10, FMT_L
),
8597 R6_OPC_CMP_SEUQ_D
= FOP(11, FMT_L
),
8598 R6_OPC_CMP_SLT_D
= FOP(12, FMT_L
),
8599 R6_OPC_CMP_SULT_D
= FOP(13, FMT_L
),
8600 R6_OPC_CMP_SLE_D
= FOP(14, FMT_L
),
8601 R6_OPC_CMP_SULE_D
= FOP(15, FMT_L
),
8602 R6_OPC_CMP_OR_D
= FOP(17, FMT_L
),
8603 R6_OPC_CMP_UNE_D
= FOP(18, FMT_L
),
8604 R6_OPC_CMP_NE_D
= FOP(19, FMT_L
),
8605 R6_OPC_CMP_SOR_D
= FOP(25, FMT_L
),
8606 R6_OPC_CMP_SUNE_D
= FOP(26, FMT_L
),
8607 R6_OPC_CMP_SNE_D
= FOP(27, FMT_L
),
8609 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
8611 const char *opn
= "cp1 move";
8612 TCGv t0
= tcg_temp_new();
8617 TCGv_i32 fp0
= tcg_temp_new_i32();
8619 gen_load_fpr32(ctx
, fp0
, fs
);
8620 tcg_gen_ext_i32_tl(t0
, fp0
);
8621 tcg_temp_free_i32(fp0
);
8623 gen_store_gpr(t0
, rt
);
8627 gen_load_gpr(t0
, rt
);
8629 TCGv_i32 fp0
= tcg_temp_new_i32();
8631 tcg_gen_trunc_tl_i32(fp0
, t0
);
8632 gen_store_fpr32(ctx
, fp0
, fs
);
8633 tcg_temp_free_i32(fp0
);
8638 gen_helper_1e0i(cfc1
, t0
, fs
);
8639 gen_store_gpr(t0
, rt
);
8643 gen_load_gpr(t0
, rt
);
8644 save_cpu_state(ctx
, 1);
8646 TCGv_i32 fs_tmp
= tcg_const_i32(fs
);
8648 gen_helper_0e2i(ctc1
, t0
, fs_tmp
, rt
);
8649 tcg_temp_free_i32(fs_tmp
);
8651 /* Stop translation as we may have changed hflags */
8652 ctx
->bstate
= BS_STOP
;
8655 #if defined(TARGET_MIPS64)
8657 gen_load_fpr64(ctx
, t0
, fs
);
8658 gen_store_gpr(t0
, rt
);
8662 gen_load_gpr(t0
, rt
);
8663 gen_store_fpr64(ctx
, t0
, fs
);
8669 TCGv_i32 fp0
= tcg_temp_new_i32();
8671 gen_load_fpr32h(ctx
, fp0
, fs
);
8672 tcg_gen_ext_i32_tl(t0
, fp0
);
8673 tcg_temp_free_i32(fp0
);
8675 gen_store_gpr(t0
, rt
);
8679 gen_load_gpr(t0
, rt
);
8681 TCGv_i32 fp0
= tcg_temp_new_i32();
8683 tcg_gen_trunc_tl_i32(fp0
, t0
);
8684 gen_store_fpr32h(ctx
, fp0
, fs
);
8685 tcg_temp_free_i32(fp0
);
8691 generate_exception (ctx
, EXCP_RI
);
8694 (void)opn
; /* avoid a compiler warning */
8695 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
8701 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
8717 l1
= gen_new_label();
8718 t0
= tcg_temp_new_i32();
8719 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
8720 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
8721 tcg_temp_free_i32(t0
);
8723 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
8725 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
8730 static inline void gen_movcf_s(DisasContext
*ctx
, int fs
, int fd
, int cc
,
8734 TCGv_i32 t0
= tcg_temp_new_i32();
8735 TCGLabel
*l1
= gen_new_label();
8742 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
8743 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
8744 gen_load_fpr32(ctx
, t0
, fs
);
8745 gen_store_fpr32(ctx
, t0
, fd
);
8747 tcg_temp_free_i32(t0
);
8750 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
8753 TCGv_i32 t0
= tcg_temp_new_i32();
8755 TCGLabel
*l1
= gen_new_label();
8762 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
8763 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
8764 tcg_temp_free_i32(t0
);
8765 fp0
= tcg_temp_new_i64();
8766 gen_load_fpr64(ctx
, fp0
, fs
);
8767 gen_store_fpr64(ctx
, fp0
, fd
);
8768 tcg_temp_free_i64(fp0
);
8772 static inline void gen_movcf_ps(DisasContext
*ctx
, int fs
, int fd
,
8776 TCGv_i32 t0
= tcg_temp_new_i32();
8777 TCGLabel
*l1
= gen_new_label();
8778 TCGLabel
*l2
= gen_new_label();
8785 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
8786 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
8787 gen_load_fpr32(ctx
, t0
, fs
);
8788 gen_store_fpr32(ctx
, t0
, fd
);
8791 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+1));
8792 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
8793 gen_load_fpr32h(ctx
, t0
, fs
);
8794 gen_store_fpr32h(ctx
, t0
, fd
);
8795 tcg_temp_free_i32(t0
);
8799 static void gen_sel_s(DisasContext
*ctx
, enum fopcode op1
, int fd
, int ft
,
8802 TCGv_i32 t1
= tcg_const_i32(0);
8803 TCGv_i32 fp0
= tcg_temp_new_i32();
8804 TCGv_i32 fp1
= tcg_temp_new_i32();
8805 TCGv_i32 fp2
= tcg_temp_new_i32();
8806 gen_load_fpr32(ctx
, fp0
, fd
);
8807 gen_load_fpr32(ctx
, fp1
, ft
);
8808 gen_load_fpr32(ctx
, fp2
, fs
);
8812 tcg_gen_andi_i32(fp0
, fp0
, 1);
8813 tcg_gen_movcond_i32(TCG_COND_NE
, fp0
, fp0
, t1
, fp1
, fp2
);
8816 tcg_gen_andi_i32(fp1
, fp1
, 1);
8817 tcg_gen_movcond_i32(TCG_COND_EQ
, fp0
, fp1
, t1
, fp2
, t1
);
8820 tcg_gen_andi_i32(fp1
, fp1
, 1);
8821 tcg_gen_movcond_i32(TCG_COND_NE
, fp0
, fp1
, t1
, fp2
, t1
);
8824 MIPS_INVAL("gen_sel_s");
8825 generate_exception (ctx
, EXCP_RI
);
8829 gen_store_fpr32(ctx
, fp0
, fd
);
8830 tcg_temp_free_i32(fp2
);
8831 tcg_temp_free_i32(fp1
);
8832 tcg_temp_free_i32(fp0
);
8833 tcg_temp_free_i32(t1
);
8836 static void gen_sel_d(DisasContext
*ctx
, enum fopcode op1
, int fd
, int ft
,
8839 TCGv_i64 t1
= tcg_const_i64(0);
8840 TCGv_i64 fp0
= tcg_temp_new_i64();
8841 TCGv_i64 fp1
= tcg_temp_new_i64();
8842 TCGv_i64 fp2
= tcg_temp_new_i64();
8843 gen_load_fpr64(ctx
, fp0
, fd
);
8844 gen_load_fpr64(ctx
, fp1
, ft
);
8845 gen_load_fpr64(ctx
, fp2
, fs
);
8849 tcg_gen_andi_i64(fp0
, fp0
, 1);
8850 tcg_gen_movcond_i64(TCG_COND_NE
, fp0
, fp0
, t1
, fp1
, fp2
);
8853 tcg_gen_andi_i64(fp1
, fp1
, 1);
8854 tcg_gen_movcond_i64(TCG_COND_EQ
, fp0
, fp1
, t1
, fp2
, t1
);
8857 tcg_gen_andi_i64(fp1
, fp1
, 1);
8858 tcg_gen_movcond_i64(TCG_COND_NE
, fp0
, fp1
, t1
, fp2
, t1
);
8861 MIPS_INVAL("gen_sel_d");
8862 generate_exception (ctx
, EXCP_RI
);
8866 gen_store_fpr64(ctx
, fp0
, fd
);
8867 tcg_temp_free_i64(fp2
);
8868 tcg_temp_free_i64(fp1
);
8869 tcg_temp_free_i64(fp0
);
8870 tcg_temp_free_i64(t1
);
8873 static void gen_farith (DisasContext
*ctx
, enum fopcode op1
,
8874 int ft
, int fs
, int fd
, int cc
)
8876 const char *opn
= "farith";
8877 const char *condnames
[] = {
8895 const char *condnames_abs
[] = {
8913 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
8914 uint32_t func
= ctx
->opcode
& 0x3f;
8919 TCGv_i32 fp0
= tcg_temp_new_i32();
8920 TCGv_i32 fp1
= tcg_temp_new_i32();
8922 gen_load_fpr32(ctx
, fp0
, fs
);
8923 gen_load_fpr32(ctx
, fp1
, ft
);
8924 gen_helper_float_add_s(fp0
, cpu_env
, fp0
, fp1
);
8925 tcg_temp_free_i32(fp1
);
8926 gen_store_fpr32(ctx
, fp0
, fd
);
8927 tcg_temp_free_i32(fp0
);
8934 TCGv_i32 fp0
= tcg_temp_new_i32();
8935 TCGv_i32 fp1
= tcg_temp_new_i32();
8937 gen_load_fpr32(ctx
, fp0
, fs
);
8938 gen_load_fpr32(ctx
, fp1
, ft
);
8939 gen_helper_float_sub_s(fp0
, cpu_env
, fp0
, fp1
);
8940 tcg_temp_free_i32(fp1
);
8941 gen_store_fpr32(ctx
, fp0
, fd
);
8942 tcg_temp_free_i32(fp0
);
8949 TCGv_i32 fp0
= tcg_temp_new_i32();
8950 TCGv_i32 fp1
= tcg_temp_new_i32();
8952 gen_load_fpr32(ctx
, fp0
, fs
);
8953 gen_load_fpr32(ctx
, fp1
, ft
);
8954 gen_helper_float_mul_s(fp0
, cpu_env
, fp0
, fp1
);
8955 tcg_temp_free_i32(fp1
);
8956 gen_store_fpr32(ctx
, fp0
, fd
);
8957 tcg_temp_free_i32(fp0
);
8964 TCGv_i32 fp0
= tcg_temp_new_i32();
8965 TCGv_i32 fp1
= tcg_temp_new_i32();
8967 gen_load_fpr32(ctx
, fp0
, fs
);
8968 gen_load_fpr32(ctx
, fp1
, ft
);
8969 gen_helper_float_div_s(fp0
, cpu_env
, fp0
, fp1
);
8970 tcg_temp_free_i32(fp1
);
8971 gen_store_fpr32(ctx
, fp0
, fd
);
8972 tcg_temp_free_i32(fp0
);
8979 TCGv_i32 fp0
= tcg_temp_new_i32();
8981 gen_load_fpr32(ctx
, fp0
, fs
);
8982 gen_helper_float_sqrt_s(fp0
, cpu_env
, fp0
);
8983 gen_store_fpr32(ctx
, fp0
, fd
);
8984 tcg_temp_free_i32(fp0
);
8990 TCGv_i32 fp0
= tcg_temp_new_i32();
8992 gen_load_fpr32(ctx
, fp0
, fs
);
8993 gen_helper_float_abs_s(fp0
, fp0
);
8994 gen_store_fpr32(ctx
, fp0
, fd
);
8995 tcg_temp_free_i32(fp0
);
9001 TCGv_i32 fp0
= tcg_temp_new_i32();
9003 gen_load_fpr32(ctx
, fp0
, fs
);
9004 gen_store_fpr32(ctx
, fp0
, fd
);
9005 tcg_temp_free_i32(fp0
);
9011 TCGv_i32 fp0
= tcg_temp_new_i32();
9013 gen_load_fpr32(ctx
, fp0
, fs
);
9014 gen_helper_float_chs_s(fp0
, fp0
);
9015 gen_store_fpr32(ctx
, fp0
, fd
);
9016 tcg_temp_free_i32(fp0
);
9021 check_cp1_64bitmode(ctx
);
9023 TCGv_i32 fp32
= tcg_temp_new_i32();
9024 TCGv_i64 fp64
= tcg_temp_new_i64();
9026 gen_load_fpr32(ctx
, fp32
, fs
);
9027 gen_helper_float_roundl_s(fp64
, cpu_env
, fp32
);
9028 tcg_temp_free_i32(fp32
);
9029 gen_store_fpr64(ctx
, fp64
, fd
);
9030 tcg_temp_free_i64(fp64
);
9035 check_cp1_64bitmode(ctx
);
9037 TCGv_i32 fp32
= tcg_temp_new_i32();
9038 TCGv_i64 fp64
= tcg_temp_new_i64();
9040 gen_load_fpr32(ctx
, fp32
, fs
);
9041 gen_helper_float_truncl_s(fp64
, cpu_env
, fp32
);
9042 tcg_temp_free_i32(fp32
);
9043 gen_store_fpr64(ctx
, fp64
, fd
);
9044 tcg_temp_free_i64(fp64
);
9049 check_cp1_64bitmode(ctx
);
9051 TCGv_i32 fp32
= tcg_temp_new_i32();
9052 TCGv_i64 fp64
= tcg_temp_new_i64();
9054 gen_load_fpr32(ctx
, fp32
, fs
);
9055 gen_helper_float_ceill_s(fp64
, cpu_env
, fp32
);
9056 tcg_temp_free_i32(fp32
);
9057 gen_store_fpr64(ctx
, fp64
, fd
);
9058 tcg_temp_free_i64(fp64
);
9063 check_cp1_64bitmode(ctx
);
9065 TCGv_i32 fp32
= tcg_temp_new_i32();
9066 TCGv_i64 fp64
= tcg_temp_new_i64();
9068 gen_load_fpr32(ctx
, fp32
, fs
);
9069 gen_helper_float_floorl_s(fp64
, cpu_env
, fp32
);
9070 tcg_temp_free_i32(fp32
);
9071 gen_store_fpr64(ctx
, fp64
, fd
);
9072 tcg_temp_free_i64(fp64
);
9078 TCGv_i32 fp0
= tcg_temp_new_i32();
9080 gen_load_fpr32(ctx
, fp0
, fs
);
9081 gen_helper_float_roundw_s(fp0
, cpu_env
, fp0
);
9082 gen_store_fpr32(ctx
, fp0
, fd
);
9083 tcg_temp_free_i32(fp0
);
9089 TCGv_i32 fp0
= tcg_temp_new_i32();
9091 gen_load_fpr32(ctx
, fp0
, fs
);
9092 gen_helper_float_truncw_s(fp0
, cpu_env
, fp0
);
9093 gen_store_fpr32(ctx
, fp0
, fd
);
9094 tcg_temp_free_i32(fp0
);
9100 TCGv_i32 fp0
= tcg_temp_new_i32();
9102 gen_load_fpr32(ctx
, fp0
, fs
);
9103 gen_helper_float_ceilw_s(fp0
, cpu_env
, fp0
);
9104 gen_store_fpr32(ctx
, fp0
, fd
);
9105 tcg_temp_free_i32(fp0
);
9111 TCGv_i32 fp0
= tcg_temp_new_i32();
9113 gen_load_fpr32(ctx
, fp0
, fs
);
9114 gen_helper_float_floorw_s(fp0
, cpu_env
, fp0
);
9115 gen_store_fpr32(ctx
, fp0
, fd
);
9116 tcg_temp_free_i32(fp0
);
9121 check_insn(ctx
, ISA_MIPS32R6
);
9122 gen_sel_s(ctx
, op1
, fd
, ft
, fs
);
9126 check_insn(ctx
, ISA_MIPS32R6
);
9127 gen_sel_s(ctx
, op1
, fd
, ft
, fs
);
9131 check_insn(ctx
, ISA_MIPS32R6
);
9132 gen_sel_s(ctx
, op1
, fd
, ft
, fs
);
9136 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9137 gen_movcf_s(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
9141 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9143 TCGLabel
*l1
= gen_new_label();
9147 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
9149 fp0
= tcg_temp_new_i32();
9150 gen_load_fpr32(ctx
, fp0
, fs
);
9151 gen_store_fpr32(ctx
, fp0
, fd
);
9152 tcg_temp_free_i32(fp0
);
9158 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9160 TCGLabel
*l1
= gen_new_label();
9164 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
9165 fp0
= tcg_temp_new_i32();
9166 gen_load_fpr32(ctx
, fp0
, fs
);
9167 gen_store_fpr32(ctx
, fp0
, fd
);
9168 tcg_temp_free_i32(fp0
);
9177 TCGv_i32 fp0
= tcg_temp_new_i32();
9179 gen_load_fpr32(ctx
, fp0
, fs
);
9180 gen_helper_float_recip_s(fp0
, cpu_env
, fp0
);
9181 gen_store_fpr32(ctx
, fp0
, fd
);
9182 tcg_temp_free_i32(fp0
);
9189 TCGv_i32 fp0
= tcg_temp_new_i32();
9191 gen_load_fpr32(ctx
, fp0
, fs
);
9192 gen_helper_float_rsqrt_s(fp0
, cpu_env
, fp0
);
9193 gen_store_fpr32(ctx
, fp0
, fd
);
9194 tcg_temp_free_i32(fp0
);
9199 check_insn(ctx
, ISA_MIPS32R6
);
9201 TCGv_i32 fp0
= tcg_temp_new_i32();
9202 TCGv_i32 fp1
= tcg_temp_new_i32();
9203 TCGv_i32 fp2
= tcg_temp_new_i32();
9204 gen_load_fpr32(ctx
, fp0
, fs
);
9205 gen_load_fpr32(ctx
, fp1
, ft
);
9206 gen_load_fpr32(ctx
, fp2
, fd
);
9207 gen_helper_float_maddf_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
9208 gen_store_fpr32(ctx
, fp2
, fd
);
9209 tcg_temp_free_i32(fp2
);
9210 tcg_temp_free_i32(fp1
);
9211 tcg_temp_free_i32(fp0
);
9216 check_insn(ctx
, ISA_MIPS32R6
);
9218 TCGv_i32 fp0
= tcg_temp_new_i32();
9219 TCGv_i32 fp1
= tcg_temp_new_i32();
9220 TCGv_i32 fp2
= tcg_temp_new_i32();
9221 gen_load_fpr32(ctx
, fp0
, fs
);
9222 gen_load_fpr32(ctx
, fp1
, ft
);
9223 gen_load_fpr32(ctx
, fp2
, fd
);
9224 gen_helper_float_msubf_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
9225 gen_store_fpr32(ctx
, fp2
, fd
);
9226 tcg_temp_free_i32(fp2
);
9227 tcg_temp_free_i32(fp1
);
9228 tcg_temp_free_i32(fp0
);
9233 check_insn(ctx
, ISA_MIPS32R6
);
9235 TCGv_i32 fp0
= tcg_temp_new_i32();
9236 gen_load_fpr32(ctx
, fp0
, fs
);
9237 gen_helper_float_rint_s(fp0
, cpu_env
, fp0
);
9238 gen_store_fpr32(ctx
, fp0
, fd
);
9239 tcg_temp_free_i32(fp0
);
9244 check_insn(ctx
, ISA_MIPS32R6
);
9246 TCGv_i32 fp0
= tcg_temp_new_i32();
9247 gen_load_fpr32(ctx
, fp0
, fs
);
9248 gen_helper_float_class_s(fp0
, fp0
);
9249 gen_store_fpr32(ctx
, fp0
, fd
);
9250 tcg_temp_free_i32(fp0
);
9254 case OPC_MIN_S
: /* OPC_RECIP2_S */
9255 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9257 TCGv_i32 fp0
= tcg_temp_new_i32();
9258 TCGv_i32 fp1
= tcg_temp_new_i32();
9259 TCGv_i32 fp2
= tcg_temp_new_i32();
9260 gen_load_fpr32(ctx
, fp0
, fs
);
9261 gen_load_fpr32(ctx
, fp1
, ft
);
9262 gen_helper_float_min_s(fp2
, cpu_env
, fp0
, fp1
);
9263 gen_store_fpr32(ctx
, fp2
, fd
);
9264 tcg_temp_free_i32(fp2
);
9265 tcg_temp_free_i32(fp1
);
9266 tcg_temp_free_i32(fp0
);
9270 check_cp1_64bitmode(ctx
);
9272 TCGv_i32 fp0
= tcg_temp_new_i32();
9273 TCGv_i32 fp1
= tcg_temp_new_i32();
9275 gen_load_fpr32(ctx
, fp0
, fs
);
9276 gen_load_fpr32(ctx
, fp1
, ft
);
9277 gen_helper_float_recip2_s(fp0
, cpu_env
, fp0
, fp1
);
9278 tcg_temp_free_i32(fp1
);
9279 gen_store_fpr32(ctx
, fp0
, fd
);
9280 tcg_temp_free_i32(fp0
);
9285 case OPC_MINA_S
: /* OPC_RECIP1_S */
9286 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9288 TCGv_i32 fp0
= tcg_temp_new_i32();
9289 TCGv_i32 fp1
= tcg_temp_new_i32();
9290 TCGv_i32 fp2
= tcg_temp_new_i32();
9291 gen_load_fpr32(ctx
, fp0
, fs
);
9292 gen_load_fpr32(ctx
, fp1
, ft
);
9293 gen_helper_float_mina_s(fp2
, cpu_env
, fp0
, fp1
);
9294 gen_store_fpr32(ctx
, fp2
, fd
);
9295 tcg_temp_free_i32(fp2
);
9296 tcg_temp_free_i32(fp1
);
9297 tcg_temp_free_i32(fp0
);
9301 check_cp1_64bitmode(ctx
);
9303 TCGv_i32 fp0
= tcg_temp_new_i32();
9305 gen_load_fpr32(ctx
, fp0
, fs
);
9306 gen_helper_float_recip1_s(fp0
, cpu_env
, fp0
);
9307 gen_store_fpr32(ctx
, fp0
, fd
);
9308 tcg_temp_free_i32(fp0
);
9313 case OPC_MAX_S
: /* OPC_RSQRT1_S */
9314 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9316 TCGv_i32 fp0
= tcg_temp_new_i32();
9317 TCGv_i32 fp1
= tcg_temp_new_i32();
9318 gen_load_fpr32(ctx
, fp0
, fs
);
9319 gen_load_fpr32(ctx
, fp1
, ft
);
9320 gen_helper_float_max_s(fp1
, cpu_env
, fp0
, fp1
);
9321 gen_store_fpr32(ctx
, fp1
, fd
);
9322 tcg_temp_free_i32(fp1
);
9323 tcg_temp_free_i32(fp0
);
9327 check_cp1_64bitmode(ctx
);
9329 TCGv_i32 fp0
= tcg_temp_new_i32();
9331 gen_load_fpr32(ctx
, fp0
, fs
);
9332 gen_helper_float_rsqrt1_s(fp0
, cpu_env
, fp0
);
9333 gen_store_fpr32(ctx
, fp0
, fd
);
9334 tcg_temp_free_i32(fp0
);
9339 case OPC_MAXA_S
: /* OPC_RSQRT2_S */
9340 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9342 TCGv_i32 fp0
= tcg_temp_new_i32();
9343 TCGv_i32 fp1
= tcg_temp_new_i32();
9344 gen_load_fpr32(ctx
, fp0
, fs
);
9345 gen_load_fpr32(ctx
, fp1
, ft
);
9346 gen_helper_float_maxa_s(fp1
, cpu_env
, fp0
, fp1
);
9347 gen_store_fpr32(ctx
, fp1
, fd
);
9348 tcg_temp_free_i32(fp1
);
9349 tcg_temp_free_i32(fp0
);
9353 check_cp1_64bitmode(ctx
);
9355 TCGv_i32 fp0
= tcg_temp_new_i32();
9356 TCGv_i32 fp1
= tcg_temp_new_i32();
9358 gen_load_fpr32(ctx
, fp0
, fs
);
9359 gen_load_fpr32(ctx
, fp1
, ft
);
9360 gen_helper_float_rsqrt2_s(fp0
, cpu_env
, fp0
, fp1
);
9361 tcg_temp_free_i32(fp1
);
9362 gen_store_fpr32(ctx
, fp0
, fd
);
9363 tcg_temp_free_i32(fp0
);
9369 check_cp1_registers(ctx
, fd
);
9371 TCGv_i32 fp32
= tcg_temp_new_i32();
9372 TCGv_i64 fp64
= tcg_temp_new_i64();
9374 gen_load_fpr32(ctx
, fp32
, fs
);
9375 gen_helper_float_cvtd_s(fp64
, cpu_env
, fp32
);
9376 tcg_temp_free_i32(fp32
);
9377 gen_store_fpr64(ctx
, fp64
, fd
);
9378 tcg_temp_free_i64(fp64
);
9384 TCGv_i32 fp0
= tcg_temp_new_i32();
9386 gen_load_fpr32(ctx
, fp0
, fs
);
9387 gen_helper_float_cvtw_s(fp0
, cpu_env
, fp0
);
9388 gen_store_fpr32(ctx
, fp0
, fd
);
9389 tcg_temp_free_i32(fp0
);
9394 check_cp1_64bitmode(ctx
);
9396 TCGv_i32 fp32
= tcg_temp_new_i32();
9397 TCGv_i64 fp64
= tcg_temp_new_i64();
9399 gen_load_fpr32(ctx
, fp32
, fs
);
9400 gen_helper_float_cvtl_s(fp64
, cpu_env
, fp32
);
9401 tcg_temp_free_i32(fp32
);
9402 gen_store_fpr64(ctx
, fp64
, fd
);
9403 tcg_temp_free_i64(fp64
);
9408 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9409 check_cp1_64bitmode(ctx
);
9411 TCGv_i64 fp64
= tcg_temp_new_i64();
9412 TCGv_i32 fp32_0
= tcg_temp_new_i32();
9413 TCGv_i32 fp32_1
= tcg_temp_new_i32();
9415 gen_load_fpr32(ctx
, fp32_0
, fs
);
9416 gen_load_fpr32(ctx
, fp32_1
, ft
);
9417 tcg_gen_concat_i32_i64(fp64
, fp32_1
, fp32_0
);
9418 tcg_temp_free_i32(fp32_1
);
9419 tcg_temp_free_i32(fp32_0
);
9420 gen_store_fpr64(ctx
, fp64
, fd
);
9421 tcg_temp_free_i64(fp64
);
9434 case OPC_CMP_NGLE_S
:
9441 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9442 if (ctx
->opcode
& (1 << 6)) {
9443 gen_cmpabs_s(ctx
, func
-48, ft
, fs
, cc
);
9444 opn
= condnames_abs
[func
-48];
9446 gen_cmp_s(ctx
, func
-48, ft
, fs
, cc
);
9447 opn
= condnames
[func
-48];
9451 check_cp1_registers(ctx
, fs
| ft
| fd
);
9453 TCGv_i64 fp0
= tcg_temp_new_i64();
9454 TCGv_i64 fp1
= tcg_temp_new_i64();
9456 gen_load_fpr64(ctx
, fp0
, fs
);
9457 gen_load_fpr64(ctx
, fp1
, ft
);
9458 gen_helper_float_add_d(fp0
, cpu_env
, fp0
, fp1
);
9459 tcg_temp_free_i64(fp1
);
9460 gen_store_fpr64(ctx
, fp0
, fd
);
9461 tcg_temp_free_i64(fp0
);
9467 check_cp1_registers(ctx
, fs
| ft
| fd
);
9469 TCGv_i64 fp0
= tcg_temp_new_i64();
9470 TCGv_i64 fp1
= tcg_temp_new_i64();
9472 gen_load_fpr64(ctx
, fp0
, fs
);
9473 gen_load_fpr64(ctx
, fp1
, ft
);
9474 gen_helper_float_sub_d(fp0
, cpu_env
, fp0
, fp1
);
9475 tcg_temp_free_i64(fp1
);
9476 gen_store_fpr64(ctx
, fp0
, fd
);
9477 tcg_temp_free_i64(fp0
);
9483 check_cp1_registers(ctx
, fs
| ft
| fd
);
9485 TCGv_i64 fp0
= tcg_temp_new_i64();
9486 TCGv_i64 fp1
= tcg_temp_new_i64();
9488 gen_load_fpr64(ctx
, fp0
, fs
);
9489 gen_load_fpr64(ctx
, fp1
, ft
);
9490 gen_helper_float_mul_d(fp0
, cpu_env
, fp0
, fp1
);
9491 tcg_temp_free_i64(fp1
);
9492 gen_store_fpr64(ctx
, fp0
, fd
);
9493 tcg_temp_free_i64(fp0
);
9499 check_cp1_registers(ctx
, fs
| ft
| fd
);
9501 TCGv_i64 fp0
= tcg_temp_new_i64();
9502 TCGv_i64 fp1
= tcg_temp_new_i64();
9504 gen_load_fpr64(ctx
, fp0
, fs
);
9505 gen_load_fpr64(ctx
, fp1
, ft
);
9506 gen_helper_float_div_d(fp0
, cpu_env
, fp0
, fp1
);
9507 tcg_temp_free_i64(fp1
);
9508 gen_store_fpr64(ctx
, fp0
, fd
);
9509 tcg_temp_free_i64(fp0
);
9515 check_cp1_registers(ctx
, fs
| fd
);
9517 TCGv_i64 fp0
= tcg_temp_new_i64();
9519 gen_load_fpr64(ctx
, fp0
, fs
);
9520 gen_helper_float_sqrt_d(fp0
, cpu_env
, fp0
);
9521 gen_store_fpr64(ctx
, fp0
, fd
);
9522 tcg_temp_free_i64(fp0
);
9527 check_cp1_registers(ctx
, fs
| fd
);
9529 TCGv_i64 fp0
= tcg_temp_new_i64();
9531 gen_load_fpr64(ctx
, fp0
, fs
);
9532 gen_helper_float_abs_d(fp0
, fp0
);
9533 gen_store_fpr64(ctx
, fp0
, fd
);
9534 tcg_temp_free_i64(fp0
);
9539 check_cp1_registers(ctx
, fs
| fd
);
9541 TCGv_i64 fp0
= tcg_temp_new_i64();
9543 gen_load_fpr64(ctx
, fp0
, fs
);
9544 gen_store_fpr64(ctx
, fp0
, fd
);
9545 tcg_temp_free_i64(fp0
);
9550 check_cp1_registers(ctx
, fs
| fd
);
9552 TCGv_i64 fp0
= tcg_temp_new_i64();
9554 gen_load_fpr64(ctx
, fp0
, fs
);
9555 gen_helper_float_chs_d(fp0
, fp0
);
9556 gen_store_fpr64(ctx
, fp0
, fd
);
9557 tcg_temp_free_i64(fp0
);
9562 check_cp1_64bitmode(ctx
);
9564 TCGv_i64 fp0
= tcg_temp_new_i64();
9566 gen_load_fpr64(ctx
, fp0
, fs
);
9567 gen_helper_float_roundl_d(fp0
, cpu_env
, fp0
);
9568 gen_store_fpr64(ctx
, fp0
, fd
);
9569 tcg_temp_free_i64(fp0
);
9574 check_cp1_64bitmode(ctx
);
9576 TCGv_i64 fp0
= tcg_temp_new_i64();
9578 gen_load_fpr64(ctx
, fp0
, fs
);
9579 gen_helper_float_truncl_d(fp0
, cpu_env
, fp0
);
9580 gen_store_fpr64(ctx
, fp0
, fd
);
9581 tcg_temp_free_i64(fp0
);
9586 check_cp1_64bitmode(ctx
);
9588 TCGv_i64 fp0
= tcg_temp_new_i64();
9590 gen_load_fpr64(ctx
, fp0
, fs
);
9591 gen_helper_float_ceill_d(fp0
, cpu_env
, fp0
);
9592 gen_store_fpr64(ctx
, fp0
, fd
);
9593 tcg_temp_free_i64(fp0
);
9598 check_cp1_64bitmode(ctx
);
9600 TCGv_i64 fp0
= tcg_temp_new_i64();
9602 gen_load_fpr64(ctx
, fp0
, fs
);
9603 gen_helper_float_floorl_d(fp0
, cpu_env
, fp0
);
9604 gen_store_fpr64(ctx
, fp0
, fd
);
9605 tcg_temp_free_i64(fp0
);
9610 check_cp1_registers(ctx
, fs
);
9612 TCGv_i32 fp32
= tcg_temp_new_i32();
9613 TCGv_i64 fp64
= tcg_temp_new_i64();
9615 gen_load_fpr64(ctx
, fp64
, fs
);
9616 gen_helper_float_roundw_d(fp32
, cpu_env
, fp64
);
9617 tcg_temp_free_i64(fp64
);
9618 gen_store_fpr32(ctx
, fp32
, fd
);
9619 tcg_temp_free_i32(fp32
);
9624 check_cp1_registers(ctx
, fs
);
9626 TCGv_i32 fp32
= tcg_temp_new_i32();
9627 TCGv_i64 fp64
= tcg_temp_new_i64();
9629 gen_load_fpr64(ctx
, fp64
, fs
);
9630 gen_helper_float_truncw_d(fp32
, cpu_env
, fp64
);
9631 tcg_temp_free_i64(fp64
);
9632 gen_store_fpr32(ctx
, fp32
, fd
);
9633 tcg_temp_free_i32(fp32
);
9638 check_cp1_registers(ctx
, fs
);
9640 TCGv_i32 fp32
= tcg_temp_new_i32();
9641 TCGv_i64 fp64
= tcg_temp_new_i64();
9643 gen_load_fpr64(ctx
, fp64
, fs
);
9644 gen_helper_float_ceilw_d(fp32
, cpu_env
, fp64
);
9645 tcg_temp_free_i64(fp64
);
9646 gen_store_fpr32(ctx
, fp32
, fd
);
9647 tcg_temp_free_i32(fp32
);
9652 check_cp1_registers(ctx
, fs
);
9654 TCGv_i32 fp32
= tcg_temp_new_i32();
9655 TCGv_i64 fp64
= tcg_temp_new_i64();
9657 gen_load_fpr64(ctx
, fp64
, fs
);
9658 gen_helper_float_floorw_d(fp32
, cpu_env
, fp64
);
9659 tcg_temp_free_i64(fp64
);
9660 gen_store_fpr32(ctx
, fp32
, fd
);
9661 tcg_temp_free_i32(fp32
);
9666 check_insn(ctx
, ISA_MIPS32R6
);
9667 gen_sel_d(ctx
, op1
, fd
, ft
, fs
);
9671 check_insn(ctx
, ISA_MIPS32R6
);
9672 gen_sel_d(ctx
, op1
, fd
, ft
, fs
);
9676 check_insn(ctx
, ISA_MIPS32R6
);
9677 gen_sel_d(ctx
, op1
, fd
, ft
, fs
);
9681 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9682 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
9686 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9688 TCGLabel
*l1
= gen_new_label();
9692 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
9694 fp0
= tcg_temp_new_i64();
9695 gen_load_fpr64(ctx
, fp0
, fs
);
9696 gen_store_fpr64(ctx
, fp0
, fd
);
9697 tcg_temp_free_i64(fp0
);
9703 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9705 TCGLabel
*l1
= gen_new_label();
9709 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
9710 fp0
= tcg_temp_new_i64();
9711 gen_load_fpr64(ctx
, fp0
, fs
);
9712 gen_store_fpr64(ctx
, fp0
, fd
);
9713 tcg_temp_free_i64(fp0
);
9720 check_cp1_64bitmode(ctx
);
9722 TCGv_i64 fp0
= tcg_temp_new_i64();
9724 gen_load_fpr64(ctx
, fp0
, fs
);
9725 gen_helper_float_recip_d(fp0
, cpu_env
, fp0
);
9726 gen_store_fpr64(ctx
, fp0
, fd
);
9727 tcg_temp_free_i64(fp0
);
9732 check_cp1_64bitmode(ctx
);
9734 TCGv_i64 fp0
= tcg_temp_new_i64();
9736 gen_load_fpr64(ctx
, fp0
, fs
);
9737 gen_helper_float_rsqrt_d(fp0
, cpu_env
, fp0
);
9738 gen_store_fpr64(ctx
, fp0
, fd
);
9739 tcg_temp_free_i64(fp0
);
9744 check_insn(ctx
, ISA_MIPS32R6
);
9746 TCGv_i64 fp0
= tcg_temp_new_i64();
9747 TCGv_i64 fp1
= tcg_temp_new_i64();
9748 TCGv_i64 fp2
= tcg_temp_new_i64();
9749 gen_load_fpr64(ctx
, fp0
, fs
);
9750 gen_load_fpr64(ctx
, fp1
, ft
);
9751 gen_load_fpr64(ctx
, fp2
, fd
);
9752 gen_helper_float_maddf_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
9753 gen_store_fpr64(ctx
, fp2
, fd
);
9754 tcg_temp_free_i64(fp2
);
9755 tcg_temp_free_i64(fp1
);
9756 tcg_temp_free_i64(fp0
);
9761 check_insn(ctx
, ISA_MIPS32R6
);
9763 TCGv_i64 fp0
= tcg_temp_new_i64();
9764 TCGv_i64 fp1
= tcg_temp_new_i64();
9765 TCGv_i64 fp2
= tcg_temp_new_i64();
9766 gen_load_fpr64(ctx
, fp0
, fs
);
9767 gen_load_fpr64(ctx
, fp1
, ft
);
9768 gen_load_fpr64(ctx
, fp2
, fd
);
9769 gen_helper_float_msubf_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
9770 gen_store_fpr64(ctx
, fp2
, fd
);
9771 tcg_temp_free_i64(fp2
);
9772 tcg_temp_free_i64(fp1
);
9773 tcg_temp_free_i64(fp0
);
9778 check_insn(ctx
, ISA_MIPS32R6
);
9780 TCGv_i64 fp0
= tcg_temp_new_i64();
9781 gen_load_fpr64(ctx
, fp0
, fs
);
9782 gen_helper_float_rint_d(fp0
, cpu_env
, fp0
);
9783 gen_store_fpr64(ctx
, fp0
, fd
);
9784 tcg_temp_free_i64(fp0
);
9789 check_insn(ctx
, ISA_MIPS32R6
);
9791 TCGv_i64 fp0
= tcg_temp_new_i64();
9792 gen_load_fpr64(ctx
, fp0
, fs
);
9793 gen_helper_float_class_d(fp0
, fp0
);
9794 gen_store_fpr64(ctx
, fp0
, fd
);
9795 tcg_temp_free_i64(fp0
);
9799 case OPC_MIN_D
: /* OPC_RECIP2_D */
9800 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9802 TCGv_i64 fp0
= tcg_temp_new_i64();
9803 TCGv_i64 fp1
= tcg_temp_new_i64();
9804 gen_load_fpr64(ctx
, fp0
, fs
);
9805 gen_load_fpr64(ctx
, fp1
, ft
);
9806 gen_helper_float_min_d(fp1
, cpu_env
, fp0
, fp1
);
9807 gen_store_fpr64(ctx
, fp1
, fd
);
9808 tcg_temp_free_i64(fp1
);
9809 tcg_temp_free_i64(fp0
);
9813 check_cp1_64bitmode(ctx
);
9815 TCGv_i64 fp0
= tcg_temp_new_i64();
9816 TCGv_i64 fp1
= tcg_temp_new_i64();
9818 gen_load_fpr64(ctx
, fp0
, fs
);
9819 gen_load_fpr64(ctx
, fp1
, ft
);
9820 gen_helper_float_recip2_d(fp0
, cpu_env
, fp0
, fp1
);
9821 tcg_temp_free_i64(fp1
);
9822 gen_store_fpr64(ctx
, fp0
, fd
);
9823 tcg_temp_free_i64(fp0
);
9828 case OPC_MINA_D
: /* OPC_RECIP1_D */
9829 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9831 TCGv_i64 fp0
= tcg_temp_new_i64();
9832 TCGv_i64 fp1
= tcg_temp_new_i64();
9833 gen_load_fpr64(ctx
, fp0
, fs
);
9834 gen_load_fpr64(ctx
, fp1
, ft
);
9835 gen_helper_float_mina_d(fp1
, cpu_env
, fp0
, fp1
);
9836 gen_store_fpr64(ctx
, fp1
, fd
);
9837 tcg_temp_free_i64(fp1
);
9838 tcg_temp_free_i64(fp0
);
9842 check_cp1_64bitmode(ctx
);
9844 TCGv_i64 fp0
= tcg_temp_new_i64();
9846 gen_load_fpr64(ctx
, fp0
, fs
);
9847 gen_helper_float_recip1_d(fp0
, cpu_env
, fp0
);
9848 gen_store_fpr64(ctx
, fp0
, fd
);
9849 tcg_temp_free_i64(fp0
);
9854 case OPC_MAX_D
: /* OPC_RSQRT1_D */
9855 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9857 TCGv_i64 fp0
= tcg_temp_new_i64();
9858 TCGv_i64 fp1
= tcg_temp_new_i64();
9859 gen_load_fpr64(ctx
, fp0
, fs
);
9860 gen_load_fpr64(ctx
, fp1
, ft
);
9861 gen_helper_float_max_d(fp1
, cpu_env
, fp0
, fp1
);
9862 gen_store_fpr64(ctx
, fp1
, fd
);
9863 tcg_temp_free_i64(fp1
);
9864 tcg_temp_free_i64(fp0
);
9868 check_cp1_64bitmode(ctx
);
9870 TCGv_i64 fp0
= tcg_temp_new_i64();
9872 gen_load_fpr64(ctx
, fp0
, fs
);
9873 gen_helper_float_rsqrt1_d(fp0
, cpu_env
, fp0
);
9874 gen_store_fpr64(ctx
, fp0
, fd
);
9875 tcg_temp_free_i64(fp0
);
9880 case OPC_MAXA_D
: /* OPC_RSQRT2_D */
9881 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
9883 TCGv_i64 fp0
= tcg_temp_new_i64();
9884 TCGv_i64 fp1
= tcg_temp_new_i64();
9885 gen_load_fpr64(ctx
, fp0
, fs
);
9886 gen_load_fpr64(ctx
, fp1
, ft
);
9887 gen_helper_float_maxa_d(fp1
, cpu_env
, fp0
, fp1
);
9888 gen_store_fpr64(ctx
, fp1
, fd
);
9889 tcg_temp_free_i64(fp1
);
9890 tcg_temp_free_i64(fp0
);
9894 check_cp1_64bitmode(ctx
);
9896 TCGv_i64 fp0
= tcg_temp_new_i64();
9897 TCGv_i64 fp1
= tcg_temp_new_i64();
9899 gen_load_fpr64(ctx
, fp0
, fs
);
9900 gen_load_fpr64(ctx
, fp1
, ft
);
9901 gen_helper_float_rsqrt2_d(fp0
, cpu_env
, fp0
, fp1
);
9902 tcg_temp_free_i64(fp1
);
9903 gen_store_fpr64(ctx
, fp0
, fd
);
9904 tcg_temp_free_i64(fp0
);
9918 case OPC_CMP_NGLE_D
:
9925 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
9926 if (ctx
->opcode
& (1 << 6)) {
9927 gen_cmpabs_d(ctx
, func
-48, ft
, fs
, cc
);
9928 opn
= condnames_abs
[func
-48];
9930 gen_cmp_d(ctx
, func
-48, ft
, fs
, cc
);
9931 opn
= condnames
[func
-48];
9935 check_cp1_registers(ctx
, fs
);
9937 TCGv_i32 fp32
= tcg_temp_new_i32();
9938 TCGv_i64 fp64
= tcg_temp_new_i64();
9940 gen_load_fpr64(ctx
, fp64
, fs
);
9941 gen_helper_float_cvts_d(fp32
, cpu_env
, fp64
);
9942 tcg_temp_free_i64(fp64
);
9943 gen_store_fpr32(ctx
, fp32
, fd
);
9944 tcg_temp_free_i32(fp32
);
9949 check_cp1_registers(ctx
, fs
);
9951 TCGv_i32 fp32
= tcg_temp_new_i32();
9952 TCGv_i64 fp64
= tcg_temp_new_i64();
9954 gen_load_fpr64(ctx
, fp64
, fs
);
9955 gen_helper_float_cvtw_d(fp32
, cpu_env
, fp64
);
9956 tcg_temp_free_i64(fp64
);
9957 gen_store_fpr32(ctx
, fp32
, fd
);
9958 tcg_temp_free_i32(fp32
);
9963 check_cp1_64bitmode(ctx
);
9965 TCGv_i64 fp0
= tcg_temp_new_i64();
9967 gen_load_fpr64(ctx
, fp0
, fs
);
9968 gen_helper_float_cvtl_d(fp0
, cpu_env
, fp0
);
9969 gen_store_fpr64(ctx
, fp0
, fd
);
9970 tcg_temp_free_i64(fp0
);
9976 TCGv_i32 fp0
= tcg_temp_new_i32();
9978 gen_load_fpr32(ctx
, fp0
, fs
);
9979 gen_helper_float_cvts_w(fp0
, cpu_env
, fp0
);
9980 gen_store_fpr32(ctx
, fp0
, fd
);
9981 tcg_temp_free_i32(fp0
);
9986 check_cp1_registers(ctx
, fd
);
9988 TCGv_i32 fp32
= tcg_temp_new_i32();
9989 TCGv_i64 fp64
= tcg_temp_new_i64();
9991 gen_load_fpr32(ctx
, fp32
, fs
);
9992 gen_helper_float_cvtd_w(fp64
, cpu_env
, fp32
);
9993 tcg_temp_free_i32(fp32
);
9994 gen_store_fpr64(ctx
, fp64
, fd
);
9995 tcg_temp_free_i64(fp64
);
10000 check_cp1_64bitmode(ctx
);
10002 TCGv_i32 fp32
= tcg_temp_new_i32();
10003 TCGv_i64 fp64
= tcg_temp_new_i64();
10005 gen_load_fpr64(ctx
, fp64
, fs
);
10006 gen_helper_float_cvts_l(fp32
, cpu_env
, fp64
);
10007 tcg_temp_free_i64(fp64
);
10008 gen_store_fpr32(ctx
, fp32
, fd
);
10009 tcg_temp_free_i32(fp32
);
10014 check_cp1_64bitmode(ctx
);
10016 TCGv_i64 fp0
= tcg_temp_new_i64();
10018 gen_load_fpr64(ctx
, fp0
, fs
);
10019 gen_helper_float_cvtd_l(fp0
, cpu_env
, fp0
);
10020 gen_store_fpr64(ctx
, fp0
, fd
);
10021 tcg_temp_free_i64(fp0
);
10025 case OPC_CVT_PS_PW
:
10026 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
10027 check_cp1_64bitmode(ctx
);
10029 TCGv_i64 fp0
= tcg_temp_new_i64();
10031 gen_load_fpr64(ctx
, fp0
, fs
);
10032 gen_helper_float_cvtps_pw(fp0
, cpu_env
, fp0
);
10033 gen_store_fpr64(ctx
, fp0
, fd
);
10034 tcg_temp_free_i64(fp0
);
10039 check_cp1_64bitmode(ctx
);
10041 TCGv_i64 fp0
= tcg_temp_new_i64();
10042 TCGv_i64 fp1
= tcg_temp_new_i64();
10044 gen_load_fpr64(ctx
, fp0
, fs
);
10045 gen_load_fpr64(ctx
, fp1
, ft
);
10046 gen_helper_float_add_ps(fp0
, cpu_env
, fp0
, fp1
);
10047 tcg_temp_free_i64(fp1
);
10048 gen_store_fpr64(ctx
, fp0
, fd
);
10049 tcg_temp_free_i64(fp0
);
10054 check_cp1_64bitmode(ctx
);
10056 TCGv_i64 fp0
= tcg_temp_new_i64();
10057 TCGv_i64 fp1
= tcg_temp_new_i64();
10059 gen_load_fpr64(ctx
, fp0
, fs
);
10060 gen_load_fpr64(ctx
, fp1
, ft
);
10061 gen_helper_float_sub_ps(fp0
, cpu_env
, fp0
, fp1
);
10062 tcg_temp_free_i64(fp1
);
10063 gen_store_fpr64(ctx
, fp0
, fd
);
10064 tcg_temp_free_i64(fp0
);
10069 check_cp1_64bitmode(ctx
);
10071 TCGv_i64 fp0
= tcg_temp_new_i64();
10072 TCGv_i64 fp1
= tcg_temp_new_i64();
10074 gen_load_fpr64(ctx
, fp0
, fs
);
10075 gen_load_fpr64(ctx
, fp1
, ft
);
10076 gen_helper_float_mul_ps(fp0
, cpu_env
, fp0
, fp1
);
10077 tcg_temp_free_i64(fp1
);
10078 gen_store_fpr64(ctx
, fp0
, fd
);
10079 tcg_temp_free_i64(fp0
);
10084 check_cp1_64bitmode(ctx
);
10086 TCGv_i64 fp0
= tcg_temp_new_i64();
10088 gen_load_fpr64(ctx
, fp0
, fs
);
10089 gen_helper_float_abs_ps(fp0
, fp0
);
10090 gen_store_fpr64(ctx
, fp0
, fd
);
10091 tcg_temp_free_i64(fp0
);
10096 check_cp1_64bitmode(ctx
);
10098 TCGv_i64 fp0
= tcg_temp_new_i64();
10100 gen_load_fpr64(ctx
, fp0
, fs
);
10101 gen_store_fpr64(ctx
, fp0
, fd
);
10102 tcg_temp_free_i64(fp0
);
10107 check_cp1_64bitmode(ctx
);
10109 TCGv_i64 fp0
= tcg_temp_new_i64();
10111 gen_load_fpr64(ctx
, fp0
, fs
);
10112 gen_helper_float_chs_ps(fp0
, fp0
);
10113 gen_store_fpr64(ctx
, fp0
, fd
);
10114 tcg_temp_free_i64(fp0
);
10119 check_cp1_64bitmode(ctx
);
10120 gen_movcf_ps(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
10124 check_cp1_64bitmode(ctx
);
10126 TCGLabel
*l1
= gen_new_label();
10130 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
10131 fp0
= tcg_temp_new_i64();
10132 gen_load_fpr64(ctx
, fp0
, fs
);
10133 gen_store_fpr64(ctx
, fp0
, fd
);
10134 tcg_temp_free_i64(fp0
);
10140 check_cp1_64bitmode(ctx
);
10142 TCGLabel
*l1
= gen_new_label();
10146 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
10147 fp0
= tcg_temp_new_i64();
10148 gen_load_fpr64(ctx
, fp0
, fs
);
10149 gen_store_fpr64(ctx
, fp0
, fd
);
10150 tcg_temp_free_i64(fp0
);
10157 check_cp1_64bitmode(ctx
);
10159 TCGv_i64 fp0
= tcg_temp_new_i64();
10160 TCGv_i64 fp1
= tcg_temp_new_i64();
10162 gen_load_fpr64(ctx
, fp0
, ft
);
10163 gen_load_fpr64(ctx
, fp1
, fs
);
10164 gen_helper_float_addr_ps(fp0
, cpu_env
, fp0
, fp1
);
10165 tcg_temp_free_i64(fp1
);
10166 gen_store_fpr64(ctx
, fp0
, fd
);
10167 tcg_temp_free_i64(fp0
);
10172 check_cp1_64bitmode(ctx
);
10174 TCGv_i64 fp0
= tcg_temp_new_i64();
10175 TCGv_i64 fp1
= tcg_temp_new_i64();
10177 gen_load_fpr64(ctx
, fp0
, ft
);
10178 gen_load_fpr64(ctx
, fp1
, fs
);
10179 gen_helper_float_mulr_ps(fp0
, cpu_env
, fp0
, fp1
);
10180 tcg_temp_free_i64(fp1
);
10181 gen_store_fpr64(ctx
, fp0
, fd
);
10182 tcg_temp_free_i64(fp0
);
10186 case OPC_RECIP2_PS
:
10187 check_cp1_64bitmode(ctx
);
10189 TCGv_i64 fp0
= tcg_temp_new_i64();
10190 TCGv_i64 fp1
= tcg_temp_new_i64();
10192 gen_load_fpr64(ctx
, fp0
, fs
);
10193 gen_load_fpr64(ctx
, fp1
, ft
);
10194 gen_helper_float_recip2_ps(fp0
, cpu_env
, fp0
, fp1
);
10195 tcg_temp_free_i64(fp1
);
10196 gen_store_fpr64(ctx
, fp0
, fd
);
10197 tcg_temp_free_i64(fp0
);
10201 case OPC_RECIP1_PS
:
10202 check_cp1_64bitmode(ctx
);
10204 TCGv_i64 fp0
= tcg_temp_new_i64();
10206 gen_load_fpr64(ctx
, fp0
, fs
);
10207 gen_helper_float_recip1_ps(fp0
, cpu_env
, fp0
);
10208 gen_store_fpr64(ctx
, fp0
, fd
);
10209 tcg_temp_free_i64(fp0
);
10213 case OPC_RSQRT1_PS
:
10214 check_cp1_64bitmode(ctx
);
10216 TCGv_i64 fp0
= tcg_temp_new_i64();
10218 gen_load_fpr64(ctx
, fp0
, fs
);
10219 gen_helper_float_rsqrt1_ps(fp0
, cpu_env
, fp0
);
10220 gen_store_fpr64(ctx
, fp0
, fd
);
10221 tcg_temp_free_i64(fp0
);
10225 case OPC_RSQRT2_PS
:
10226 check_cp1_64bitmode(ctx
);
10228 TCGv_i64 fp0
= tcg_temp_new_i64();
10229 TCGv_i64 fp1
= tcg_temp_new_i64();
10231 gen_load_fpr64(ctx
, fp0
, fs
);
10232 gen_load_fpr64(ctx
, fp1
, ft
);
10233 gen_helper_float_rsqrt2_ps(fp0
, cpu_env
, fp0
, fp1
);
10234 tcg_temp_free_i64(fp1
);
10235 gen_store_fpr64(ctx
, fp0
, fd
);
10236 tcg_temp_free_i64(fp0
);
10241 check_cp1_64bitmode(ctx
);
10243 TCGv_i32 fp0
= tcg_temp_new_i32();
10245 gen_load_fpr32h(ctx
, fp0
, fs
);
10246 gen_helper_float_cvts_pu(fp0
, cpu_env
, fp0
);
10247 gen_store_fpr32(ctx
, fp0
, fd
);
10248 tcg_temp_free_i32(fp0
);
10252 case OPC_CVT_PW_PS
:
10253 check_cp1_64bitmode(ctx
);
10255 TCGv_i64 fp0
= tcg_temp_new_i64();
10257 gen_load_fpr64(ctx
, fp0
, fs
);
10258 gen_helper_float_cvtpw_ps(fp0
, cpu_env
, fp0
);
10259 gen_store_fpr64(ctx
, fp0
, fd
);
10260 tcg_temp_free_i64(fp0
);
10265 check_cp1_64bitmode(ctx
);
10267 TCGv_i32 fp0
= tcg_temp_new_i32();
10269 gen_load_fpr32(ctx
, fp0
, fs
);
10270 gen_helper_float_cvts_pl(fp0
, cpu_env
, fp0
);
10271 gen_store_fpr32(ctx
, fp0
, fd
);
10272 tcg_temp_free_i32(fp0
);
10277 check_cp1_64bitmode(ctx
);
10279 TCGv_i32 fp0
= tcg_temp_new_i32();
10280 TCGv_i32 fp1
= tcg_temp_new_i32();
10282 gen_load_fpr32(ctx
, fp0
, fs
);
10283 gen_load_fpr32(ctx
, fp1
, ft
);
10284 gen_store_fpr32h(ctx
, fp0
, fd
);
10285 gen_store_fpr32(ctx
, fp1
, fd
);
10286 tcg_temp_free_i32(fp0
);
10287 tcg_temp_free_i32(fp1
);
10292 check_cp1_64bitmode(ctx
);
10294 TCGv_i32 fp0
= tcg_temp_new_i32();
10295 TCGv_i32 fp1
= tcg_temp_new_i32();
10297 gen_load_fpr32(ctx
, fp0
, fs
);
10298 gen_load_fpr32h(ctx
, fp1
, ft
);
10299 gen_store_fpr32(ctx
, fp1
, fd
);
10300 gen_store_fpr32h(ctx
, fp0
, fd
);
10301 tcg_temp_free_i32(fp0
);
10302 tcg_temp_free_i32(fp1
);
10307 check_cp1_64bitmode(ctx
);
10309 TCGv_i32 fp0
= tcg_temp_new_i32();
10310 TCGv_i32 fp1
= tcg_temp_new_i32();
10312 gen_load_fpr32h(ctx
, fp0
, fs
);
10313 gen_load_fpr32(ctx
, fp1
, ft
);
10314 gen_store_fpr32(ctx
, fp1
, fd
);
10315 gen_store_fpr32h(ctx
, fp0
, fd
);
10316 tcg_temp_free_i32(fp0
);
10317 tcg_temp_free_i32(fp1
);
10322 check_cp1_64bitmode(ctx
);
10324 TCGv_i32 fp0
= tcg_temp_new_i32();
10325 TCGv_i32 fp1
= tcg_temp_new_i32();
10327 gen_load_fpr32h(ctx
, fp0
, fs
);
10328 gen_load_fpr32h(ctx
, fp1
, ft
);
10329 gen_store_fpr32(ctx
, fp1
, fd
);
10330 gen_store_fpr32h(ctx
, fp0
, fd
);
10331 tcg_temp_free_i32(fp0
);
10332 tcg_temp_free_i32(fp1
);
10337 case OPC_CMP_UN_PS
:
10338 case OPC_CMP_EQ_PS
:
10339 case OPC_CMP_UEQ_PS
:
10340 case OPC_CMP_OLT_PS
:
10341 case OPC_CMP_ULT_PS
:
10342 case OPC_CMP_OLE_PS
:
10343 case OPC_CMP_ULE_PS
:
10344 case OPC_CMP_SF_PS
:
10345 case OPC_CMP_NGLE_PS
:
10346 case OPC_CMP_SEQ_PS
:
10347 case OPC_CMP_NGL_PS
:
10348 case OPC_CMP_LT_PS
:
10349 case OPC_CMP_NGE_PS
:
10350 case OPC_CMP_LE_PS
:
10351 case OPC_CMP_NGT_PS
:
10352 if (ctx
->opcode
& (1 << 6)) {
10353 gen_cmpabs_ps(ctx
, func
-48, ft
, fs
, cc
);
10354 opn
= condnames_abs
[func
-48];
10356 gen_cmp_ps(ctx
, func
-48, ft
, fs
, cc
);
10357 opn
= condnames
[func
-48];
10362 generate_exception (ctx
, EXCP_RI
);
10365 (void)opn
; /* avoid a compiler warning */
10368 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
10371 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
10374 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
10379 /* Coprocessor 3 (FPU) */
10380 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
10381 int fd
, int fs
, int base
, int index
)
10383 const char *opn
= "extended float load/store";
10385 TCGv t0
= tcg_temp_new();
10388 gen_load_gpr(t0
, index
);
10389 } else if (index
== 0) {
10390 gen_load_gpr(t0
, base
);
10392 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], cpu_gpr
[index
]);
10394 /* Don't do NOP if destination is zero: we must perform the actual
10400 TCGv_i32 fp0
= tcg_temp_new_i32();
10402 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESL
);
10403 tcg_gen_trunc_tl_i32(fp0
, t0
);
10404 gen_store_fpr32(ctx
, fp0
, fd
);
10405 tcg_temp_free_i32(fp0
);
10411 check_cp1_registers(ctx
, fd
);
10413 TCGv_i64 fp0
= tcg_temp_new_i64();
10414 tcg_gen_qemu_ld_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
10415 gen_store_fpr64(ctx
, fp0
, fd
);
10416 tcg_temp_free_i64(fp0
);
10421 check_cp1_64bitmode(ctx
);
10422 tcg_gen_andi_tl(t0
, t0
, ~0x7);
10424 TCGv_i64 fp0
= tcg_temp_new_i64();
10426 tcg_gen_qemu_ld_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
10427 gen_store_fpr64(ctx
, fp0
, fd
);
10428 tcg_temp_free_i64(fp0
);
10435 TCGv_i32 fp0
= tcg_temp_new_i32();
10436 gen_load_fpr32(ctx
, fp0
, fs
);
10437 tcg_gen_qemu_st_i32(fp0
, t0
, ctx
->mem_idx
, MO_TEUL
);
10438 tcg_temp_free_i32(fp0
);
10445 check_cp1_registers(ctx
, fs
);
10447 TCGv_i64 fp0
= tcg_temp_new_i64();
10448 gen_load_fpr64(ctx
, fp0
, fs
);
10449 tcg_gen_qemu_st_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
10450 tcg_temp_free_i64(fp0
);
10456 check_cp1_64bitmode(ctx
);
10457 tcg_gen_andi_tl(t0
, t0
, ~0x7);
10459 TCGv_i64 fp0
= tcg_temp_new_i64();
10460 gen_load_fpr64(ctx
, fp0
, fs
);
10461 tcg_gen_qemu_st_i64(fp0
, t0
, ctx
->mem_idx
, MO_TEQ
);
10462 tcg_temp_free_i64(fp0
);
10469 (void)opn
; (void)store
; /* avoid compiler warnings */
10470 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
10471 regnames
[index
], regnames
[base
]);
10474 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
10475 int fd
, int fr
, int fs
, int ft
)
10477 const char *opn
= "flt3_arith";
10481 check_cp1_64bitmode(ctx
);
10483 TCGv t0
= tcg_temp_local_new();
10484 TCGv_i32 fp
= tcg_temp_new_i32();
10485 TCGv_i32 fph
= tcg_temp_new_i32();
10486 TCGLabel
*l1
= gen_new_label();
10487 TCGLabel
*l2
= gen_new_label();
10489 gen_load_gpr(t0
, fr
);
10490 tcg_gen_andi_tl(t0
, t0
, 0x7);
10492 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
10493 gen_load_fpr32(ctx
, fp
, fs
);
10494 gen_load_fpr32h(ctx
, fph
, fs
);
10495 gen_store_fpr32(ctx
, fp
, fd
);
10496 gen_store_fpr32h(ctx
, fph
, fd
);
10499 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
10501 #ifdef TARGET_WORDS_BIGENDIAN
10502 gen_load_fpr32(ctx
, fp
, fs
);
10503 gen_load_fpr32h(ctx
, fph
, ft
);
10504 gen_store_fpr32h(ctx
, fp
, fd
);
10505 gen_store_fpr32(ctx
, fph
, fd
);
10507 gen_load_fpr32h(ctx
, fph
, fs
);
10508 gen_load_fpr32(ctx
, fp
, ft
);
10509 gen_store_fpr32(ctx
, fph
, fd
);
10510 gen_store_fpr32h(ctx
, fp
, fd
);
10513 tcg_temp_free_i32(fp
);
10514 tcg_temp_free_i32(fph
);
10521 TCGv_i32 fp0
= tcg_temp_new_i32();
10522 TCGv_i32 fp1
= tcg_temp_new_i32();
10523 TCGv_i32 fp2
= tcg_temp_new_i32();
10525 gen_load_fpr32(ctx
, fp0
, fs
);
10526 gen_load_fpr32(ctx
, fp1
, ft
);
10527 gen_load_fpr32(ctx
, fp2
, fr
);
10528 gen_helper_float_madd_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10529 tcg_temp_free_i32(fp0
);
10530 tcg_temp_free_i32(fp1
);
10531 gen_store_fpr32(ctx
, fp2
, fd
);
10532 tcg_temp_free_i32(fp2
);
10538 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
10540 TCGv_i64 fp0
= tcg_temp_new_i64();
10541 TCGv_i64 fp1
= tcg_temp_new_i64();
10542 TCGv_i64 fp2
= tcg_temp_new_i64();
10544 gen_load_fpr64(ctx
, fp0
, fs
);
10545 gen_load_fpr64(ctx
, fp1
, ft
);
10546 gen_load_fpr64(ctx
, fp2
, fr
);
10547 gen_helper_float_madd_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10548 tcg_temp_free_i64(fp0
);
10549 tcg_temp_free_i64(fp1
);
10550 gen_store_fpr64(ctx
, fp2
, fd
);
10551 tcg_temp_free_i64(fp2
);
10556 check_cp1_64bitmode(ctx
);
10558 TCGv_i64 fp0
= tcg_temp_new_i64();
10559 TCGv_i64 fp1
= tcg_temp_new_i64();
10560 TCGv_i64 fp2
= tcg_temp_new_i64();
10562 gen_load_fpr64(ctx
, fp0
, fs
);
10563 gen_load_fpr64(ctx
, fp1
, ft
);
10564 gen_load_fpr64(ctx
, fp2
, fr
);
10565 gen_helper_float_madd_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10566 tcg_temp_free_i64(fp0
);
10567 tcg_temp_free_i64(fp1
);
10568 gen_store_fpr64(ctx
, fp2
, fd
);
10569 tcg_temp_free_i64(fp2
);
10576 TCGv_i32 fp0
= tcg_temp_new_i32();
10577 TCGv_i32 fp1
= tcg_temp_new_i32();
10578 TCGv_i32 fp2
= tcg_temp_new_i32();
10580 gen_load_fpr32(ctx
, fp0
, fs
);
10581 gen_load_fpr32(ctx
, fp1
, ft
);
10582 gen_load_fpr32(ctx
, fp2
, fr
);
10583 gen_helper_float_msub_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10584 tcg_temp_free_i32(fp0
);
10585 tcg_temp_free_i32(fp1
);
10586 gen_store_fpr32(ctx
, fp2
, fd
);
10587 tcg_temp_free_i32(fp2
);
10593 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
10595 TCGv_i64 fp0
= tcg_temp_new_i64();
10596 TCGv_i64 fp1
= tcg_temp_new_i64();
10597 TCGv_i64 fp2
= tcg_temp_new_i64();
10599 gen_load_fpr64(ctx
, fp0
, fs
);
10600 gen_load_fpr64(ctx
, fp1
, ft
);
10601 gen_load_fpr64(ctx
, fp2
, fr
);
10602 gen_helper_float_msub_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10603 tcg_temp_free_i64(fp0
);
10604 tcg_temp_free_i64(fp1
);
10605 gen_store_fpr64(ctx
, fp2
, fd
);
10606 tcg_temp_free_i64(fp2
);
10611 check_cp1_64bitmode(ctx
);
10613 TCGv_i64 fp0
= tcg_temp_new_i64();
10614 TCGv_i64 fp1
= tcg_temp_new_i64();
10615 TCGv_i64 fp2
= tcg_temp_new_i64();
10617 gen_load_fpr64(ctx
, fp0
, fs
);
10618 gen_load_fpr64(ctx
, fp1
, ft
);
10619 gen_load_fpr64(ctx
, fp2
, fr
);
10620 gen_helper_float_msub_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10621 tcg_temp_free_i64(fp0
);
10622 tcg_temp_free_i64(fp1
);
10623 gen_store_fpr64(ctx
, fp2
, fd
);
10624 tcg_temp_free_i64(fp2
);
10631 TCGv_i32 fp0
= tcg_temp_new_i32();
10632 TCGv_i32 fp1
= tcg_temp_new_i32();
10633 TCGv_i32 fp2
= tcg_temp_new_i32();
10635 gen_load_fpr32(ctx
, fp0
, fs
);
10636 gen_load_fpr32(ctx
, fp1
, ft
);
10637 gen_load_fpr32(ctx
, fp2
, fr
);
10638 gen_helper_float_nmadd_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10639 tcg_temp_free_i32(fp0
);
10640 tcg_temp_free_i32(fp1
);
10641 gen_store_fpr32(ctx
, fp2
, fd
);
10642 tcg_temp_free_i32(fp2
);
10648 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
10650 TCGv_i64 fp0
= tcg_temp_new_i64();
10651 TCGv_i64 fp1
= tcg_temp_new_i64();
10652 TCGv_i64 fp2
= tcg_temp_new_i64();
10654 gen_load_fpr64(ctx
, fp0
, fs
);
10655 gen_load_fpr64(ctx
, fp1
, ft
);
10656 gen_load_fpr64(ctx
, fp2
, fr
);
10657 gen_helper_float_nmadd_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10658 tcg_temp_free_i64(fp0
);
10659 tcg_temp_free_i64(fp1
);
10660 gen_store_fpr64(ctx
, fp2
, fd
);
10661 tcg_temp_free_i64(fp2
);
10666 check_cp1_64bitmode(ctx
);
10668 TCGv_i64 fp0
= tcg_temp_new_i64();
10669 TCGv_i64 fp1
= tcg_temp_new_i64();
10670 TCGv_i64 fp2
= tcg_temp_new_i64();
10672 gen_load_fpr64(ctx
, fp0
, fs
);
10673 gen_load_fpr64(ctx
, fp1
, ft
);
10674 gen_load_fpr64(ctx
, fp2
, fr
);
10675 gen_helper_float_nmadd_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10676 tcg_temp_free_i64(fp0
);
10677 tcg_temp_free_i64(fp1
);
10678 gen_store_fpr64(ctx
, fp2
, fd
);
10679 tcg_temp_free_i64(fp2
);
10686 TCGv_i32 fp0
= tcg_temp_new_i32();
10687 TCGv_i32 fp1
= tcg_temp_new_i32();
10688 TCGv_i32 fp2
= tcg_temp_new_i32();
10690 gen_load_fpr32(ctx
, fp0
, fs
);
10691 gen_load_fpr32(ctx
, fp1
, ft
);
10692 gen_load_fpr32(ctx
, fp2
, fr
);
10693 gen_helper_float_nmsub_s(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10694 tcg_temp_free_i32(fp0
);
10695 tcg_temp_free_i32(fp1
);
10696 gen_store_fpr32(ctx
, fp2
, fd
);
10697 tcg_temp_free_i32(fp2
);
10703 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
10705 TCGv_i64 fp0
= tcg_temp_new_i64();
10706 TCGv_i64 fp1
= tcg_temp_new_i64();
10707 TCGv_i64 fp2
= tcg_temp_new_i64();
10709 gen_load_fpr64(ctx
, fp0
, fs
);
10710 gen_load_fpr64(ctx
, fp1
, ft
);
10711 gen_load_fpr64(ctx
, fp2
, fr
);
10712 gen_helper_float_nmsub_d(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10713 tcg_temp_free_i64(fp0
);
10714 tcg_temp_free_i64(fp1
);
10715 gen_store_fpr64(ctx
, fp2
, fd
);
10716 tcg_temp_free_i64(fp2
);
10721 check_cp1_64bitmode(ctx
);
10723 TCGv_i64 fp0
= tcg_temp_new_i64();
10724 TCGv_i64 fp1
= tcg_temp_new_i64();
10725 TCGv_i64 fp2
= tcg_temp_new_i64();
10727 gen_load_fpr64(ctx
, fp0
, fs
);
10728 gen_load_fpr64(ctx
, fp1
, ft
);
10729 gen_load_fpr64(ctx
, fp2
, fr
);
10730 gen_helper_float_nmsub_ps(fp2
, cpu_env
, fp0
, fp1
, fp2
);
10731 tcg_temp_free_i64(fp0
);
10732 tcg_temp_free_i64(fp1
);
10733 gen_store_fpr64(ctx
, fp2
, fd
);
10734 tcg_temp_free_i64(fp2
);
10740 generate_exception (ctx
, EXCP_RI
);
10743 (void)opn
; /* avoid a compiler warning */
10744 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
10745 fregnames
[fs
], fregnames
[ft
]);
10748 static void gen_rdhwr(DisasContext
*ctx
, int rt
, int rd
)
10752 #if !defined(CONFIG_USER_ONLY)
10753 /* The Linux kernel will emulate rdhwr if it's not supported natively.
10754 Therefore only check the ISA in system mode. */
10755 check_insn(ctx
, ISA_MIPS32R2
);
10757 t0
= tcg_temp_new();
10761 save_cpu_state(ctx
, 1);
10762 gen_helper_rdhwr_cpunum(t0
, cpu_env
);
10763 gen_store_gpr(t0
, rt
);
10766 save_cpu_state(ctx
, 1);
10767 gen_helper_rdhwr_synci_step(t0
, cpu_env
);
10768 gen_store_gpr(t0
, rt
);
10771 save_cpu_state(ctx
, 1);
10772 gen_helper_rdhwr_cc(t0
, cpu_env
);
10773 gen_store_gpr(t0
, rt
);
10776 save_cpu_state(ctx
, 1);
10777 gen_helper_rdhwr_ccres(t0
, cpu_env
);
10778 gen_store_gpr(t0
, rt
);
10781 #if defined(CONFIG_USER_ONLY)
10782 tcg_gen_ld_tl(t0
, cpu_env
,
10783 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
10784 gen_store_gpr(t0
, rt
);
10787 if ((ctx
->hflags
& MIPS_HFLAG_CP0
) ||
10788 (ctx
->hflags
& MIPS_HFLAG_HWRENA_ULR
)) {
10789 tcg_gen_ld_tl(t0
, cpu_env
,
10790 offsetof(CPUMIPSState
, active_tc
.CP0_UserLocal
));
10791 gen_store_gpr(t0
, rt
);
10793 generate_exception(ctx
, EXCP_RI
);
10797 default: /* Invalid */
10798 MIPS_INVAL("rdhwr");
10799 generate_exception(ctx
, EXCP_RI
);
10805 static inline void clear_branch_hflags(DisasContext
*ctx
)
10807 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
10808 if (ctx
->bstate
== BS_NONE
) {
10809 save_cpu_state(ctx
, 0);
10811 /* it is not safe to save ctx->hflags as hflags may be changed
10812 in execution time by the instruction in delay / forbidden slot. */
10813 tcg_gen_andi_i32(hflags
, hflags
, ~MIPS_HFLAG_BMASK
);
10817 static void gen_branch(DisasContext
*ctx
, int insn_bytes
)
10819 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
10820 int proc_hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
10821 /* Branches completion */
10822 clear_branch_hflags(ctx
);
10823 ctx
->bstate
= BS_BRANCH
;
10824 /* FIXME: Need to clear can_do_io. */
10825 switch (proc_hflags
& MIPS_HFLAG_BMASK_BASE
) {
10826 case MIPS_HFLAG_FBNSLOT
:
10827 MIPS_DEBUG("forbidden slot");
10828 gen_goto_tb(ctx
, 0, ctx
->pc
+ insn_bytes
);
10831 /* unconditional branch */
10832 MIPS_DEBUG("unconditional branch");
10833 if (proc_hflags
& MIPS_HFLAG_BX
) {
10834 tcg_gen_xori_i32(hflags
, hflags
, MIPS_HFLAG_M16
);
10836 gen_goto_tb(ctx
, 0, ctx
->btarget
);
10838 case MIPS_HFLAG_BL
:
10839 /* blikely taken case */
10840 MIPS_DEBUG("blikely branch taken");
10841 gen_goto_tb(ctx
, 0, ctx
->btarget
);
10843 case MIPS_HFLAG_BC
:
10844 /* Conditional branch */
10845 MIPS_DEBUG("conditional branch");
10847 TCGLabel
*l1
= gen_new_label();
10849 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
10850 gen_goto_tb(ctx
, 1, ctx
->pc
+ insn_bytes
);
10852 gen_goto_tb(ctx
, 0, ctx
->btarget
);
10855 case MIPS_HFLAG_BR
:
10856 /* unconditional branch to register */
10857 MIPS_DEBUG("branch to register");
10858 if (ctx
->insn_flags
& (ASE_MIPS16
| ASE_MICROMIPS
)) {
10859 TCGv t0
= tcg_temp_new();
10860 TCGv_i32 t1
= tcg_temp_new_i32();
10862 tcg_gen_andi_tl(t0
, btarget
, 0x1);
10863 tcg_gen_trunc_tl_i32(t1
, t0
);
10865 tcg_gen_andi_i32(hflags
, hflags
, ~(uint32_t)MIPS_HFLAG_M16
);
10866 tcg_gen_shli_i32(t1
, t1
, MIPS_HFLAG_M16_SHIFT
);
10867 tcg_gen_or_i32(hflags
, hflags
, t1
);
10868 tcg_temp_free_i32(t1
);
10870 tcg_gen_andi_tl(cpu_PC
, btarget
, ~(target_ulong
)0x1);
10872 tcg_gen_mov_tl(cpu_PC
, btarget
);
10874 if (ctx
->singlestep_enabled
) {
10875 save_cpu_state(ctx
, 0);
10876 gen_helper_0e0i(raise_exception
, EXCP_DEBUG
);
10878 tcg_gen_exit_tb(0);
10881 fprintf(stderr
, "unknown branch 0x%x\n", proc_hflags
);
10887 /* ISA extensions (ASEs) */
10888 /* MIPS16 extension to MIPS32 */
10890 /* MIPS16 major opcodes */
10892 M16_OPC_ADDIUSP
= 0x00,
10893 M16_OPC_ADDIUPC
= 0x01,
10895 M16_OPC_JAL
= 0x03,
10896 M16_OPC_BEQZ
= 0x04,
10897 M16_OPC_BNEQZ
= 0x05,
10898 M16_OPC_SHIFT
= 0x06,
10900 M16_OPC_RRIA
= 0x08,
10901 M16_OPC_ADDIU8
= 0x09,
10902 M16_OPC_SLTI
= 0x0a,
10903 M16_OPC_SLTIU
= 0x0b,
10906 M16_OPC_CMPI
= 0x0e,
10910 M16_OPC_LWSP
= 0x12,
10912 M16_OPC_LBU
= 0x14,
10913 M16_OPC_LHU
= 0x15,
10914 M16_OPC_LWPC
= 0x16,
10915 M16_OPC_LWU
= 0x17,
10918 M16_OPC_SWSP
= 0x1a,
10920 M16_OPC_RRR
= 0x1c,
10922 M16_OPC_EXTEND
= 0x1e,
10926 /* I8 funct field */
10945 /* RR funct field */
10979 /* I64 funct field */
10987 I64_DADDIUPC
= 0x6,
10991 /* RR ry field for CNVT */
10993 RR_RY_CNVT_ZEB
= 0x0,
10994 RR_RY_CNVT_ZEH
= 0x1,
10995 RR_RY_CNVT_ZEW
= 0x2,
10996 RR_RY_CNVT_SEB
= 0x4,
10997 RR_RY_CNVT_SEH
= 0x5,
10998 RR_RY_CNVT_SEW
= 0x6,
11001 static int xlat (int r
)
11003 static int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
11008 static void gen_mips16_save (DisasContext
*ctx
,
11009 int xsregs
, int aregs
,
11010 int do_ra
, int do_s0
, int do_s1
,
11013 TCGv t0
= tcg_temp_new();
11014 TCGv t1
= tcg_temp_new();
11015 TCGv t2
= tcg_temp_new();
11045 generate_exception(ctx
, EXCP_RI
);
11051 gen_base_offset_addr(ctx
, t0
, 29, 12);
11052 gen_load_gpr(t1
, 7);
11053 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
11056 gen_base_offset_addr(ctx
, t0
, 29, 8);
11057 gen_load_gpr(t1
, 6);
11058 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
11061 gen_base_offset_addr(ctx
, t0
, 29, 4);
11062 gen_load_gpr(t1
, 5);
11063 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
11066 gen_base_offset_addr(ctx
, t0
, 29, 0);
11067 gen_load_gpr(t1
, 4);
11068 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
11071 gen_load_gpr(t0
, 29);
11073 #define DECR_AND_STORE(reg) do { \
11074 tcg_gen_movi_tl(t2, -4); \
11075 gen_op_addr_add(ctx, t0, t0, t2); \
11076 gen_load_gpr(t1, reg); \
11077 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
11081 DECR_AND_STORE(31);
11086 DECR_AND_STORE(30);
11089 DECR_AND_STORE(23);
11092 DECR_AND_STORE(22);
11095 DECR_AND_STORE(21);
11098 DECR_AND_STORE(20);
11101 DECR_AND_STORE(19);
11104 DECR_AND_STORE(18);
11108 DECR_AND_STORE(17);
11111 DECR_AND_STORE(16);
11141 generate_exception(ctx
, EXCP_RI
);
11157 #undef DECR_AND_STORE
11159 tcg_gen_movi_tl(t2
, -framesize
);
11160 gen_op_addr_add(ctx
, cpu_gpr
[29], cpu_gpr
[29], t2
);
11166 static void gen_mips16_restore (DisasContext
*ctx
,
11167 int xsregs
, int aregs
,
11168 int do_ra
, int do_s0
, int do_s1
,
11172 TCGv t0
= tcg_temp_new();
11173 TCGv t1
= tcg_temp_new();
11174 TCGv t2
= tcg_temp_new();
11176 tcg_gen_movi_tl(t2
, framesize
);
11177 gen_op_addr_add(ctx
, t0
, cpu_gpr
[29], t2
);
11179 #define DECR_AND_LOAD(reg) do { \
11180 tcg_gen_movi_tl(t2, -4); \
11181 gen_op_addr_add(ctx, t0, t0, t2); \
11182 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
11183 gen_store_gpr(t1, reg); \
11247 generate_exception(ctx
, EXCP_RI
);
11263 #undef DECR_AND_LOAD
11265 tcg_gen_movi_tl(t2
, framesize
);
11266 gen_op_addr_add(ctx
, cpu_gpr
[29], cpu_gpr
[29], t2
);
11272 static void gen_addiupc (DisasContext
*ctx
, int rx
, int imm
,
11273 int is_64_bit
, int extended
)
11277 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
11278 generate_exception(ctx
, EXCP_RI
);
11282 t0
= tcg_temp_new();
11284 tcg_gen_movi_tl(t0
, pc_relative_pc(ctx
));
11285 tcg_gen_addi_tl(cpu_gpr
[rx
], t0
, imm
);
11287 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11293 #if defined(TARGET_MIPS64)
11294 static void decode_i64_mips16 (DisasContext
*ctx
,
11295 int ry
, int funct
, int16_t offset
,
11300 check_insn(ctx
, ISA_MIPS3
);
11301 check_mips_64(ctx
);
11302 offset
= extended
? offset
: offset
<< 3;
11303 gen_ld(ctx
, OPC_LD
, ry
, 29, offset
);
11306 check_insn(ctx
, ISA_MIPS3
);
11307 check_mips_64(ctx
);
11308 offset
= extended
? offset
: offset
<< 3;
11309 gen_st(ctx
, OPC_SD
, ry
, 29, offset
);
11312 check_insn(ctx
, ISA_MIPS3
);
11313 check_mips_64(ctx
);
11314 offset
= extended
? offset
: (ctx
->opcode
& 0xff) << 3;
11315 gen_st(ctx
, OPC_SD
, 31, 29, offset
);
11318 check_insn(ctx
, ISA_MIPS3
);
11319 check_mips_64(ctx
);
11320 offset
= extended
? offset
: ((int8_t)ctx
->opcode
) << 3;
11321 gen_arith_imm(ctx
, OPC_DADDIU
, 29, 29, offset
);
11324 check_insn(ctx
, ISA_MIPS3
);
11325 check_mips_64(ctx
);
11326 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
11327 generate_exception(ctx
, EXCP_RI
);
11329 offset
= extended
? offset
: offset
<< 3;
11330 gen_ld(ctx
, OPC_LDPC
, ry
, 0, offset
);
11334 check_insn(ctx
, ISA_MIPS3
);
11335 check_mips_64(ctx
);
11336 offset
= extended
? offset
: ((int8_t)(offset
<< 3)) >> 3;
11337 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, ry
, offset
);
11340 check_insn(ctx
, ISA_MIPS3
);
11341 check_mips_64(ctx
);
11342 offset
= extended
? offset
: offset
<< 2;
11343 gen_addiupc(ctx
, ry
, offset
, 1, extended
);
11346 check_insn(ctx
, ISA_MIPS3
);
11347 check_mips_64(ctx
);
11348 offset
= extended
? offset
: offset
<< 2;
11349 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, 29, offset
);
11355 static int decode_extended_mips16_opc (CPUMIPSState
*env
, DisasContext
*ctx
)
11357 int extend
= cpu_lduw_code(env
, ctx
->pc
+ 2);
11358 int op
, rx
, ry
, funct
, sa
;
11359 int16_t imm
, offset
;
11361 ctx
->opcode
= (ctx
->opcode
<< 16) | extend
;
11362 op
= (ctx
->opcode
>> 11) & 0x1f;
11363 sa
= (ctx
->opcode
>> 22) & 0x1f;
11364 funct
= (ctx
->opcode
>> 8) & 0x7;
11365 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
11366 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
11367 offset
= imm
= (int16_t) (((ctx
->opcode
>> 16) & 0x1f) << 11
11368 | ((ctx
->opcode
>> 21) & 0x3f) << 5
11369 | (ctx
->opcode
& 0x1f));
11371 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
11374 case M16_OPC_ADDIUSP
:
11375 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, 29, imm
);
11377 case M16_OPC_ADDIUPC
:
11378 gen_addiupc(ctx
, rx
, imm
, 0, 1);
11381 gen_compute_branch(ctx
, OPC_BEQ
, 4, 0, 0, offset
<< 1, 0);
11382 /* No delay slot, so just process as a normal instruction */
11385 gen_compute_branch(ctx
, OPC_BEQ
, 4, rx
, 0, offset
<< 1, 0);
11386 /* No delay slot, so just process as a normal instruction */
11388 case M16_OPC_BNEQZ
:
11389 gen_compute_branch(ctx
, OPC_BNE
, 4, rx
, 0, offset
<< 1, 0);
11390 /* No delay slot, so just process as a normal instruction */
11392 case M16_OPC_SHIFT
:
11393 switch (ctx
->opcode
& 0x3) {
11395 gen_shift_imm(ctx
, OPC_SLL
, rx
, ry
, sa
);
11398 #if defined(TARGET_MIPS64)
11399 check_mips_64(ctx
);
11400 gen_shift_imm(ctx
, OPC_DSLL
, rx
, ry
, sa
);
11402 generate_exception(ctx
, EXCP_RI
);
11406 gen_shift_imm(ctx
, OPC_SRL
, rx
, ry
, sa
);
11409 gen_shift_imm(ctx
, OPC_SRA
, rx
, ry
, sa
);
11413 #if defined(TARGET_MIPS64)
11415 check_insn(ctx
, ISA_MIPS3
);
11416 check_mips_64(ctx
);
11417 gen_ld(ctx
, OPC_LD
, ry
, rx
, offset
);
11421 imm
= ctx
->opcode
& 0xf;
11422 imm
= imm
| ((ctx
->opcode
>> 20) & 0x7f) << 4;
11423 imm
= imm
| ((ctx
->opcode
>> 16) & 0xf) << 11;
11424 imm
= (int16_t) (imm
<< 1) >> 1;
11425 if ((ctx
->opcode
>> 4) & 0x1) {
11426 #if defined(TARGET_MIPS64)
11427 check_mips_64(ctx
);
11428 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, rx
, imm
);
11430 generate_exception(ctx
, EXCP_RI
);
11433 gen_arith_imm(ctx
, OPC_ADDIU
, ry
, rx
, imm
);
11436 case M16_OPC_ADDIU8
:
11437 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, rx
, imm
);
11440 gen_slt_imm(ctx
, OPC_SLTI
, 24, rx
, imm
);
11442 case M16_OPC_SLTIU
:
11443 gen_slt_imm(ctx
, OPC_SLTIU
, 24, rx
, imm
);
11448 gen_compute_branch(ctx
, OPC_BEQ
, 4, 24, 0, offset
<< 1, 0);
11451 gen_compute_branch(ctx
, OPC_BNE
, 4, 24, 0, offset
<< 1, 0);
11454 gen_st(ctx
, OPC_SW
, 31, 29, imm
);
11457 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, imm
);
11460 check_insn(ctx
, ISA_MIPS32
);
11462 int xsregs
= (ctx
->opcode
>> 24) & 0x7;
11463 int aregs
= (ctx
->opcode
>> 16) & 0xf;
11464 int do_ra
= (ctx
->opcode
>> 6) & 0x1;
11465 int do_s0
= (ctx
->opcode
>> 5) & 0x1;
11466 int do_s1
= (ctx
->opcode
>> 4) & 0x1;
11467 int framesize
= (((ctx
->opcode
>> 20) & 0xf) << 4
11468 | (ctx
->opcode
& 0xf)) << 3;
11470 if (ctx
->opcode
& (1 << 7)) {
11471 gen_mips16_save(ctx
, xsregs
, aregs
,
11472 do_ra
, do_s0
, do_s1
,
11475 gen_mips16_restore(ctx
, xsregs
, aregs
,
11476 do_ra
, do_s0
, do_s1
,
11482 generate_exception(ctx
, EXCP_RI
);
11487 tcg_gen_movi_tl(cpu_gpr
[rx
], (uint16_t) imm
);
11490 tcg_gen_xori_tl(cpu_gpr
[24], cpu_gpr
[rx
], (uint16_t) imm
);
11492 #if defined(TARGET_MIPS64)
11494 check_insn(ctx
, ISA_MIPS3
);
11495 check_mips_64(ctx
);
11496 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
);
11500 gen_ld(ctx
, OPC_LB
, ry
, rx
, offset
);
11503 gen_ld(ctx
, OPC_LH
, ry
, rx
, offset
);
11506 gen_ld(ctx
, OPC_LW
, rx
, 29, offset
);
11509 gen_ld(ctx
, OPC_LW
, ry
, rx
, offset
);
11512 gen_ld(ctx
, OPC_LBU
, ry
, rx
, offset
);
11515 gen_ld(ctx
, OPC_LHU
, ry
, rx
, offset
);
11518 gen_ld(ctx
, OPC_LWPC
, rx
, 0, offset
);
11520 #if defined(TARGET_MIPS64)
11522 check_insn(ctx
, ISA_MIPS3
);
11523 check_mips_64(ctx
);
11524 gen_ld(ctx
, OPC_LWU
, ry
, rx
, offset
);
11528 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
11531 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
);
11534 gen_st(ctx
, OPC_SW
, rx
, 29, offset
);
11537 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
);
11539 #if defined(TARGET_MIPS64)
11541 decode_i64_mips16(ctx
, ry
, funct
, offset
, 1);
11545 generate_exception(ctx
, EXCP_RI
);
11552 static int decode_mips16_opc (CPUMIPSState
*env
, DisasContext
*ctx
)
11556 int op
, cnvt_op
, op1
, offset
;
11560 op
= (ctx
->opcode
>> 11) & 0x1f;
11561 sa
= (ctx
->opcode
>> 2) & 0x7;
11562 sa
= sa
== 0 ? 8 : sa
;
11563 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
11564 cnvt_op
= (ctx
->opcode
>> 5) & 0x7;
11565 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
11566 op1
= offset
= ctx
->opcode
& 0x1f;
11571 case M16_OPC_ADDIUSP
:
11573 int16_t imm
= ((uint8_t) ctx
->opcode
) << 2;
11575 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, 29, imm
);
11578 case M16_OPC_ADDIUPC
:
11579 gen_addiupc(ctx
, rx
, ((uint8_t) ctx
->opcode
) << 2, 0, 0);
11582 offset
= (ctx
->opcode
& 0x7ff) << 1;
11583 offset
= (int16_t)(offset
<< 4) >> 4;
11584 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0, offset
, 0);
11585 /* No delay slot, so just process as a normal instruction */
11588 offset
= cpu_lduw_code(env
, ctx
->pc
+ 2);
11589 offset
= (((ctx
->opcode
& 0x1f) << 21)
11590 | ((ctx
->opcode
>> 5) & 0x1f) << 16
11592 op
= ((ctx
->opcode
>> 10) & 0x1) ? OPC_JALX
: OPC_JAL
;
11593 gen_compute_branch(ctx
, op
, 4, rx
, ry
, offset
, 2);
11597 gen_compute_branch(ctx
, OPC_BEQ
, 2, rx
, 0,
11598 ((int8_t)ctx
->opcode
) << 1, 0);
11599 /* No delay slot, so just process as a normal instruction */
11601 case M16_OPC_BNEQZ
:
11602 gen_compute_branch(ctx
, OPC_BNE
, 2, rx
, 0,
11603 ((int8_t)ctx
->opcode
) << 1, 0);
11604 /* No delay slot, so just process as a normal instruction */
11606 case M16_OPC_SHIFT
:
11607 switch (ctx
->opcode
& 0x3) {
11609 gen_shift_imm(ctx
, OPC_SLL
, rx
, ry
, sa
);
11612 #if defined(TARGET_MIPS64)
11613 check_insn(ctx
, ISA_MIPS3
);
11614 check_mips_64(ctx
);
11615 gen_shift_imm(ctx
, OPC_DSLL
, rx
, ry
, sa
);
11617 generate_exception(ctx
, EXCP_RI
);
11621 gen_shift_imm(ctx
, OPC_SRL
, rx
, ry
, sa
);
11624 gen_shift_imm(ctx
, OPC_SRA
, rx
, ry
, sa
);
11628 #if defined(TARGET_MIPS64)
11630 check_insn(ctx
, ISA_MIPS3
);
11631 check_mips_64(ctx
);
11632 gen_ld(ctx
, OPC_LD
, ry
, rx
, offset
<< 3);
11637 int16_t imm
= (int8_t)((ctx
->opcode
& 0xf) << 4) >> 4;
11639 if ((ctx
->opcode
>> 4) & 1) {
11640 #if defined(TARGET_MIPS64)
11641 check_insn(ctx
, ISA_MIPS3
);
11642 check_mips_64(ctx
);
11643 gen_arith_imm(ctx
, OPC_DADDIU
, ry
, rx
, imm
);
11645 generate_exception(ctx
, EXCP_RI
);
11648 gen_arith_imm(ctx
, OPC_ADDIU
, ry
, rx
, imm
);
11652 case M16_OPC_ADDIU8
:
11654 int16_t imm
= (int8_t) ctx
->opcode
;
11656 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, rx
, imm
);
11661 int16_t imm
= (uint8_t) ctx
->opcode
;
11662 gen_slt_imm(ctx
, OPC_SLTI
, 24, rx
, imm
);
11665 case M16_OPC_SLTIU
:
11667 int16_t imm
= (uint8_t) ctx
->opcode
;
11668 gen_slt_imm(ctx
, OPC_SLTIU
, 24, rx
, imm
);
11675 funct
= (ctx
->opcode
>> 8) & 0x7;
11678 gen_compute_branch(ctx
, OPC_BEQ
, 2, 24, 0,
11679 ((int8_t)ctx
->opcode
) << 1, 0);
11682 gen_compute_branch(ctx
, OPC_BNE
, 2, 24, 0,
11683 ((int8_t)ctx
->opcode
) << 1, 0);
11686 gen_st(ctx
, OPC_SW
, 31, 29, (ctx
->opcode
& 0xff) << 2);
11689 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29,
11690 ((int8_t)ctx
->opcode
) << 3);
11693 check_insn(ctx
, ISA_MIPS32
);
11695 int do_ra
= ctx
->opcode
& (1 << 6);
11696 int do_s0
= ctx
->opcode
& (1 << 5);
11697 int do_s1
= ctx
->opcode
& (1 << 4);
11698 int framesize
= ctx
->opcode
& 0xf;
11700 if (framesize
== 0) {
11703 framesize
= framesize
<< 3;
11706 if (ctx
->opcode
& (1 << 7)) {
11707 gen_mips16_save(ctx
, 0, 0,
11708 do_ra
, do_s0
, do_s1
, framesize
);
11710 gen_mips16_restore(ctx
, 0, 0,
11711 do_ra
, do_s0
, do_s1
, framesize
);
11717 int rz
= xlat(ctx
->opcode
& 0x7);
11719 reg32
= (((ctx
->opcode
>> 3) & 0x3) << 3) |
11720 ((ctx
->opcode
>> 5) & 0x7);
11721 gen_arith(ctx
, OPC_ADDU
, reg32
, rz
, 0);
11725 reg32
= ctx
->opcode
& 0x1f;
11726 gen_arith(ctx
, OPC_ADDU
, ry
, reg32
, 0);
11729 generate_exception(ctx
, EXCP_RI
);
11736 int16_t imm
= (uint8_t) ctx
->opcode
;
11738 gen_arith_imm(ctx
, OPC_ADDIU
, rx
, 0, imm
);
11743 int16_t imm
= (uint8_t) ctx
->opcode
;
11744 gen_logic_imm(ctx
, OPC_XORI
, 24, rx
, imm
);
11747 #if defined(TARGET_MIPS64)
11749 check_insn(ctx
, ISA_MIPS3
);
11750 check_mips_64(ctx
);
11751 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
<< 3);
11755 gen_ld(ctx
, OPC_LB
, ry
, rx
, offset
);
11758 gen_ld(ctx
, OPC_LH
, ry
, rx
, offset
<< 1);
11761 gen_ld(ctx
, OPC_LW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
11764 gen_ld(ctx
, OPC_LW
, ry
, rx
, offset
<< 2);
11767 gen_ld(ctx
, OPC_LBU
, ry
, rx
, offset
);
11770 gen_ld(ctx
, OPC_LHU
, ry
, rx
, offset
<< 1);
11773 gen_ld(ctx
, OPC_LWPC
, rx
, 0, ((uint8_t)ctx
->opcode
) << 2);
11775 #if defined (TARGET_MIPS64)
11777 check_insn(ctx
, ISA_MIPS3
);
11778 check_mips_64(ctx
);
11779 gen_ld(ctx
, OPC_LWU
, ry
, rx
, offset
<< 2);
11783 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
11786 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
<< 1);
11789 gen_st(ctx
, OPC_SW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
11792 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
<< 2);
11796 int rz
= xlat((ctx
->opcode
>> 2) & 0x7);
11799 switch (ctx
->opcode
& 0x3) {
11801 mips32_op
= OPC_ADDU
;
11804 mips32_op
= OPC_SUBU
;
11806 #if defined(TARGET_MIPS64)
11808 mips32_op
= OPC_DADDU
;
11809 check_insn(ctx
, ISA_MIPS3
);
11810 check_mips_64(ctx
);
11813 mips32_op
= OPC_DSUBU
;
11814 check_insn(ctx
, ISA_MIPS3
);
11815 check_mips_64(ctx
);
11819 generate_exception(ctx
, EXCP_RI
);
11823 gen_arith(ctx
, mips32_op
, rz
, rx
, ry
);
11832 int nd
= (ctx
->opcode
>> 7) & 0x1;
11833 int link
= (ctx
->opcode
>> 6) & 0x1;
11834 int ra
= (ctx
->opcode
>> 5) & 0x1;
11837 check_insn(ctx
, ISA_MIPS32
);
11846 gen_compute_branch(ctx
, op
, 2, ra
? 31 : rx
, 31, 0,
11851 /* XXX: not clear which exception should be raised
11852 * when in debug mode...
11854 check_insn(ctx
, ISA_MIPS32
);
11855 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
11856 generate_exception(ctx
, EXCP_DBp
);
11858 generate_exception(ctx
, EXCP_DBp
);
11862 gen_slt(ctx
, OPC_SLT
, 24, rx
, ry
);
11865 gen_slt(ctx
, OPC_SLTU
, 24, rx
, ry
);
11868 generate_exception(ctx
, EXCP_BREAK
);
11871 gen_shift(ctx
, OPC_SLLV
, ry
, rx
, ry
);
11874 gen_shift(ctx
, OPC_SRLV
, ry
, rx
, ry
);
11877 gen_shift(ctx
, OPC_SRAV
, ry
, rx
, ry
);
11879 #if defined (TARGET_MIPS64)
11881 check_insn(ctx
, ISA_MIPS3
);
11882 check_mips_64(ctx
);
11883 gen_shift_imm(ctx
, OPC_DSRL
, ry
, ry
, sa
);
11887 gen_logic(ctx
, OPC_XOR
, 24, rx
, ry
);
11890 gen_arith(ctx
, OPC_SUBU
, rx
, 0, ry
);
11893 gen_logic(ctx
, OPC_AND
, rx
, rx
, ry
);
11896 gen_logic(ctx
, OPC_OR
, rx
, rx
, ry
);
11899 gen_logic(ctx
, OPC_XOR
, rx
, rx
, ry
);
11902 gen_logic(ctx
, OPC_NOR
, rx
, ry
, 0);
11905 gen_HILO(ctx
, OPC_MFHI
, 0, rx
);
11908 check_insn(ctx
, ISA_MIPS32
);
11910 case RR_RY_CNVT_ZEB
:
11911 tcg_gen_ext8u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11913 case RR_RY_CNVT_ZEH
:
11914 tcg_gen_ext16u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11916 case RR_RY_CNVT_SEB
:
11917 tcg_gen_ext8s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11919 case RR_RY_CNVT_SEH
:
11920 tcg_gen_ext16s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11922 #if defined (TARGET_MIPS64)
11923 case RR_RY_CNVT_ZEW
:
11924 check_insn(ctx
, ISA_MIPS64
);
11925 check_mips_64(ctx
);
11926 tcg_gen_ext32u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11928 case RR_RY_CNVT_SEW
:
11929 check_insn(ctx
, ISA_MIPS64
);
11930 check_mips_64(ctx
);
11931 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
11935 generate_exception(ctx
, EXCP_RI
);
11940 gen_HILO(ctx
, OPC_MFLO
, 0, rx
);
11942 #if defined (TARGET_MIPS64)
11944 check_insn(ctx
, ISA_MIPS3
);
11945 check_mips_64(ctx
);
11946 gen_shift_imm(ctx
, OPC_DSRA
, ry
, ry
, sa
);
11949 check_insn(ctx
, ISA_MIPS3
);
11950 check_mips_64(ctx
);
11951 gen_shift(ctx
, OPC_DSLLV
, ry
, rx
, ry
);
11954 check_insn(ctx
, ISA_MIPS3
);
11955 check_mips_64(ctx
);
11956 gen_shift(ctx
, OPC_DSRLV
, ry
, rx
, ry
);
11959 check_insn(ctx
, ISA_MIPS3
);
11960 check_mips_64(ctx
);
11961 gen_shift(ctx
, OPC_DSRAV
, ry
, rx
, ry
);
11965 gen_muldiv(ctx
, OPC_MULT
, 0, rx
, ry
);
11968 gen_muldiv(ctx
, OPC_MULTU
, 0, rx
, ry
);
11971 gen_muldiv(ctx
, OPC_DIV
, 0, rx
, ry
);
11974 gen_muldiv(ctx
, OPC_DIVU
, 0, rx
, ry
);
11976 #if defined (TARGET_MIPS64)
11978 check_insn(ctx
, ISA_MIPS3
);
11979 check_mips_64(ctx
);
11980 gen_muldiv(ctx
, OPC_DMULT
, 0, rx
, ry
);
11983 check_insn(ctx
, ISA_MIPS3
);
11984 check_mips_64(ctx
);
11985 gen_muldiv(ctx
, OPC_DMULTU
, 0, rx
, ry
);
11988 check_insn(ctx
, ISA_MIPS3
);
11989 check_mips_64(ctx
);
11990 gen_muldiv(ctx
, OPC_DDIV
, 0, rx
, ry
);
11993 check_insn(ctx
, ISA_MIPS3
);
11994 check_mips_64(ctx
);
11995 gen_muldiv(ctx
, OPC_DDIVU
, 0, rx
, ry
);
11999 generate_exception(ctx
, EXCP_RI
);
12003 case M16_OPC_EXTEND
:
12004 decode_extended_mips16_opc(env
, ctx
);
12007 #if defined(TARGET_MIPS64)
12009 funct
= (ctx
->opcode
>> 8) & 0x7;
12010 decode_i64_mips16(ctx
, ry
, funct
, offset
, 0);
12014 generate_exception(ctx
, EXCP_RI
);
12021 /* microMIPS extension to MIPS32/MIPS64 */
12024 * microMIPS32/microMIPS64 major opcodes
12026 * 1. MIPS Architecture for Programmers Volume II-B:
12027 * The microMIPS32 Instruction Set (Revision 3.05)
12029 * Table 6.2 microMIPS32 Encoding of Major Opcode Field
12031 * 2. MIPS Architecture For Programmers Volume II-A:
12032 * The MIPS64 Instruction Set (Revision 3.51)
12060 POOL32S
= 0x16, /* MIPS64 */
12061 DADDIU32
= 0x17, /* MIPS64 */
12063 /* 0x1f is reserved */
12072 /* 0x20 is reserved */
12082 /* 0x28 and 0x29 are reserved */
12092 /* 0x30 and 0x31 are reserved */
12099 SD32
= 0x36, /* MIPS64 */
12100 LD32
= 0x37, /* MIPS64 */
12102 /* 0x38 and 0x39 are reserved */
12113 /* POOL32A encoding of minor opcode field */
12116 /* These opcodes are distinguished only by bits 9..6; those bits are
12117 * what are recorded below. */
12143 /* The following can be distinguished by their lower 6 bits. */
12149 /* POOL32AXF encoding of minor opcode field extension */
12152 * 1. MIPS Architecture for Programmers Volume II-B:
12153 * The microMIPS32 Instruction Set (Revision 3.05)
12155 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
12157 * 2. MIPS Architecture for Programmers VolumeIV-e:
12158 * The MIPS DSP Application-Specific Extension
12159 * to the microMIPS32 Architecture (Revision 2.34)
12161 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
12176 /* begin of microMIPS32 DSP */
12178 /* bits 13..12 for 0x01 */
12184 /* bits 13..12 for 0x2a */
12190 /* bits 13..12 for 0x32 */
12194 /* end of microMIPS32 DSP */
12196 /* bits 15..12 for 0x2c */
12212 /* bits 15..12 for 0x34 */
12220 /* bits 15..12 for 0x3c */
12222 JR
= 0x0, /* alias */
12227 /* bits 15..12 for 0x05 */
12231 /* bits 15..12 for 0x0d */
12241 /* bits 15..12 for 0x15 */
12247 /* bits 15..12 for 0x1d */
12251 /* bits 15..12 for 0x2d */
12256 /* bits 15..12 for 0x35 */
12263 /* POOL32B encoding of minor opcode field (bits 15..12) */
12279 /* POOL32C encoding of minor opcode field (bits 15..12) */
12287 /* 0xa is reserved */
12294 /* 0x6 is reserved */
12300 /* POOL32F encoding of minor opcode field (bits 5..0) */
12303 /* These are the bit 7..6 values */
12314 /* These are the bit 8..6 values */
12358 CABS_COND_FMT
= 0x1c, /* MIPS3D */
12362 /* POOL32Fxf encoding of minor opcode extension field */
12400 /* POOL32I encoding of minor opcode field (bits 25..21) */
12425 /* These overlap and are distinguished by bit16 of the instruction */
12434 /* POOL16A encoding of minor opcode field */
12441 /* POOL16B encoding of minor opcode field */
12448 /* POOL16C encoding of minor opcode field */
12468 /* POOL16D encoding of minor opcode field */
12475 /* POOL16E encoding of minor opcode field */
12482 static int mmreg (int r
)
12484 static const int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
12489 /* Used for 16-bit store instructions. */
12490 static int mmreg2 (int r
)
12492 static const int map
[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
12497 #define uMIPS_RD(op) ((op >> 7) & 0x7)
12498 #define uMIPS_RS(op) ((op >> 4) & 0x7)
12499 #define uMIPS_RS2(op) uMIPS_RS(op)
12500 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
12501 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
12502 #define uMIPS_RS5(op) (op & 0x1f)
12504 /* Signed immediate */
12505 #define SIMM(op, start, width) \
12506 ((int32_t)(((op >> start) & ((~0U) >> (32-width))) \
12509 /* Zero-extended immediate */
12510 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
12512 static void gen_addiur1sp(DisasContext
*ctx
)
12514 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
12516 gen_arith_imm(ctx
, OPC_ADDIU
, rd
, 29, ((ctx
->opcode
>> 1) & 0x3f) << 2);
12519 static void gen_addiur2(DisasContext
*ctx
)
12521 static const int decoded_imm
[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
12522 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
12523 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
12525 gen_arith_imm(ctx
, OPC_ADDIU
, rd
, rs
, decoded_imm
[ZIMM(ctx
->opcode
, 1, 3)]);
12528 static void gen_addiusp(DisasContext
*ctx
)
12530 int encoded
= ZIMM(ctx
->opcode
, 1, 9);
12533 if (encoded
<= 1) {
12534 decoded
= 256 + encoded
;
12535 } else if (encoded
<= 255) {
12537 } else if (encoded
<= 509) {
12538 decoded
= encoded
- 512;
12540 decoded
= encoded
- 768;
12543 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, decoded
<< 2);
12546 static void gen_addius5(DisasContext
*ctx
)
12548 int imm
= SIMM(ctx
->opcode
, 1, 4);
12549 int rd
= (ctx
->opcode
>> 5) & 0x1f;
12551 gen_arith_imm(ctx
, OPC_ADDIU
, rd
, rd
, imm
);
12554 static void gen_andi16(DisasContext
*ctx
)
12556 static const int decoded_imm
[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
12557 31, 32, 63, 64, 255, 32768, 65535 };
12558 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
12559 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
12560 int encoded
= ZIMM(ctx
->opcode
, 0, 4);
12562 gen_logic_imm(ctx
, OPC_ANDI
, rd
, rs
, decoded_imm
[encoded
]);
12565 static void gen_ldst_multiple (DisasContext
*ctx
, uint32_t opc
, int reglist
,
12566 int base
, int16_t offset
)
12568 const char *opn
= "ldst_multiple";
12572 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
12573 generate_exception(ctx
, EXCP_RI
);
12577 t0
= tcg_temp_new();
12579 gen_base_offset_addr(ctx
, t0
, base
, offset
);
12581 t1
= tcg_const_tl(reglist
);
12582 t2
= tcg_const_i32(ctx
->mem_idx
);
12584 save_cpu_state(ctx
, 1);
12587 gen_helper_lwm(cpu_env
, t0
, t1
, t2
);
12591 gen_helper_swm(cpu_env
, t0
, t1
, t2
);
12594 #ifdef TARGET_MIPS64
12596 gen_helper_ldm(cpu_env
, t0
, t1
, t2
);
12600 gen_helper_sdm(cpu_env
, t0
, t1
, t2
);
12606 MIPS_DEBUG("%s, %x, %d(%s)", opn
, reglist
, offset
, regnames
[base
]);
12609 tcg_temp_free_i32(t2
);
12613 static void gen_pool16c_insn(DisasContext
*ctx
)
12615 int rd
= mmreg((ctx
->opcode
>> 3) & 0x7);
12616 int rs
= mmreg(ctx
->opcode
& 0x7);
12618 switch (((ctx
->opcode
) >> 4) & 0x3f) {
12623 gen_logic(ctx
, OPC_NOR
, rd
, rs
, 0);
12629 gen_logic(ctx
, OPC_XOR
, rd
, rd
, rs
);
12635 gen_logic(ctx
, OPC_AND
, rd
, rd
, rs
);
12641 gen_logic(ctx
, OPC_OR
, rd
, rd
, rs
);
12648 static const int lwm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
12649 int offset
= ZIMM(ctx
->opcode
, 0, 4);
12651 gen_ldst_multiple(ctx
, LWM32
, lwm_convert
[(ctx
->opcode
>> 4) & 0x3],
12660 static const int swm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
12661 int offset
= ZIMM(ctx
->opcode
, 0, 4);
12663 gen_ldst_multiple(ctx
, SWM32
, swm_convert
[(ctx
->opcode
>> 4) & 0x3],
12670 int reg
= ctx
->opcode
& 0x1f;
12672 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0, 4);
12678 int reg
= ctx
->opcode
& 0x1f;
12679 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0, 0);
12680 /* Let normal delay slot handling in our caller take us
12681 to the branch target. */
12686 gen_compute_branch(ctx
, OPC_JALR
, 2, ctx
->opcode
& 0x1f, 31, 0, 4);
12687 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
12691 gen_compute_branch(ctx
, OPC_JALR
, 2, ctx
->opcode
& 0x1f, 31, 0, 2);
12692 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
12696 gen_HILO(ctx
, OPC_MFHI
, 0, uMIPS_RS5(ctx
->opcode
));
12700 gen_HILO(ctx
, OPC_MFLO
, 0, uMIPS_RS5(ctx
->opcode
));
12703 generate_exception(ctx
, EXCP_BREAK
);
12706 /* XXX: not clear which exception should be raised
12707 * when in debug mode...
12709 check_insn(ctx
, ISA_MIPS32
);
12710 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
12711 generate_exception(ctx
, EXCP_DBp
);
12713 generate_exception(ctx
, EXCP_DBp
);
12716 case JRADDIUSP
+ 0:
12717 case JRADDIUSP
+ 1:
12719 int imm
= ZIMM(ctx
->opcode
, 0, 5);
12720 gen_compute_branch(ctx
, OPC_JR
, 2, 31, 0, 0, 0);
12721 gen_arith_imm(ctx
, OPC_ADDIU
, 29, 29, imm
<< 2);
12722 /* Let normal delay slot handling in our caller take us
12723 to the branch target. */
12727 generate_exception(ctx
, EXCP_RI
);
12732 static void gen_ldxs (DisasContext
*ctx
, int base
, int index
, int rd
)
12734 TCGv t0
= tcg_temp_new();
12735 TCGv t1
= tcg_temp_new();
12737 gen_load_gpr(t0
, base
);
12740 gen_load_gpr(t1
, index
);
12741 tcg_gen_shli_tl(t1
, t1
, 2);
12742 gen_op_addr_add(ctx
, t0
, t1
, t0
);
12745 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TESL
);
12746 gen_store_gpr(t1
, rd
);
12752 static void gen_ldst_pair (DisasContext
*ctx
, uint32_t opc
, int rd
,
12753 int base
, int16_t offset
)
12755 const char *opn
= "ldst_pair";
12758 if (ctx
->hflags
& MIPS_HFLAG_BMASK
|| rd
== 31) {
12759 generate_exception(ctx
, EXCP_RI
);
12763 t0
= tcg_temp_new();
12764 t1
= tcg_temp_new();
12766 gen_base_offset_addr(ctx
, t0
, base
, offset
);
12771 generate_exception(ctx
, EXCP_RI
);
12774 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TESL
);
12775 gen_store_gpr(t1
, rd
);
12776 tcg_gen_movi_tl(t1
, 4);
12777 gen_op_addr_add(ctx
, t0
, t0
, t1
);
12778 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TESL
);
12779 gen_store_gpr(t1
, rd
+1);
12783 gen_load_gpr(t1
, rd
);
12784 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
12785 tcg_gen_movi_tl(t1
, 4);
12786 gen_op_addr_add(ctx
, t0
, t0
, t1
);
12787 gen_load_gpr(t1
, rd
+1);
12788 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEUL
);
12791 #ifdef TARGET_MIPS64
12794 generate_exception(ctx
, EXCP_RI
);
12797 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
12798 gen_store_gpr(t1
, rd
);
12799 tcg_gen_movi_tl(t1
, 8);
12800 gen_op_addr_add(ctx
, t0
, t0
, t1
);
12801 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
12802 gen_store_gpr(t1
, rd
+1);
12806 gen_load_gpr(t1
, rd
);
12807 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
12808 tcg_gen_movi_tl(t1
, 8);
12809 gen_op_addr_add(ctx
, t0
, t0
, t1
);
12810 gen_load_gpr(t1
, rd
+1);
12811 tcg_gen_qemu_st_tl(t1
, t0
, ctx
->mem_idx
, MO_TEQ
);
12816 (void)opn
; /* avoid a compiler warning */
12817 MIPS_DEBUG("%s, %s, %d(%s)", opn
, regnames
[rd
], offset
, regnames
[base
]);
12822 static void gen_pool32axf (CPUMIPSState
*env
, DisasContext
*ctx
, int rt
, int rs
)
12824 int extension
= (ctx
->opcode
>> 6) & 0x3f;
12825 int minor
= (ctx
->opcode
>> 12) & 0xf;
12826 uint32_t mips32_op
;
12828 switch (extension
) {
12830 mips32_op
= OPC_TEQ
;
12833 mips32_op
= OPC_TGE
;
12836 mips32_op
= OPC_TGEU
;
12839 mips32_op
= OPC_TLT
;
12842 mips32_op
= OPC_TLTU
;
12845 mips32_op
= OPC_TNE
;
12847 gen_trap(ctx
, mips32_op
, rs
, rt
, -1);
12849 #ifndef CONFIG_USER_ONLY
12852 check_cp0_enabled(ctx
);
12854 /* Treat as NOP. */
12857 gen_mfc0(ctx
, cpu_gpr
[rt
], rs
, (ctx
->opcode
>> 11) & 0x7);
12861 check_cp0_enabled(ctx
);
12863 TCGv t0
= tcg_temp_new();
12865 gen_load_gpr(t0
, rt
);
12866 gen_mtc0(ctx
, t0
, rs
, (ctx
->opcode
>> 11) & 0x7);
12872 switch (minor
& 3) {
12874 gen_muldiv(ctx
, OPC_MADD
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
12877 gen_muldiv(ctx
, OPC_MADDU
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
12880 gen_muldiv(ctx
, OPC_MSUB
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
12883 gen_muldiv(ctx
, OPC_MSUBU
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
12886 goto pool32axf_invalid
;
12890 switch (minor
& 3) {
12892 gen_muldiv(ctx
, OPC_MULT
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
12895 gen_muldiv(ctx
, OPC_MULTU
, (ctx
->opcode
>> 14) & 3, rs
, rt
);
12898 goto pool32axf_invalid
;
12904 gen_bshfl(ctx
, OPC_SEB
, rs
, rt
);
12907 gen_bshfl(ctx
, OPC_SEH
, rs
, rt
);
12910 mips32_op
= OPC_CLO
;
12913 mips32_op
= OPC_CLZ
;
12915 check_insn(ctx
, ISA_MIPS32
);
12916 gen_cl(ctx
, mips32_op
, rt
, rs
);
12919 gen_rdhwr(ctx
, rt
, rs
);
12922 gen_bshfl(ctx
, OPC_WSBH
, rs
, rt
);
12925 mips32_op
= OPC_MULT
;
12928 mips32_op
= OPC_MULTU
;
12931 mips32_op
= OPC_DIV
;
12934 mips32_op
= OPC_DIVU
;
12937 check_insn(ctx
, ISA_MIPS32
);
12938 gen_muldiv(ctx
, mips32_op
, 0, rs
, rt
);
12941 mips32_op
= OPC_MADD
;
12944 mips32_op
= OPC_MADDU
;
12947 mips32_op
= OPC_MSUB
;
12950 mips32_op
= OPC_MSUBU
;
12952 check_insn(ctx
, ISA_MIPS32
);
12953 gen_muldiv(ctx
, mips32_op
, 0, rs
, rt
);
12956 goto pool32axf_invalid
;
12967 generate_exception_err(ctx
, EXCP_CpU
, 2);
12970 goto pool32axf_invalid
;
12977 gen_compute_branch(ctx
, OPC_JALR
, 4, rs
, rt
, 0, 4);
12978 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
12982 gen_compute_branch(ctx
, OPC_JALR
, 4, rs
, rt
, 0, 2);
12983 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
12986 goto pool32axf_invalid
;
12992 check_cp0_enabled(ctx
);
12993 check_insn(ctx
, ISA_MIPS32R2
);
12994 gen_load_srsgpr(rt
, rs
);
12997 check_cp0_enabled(ctx
);
12998 check_insn(ctx
, ISA_MIPS32R2
);
12999 gen_store_srsgpr(rt
, rs
);
13002 goto pool32axf_invalid
;
13005 #ifndef CONFIG_USER_ONLY
13009 mips32_op
= OPC_TLBP
;
13012 mips32_op
= OPC_TLBR
;
13015 mips32_op
= OPC_TLBWI
;
13018 mips32_op
= OPC_TLBWR
;
13021 mips32_op
= OPC_WAIT
;
13024 mips32_op
= OPC_DERET
;
13027 mips32_op
= OPC_ERET
;
13029 gen_cp0(env
, ctx
, mips32_op
, rt
, rs
);
13032 goto pool32axf_invalid
;
13038 check_cp0_enabled(ctx
);
13040 TCGv t0
= tcg_temp_new();
13042 save_cpu_state(ctx
, 1);
13043 gen_helper_di(t0
, cpu_env
);
13044 gen_store_gpr(t0
, rs
);
13045 /* Stop translation as we may have switched the execution mode */
13046 ctx
->bstate
= BS_STOP
;
13051 check_cp0_enabled(ctx
);
13053 TCGv t0
= tcg_temp_new();
13055 save_cpu_state(ctx
, 1);
13056 gen_helper_ei(t0
, cpu_env
);
13057 gen_store_gpr(t0
, rs
);
13058 /* Stop translation as we may have switched the execution mode */
13059 ctx
->bstate
= BS_STOP
;
13064 goto pool32axf_invalid
;
13074 generate_exception(ctx
, EXCP_SYSCALL
);
13075 ctx
->bstate
= BS_STOP
;
13078 check_insn(ctx
, ISA_MIPS32
);
13079 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
13080 generate_exception(ctx
, EXCP_DBp
);
13082 generate_exception(ctx
, EXCP_DBp
);
13086 goto pool32axf_invalid
;
13090 switch (minor
& 3) {
13092 gen_HILO(ctx
, OPC_MFHI
, minor
>> 2, rs
);
13095 gen_HILO(ctx
, OPC_MFLO
, minor
>> 2, rs
);
13098 gen_HILO(ctx
, OPC_MTHI
, minor
>> 2, rs
);
13101 gen_HILO(ctx
, OPC_MTLO
, minor
>> 2, rs
);
13104 goto pool32axf_invalid
;
13110 gen_HILO(ctx
, OPC_MFHI
, 0, rs
);
13113 gen_HILO(ctx
, OPC_MFLO
, 0, rs
);
13116 gen_HILO(ctx
, OPC_MTHI
, 0, rs
);
13119 gen_HILO(ctx
, OPC_MTLO
, 0, rs
);
13122 goto pool32axf_invalid
;
13127 MIPS_INVAL("pool32axf");
13128 generate_exception(ctx
, EXCP_RI
);
13133 /* Values for microMIPS fmt field. Variable-width, depending on which
13134 formats the instruction supports. */
13153 static void gen_pool32fxf(DisasContext
*ctx
, int rt
, int rs
)
13155 int extension
= (ctx
->opcode
>> 6) & 0x3ff;
13156 uint32_t mips32_op
;
13158 #define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
13159 #define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
13160 #define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
13162 switch (extension
) {
13163 case FLOAT_1BIT_FMT(CFC1
, 0):
13164 mips32_op
= OPC_CFC1
;
13166 case FLOAT_1BIT_FMT(CTC1
, 0):
13167 mips32_op
= OPC_CTC1
;
13169 case FLOAT_1BIT_FMT(MFC1
, 0):
13170 mips32_op
= OPC_MFC1
;
13172 case FLOAT_1BIT_FMT(MTC1
, 0):
13173 mips32_op
= OPC_MTC1
;
13175 case FLOAT_1BIT_FMT(MFHC1
, 0):
13176 mips32_op
= OPC_MFHC1
;
13178 case FLOAT_1BIT_FMT(MTHC1
, 0):
13179 mips32_op
= OPC_MTHC1
;
13181 gen_cp1(ctx
, mips32_op
, rt
, rs
);
13184 /* Reciprocal square root */
13185 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_S
):
13186 mips32_op
= OPC_RSQRT_S
;
13188 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_D
):
13189 mips32_op
= OPC_RSQRT_D
;
13193 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_S
):
13194 mips32_op
= OPC_SQRT_S
;
13196 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_D
):
13197 mips32_op
= OPC_SQRT_D
;
13201 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_S
):
13202 mips32_op
= OPC_RECIP_S
;
13204 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_D
):
13205 mips32_op
= OPC_RECIP_D
;
13209 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_S
):
13210 mips32_op
= OPC_FLOOR_L_S
;
13212 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_D
):
13213 mips32_op
= OPC_FLOOR_L_D
;
13215 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_S
):
13216 mips32_op
= OPC_FLOOR_W_S
;
13218 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_D
):
13219 mips32_op
= OPC_FLOOR_W_D
;
13223 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_S
):
13224 mips32_op
= OPC_CEIL_L_S
;
13226 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_D
):
13227 mips32_op
= OPC_CEIL_L_D
;
13229 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_S
):
13230 mips32_op
= OPC_CEIL_W_S
;
13232 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_D
):
13233 mips32_op
= OPC_CEIL_W_D
;
13237 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_S
):
13238 mips32_op
= OPC_TRUNC_L_S
;
13240 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_D
):
13241 mips32_op
= OPC_TRUNC_L_D
;
13243 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_S
):
13244 mips32_op
= OPC_TRUNC_W_S
;
13246 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_D
):
13247 mips32_op
= OPC_TRUNC_W_D
;
13251 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_S
):
13252 mips32_op
= OPC_ROUND_L_S
;
13254 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_D
):
13255 mips32_op
= OPC_ROUND_L_D
;
13257 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_S
):
13258 mips32_op
= OPC_ROUND_W_S
;
13260 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_D
):
13261 mips32_op
= OPC_ROUND_W_D
;
13264 /* Integer to floating-point conversion */
13265 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_S
):
13266 mips32_op
= OPC_CVT_L_S
;
13268 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_D
):
13269 mips32_op
= OPC_CVT_L_D
;
13271 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_S
):
13272 mips32_op
= OPC_CVT_W_S
;
13274 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_D
):
13275 mips32_op
= OPC_CVT_W_D
;
13278 /* Paired-foo conversions */
13279 case FLOAT_1BIT_FMT(CVT_S_PL
, 0):
13280 mips32_op
= OPC_CVT_S_PL
;
13282 case FLOAT_1BIT_FMT(CVT_S_PU
, 0):
13283 mips32_op
= OPC_CVT_S_PU
;
13285 case FLOAT_1BIT_FMT(CVT_PW_PS
, 0):
13286 mips32_op
= OPC_CVT_PW_PS
;
13288 case FLOAT_1BIT_FMT(CVT_PS_PW
, 0):
13289 mips32_op
= OPC_CVT_PS_PW
;
13292 /* Floating-point moves */
13293 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_S
):
13294 mips32_op
= OPC_MOV_S
;
13296 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_D
):
13297 mips32_op
= OPC_MOV_D
;
13299 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_PS
):
13300 mips32_op
= OPC_MOV_PS
;
13303 /* Absolute value */
13304 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_S
):
13305 mips32_op
= OPC_ABS_S
;
13307 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_D
):
13308 mips32_op
= OPC_ABS_D
;
13310 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_PS
):
13311 mips32_op
= OPC_ABS_PS
;
13315 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_S
):
13316 mips32_op
= OPC_NEG_S
;
13318 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_D
):
13319 mips32_op
= OPC_NEG_D
;
13321 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_PS
):
13322 mips32_op
= OPC_NEG_PS
;
13325 /* Reciprocal square root step */
13326 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_S
):
13327 mips32_op
= OPC_RSQRT1_S
;
13329 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_D
):
13330 mips32_op
= OPC_RSQRT1_D
;
13332 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_PS
):
13333 mips32_op
= OPC_RSQRT1_PS
;
13336 /* Reciprocal step */
13337 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_S
):
13338 mips32_op
= OPC_RECIP1_S
;
13340 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_D
):
13341 mips32_op
= OPC_RECIP1_S
;
13343 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_PS
):
13344 mips32_op
= OPC_RECIP1_PS
;
13347 /* Conversions from double */
13348 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_S
):
13349 mips32_op
= OPC_CVT_D_S
;
13351 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_W
):
13352 mips32_op
= OPC_CVT_D_W
;
13354 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_L
):
13355 mips32_op
= OPC_CVT_D_L
;
13358 /* Conversions from single */
13359 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_D
):
13360 mips32_op
= OPC_CVT_S_D
;
13362 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_W
):
13363 mips32_op
= OPC_CVT_S_W
;
13365 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_L
):
13366 mips32_op
= OPC_CVT_S_L
;
13368 gen_farith(ctx
, mips32_op
, -1, rs
, rt
, 0);
13371 /* Conditional moves on floating-point codes */
13372 case COND_FLOAT_MOV(MOVT
, 0):
13373 case COND_FLOAT_MOV(MOVT
, 1):
13374 case COND_FLOAT_MOV(MOVT
, 2):
13375 case COND_FLOAT_MOV(MOVT
, 3):
13376 case COND_FLOAT_MOV(MOVT
, 4):
13377 case COND_FLOAT_MOV(MOVT
, 5):
13378 case COND_FLOAT_MOV(MOVT
, 6):
13379 case COND_FLOAT_MOV(MOVT
, 7):
13380 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 1);
13382 case COND_FLOAT_MOV(MOVF
, 0):
13383 case COND_FLOAT_MOV(MOVF
, 1):
13384 case COND_FLOAT_MOV(MOVF
, 2):
13385 case COND_FLOAT_MOV(MOVF
, 3):
13386 case COND_FLOAT_MOV(MOVF
, 4):
13387 case COND_FLOAT_MOV(MOVF
, 5):
13388 case COND_FLOAT_MOV(MOVF
, 6):
13389 case COND_FLOAT_MOV(MOVF
, 7):
13390 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 0);
13393 MIPS_INVAL("pool32fxf");
13394 generate_exception(ctx
, EXCP_RI
);
13399 static void decode_micromips32_opc (CPUMIPSState
*env
, DisasContext
*ctx
,
13404 int rt
, rs
, rd
, rr
;
13406 uint32_t op
, minor
, mips32_op
;
13407 uint32_t cond
, fmt
, cc
;
13409 insn
= cpu_lduw_code(env
, ctx
->pc
+ 2);
13410 ctx
->opcode
= (ctx
->opcode
<< 16) | insn
;
13412 rt
= (ctx
->opcode
>> 21) & 0x1f;
13413 rs
= (ctx
->opcode
>> 16) & 0x1f;
13414 rd
= (ctx
->opcode
>> 11) & 0x1f;
13415 rr
= (ctx
->opcode
>> 6) & 0x1f;
13416 imm
= (int16_t) ctx
->opcode
;
13418 op
= (ctx
->opcode
>> 26) & 0x3f;
13421 minor
= ctx
->opcode
& 0x3f;
13424 minor
= (ctx
->opcode
>> 6) & 0xf;
13427 mips32_op
= OPC_SLL
;
13430 mips32_op
= OPC_SRA
;
13433 mips32_op
= OPC_SRL
;
13436 mips32_op
= OPC_ROTR
;
13438 gen_shift_imm(ctx
, mips32_op
, rt
, rs
, rd
);
13441 goto pool32a_invalid
;
13445 minor
= (ctx
->opcode
>> 6) & 0xf;
13449 mips32_op
= OPC_ADD
;
13452 mips32_op
= OPC_ADDU
;
13455 mips32_op
= OPC_SUB
;
13458 mips32_op
= OPC_SUBU
;
13461 mips32_op
= OPC_MUL
;
13463 gen_arith(ctx
, mips32_op
, rd
, rs
, rt
);
13467 mips32_op
= OPC_SLLV
;
13470 mips32_op
= OPC_SRLV
;
13473 mips32_op
= OPC_SRAV
;
13476 mips32_op
= OPC_ROTRV
;
13478 gen_shift(ctx
, mips32_op
, rd
, rs
, rt
);
13480 /* Logical operations */
13482 mips32_op
= OPC_AND
;
13485 mips32_op
= OPC_OR
;
13488 mips32_op
= OPC_NOR
;
13491 mips32_op
= OPC_XOR
;
13493 gen_logic(ctx
, mips32_op
, rd
, rs
, rt
);
13495 /* Set less than */
13497 mips32_op
= OPC_SLT
;
13500 mips32_op
= OPC_SLTU
;
13502 gen_slt(ctx
, mips32_op
, rd
, rs
, rt
);
13505 goto pool32a_invalid
;
13509 minor
= (ctx
->opcode
>> 6) & 0xf;
13511 /* Conditional moves */
13513 mips32_op
= OPC_MOVN
;
13516 mips32_op
= OPC_MOVZ
;
13518 gen_cond_move(ctx
, mips32_op
, rd
, rs
, rt
);
13521 gen_ldxs(ctx
, rs
, rt
, rd
);
13524 goto pool32a_invalid
;
13528 gen_bitops(ctx
, OPC_INS
, rt
, rs
, rr
, rd
);
13531 gen_bitops(ctx
, OPC_EXT
, rt
, rs
, rr
, rd
);
13534 gen_pool32axf(env
, ctx
, rt
, rs
);
13537 generate_exception(ctx
, EXCP_BREAK
);
13541 MIPS_INVAL("pool32a");
13542 generate_exception(ctx
, EXCP_RI
);
13547 minor
= (ctx
->opcode
>> 12) & 0xf;
13550 check_cp0_enabled(ctx
);
13551 /* Treat as no-op. */
13555 /* COP2: Not implemented. */
13556 generate_exception_err(ctx
, EXCP_CpU
, 2);
13558 #ifdef TARGET_MIPS64
13561 check_insn(ctx
, ISA_MIPS3
);
13562 check_mips_64(ctx
);
13567 gen_ldst_pair(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
13569 #ifdef TARGET_MIPS64
13572 check_insn(ctx
, ISA_MIPS3
);
13573 check_mips_64(ctx
);
13578 gen_ldst_multiple(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
13581 MIPS_INVAL("pool32b");
13582 generate_exception(ctx
, EXCP_RI
);
13587 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
13588 minor
= ctx
->opcode
& 0x3f;
13589 check_cp1_enabled(ctx
);
13592 mips32_op
= OPC_ALNV_PS
;
13595 mips32_op
= OPC_MADD_S
;
13598 mips32_op
= OPC_MADD_D
;
13601 mips32_op
= OPC_MADD_PS
;
13604 mips32_op
= OPC_MSUB_S
;
13607 mips32_op
= OPC_MSUB_D
;
13610 mips32_op
= OPC_MSUB_PS
;
13613 mips32_op
= OPC_NMADD_S
;
13616 mips32_op
= OPC_NMADD_D
;
13619 mips32_op
= OPC_NMADD_PS
;
13622 mips32_op
= OPC_NMSUB_S
;
13625 mips32_op
= OPC_NMSUB_D
;
13628 mips32_op
= OPC_NMSUB_PS
;
13630 gen_flt3_arith(ctx
, mips32_op
, rd
, rr
, rs
, rt
);
13632 case CABS_COND_FMT
:
13633 cond
= (ctx
->opcode
>> 6) & 0xf;
13634 cc
= (ctx
->opcode
>> 13) & 0x7;
13635 fmt
= (ctx
->opcode
>> 10) & 0x3;
13638 gen_cmpabs_s(ctx
, cond
, rt
, rs
, cc
);
13641 gen_cmpabs_d(ctx
, cond
, rt
, rs
, cc
);
13644 gen_cmpabs_ps(ctx
, cond
, rt
, rs
, cc
);
13647 goto pool32f_invalid
;
13651 cond
= (ctx
->opcode
>> 6) & 0xf;
13652 cc
= (ctx
->opcode
>> 13) & 0x7;
13653 fmt
= (ctx
->opcode
>> 10) & 0x3;
13656 gen_cmp_s(ctx
, cond
, rt
, rs
, cc
);
13659 gen_cmp_d(ctx
, cond
, rt
, rs
, cc
);
13662 gen_cmp_ps(ctx
, cond
, rt
, rs
, cc
);
13665 goto pool32f_invalid
;
13669 gen_pool32fxf(ctx
, rt
, rs
);
13673 switch ((ctx
->opcode
>> 6) & 0x7) {
13675 mips32_op
= OPC_PLL_PS
;
13678 mips32_op
= OPC_PLU_PS
;
13681 mips32_op
= OPC_PUL_PS
;
13684 mips32_op
= OPC_PUU_PS
;
13687 mips32_op
= OPC_CVT_PS_S
;
13689 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
13692 goto pool32f_invalid
;
13697 switch ((ctx
->opcode
>> 6) & 0x7) {
13699 mips32_op
= OPC_LWXC1
;
13702 mips32_op
= OPC_SWXC1
;
13705 mips32_op
= OPC_LDXC1
;
13708 mips32_op
= OPC_SDXC1
;
13711 mips32_op
= OPC_LUXC1
;
13714 mips32_op
= OPC_SUXC1
;
13716 gen_flt3_ldst(ctx
, mips32_op
, rd
, rd
, rt
, rs
);
13719 goto pool32f_invalid
;
13724 fmt
= (ctx
->opcode
>> 9) & 0x3;
13725 switch ((ctx
->opcode
>> 6) & 0x7) {
13729 mips32_op
= OPC_RSQRT2_S
;
13732 mips32_op
= OPC_RSQRT2_D
;
13735 mips32_op
= OPC_RSQRT2_PS
;
13738 goto pool32f_invalid
;
13744 mips32_op
= OPC_RECIP2_S
;
13747 mips32_op
= OPC_RECIP2_D
;
13750 mips32_op
= OPC_RECIP2_PS
;
13753 goto pool32f_invalid
;
13757 mips32_op
= OPC_ADDR_PS
;
13760 mips32_op
= OPC_MULR_PS
;
13762 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
13765 goto pool32f_invalid
;
13769 /* MOV[FT].fmt and PREFX */
13770 cc
= (ctx
->opcode
>> 13) & 0x7;
13771 fmt
= (ctx
->opcode
>> 9) & 0x3;
13772 switch ((ctx
->opcode
>> 6) & 0x7) {
13776 gen_movcf_s(ctx
, rs
, rt
, cc
, 0);
13779 gen_movcf_d(ctx
, rs
, rt
, cc
, 0);
13782 gen_movcf_ps(ctx
, rs
, rt
, cc
, 0);
13785 goto pool32f_invalid
;
13791 gen_movcf_s(ctx
, rs
, rt
, cc
, 1);
13794 gen_movcf_d(ctx
, rs
, rt
, cc
, 1);
13797 gen_movcf_ps(ctx
, rs
, rt
, cc
, 1);
13800 goto pool32f_invalid
;
13806 goto pool32f_invalid
;
13809 #define FINSN_3ARG_SDPS(prfx) \
13810 switch ((ctx->opcode >> 8) & 0x3) { \
13812 mips32_op = OPC_##prfx##_S; \
13815 mips32_op = OPC_##prfx##_D; \
13817 case FMT_SDPS_PS: \
13818 mips32_op = OPC_##prfx##_PS; \
13821 goto pool32f_invalid; \
13824 /* regular FP ops */
13825 switch ((ctx
->opcode
>> 6) & 0x3) {
13827 FINSN_3ARG_SDPS(ADD
);
13830 FINSN_3ARG_SDPS(SUB
);
13833 FINSN_3ARG_SDPS(MUL
);
13836 fmt
= (ctx
->opcode
>> 8) & 0x3;
13838 mips32_op
= OPC_DIV_D
;
13839 } else if (fmt
== 0) {
13840 mips32_op
= OPC_DIV_S
;
13842 goto pool32f_invalid
;
13846 goto pool32f_invalid
;
13851 switch ((ctx
->opcode
>> 6) & 0x3) {
13853 FINSN_3ARG_SDPS(MOVN
);
13856 FINSN_3ARG_SDPS(MOVZ
);
13859 goto pool32f_invalid
;
13863 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
13867 MIPS_INVAL("pool32f");
13868 generate_exception(ctx
, EXCP_RI
);
13872 generate_exception_err(ctx
, EXCP_CpU
, 1);
13876 minor
= (ctx
->opcode
>> 21) & 0x1f;
13879 gen_compute_branch(ctx
, OPC_BLTZ
, 4, rs
, -1, imm
<< 1, 4);
13882 gen_compute_branch(ctx
, OPC_BLTZAL
, 4, rs
, -1, imm
<< 1, 4);
13883 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
13886 gen_compute_branch(ctx
, OPC_BLTZAL
, 4, rs
, -1, imm
<< 1, 2);
13887 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
13890 gen_compute_branch(ctx
, OPC_BGEZ
, 4, rs
, -1, imm
<< 1, 4);
13893 gen_compute_branch(ctx
, OPC_BGEZAL
, 4, rs
, -1, imm
<< 1, 4);
13894 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
13897 gen_compute_branch(ctx
, OPC_BGEZAL
, 4, rs
, -1, imm
<< 1, 2);
13898 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
13901 gen_compute_branch(ctx
, OPC_BLEZ
, 4, rs
, -1, imm
<< 1, 4);
13904 gen_compute_branch(ctx
, OPC_BGTZ
, 4, rs
, -1, imm
<< 1, 4);
13909 mips32_op
= OPC_TLTI
;
13912 mips32_op
= OPC_TGEI
;
13915 mips32_op
= OPC_TLTIU
;
13918 mips32_op
= OPC_TGEIU
;
13921 mips32_op
= OPC_TNEI
;
13924 mips32_op
= OPC_TEQI
;
13926 gen_trap(ctx
, mips32_op
, rs
, -1, imm
);
13931 gen_compute_branch(ctx
, minor
== BNEZC
? OPC_BNE
: OPC_BEQ
,
13932 4, rs
, 0, imm
<< 1, 0);
13933 /* Compact branches don't have a delay slot, so just let
13934 the normal delay slot handling take us to the branch
13938 gen_logic_imm(ctx
, OPC_LUI
, rs
, 0, imm
);
13941 /* Break the TB to be able to sync copied instructions
13943 ctx
->bstate
= BS_STOP
;
13947 /* COP2: Not implemented. */
13948 generate_exception_err(ctx
, EXCP_CpU
, 2);
13951 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1FANY2
: OPC_BC1F
;
13954 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1TANY2
: OPC_BC1T
;
13957 mips32_op
= OPC_BC1FANY4
;
13960 mips32_op
= OPC_BC1TANY4
;
13963 check_insn(ctx
, ASE_MIPS3D
);
13966 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
13967 check_cp1_enabled(ctx
);
13968 gen_compute_branch1(ctx
, mips32_op
,
13969 (ctx
->opcode
>> 18) & 0x7, imm
<< 1);
13971 generate_exception_err(ctx
, EXCP_CpU
, 1);
13976 /* MIPS DSP: not implemented */
13979 MIPS_INVAL("pool32i");
13980 generate_exception(ctx
, EXCP_RI
);
13985 minor
= (ctx
->opcode
>> 12) & 0xf;
13988 mips32_op
= OPC_LWL
;
13991 mips32_op
= OPC_SWL
;
13994 mips32_op
= OPC_LWR
;
13997 mips32_op
= OPC_SWR
;
13999 #if defined(TARGET_MIPS64)
14001 check_insn(ctx
, ISA_MIPS3
);
14002 check_mips_64(ctx
);
14003 mips32_op
= OPC_LDL
;
14006 check_insn(ctx
, ISA_MIPS3
);
14007 check_mips_64(ctx
);
14008 mips32_op
= OPC_SDL
;
14011 check_insn(ctx
, ISA_MIPS3
);
14012 check_mips_64(ctx
);
14013 mips32_op
= OPC_LDR
;
14016 check_insn(ctx
, ISA_MIPS3
);
14017 check_mips_64(ctx
);
14018 mips32_op
= OPC_SDR
;
14021 check_insn(ctx
, ISA_MIPS3
);
14022 check_mips_64(ctx
);
14023 mips32_op
= OPC_LWU
;
14026 check_insn(ctx
, ISA_MIPS3
);
14027 check_mips_64(ctx
);
14028 mips32_op
= OPC_LLD
;
14032 mips32_op
= OPC_LL
;
14035 gen_ld(ctx
, mips32_op
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
14038 gen_st(ctx
, mips32_op
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
14041 gen_st_cond(ctx
, OPC_SC
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
14043 #if defined(TARGET_MIPS64)
14045 check_insn(ctx
, ISA_MIPS3
);
14046 check_mips_64(ctx
);
14047 gen_st_cond(ctx
, OPC_SCD
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
14051 /* Treat as no-op */
14054 MIPS_INVAL("pool32c");
14055 generate_exception(ctx
, EXCP_RI
);
14060 mips32_op
= OPC_ADDI
;
14063 mips32_op
= OPC_ADDIU
;
14065 gen_arith_imm(ctx
, mips32_op
, rt
, rs
, imm
);
14068 /* Logical operations */
14070 mips32_op
= OPC_ORI
;
14073 mips32_op
= OPC_XORI
;
14076 mips32_op
= OPC_ANDI
;
14078 gen_logic_imm(ctx
, mips32_op
, rt
, rs
, imm
);
14081 /* Set less than immediate */
14083 mips32_op
= OPC_SLTI
;
14086 mips32_op
= OPC_SLTIU
;
14088 gen_slt_imm(ctx
, mips32_op
, rt
, rs
, imm
);
14091 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
14092 gen_compute_branch(ctx
, OPC_JALX
, 4, rt
, rs
, offset
, 4);
14093 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
14096 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1;
14097 gen_compute_branch(ctx
, OPC_JAL
, 4, rt
, rs
, offset
, 2);
14098 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
14101 gen_compute_branch(ctx
, OPC_BEQ
, 4, rt
, rs
, imm
<< 1, 4);
14104 gen_compute_branch(ctx
, OPC_BNE
, 4, rt
, rs
, imm
<< 1, 4);
14107 gen_compute_branch(ctx
, OPC_J
, 4, rt
, rs
,
14108 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1, 4);
14111 gen_compute_branch(ctx
, OPC_JAL
, 4, rt
, rs
,
14112 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1, 4);
14113 ctx
->hflags
|= MIPS_HFLAG_BDS_STRICT
;
14115 /* Floating point (COP1) */
14117 mips32_op
= OPC_LWC1
;
14120 mips32_op
= OPC_LDC1
;
14123 mips32_op
= OPC_SWC1
;
14126 mips32_op
= OPC_SDC1
;
14128 gen_cop1_ldst(ctx
, mips32_op
, rt
, rs
, imm
);
14132 int reg
= mmreg(ZIMM(ctx
->opcode
, 23, 3));
14133 int offset
= SIMM(ctx
->opcode
, 0, 23) << 2;
14135 gen_addiupc(ctx
, reg
, offset
, 0, 0);
14138 /* Loads and stores */
14140 mips32_op
= OPC_LB
;
14143 mips32_op
= OPC_LBU
;
14146 mips32_op
= OPC_LH
;
14149 mips32_op
= OPC_LHU
;
14152 mips32_op
= OPC_LW
;
14154 #ifdef TARGET_MIPS64
14156 check_insn(ctx
, ISA_MIPS3
);
14157 check_mips_64(ctx
);
14158 mips32_op
= OPC_LD
;
14161 check_insn(ctx
, ISA_MIPS3
);
14162 check_mips_64(ctx
);
14163 mips32_op
= OPC_SD
;
14167 mips32_op
= OPC_SB
;
14170 mips32_op
= OPC_SH
;
14173 mips32_op
= OPC_SW
;
14176 gen_ld(ctx
, mips32_op
, rt
, rs
, imm
);
14179 gen_st(ctx
, mips32_op
, rt
, rs
, imm
);
14182 generate_exception(ctx
, EXCP_RI
);
14187 static int decode_micromips_opc (CPUMIPSState
*env
, DisasContext
*ctx
)
14191 /* make sure instructions are on a halfword boundary */
14192 if (ctx
->pc
& 0x1) {
14193 env
->CP0_BadVAddr
= ctx
->pc
;
14194 generate_exception(ctx
, EXCP_AdEL
);
14195 ctx
->bstate
= BS_STOP
;
14199 op
= (ctx
->opcode
>> 10) & 0x3f;
14200 /* Enforce properly-sized instructions in a delay slot */
14201 if (ctx
->hflags
& MIPS_HFLAG_BDS_STRICT
) {
14202 switch (op
& 0x7) { /* MSB-3..MSB-5 */
14204 /* POOL32A, POOL32B, POOL32I, POOL32C */
14206 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */
14208 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */
14210 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */
14212 /* LB32, LH32, LWC132, LDC132, LW32 */
14213 if (ctx
->hflags
& MIPS_HFLAG_BDS16
) {
14214 generate_exception(ctx
, EXCP_RI
);
14215 /* Just stop translation; the user is confused. */
14216 ctx
->bstate
= BS_STOP
;
14221 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */
14223 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */
14225 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
14226 if (ctx
->hflags
& MIPS_HFLAG_BDS32
) {
14227 generate_exception(ctx
, EXCP_RI
);
14228 /* Just stop translation; the user is confused. */
14229 ctx
->bstate
= BS_STOP
;
14239 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
14240 int rs1
= mmreg(uMIPS_RS1(ctx
->opcode
));
14241 int rs2
= mmreg(uMIPS_RS2(ctx
->opcode
));
14244 switch (ctx
->opcode
& 0x1) {
14253 gen_arith(ctx
, opc
, rd
, rs1
, rs2
);
14258 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
14259 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
14260 int amount
= (ctx
->opcode
>> 1) & 0x7;
14262 amount
= amount
== 0 ? 8 : amount
;
14264 switch (ctx
->opcode
& 0x1) {
14273 gen_shift_imm(ctx
, opc
, rd
, rs
, amount
);
14277 gen_pool16c_insn(ctx
);
14281 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
14282 int rb
= 28; /* GP */
14283 int16_t offset
= SIMM(ctx
->opcode
, 0, 7) << 2;
14285 gen_ld(ctx
, OPC_LW
, rd
, rb
, offset
);
14289 if (ctx
->opcode
& 1) {
14290 generate_exception(ctx
, EXCP_RI
);
14293 int enc_dest
= uMIPS_RD(ctx
->opcode
);
14294 int enc_rt
= uMIPS_RS2(ctx
->opcode
);
14295 int enc_rs
= uMIPS_RS1(ctx
->opcode
);
14296 int rd
, rs
, re
, rt
;
14297 static const int rd_enc
[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
14298 static const int re_enc
[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
14299 static const int rs_rt_enc
[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
14301 rd
= rd_enc
[enc_dest
];
14302 re
= re_enc
[enc_dest
];
14303 rs
= rs_rt_enc
[enc_rs
];
14304 rt
= rs_rt_enc
[enc_rt
];
14306 gen_arith(ctx
, OPC_ADDU
, rd
, rs
, 0);
14307 gen_arith(ctx
, OPC_ADDU
, re
, rt
, 0);
14312 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
14313 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
14314 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
14315 offset
= (offset
== 0xf ? -1 : offset
);
14317 gen_ld(ctx
, OPC_LBU
, rd
, rb
, offset
);
14322 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
14323 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
14324 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
14326 gen_ld(ctx
, OPC_LHU
, rd
, rb
, offset
);
14331 int rd
= (ctx
->opcode
>> 5) & 0x1f;
14332 int rb
= 29; /* SP */
14333 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
14335 gen_ld(ctx
, OPC_LW
, rd
, rb
, offset
);
14340 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
14341 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
14342 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
14344 gen_ld(ctx
, OPC_LW
, rd
, rb
, offset
);
14349 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
14350 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
14351 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
14353 gen_st(ctx
, OPC_SB
, rd
, rb
, offset
);
14358 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
14359 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
14360 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
14362 gen_st(ctx
, OPC_SH
, rd
, rb
, offset
);
14367 int rd
= (ctx
->opcode
>> 5) & 0x1f;
14368 int rb
= 29; /* SP */
14369 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
14371 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
14376 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
14377 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
14378 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
14380 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
14385 int rd
= uMIPS_RD5(ctx
->opcode
);
14386 int rs
= uMIPS_RS5(ctx
->opcode
);
14388 gen_arith(ctx
, OPC_ADDU
, rd
, rs
, 0);
14395 switch (ctx
->opcode
& 0x1) {
14405 switch (ctx
->opcode
& 0x1) {
14410 gen_addiur1sp(ctx
);
14415 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0,
14416 SIMM(ctx
->opcode
, 0, 10) << 1, 4);
14420 gen_compute_branch(ctx
, op
== BNEZ16
? OPC_BNE
: OPC_BEQ
, 2,
14421 mmreg(uMIPS_RD(ctx
->opcode
)),
14422 0, SIMM(ctx
->opcode
, 0, 7) << 1, 4);
14426 int reg
= mmreg(uMIPS_RD(ctx
->opcode
));
14427 int imm
= ZIMM(ctx
->opcode
, 0, 7);
14429 imm
= (imm
== 0x7f ? -1 : imm
);
14430 tcg_gen_movi_tl(cpu_gpr
[reg
], imm
);
14440 generate_exception(ctx
, EXCP_RI
);
14443 decode_micromips32_opc (env
, ctx
, op
);
14450 /* SmartMIPS extension to MIPS32 */
14452 #if defined(TARGET_MIPS64)
14454 /* MDMX extension to MIPS64 */
14458 /* MIPSDSP functions. */
14459 static void gen_mipsdsp_ld(DisasContext
*ctx
, uint32_t opc
,
14460 int rd
, int base
, int offset
)
14462 const char *opn
= "ldx";
14466 t0
= tcg_temp_new();
14469 gen_load_gpr(t0
, offset
);
14470 } else if (offset
== 0) {
14471 gen_load_gpr(t0
, base
);
14473 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], cpu_gpr
[offset
]);
14478 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_UB
);
14479 gen_store_gpr(t0
, rd
);
14483 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESW
);
14484 gen_store_gpr(t0
, rd
);
14488 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TESL
);
14489 gen_store_gpr(t0
, rd
);
14492 #if defined(TARGET_MIPS64)
14494 tcg_gen_qemu_ld_tl(t0
, t0
, ctx
->mem_idx
, MO_TEQ
);
14495 gen_store_gpr(t0
, rd
);
14500 (void)opn
; /* avoid a compiler warning */
14501 MIPS_DEBUG("%s %s, %s(%s)", opn
,
14502 regnames
[rd
], regnames
[offset
], regnames
[base
]);
14506 static void gen_mipsdsp_arith(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
14507 int ret
, int v1
, int v2
)
14509 const char *opn
= "mipsdsp arith";
14514 /* Treat as NOP. */
14519 v1_t
= tcg_temp_new();
14520 v2_t
= tcg_temp_new();
14522 gen_load_gpr(v1_t
, v1
);
14523 gen_load_gpr(v2_t
, v2
);
14526 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
14527 case OPC_MULT_G_2E
:
14531 gen_helper_adduh_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
14533 case OPC_ADDUH_R_QB
:
14534 gen_helper_adduh_r_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
14537 gen_helper_addqh_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
14539 case OPC_ADDQH_R_PH
:
14540 gen_helper_addqh_r_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
14543 gen_helper_addqh_w(cpu_gpr
[ret
], v1_t
, v2_t
);
14545 case OPC_ADDQH_R_W
:
14546 gen_helper_addqh_r_w(cpu_gpr
[ret
], v1_t
, v2_t
);
14549 gen_helper_subuh_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
14551 case OPC_SUBUH_R_QB
:
14552 gen_helper_subuh_r_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
14555 gen_helper_subqh_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
14557 case OPC_SUBQH_R_PH
:
14558 gen_helper_subqh_r_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
14561 gen_helper_subqh_w(cpu_gpr
[ret
], v1_t
, v2_t
);
14563 case OPC_SUBQH_R_W
:
14564 gen_helper_subqh_r_w(cpu_gpr
[ret
], v1_t
, v2_t
);
14568 case OPC_ABSQ_S_PH_DSP
:
14570 case OPC_ABSQ_S_QB
:
14572 gen_helper_absq_s_qb(cpu_gpr
[ret
], v2_t
, cpu_env
);
14574 case OPC_ABSQ_S_PH
:
14576 gen_helper_absq_s_ph(cpu_gpr
[ret
], v2_t
, cpu_env
);
14580 gen_helper_absq_s_w(cpu_gpr
[ret
], v2_t
, cpu_env
);
14582 case OPC_PRECEQ_W_PHL
:
14584 tcg_gen_andi_tl(cpu_gpr
[ret
], v2_t
, 0xFFFF0000);
14585 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
14587 case OPC_PRECEQ_W_PHR
:
14589 tcg_gen_andi_tl(cpu_gpr
[ret
], v2_t
, 0x0000FFFF);
14590 tcg_gen_shli_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], 16);
14591 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
14593 case OPC_PRECEQU_PH_QBL
:
14595 gen_helper_precequ_ph_qbl(cpu_gpr
[ret
], v2_t
);
14597 case OPC_PRECEQU_PH_QBR
:
14599 gen_helper_precequ_ph_qbr(cpu_gpr
[ret
], v2_t
);
14601 case OPC_PRECEQU_PH_QBLA
:
14603 gen_helper_precequ_ph_qbla(cpu_gpr
[ret
], v2_t
);
14605 case OPC_PRECEQU_PH_QBRA
:
14607 gen_helper_precequ_ph_qbra(cpu_gpr
[ret
], v2_t
);
14609 case OPC_PRECEU_PH_QBL
:
14611 gen_helper_preceu_ph_qbl(cpu_gpr
[ret
], v2_t
);
14613 case OPC_PRECEU_PH_QBR
:
14615 gen_helper_preceu_ph_qbr(cpu_gpr
[ret
], v2_t
);
14617 case OPC_PRECEU_PH_QBLA
:
14619 gen_helper_preceu_ph_qbla(cpu_gpr
[ret
], v2_t
);
14621 case OPC_PRECEU_PH_QBRA
:
14623 gen_helper_preceu_ph_qbra(cpu_gpr
[ret
], v2_t
);
14627 case OPC_ADDU_QB_DSP
:
14631 gen_helper_addq_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14633 case OPC_ADDQ_S_PH
:
14635 gen_helper_addq_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14639 gen_helper_addq_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14643 gen_helper_addu_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14645 case OPC_ADDU_S_QB
:
14647 gen_helper_addu_s_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14651 gen_helper_addu_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14653 case OPC_ADDU_S_PH
:
14655 gen_helper_addu_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14659 gen_helper_subq_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14661 case OPC_SUBQ_S_PH
:
14663 gen_helper_subq_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14667 gen_helper_subq_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14671 gen_helper_subu_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14673 case OPC_SUBU_S_QB
:
14675 gen_helper_subu_s_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14679 gen_helper_subu_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14681 case OPC_SUBU_S_PH
:
14683 gen_helper_subu_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14687 gen_helper_addsc(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14691 gen_helper_addwc(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14695 gen_helper_modsub(cpu_gpr
[ret
], v1_t
, v2_t
);
14697 case OPC_RADDU_W_QB
:
14699 gen_helper_raddu_w_qb(cpu_gpr
[ret
], v1_t
);
14703 case OPC_CMPU_EQ_QB_DSP
:
14705 case OPC_PRECR_QB_PH
:
14707 gen_helper_precr_qb_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
14709 case OPC_PRECRQ_QB_PH
:
14711 gen_helper_precrq_qb_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
14713 case OPC_PRECR_SRA_PH_W
:
14716 TCGv_i32 sa_t
= tcg_const_i32(v2
);
14717 gen_helper_precr_sra_ph_w(cpu_gpr
[ret
], sa_t
, v1_t
,
14719 tcg_temp_free_i32(sa_t
);
14722 case OPC_PRECR_SRA_R_PH_W
:
14725 TCGv_i32 sa_t
= tcg_const_i32(v2
);
14726 gen_helper_precr_sra_r_ph_w(cpu_gpr
[ret
], sa_t
, v1_t
,
14728 tcg_temp_free_i32(sa_t
);
14731 case OPC_PRECRQ_PH_W
:
14733 gen_helper_precrq_ph_w(cpu_gpr
[ret
], v1_t
, v2_t
);
14735 case OPC_PRECRQ_RS_PH_W
:
14737 gen_helper_precrq_rs_ph_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14739 case OPC_PRECRQU_S_QB_PH
:
14741 gen_helper_precrqu_s_qb_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14745 #ifdef TARGET_MIPS64
14746 case OPC_ABSQ_S_QH_DSP
:
14748 case OPC_PRECEQ_L_PWL
:
14750 tcg_gen_andi_tl(cpu_gpr
[ret
], v2_t
, 0xFFFFFFFF00000000ull
);
14752 case OPC_PRECEQ_L_PWR
:
14754 tcg_gen_shli_tl(cpu_gpr
[ret
], v2_t
, 32);
14756 case OPC_PRECEQ_PW_QHL
:
14758 gen_helper_preceq_pw_qhl(cpu_gpr
[ret
], v2_t
);
14760 case OPC_PRECEQ_PW_QHR
:
14762 gen_helper_preceq_pw_qhr(cpu_gpr
[ret
], v2_t
);
14764 case OPC_PRECEQ_PW_QHLA
:
14766 gen_helper_preceq_pw_qhla(cpu_gpr
[ret
], v2_t
);
14768 case OPC_PRECEQ_PW_QHRA
:
14770 gen_helper_preceq_pw_qhra(cpu_gpr
[ret
], v2_t
);
14772 case OPC_PRECEQU_QH_OBL
:
14774 gen_helper_precequ_qh_obl(cpu_gpr
[ret
], v2_t
);
14776 case OPC_PRECEQU_QH_OBR
:
14778 gen_helper_precequ_qh_obr(cpu_gpr
[ret
], v2_t
);
14780 case OPC_PRECEQU_QH_OBLA
:
14782 gen_helper_precequ_qh_obla(cpu_gpr
[ret
], v2_t
);
14784 case OPC_PRECEQU_QH_OBRA
:
14786 gen_helper_precequ_qh_obra(cpu_gpr
[ret
], v2_t
);
14788 case OPC_PRECEU_QH_OBL
:
14790 gen_helper_preceu_qh_obl(cpu_gpr
[ret
], v2_t
);
14792 case OPC_PRECEU_QH_OBR
:
14794 gen_helper_preceu_qh_obr(cpu_gpr
[ret
], v2_t
);
14796 case OPC_PRECEU_QH_OBLA
:
14798 gen_helper_preceu_qh_obla(cpu_gpr
[ret
], v2_t
);
14800 case OPC_PRECEU_QH_OBRA
:
14802 gen_helper_preceu_qh_obra(cpu_gpr
[ret
], v2_t
);
14804 case OPC_ABSQ_S_OB
:
14806 gen_helper_absq_s_ob(cpu_gpr
[ret
], v2_t
, cpu_env
);
14808 case OPC_ABSQ_S_PW
:
14810 gen_helper_absq_s_pw(cpu_gpr
[ret
], v2_t
, cpu_env
);
14812 case OPC_ABSQ_S_QH
:
14814 gen_helper_absq_s_qh(cpu_gpr
[ret
], v2_t
, cpu_env
);
14818 case OPC_ADDU_OB_DSP
:
14820 case OPC_RADDU_L_OB
:
14822 gen_helper_raddu_l_ob(cpu_gpr
[ret
], v1_t
);
14826 gen_helper_subq_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14828 case OPC_SUBQ_S_PW
:
14830 gen_helper_subq_s_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14834 gen_helper_subq_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14836 case OPC_SUBQ_S_QH
:
14838 gen_helper_subq_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14842 gen_helper_subu_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14844 case OPC_SUBU_S_OB
:
14846 gen_helper_subu_s_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14850 gen_helper_subu_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14852 case OPC_SUBU_S_QH
:
14854 gen_helper_subu_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14858 gen_helper_subuh_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
14860 case OPC_SUBUH_R_OB
:
14862 gen_helper_subuh_r_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
14866 gen_helper_addq_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14868 case OPC_ADDQ_S_PW
:
14870 gen_helper_addq_s_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14874 gen_helper_addq_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14876 case OPC_ADDQ_S_QH
:
14878 gen_helper_addq_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14882 gen_helper_addu_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14884 case OPC_ADDU_S_OB
:
14886 gen_helper_addu_s_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14890 gen_helper_addu_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14892 case OPC_ADDU_S_QH
:
14894 gen_helper_addu_s_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14898 gen_helper_adduh_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
14900 case OPC_ADDUH_R_OB
:
14902 gen_helper_adduh_r_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
14906 case OPC_CMPU_EQ_OB_DSP
:
14908 case OPC_PRECR_OB_QH
:
14910 gen_helper_precr_ob_qh(cpu_gpr
[ret
], v1_t
, v2_t
);
14912 case OPC_PRECR_SRA_QH_PW
:
14915 TCGv_i32 ret_t
= tcg_const_i32(ret
);
14916 gen_helper_precr_sra_qh_pw(v2_t
, v1_t
, v2_t
, ret_t
);
14917 tcg_temp_free_i32(ret_t
);
14920 case OPC_PRECR_SRA_R_QH_PW
:
14923 TCGv_i32 sa_v
= tcg_const_i32(ret
);
14924 gen_helper_precr_sra_r_qh_pw(v2_t
, v1_t
, v2_t
, sa_v
);
14925 tcg_temp_free_i32(sa_v
);
14928 case OPC_PRECRQ_OB_QH
:
14930 gen_helper_precrq_ob_qh(cpu_gpr
[ret
], v1_t
, v2_t
);
14932 case OPC_PRECRQ_PW_L
:
14934 gen_helper_precrq_pw_l(cpu_gpr
[ret
], v1_t
, v2_t
);
14936 case OPC_PRECRQ_QH_PW
:
14938 gen_helper_precrq_qh_pw(cpu_gpr
[ret
], v1_t
, v2_t
);
14940 case OPC_PRECRQ_RS_QH_PW
:
14942 gen_helper_precrq_rs_qh_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14944 case OPC_PRECRQU_S_OB_QH
:
14946 gen_helper_precrqu_s_ob_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14953 tcg_temp_free(v1_t
);
14954 tcg_temp_free(v2_t
);
14956 (void)opn
; /* avoid a compiler warning */
14957 MIPS_DEBUG("%s", opn
);
14960 static void gen_mipsdsp_shift(DisasContext
*ctx
, uint32_t opc
,
14961 int ret
, int v1
, int v2
)
14964 const char *opn
= "mipsdsp shift";
14970 /* Treat as NOP. */
14975 t0
= tcg_temp_new();
14976 v1_t
= tcg_temp_new();
14977 v2_t
= tcg_temp_new();
14979 tcg_gen_movi_tl(t0
, v1
);
14980 gen_load_gpr(v1_t
, v1
);
14981 gen_load_gpr(v2_t
, v2
);
14984 case OPC_SHLL_QB_DSP
:
14986 op2
= MASK_SHLL_QB(ctx
->opcode
);
14990 gen_helper_shll_qb(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
14994 gen_helper_shll_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
14998 gen_helper_shll_ph(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
15002 gen_helper_shll_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15004 case OPC_SHLL_S_PH
:
15006 gen_helper_shll_s_ph(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
15008 case OPC_SHLLV_S_PH
:
15010 gen_helper_shll_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15014 gen_helper_shll_s_w(cpu_gpr
[ret
], t0
, v2_t
, cpu_env
);
15016 case OPC_SHLLV_S_W
:
15018 gen_helper_shll_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15022 gen_helper_shrl_qb(cpu_gpr
[ret
], t0
, v2_t
);
15026 gen_helper_shrl_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
15030 gen_helper_shrl_ph(cpu_gpr
[ret
], t0
, v2_t
);
15034 gen_helper_shrl_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
15038 gen_helper_shra_qb(cpu_gpr
[ret
], t0
, v2_t
);
15040 case OPC_SHRA_R_QB
:
15042 gen_helper_shra_r_qb(cpu_gpr
[ret
], t0
, v2_t
);
15046 gen_helper_shra_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
15048 case OPC_SHRAV_R_QB
:
15050 gen_helper_shra_r_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
15054 gen_helper_shra_ph(cpu_gpr
[ret
], t0
, v2_t
);
15056 case OPC_SHRA_R_PH
:
15058 gen_helper_shra_r_ph(cpu_gpr
[ret
], t0
, v2_t
);
15062 gen_helper_shra_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
15064 case OPC_SHRAV_R_PH
:
15066 gen_helper_shra_r_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
15070 gen_helper_shra_r_w(cpu_gpr
[ret
], t0
, v2_t
);
15072 case OPC_SHRAV_R_W
:
15074 gen_helper_shra_r_w(cpu_gpr
[ret
], v1_t
, v2_t
);
15076 default: /* Invalid */
15077 MIPS_INVAL("MASK SHLL.QB");
15078 generate_exception(ctx
, EXCP_RI
);
15083 #ifdef TARGET_MIPS64
15084 case OPC_SHLL_OB_DSP
:
15085 op2
= MASK_SHLL_OB(ctx
->opcode
);
15089 gen_helper_shll_pw(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
15093 gen_helper_shll_pw(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
15095 case OPC_SHLL_S_PW
:
15097 gen_helper_shll_s_pw(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
15099 case OPC_SHLLV_S_PW
:
15101 gen_helper_shll_s_pw(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
15105 gen_helper_shll_ob(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
15109 gen_helper_shll_ob(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
15113 gen_helper_shll_qh(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
15117 gen_helper_shll_qh(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
15119 case OPC_SHLL_S_QH
:
15121 gen_helper_shll_s_qh(cpu_gpr
[ret
], v2_t
, t0
, cpu_env
);
15123 case OPC_SHLLV_S_QH
:
15125 gen_helper_shll_s_qh(cpu_gpr
[ret
], v2_t
, v1_t
, cpu_env
);
15129 gen_helper_shra_ob(cpu_gpr
[ret
], v2_t
, t0
);
15133 gen_helper_shra_ob(cpu_gpr
[ret
], v2_t
, v1_t
);
15135 case OPC_SHRA_R_OB
:
15137 gen_helper_shra_r_ob(cpu_gpr
[ret
], v2_t
, t0
);
15139 case OPC_SHRAV_R_OB
:
15141 gen_helper_shra_r_ob(cpu_gpr
[ret
], v2_t
, v1_t
);
15145 gen_helper_shra_pw(cpu_gpr
[ret
], v2_t
, t0
);
15149 gen_helper_shra_pw(cpu_gpr
[ret
], v2_t
, v1_t
);
15151 case OPC_SHRA_R_PW
:
15153 gen_helper_shra_r_pw(cpu_gpr
[ret
], v2_t
, t0
);
15155 case OPC_SHRAV_R_PW
:
15157 gen_helper_shra_r_pw(cpu_gpr
[ret
], v2_t
, v1_t
);
15161 gen_helper_shra_qh(cpu_gpr
[ret
], v2_t
, t0
);
15165 gen_helper_shra_qh(cpu_gpr
[ret
], v2_t
, v1_t
);
15167 case OPC_SHRA_R_QH
:
15169 gen_helper_shra_r_qh(cpu_gpr
[ret
], v2_t
, t0
);
15171 case OPC_SHRAV_R_QH
:
15173 gen_helper_shra_r_qh(cpu_gpr
[ret
], v2_t
, v1_t
);
15177 gen_helper_shrl_ob(cpu_gpr
[ret
], v2_t
, t0
);
15181 gen_helper_shrl_ob(cpu_gpr
[ret
], v2_t
, v1_t
);
15185 gen_helper_shrl_qh(cpu_gpr
[ret
], v2_t
, t0
);
15189 gen_helper_shrl_qh(cpu_gpr
[ret
], v2_t
, v1_t
);
15191 default: /* Invalid */
15192 MIPS_INVAL("MASK SHLL.OB");
15193 generate_exception(ctx
, EXCP_RI
);
15201 tcg_temp_free(v1_t
);
15202 tcg_temp_free(v2_t
);
15203 (void)opn
; /* avoid a compiler warning */
15204 MIPS_DEBUG("%s", opn
);
15207 static void gen_mipsdsp_multiply(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
15208 int ret
, int v1
, int v2
, int check_ret
)
15210 const char *opn
= "mipsdsp multiply";
15215 if ((ret
== 0) && (check_ret
== 1)) {
15216 /* Treat as NOP. */
15221 t0
= tcg_temp_new_i32();
15222 v1_t
= tcg_temp_new();
15223 v2_t
= tcg_temp_new();
15225 tcg_gen_movi_i32(t0
, ret
);
15226 gen_load_gpr(v1_t
, v1
);
15227 gen_load_gpr(v2_t
, v2
);
15230 /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
15231 * the same mask and op1. */
15232 case OPC_MULT_G_2E
:
15236 gen_helper_mul_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15239 gen_helper_mul_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15242 gen_helper_mulq_s_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15244 case OPC_MULQ_RS_W
:
15245 gen_helper_mulq_rs_w(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15249 case OPC_DPA_W_PH_DSP
:
15251 case OPC_DPAU_H_QBL
:
15253 gen_helper_dpau_h_qbl(t0
, v1_t
, v2_t
, cpu_env
);
15255 case OPC_DPAU_H_QBR
:
15257 gen_helper_dpau_h_qbr(t0
, v1_t
, v2_t
, cpu_env
);
15259 case OPC_DPSU_H_QBL
:
15261 gen_helper_dpsu_h_qbl(t0
, v1_t
, v2_t
, cpu_env
);
15263 case OPC_DPSU_H_QBR
:
15265 gen_helper_dpsu_h_qbr(t0
, v1_t
, v2_t
, cpu_env
);
15269 gen_helper_dpa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15271 case OPC_DPAX_W_PH
:
15273 gen_helper_dpax_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15275 case OPC_DPAQ_S_W_PH
:
15277 gen_helper_dpaq_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15279 case OPC_DPAQX_S_W_PH
:
15281 gen_helper_dpaqx_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15283 case OPC_DPAQX_SA_W_PH
:
15285 gen_helper_dpaqx_sa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15289 gen_helper_dps_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15291 case OPC_DPSX_W_PH
:
15293 gen_helper_dpsx_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15295 case OPC_DPSQ_S_W_PH
:
15297 gen_helper_dpsq_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15299 case OPC_DPSQX_S_W_PH
:
15301 gen_helper_dpsqx_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15303 case OPC_DPSQX_SA_W_PH
:
15305 gen_helper_dpsqx_sa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15307 case OPC_MULSAQ_S_W_PH
:
15309 gen_helper_mulsaq_s_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15311 case OPC_DPAQ_SA_L_W
:
15313 gen_helper_dpaq_sa_l_w(t0
, v1_t
, v2_t
, cpu_env
);
15315 case OPC_DPSQ_SA_L_W
:
15317 gen_helper_dpsq_sa_l_w(t0
, v1_t
, v2_t
, cpu_env
);
15319 case OPC_MAQ_S_W_PHL
:
15321 gen_helper_maq_s_w_phl(t0
, v1_t
, v2_t
, cpu_env
);
15323 case OPC_MAQ_S_W_PHR
:
15325 gen_helper_maq_s_w_phr(t0
, v1_t
, v2_t
, cpu_env
);
15327 case OPC_MAQ_SA_W_PHL
:
15329 gen_helper_maq_sa_w_phl(t0
, v1_t
, v2_t
, cpu_env
);
15331 case OPC_MAQ_SA_W_PHR
:
15333 gen_helper_maq_sa_w_phr(t0
, v1_t
, v2_t
, cpu_env
);
15335 case OPC_MULSA_W_PH
:
15337 gen_helper_mulsa_w_ph(t0
, v1_t
, v2_t
, cpu_env
);
15341 #ifdef TARGET_MIPS64
15342 case OPC_DPAQ_W_QH_DSP
:
15344 int ac
= ret
& 0x03;
15345 tcg_gen_movi_i32(t0
, ac
);
15350 gen_helper_dmadd(v1_t
, v2_t
, t0
, cpu_env
);
15354 gen_helper_dmaddu(v1_t
, v2_t
, t0
, cpu_env
);
15358 gen_helper_dmsub(v1_t
, v2_t
, t0
, cpu_env
);
15362 gen_helper_dmsubu(v1_t
, v2_t
, t0
, cpu_env
);
15366 gen_helper_dpa_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
15368 case OPC_DPAQ_S_W_QH
:
15370 gen_helper_dpaq_s_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
15372 case OPC_DPAQ_SA_L_PW
:
15374 gen_helper_dpaq_sa_l_pw(v1_t
, v2_t
, t0
, cpu_env
);
15376 case OPC_DPAU_H_OBL
:
15378 gen_helper_dpau_h_obl(v1_t
, v2_t
, t0
, cpu_env
);
15380 case OPC_DPAU_H_OBR
:
15382 gen_helper_dpau_h_obr(v1_t
, v2_t
, t0
, cpu_env
);
15386 gen_helper_dps_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
15388 case OPC_DPSQ_S_W_QH
:
15390 gen_helper_dpsq_s_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
15392 case OPC_DPSQ_SA_L_PW
:
15394 gen_helper_dpsq_sa_l_pw(v1_t
, v2_t
, t0
, cpu_env
);
15396 case OPC_DPSU_H_OBL
:
15398 gen_helper_dpsu_h_obl(v1_t
, v2_t
, t0
, cpu_env
);
15400 case OPC_DPSU_H_OBR
:
15402 gen_helper_dpsu_h_obr(v1_t
, v2_t
, t0
, cpu_env
);
15404 case OPC_MAQ_S_L_PWL
:
15406 gen_helper_maq_s_l_pwl(v1_t
, v2_t
, t0
, cpu_env
);
15408 case OPC_MAQ_S_L_PWR
:
15410 gen_helper_maq_s_l_pwr(v1_t
, v2_t
, t0
, cpu_env
);
15412 case OPC_MAQ_S_W_QHLL
:
15414 gen_helper_maq_s_w_qhll(v1_t
, v2_t
, t0
, cpu_env
);
15416 case OPC_MAQ_SA_W_QHLL
:
15418 gen_helper_maq_sa_w_qhll(v1_t
, v2_t
, t0
, cpu_env
);
15420 case OPC_MAQ_S_W_QHLR
:
15422 gen_helper_maq_s_w_qhlr(v1_t
, v2_t
, t0
, cpu_env
);
15424 case OPC_MAQ_SA_W_QHLR
:
15426 gen_helper_maq_sa_w_qhlr(v1_t
, v2_t
, t0
, cpu_env
);
15428 case OPC_MAQ_S_W_QHRL
:
15430 gen_helper_maq_s_w_qhrl(v1_t
, v2_t
, t0
, cpu_env
);
15432 case OPC_MAQ_SA_W_QHRL
:
15434 gen_helper_maq_sa_w_qhrl(v1_t
, v2_t
, t0
, cpu_env
);
15436 case OPC_MAQ_S_W_QHRR
:
15438 gen_helper_maq_s_w_qhrr(v1_t
, v2_t
, t0
, cpu_env
);
15440 case OPC_MAQ_SA_W_QHRR
:
15442 gen_helper_maq_sa_w_qhrr(v1_t
, v2_t
, t0
, cpu_env
);
15444 case OPC_MULSAQ_S_L_PW
:
15446 gen_helper_mulsaq_s_l_pw(v1_t
, v2_t
, t0
, cpu_env
);
15448 case OPC_MULSAQ_S_W_QH
:
15450 gen_helper_mulsaq_s_w_qh(v1_t
, v2_t
, t0
, cpu_env
);
15456 case OPC_ADDU_QB_DSP
:
15458 case OPC_MULEU_S_PH_QBL
:
15460 gen_helper_muleu_s_ph_qbl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15462 case OPC_MULEU_S_PH_QBR
:
15464 gen_helper_muleu_s_ph_qbr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15466 case OPC_MULQ_RS_PH
:
15468 gen_helper_mulq_rs_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15470 case OPC_MULEQ_S_W_PHL
:
15472 gen_helper_muleq_s_w_phl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15474 case OPC_MULEQ_S_W_PHR
:
15476 gen_helper_muleq_s_w_phr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15478 case OPC_MULQ_S_PH
:
15480 gen_helper_mulq_s_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15484 #ifdef TARGET_MIPS64
15485 case OPC_ADDU_OB_DSP
:
15487 case OPC_MULEQ_S_PW_QHL
:
15489 gen_helper_muleq_s_pw_qhl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15491 case OPC_MULEQ_S_PW_QHR
:
15493 gen_helper_muleq_s_pw_qhr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15495 case OPC_MULEU_S_QH_OBL
:
15497 gen_helper_muleu_s_qh_obl(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15499 case OPC_MULEU_S_QH_OBR
:
15501 gen_helper_muleu_s_qh_obr(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15503 case OPC_MULQ_RS_QH
:
15505 gen_helper_mulq_rs_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15512 tcg_temp_free_i32(t0
);
15513 tcg_temp_free(v1_t
);
15514 tcg_temp_free(v2_t
);
15516 (void)opn
; /* avoid a compiler warning */
15517 MIPS_DEBUG("%s", opn
);
15521 static void gen_mipsdsp_bitinsn(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
15524 const char *opn
= "mipsdsp Bit/ Manipulation";
15530 /* Treat as NOP. */
15535 t0
= tcg_temp_new();
15536 val_t
= tcg_temp_new();
15537 gen_load_gpr(val_t
, val
);
15540 case OPC_ABSQ_S_PH_DSP
:
15544 gen_helper_bitrev(cpu_gpr
[ret
], val_t
);
15549 target_long result
;
15550 imm
= (ctx
->opcode
>> 16) & 0xFF;
15551 result
= (uint32_t)imm
<< 24 |
15552 (uint32_t)imm
<< 16 |
15553 (uint32_t)imm
<< 8 |
15555 result
= (int32_t)result
;
15556 tcg_gen_movi_tl(cpu_gpr
[ret
], result
);
15561 tcg_gen_ext8u_tl(cpu_gpr
[ret
], val_t
);
15562 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 8);
15563 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15564 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
15565 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15566 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
15571 imm
= (ctx
->opcode
>> 16) & 0x03FF;
15572 imm
= (int16_t)(imm
<< 6) >> 6;
15573 tcg_gen_movi_tl(cpu_gpr
[ret
], \
15574 (target_long
)((int32_t)imm
<< 16 | \
15580 tcg_gen_ext16u_tl(cpu_gpr
[ret
], val_t
);
15581 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
15582 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15583 tcg_gen_ext32s_tl(cpu_gpr
[ret
], cpu_gpr
[ret
]);
15587 #ifdef TARGET_MIPS64
15588 case OPC_ABSQ_S_QH_DSP
:
15595 imm
= (ctx
->opcode
>> 16) & 0xFF;
15596 temp
= ((uint64_t)imm
<< 8) | (uint64_t)imm
;
15597 temp
= (temp
<< 16) | temp
;
15598 temp
= (temp
<< 32) | temp
;
15599 tcg_gen_movi_tl(cpu_gpr
[ret
], temp
);
15607 imm
= (ctx
->opcode
>> 16) & 0x03FF;
15608 imm
= (int16_t)(imm
<< 6) >> 6;
15609 temp
= ((target_long
)imm
<< 32) \
15610 | ((target_long
)imm
& 0xFFFFFFFF);
15611 tcg_gen_movi_tl(cpu_gpr
[ret
], temp
);
15619 imm
= (ctx
->opcode
>> 16) & 0x03FF;
15620 imm
= (int16_t)(imm
<< 6) >> 6;
15622 temp
= ((uint64_t)(uint16_t)imm
<< 48) |
15623 ((uint64_t)(uint16_t)imm
<< 32) |
15624 ((uint64_t)(uint16_t)imm
<< 16) |
15625 (uint64_t)(uint16_t)imm
;
15626 tcg_gen_movi_tl(cpu_gpr
[ret
], temp
);
15631 tcg_gen_ext8u_tl(cpu_gpr
[ret
], val_t
);
15632 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 8);
15633 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15634 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
15635 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15636 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 32);
15637 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15641 tcg_gen_ext32u_i64(cpu_gpr
[ret
], val_t
);
15642 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 32);
15643 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15647 tcg_gen_ext16u_tl(cpu_gpr
[ret
], val_t
);
15648 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 16);
15649 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15650 tcg_gen_shli_tl(t0
, cpu_gpr
[ret
], 32);
15651 tcg_gen_or_tl(cpu_gpr
[ret
], cpu_gpr
[ret
], t0
);
15658 tcg_temp_free(val_t
);
15660 (void)opn
; /* avoid a compiler warning */
15661 MIPS_DEBUG("%s", opn
);
15664 static void gen_mipsdsp_add_cmp_pick(DisasContext
*ctx
,
15665 uint32_t op1
, uint32_t op2
,
15666 int ret
, int v1
, int v2
, int check_ret
)
15668 const char *opn
= "mipsdsp add compare pick";
15673 if ((ret
== 0) && (check_ret
== 1)) {
15674 /* Treat as NOP. */
15679 t1
= tcg_temp_new();
15680 v1_t
= tcg_temp_new();
15681 v2_t
= tcg_temp_new();
15683 gen_load_gpr(v1_t
, v1
);
15684 gen_load_gpr(v2_t
, v2
);
15687 case OPC_CMPU_EQ_QB_DSP
:
15689 case OPC_CMPU_EQ_QB
:
15691 gen_helper_cmpu_eq_qb(v1_t
, v2_t
, cpu_env
);
15693 case OPC_CMPU_LT_QB
:
15695 gen_helper_cmpu_lt_qb(v1_t
, v2_t
, cpu_env
);
15697 case OPC_CMPU_LE_QB
:
15699 gen_helper_cmpu_le_qb(v1_t
, v2_t
, cpu_env
);
15701 case OPC_CMPGU_EQ_QB
:
15703 gen_helper_cmpgu_eq_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
15705 case OPC_CMPGU_LT_QB
:
15707 gen_helper_cmpgu_lt_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
15709 case OPC_CMPGU_LE_QB
:
15711 gen_helper_cmpgu_le_qb(cpu_gpr
[ret
], v1_t
, v2_t
);
15713 case OPC_CMPGDU_EQ_QB
:
15715 gen_helper_cmpgu_eq_qb(t1
, v1_t
, v2_t
);
15716 tcg_gen_mov_tl(cpu_gpr
[ret
], t1
);
15717 tcg_gen_andi_tl(cpu_dspctrl
, cpu_dspctrl
, 0xF0FFFFFF);
15718 tcg_gen_shli_tl(t1
, t1
, 24);
15719 tcg_gen_or_tl(cpu_dspctrl
, cpu_dspctrl
, t1
);
15721 case OPC_CMPGDU_LT_QB
:
15723 gen_helper_cmpgu_lt_qb(t1
, v1_t
, v2_t
);
15724 tcg_gen_mov_tl(cpu_gpr
[ret
], t1
);
15725 tcg_gen_andi_tl(cpu_dspctrl
, cpu_dspctrl
, 0xF0FFFFFF);
15726 tcg_gen_shli_tl(t1
, t1
, 24);
15727 tcg_gen_or_tl(cpu_dspctrl
, cpu_dspctrl
, t1
);
15729 case OPC_CMPGDU_LE_QB
:
15731 gen_helper_cmpgu_le_qb(t1
, v1_t
, v2_t
);
15732 tcg_gen_mov_tl(cpu_gpr
[ret
], t1
);
15733 tcg_gen_andi_tl(cpu_dspctrl
, cpu_dspctrl
, 0xF0FFFFFF);
15734 tcg_gen_shli_tl(t1
, t1
, 24);
15735 tcg_gen_or_tl(cpu_dspctrl
, cpu_dspctrl
, t1
);
15737 case OPC_CMP_EQ_PH
:
15739 gen_helper_cmp_eq_ph(v1_t
, v2_t
, cpu_env
);
15741 case OPC_CMP_LT_PH
:
15743 gen_helper_cmp_lt_ph(v1_t
, v2_t
, cpu_env
);
15745 case OPC_CMP_LE_PH
:
15747 gen_helper_cmp_le_ph(v1_t
, v2_t
, cpu_env
);
15751 gen_helper_pick_qb(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15755 gen_helper_pick_ph(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15757 case OPC_PACKRL_PH
:
15759 gen_helper_packrl_ph(cpu_gpr
[ret
], v1_t
, v2_t
);
15763 #ifdef TARGET_MIPS64
15764 case OPC_CMPU_EQ_OB_DSP
:
15766 case OPC_CMP_EQ_PW
:
15768 gen_helper_cmp_eq_pw(v1_t
, v2_t
, cpu_env
);
15770 case OPC_CMP_LT_PW
:
15772 gen_helper_cmp_lt_pw(v1_t
, v2_t
, cpu_env
);
15774 case OPC_CMP_LE_PW
:
15776 gen_helper_cmp_le_pw(v1_t
, v2_t
, cpu_env
);
15778 case OPC_CMP_EQ_QH
:
15780 gen_helper_cmp_eq_qh(v1_t
, v2_t
, cpu_env
);
15782 case OPC_CMP_LT_QH
:
15784 gen_helper_cmp_lt_qh(v1_t
, v2_t
, cpu_env
);
15786 case OPC_CMP_LE_QH
:
15788 gen_helper_cmp_le_qh(v1_t
, v2_t
, cpu_env
);
15790 case OPC_CMPGDU_EQ_OB
:
15792 gen_helper_cmpgdu_eq_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15794 case OPC_CMPGDU_LT_OB
:
15796 gen_helper_cmpgdu_lt_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15798 case OPC_CMPGDU_LE_OB
:
15800 gen_helper_cmpgdu_le_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15802 case OPC_CMPGU_EQ_OB
:
15804 gen_helper_cmpgu_eq_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
15806 case OPC_CMPGU_LT_OB
:
15808 gen_helper_cmpgu_lt_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
15810 case OPC_CMPGU_LE_OB
:
15812 gen_helper_cmpgu_le_ob(cpu_gpr
[ret
], v1_t
, v2_t
);
15814 case OPC_CMPU_EQ_OB
:
15816 gen_helper_cmpu_eq_ob(v1_t
, v2_t
, cpu_env
);
15818 case OPC_CMPU_LT_OB
:
15820 gen_helper_cmpu_lt_ob(v1_t
, v2_t
, cpu_env
);
15822 case OPC_CMPU_LE_OB
:
15824 gen_helper_cmpu_le_ob(v1_t
, v2_t
, cpu_env
);
15826 case OPC_PACKRL_PW
:
15828 gen_helper_packrl_pw(cpu_gpr
[ret
], v1_t
, v2_t
);
15832 gen_helper_pick_ob(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15836 gen_helper_pick_pw(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15840 gen_helper_pick_qh(cpu_gpr
[ret
], v1_t
, v2_t
, cpu_env
);
15848 tcg_temp_free(v1_t
);
15849 tcg_temp_free(v2_t
);
15851 (void)opn
; /* avoid a compiler warning */
15852 MIPS_DEBUG("%s", opn
);
15855 static void gen_mipsdsp_append(CPUMIPSState
*env
, DisasContext
*ctx
,
15856 uint32_t op1
, int rt
, int rs
, int sa
)
15858 const char *opn
= "mipsdsp append/dappend";
15864 /* Treat as NOP. */
15869 t0
= tcg_temp_new();
15870 gen_load_gpr(t0
, rs
);
15873 case OPC_APPEND_DSP
:
15874 switch (MASK_APPEND(ctx
->opcode
)) {
15877 tcg_gen_deposit_tl(cpu_gpr
[rt
], t0
, cpu_gpr
[rt
], sa
, 32 - sa
);
15879 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
15883 tcg_gen_ext32u_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
15884 tcg_gen_shri_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], sa
);
15885 tcg_gen_shli_tl(t0
, t0
, 32 - sa
);
15886 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
15888 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
15892 if (sa
!= 0 && sa
!= 2) {
15893 tcg_gen_shli_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], 8 * sa
);
15894 tcg_gen_ext32u_tl(t0
, t0
);
15895 tcg_gen_shri_tl(t0
, t0
, 8 * (4 - sa
));
15896 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
15898 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
15900 default: /* Invalid */
15901 MIPS_INVAL("MASK APPEND");
15902 generate_exception(ctx
, EXCP_RI
);
15906 #ifdef TARGET_MIPS64
15907 case OPC_DAPPEND_DSP
:
15908 switch (MASK_DAPPEND(ctx
->opcode
)) {
15911 tcg_gen_deposit_tl(cpu_gpr
[rt
], t0
, cpu_gpr
[rt
], sa
, 64 - sa
);
15915 tcg_gen_shri_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], 0x20 | sa
);
15916 tcg_gen_shli_tl(t0
, t0
, 64 - (0x20 | sa
));
15917 tcg_gen_or_tl(cpu_gpr
[rt
], t0
, t0
);
15921 tcg_gen_shri_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], sa
);
15922 tcg_gen_shli_tl(t0
, t0
, 64 - sa
);
15923 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
15928 if (sa
!= 0 && sa
!= 2 && sa
!= 4) {
15929 tcg_gen_shli_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], 8 * sa
);
15930 tcg_gen_shri_tl(t0
, t0
, 8 * (8 - sa
));
15931 tcg_gen_or_tl(cpu_gpr
[rt
], cpu_gpr
[rt
], t0
);
15934 default: /* Invalid */
15935 MIPS_INVAL("MASK DAPPEND");
15936 generate_exception(ctx
, EXCP_RI
);
15943 (void)opn
; /* avoid a compiler warning */
15944 MIPS_DEBUG("%s", opn
);
15947 static void gen_mipsdsp_accinsn(DisasContext
*ctx
, uint32_t op1
, uint32_t op2
,
15948 int ret
, int v1
, int v2
, int check_ret
)
15951 const char *opn
= "mipsdsp accumulator";
15958 if ((ret
== 0) && (check_ret
== 1)) {
15959 /* Treat as NOP. */
15964 t0
= tcg_temp_new();
15965 t1
= tcg_temp_new();
15966 v1_t
= tcg_temp_new();
15967 v2_t
= tcg_temp_new();
15969 gen_load_gpr(v1_t
, v1
);
15970 gen_load_gpr(v2_t
, v2
);
15973 case OPC_EXTR_W_DSP
:
15977 tcg_gen_movi_tl(t0
, v2
);
15978 tcg_gen_movi_tl(t1
, v1
);
15979 gen_helper_extr_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
15982 tcg_gen_movi_tl(t0
, v2
);
15983 tcg_gen_movi_tl(t1
, v1
);
15984 gen_helper_extr_r_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
15986 case OPC_EXTR_RS_W
:
15987 tcg_gen_movi_tl(t0
, v2
);
15988 tcg_gen_movi_tl(t1
, v1
);
15989 gen_helper_extr_rs_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
15992 tcg_gen_movi_tl(t0
, v2
);
15993 tcg_gen_movi_tl(t1
, v1
);
15994 gen_helper_extr_s_h(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
15996 case OPC_EXTRV_S_H
:
15997 tcg_gen_movi_tl(t0
, v2
);
15998 gen_helper_extr_s_h(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16001 tcg_gen_movi_tl(t0
, v2
);
16002 gen_helper_extr_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16004 case OPC_EXTRV_R_W
:
16005 tcg_gen_movi_tl(t0
, v2
);
16006 gen_helper_extr_r_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16008 case OPC_EXTRV_RS_W
:
16009 tcg_gen_movi_tl(t0
, v2
);
16010 gen_helper_extr_rs_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16013 tcg_gen_movi_tl(t0
, v2
);
16014 tcg_gen_movi_tl(t1
, v1
);
16015 gen_helper_extp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16018 tcg_gen_movi_tl(t0
, v2
);
16019 gen_helper_extp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16022 tcg_gen_movi_tl(t0
, v2
);
16023 tcg_gen_movi_tl(t1
, v1
);
16024 gen_helper_extpdp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16027 tcg_gen_movi_tl(t0
, v2
);
16028 gen_helper_extpdp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16031 imm
= (ctx
->opcode
>> 20) & 0x3F;
16032 tcg_gen_movi_tl(t0
, ret
);
16033 tcg_gen_movi_tl(t1
, imm
);
16034 gen_helper_shilo(t0
, t1
, cpu_env
);
16037 tcg_gen_movi_tl(t0
, ret
);
16038 gen_helper_shilo(t0
, v1_t
, cpu_env
);
16041 tcg_gen_movi_tl(t0
, ret
);
16042 gen_helper_mthlip(t0
, v1_t
, cpu_env
);
16045 imm
= (ctx
->opcode
>> 11) & 0x3FF;
16046 tcg_gen_movi_tl(t0
, imm
);
16047 gen_helper_wrdsp(v1_t
, t0
, cpu_env
);
16050 imm
= (ctx
->opcode
>> 16) & 0x03FF;
16051 tcg_gen_movi_tl(t0
, imm
);
16052 gen_helper_rddsp(cpu_gpr
[ret
], t0
, cpu_env
);
16056 #ifdef TARGET_MIPS64
16057 case OPC_DEXTR_W_DSP
:
16061 tcg_gen_movi_tl(t0
, ret
);
16062 gen_helper_dmthlip(v1_t
, t0
, cpu_env
);
16066 int shift
= (ctx
->opcode
>> 19) & 0x7F;
16067 int ac
= (ctx
->opcode
>> 11) & 0x03;
16068 tcg_gen_movi_tl(t0
, shift
);
16069 tcg_gen_movi_tl(t1
, ac
);
16070 gen_helper_dshilo(t0
, t1
, cpu_env
);
16075 int ac
= (ctx
->opcode
>> 11) & 0x03;
16076 tcg_gen_movi_tl(t0
, ac
);
16077 gen_helper_dshilo(v1_t
, t0
, cpu_env
);
16081 tcg_gen_movi_tl(t0
, v2
);
16082 tcg_gen_movi_tl(t1
, v1
);
16084 gen_helper_dextp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16087 tcg_gen_movi_tl(t0
, v2
);
16088 gen_helper_dextp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16091 tcg_gen_movi_tl(t0
, v2
);
16092 tcg_gen_movi_tl(t1
, v1
);
16093 gen_helper_dextpdp(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16096 tcg_gen_movi_tl(t0
, v2
);
16097 gen_helper_dextpdp(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16100 tcg_gen_movi_tl(t0
, v2
);
16101 tcg_gen_movi_tl(t1
, v1
);
16102 gen_helper_dextr_l(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16104 case OPC_DEXTR_R_L
:
16105 tcg_gen_movi_tl(t0
, v2
);
16106 tcg_gen_movi_tl(t1
, v1
);
16107 gen_helper_dextr_r_l(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16109 case OPC_DEXTR_RS_L
:
16110 tcg_gen_movi_tl(t0
, v2
);
16111 tcg_gen_movi_tl(t1
, v1
);
16112 gen_helper_dextr_rs_l(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16115 tcg_gen_movi_tl(t0
, v2
);
16116 tcg_gen_movi_tl(t1
, v1
);
16117 gen_helper_dextr_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16119 case OPC_DEXTR_R_W
:
16120 tcg_gen_movi_tl(t0
, v2
);
16121 tcg_gen_movi_tl(t1
, v1
);
16122 gen_helper_dextr_r_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16124 case OPC_DEXTR_RS_W
:
16125 tcg_gen_movi_tl(t0
, v2
);
16126 tcg_gen_movi_tl(t1
, v1
);
16127 gen_helper_dextr_rs_w(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16129 case OPC_DEXTR_S_H
:
16130 tcg_gen_movi_tl(t0
, v2
);
16131 tcg_gen_movi_tl(t1
, v1
);
16132 gen_helper_dextr_s_h(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16134 case OPC_DEXTRV_S_H
:
16135 tcg_gen_movi_tl(t0
, v2
);
16136 tcg_gen_movi_tl(t1
, v1
);
16137 gen_helper_dextr_s_h(cpu_gpr
[ret
], t0
, t1
, cpu_env
);
16140 tcg_gen_movi_tl(t0
, v2
);
16141 gen_helper_dextr_l(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16143 case OPC_DEXTRV_R_L
:
16144 tcg_gen_movi_tl(t0
, v2
);
16145 gen_helper_dextr_r_l(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16147 case OPC_DEXTRV_RS_L
:
16148 tcg_gen_movi_tl(t0
, v2
);
16149 gen_helper_dextr_rs_l(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16152 tcg_gen_movi_tl(t0
, v2
);
16153 gen_helper_dextr_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16155 case OPC_DEXTRV_R_W
:
16156 tcg_gen_movi_tl(t0
, v2
);
16157 gen_helper_dextr_r_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16159 case OPC_DEXTRV_RS_W
:
16160 tcg_gen_movi_tl(t0
, v2
);
16161 gen_helper_dextr_rs_w(cpu_gpr
[ret
], t0
, v1_t
, cpu_env
);
16170 tcg_temp_free(v1_t
);
16171 tcg_temp_free(v2_t
);
16173 (void)opn
; /* avoid a compiler warning */
16174 MIPS_DEBUG("%s", opn
);
16177 /* End MIPSDSP functions. */
16179 /* Compact Branches */
16180 static void gen_compute_compact_branch(DisasContext
*ctx
, uint32_t opc
,
16181 int rs
, int rt
, int32_t offset
)
16183 int bcond_compute
= 0;
16184 TCGv t0
= tcg_temp_new();
16185 TCGv t1
= tcg_temp_new();
16187 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
16188 #ifdef MIPS_DEBUG_DISAS
16189 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
16192 generate_exception(ctx
, EXCP_RI
);
16196 /* Load needed operands and calculate btarget */
16198 /* compact branch */
16199 case OPC_BOVC
: /* OPC_BEQZALC, OPC_BEQC */
16200 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC */
16201 gen_load_gpr(t0
, rs
);
16202 gen_load_gpr(t1
, rt
);
16204 ctx
->btarget
= addr_add(ctx
, ctx
->pc
+ 4, offset
);
16205 if (rs
<= rt
&& rs
== 0) {
16206 /* OPC_BEQZALC, OPC_BNEZALC */
16207 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 4);
16210 case OPC_BLEZC
: /* OPC_BGEZC, OPC_BGEC */
16211 case OPC_BGTZC
: /* OPC_BLTZC, OPC_BLTC */
16212 gen_load_gpr(t0
, rs
);
16213 gen_load_gpr(t1
, rt
);
16215 ctx
->btarget
= addr_add(ctx
, ctx
->pc
+ 4, offset
);
16217 case OPC_BLEZALC
: /* OPC_BGEZALC, OPC_BGEUC */
16218 case OPC_BGTZALC
: /* OPC_BLTZALC, OPC_BLTUC */
16219 if (rs
== 0 || rs
== rt
) {
16220 /* OPC_BLEZALC, OPC_BGEZALC */
16221 /* OPC_BGTZALC, OPC_BLTZALC */
16222 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 4);
16224 gen_load_gpr(t0
, rs
);
16225 gen_load_gpr(t1
, rt
);
16227 ctx
->btarget
= addr_add(ctx
, ctx
->pc
+ 4, offset
);
16231 ctx
->btarget
= addr_add(ctx
, ctx
->pc
+ 4, offset
);
16236 /* OPC_BEQZC, OPC_BNEZC */
16237 gen_load_gpr(t0
, rs
);
16239 ctx
->btarget
= addr_add(ctx
, ctx
->pc
+ 4, offset
);
16241 /* OPC_JIC, OPC_JIALC */
16242 TCGv tbase
= tcg_temp_new();
16243 TCGv toffset
= tcg_temp_new();
16245 gen_load_gpr(tbase
, rt
);
16246 tcg_gen_movi_tl(toffset
, offset
);
16247 gen_op_addr_add(ctx
, btarget
, tbase
, toffset
);
16248 tcg_temp_free(tbase
);
16249 tcg_temp_free(toffset
);
16253 MIPS_INVAL("Compact branch/jump");
16254 generate_exception(ctx
, EXCP_RI
);
16258 if (bcond_compute
== 0) {
16259 /* Uncoditional compact branch */
16262 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 4);
16265 ctx
->hflags
|= MIPS_HFLAG_BR
;
16268 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 4);
16271 ctx
->hflags
|= MIPS_HFLAG_B
;
16274 MIPS_INVAL("Compact branch/jump");
16275 generate_exception(ctx
, EXCP_RI
);
16279 /* Generating branch here as compact branches don't have delay slot */
16280 gen_branch(ctx
, 4);
16282 /* Conditional compact branch */
16283 TCGLabel
*fs
= gen_new_label();
16284 save_cpu_state(ctx
, 0);
16287 case OPC_BLEZALC
: /* OPC_BGEZALC, OPC_BGEUC */
16288 if (rs
== 0 && rt
!= 0) {
16290 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE
), t1
, 0, fs
);
16291 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
16293 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE
), t1
, 0, fs
);
16296 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU
), t0
, t1
, fs
);
16299 case OPC_BGTZALC
: /* OPC_BLTZALC, OPC_BLTUC */
16300 if (rs
== 0 && rt
!= 0) {
16302 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT
), t1
, 0, fs
);
16303 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
16305 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT
), t1
, 0, fs
);
16308 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU
), t0
, t1
, fs
);
16311 case OPC_BLEZC
: /* OPC_BGEZC, OPC_BGEC */
16312 if (rs
== 0 && rt
!= 0) {
16314 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE
), t1
, 0, fs
);
16315 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
16317 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE
), t1
, 0, fs
);
16320 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE
), t0
, t1
, fs
);
16323 case OPC_BGTZC
: /* OPC_BLTZC, OPC_BLTC */
16324 if (rs
== 0 && rt
!= 0) {
16326 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT
), t1
, 0, fs
);
16327 } else if (rs
!= 0 && rt
!= 0 && rs
== rt
) {
16329 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT
), t1
, 0, fs
);
16332 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT
), t0
, t1
, fs
);
16335 case OPC_BOVC
: /* OPC_BEQZALC, OPC_BEQC */
16336 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC */
16338 /* OPC_BOVC, OPC_BNVC */
16339 TCGv t2
= tcg_temp_new();
16340 TCGv t3
= tcg_temp_new();
16341 TCGv t4
= tcg_temp_new();
16342 TCGv input_overflow
= tcg_temp_new();
16344 gen_load_gpr(t0
, rs
);
16345 gen_load_gpr(t1
, rt
);
16346 tcg_gen_ext32s_tl(t2
, t0
);
16347 tcg_gen_setcond_tl(TCG_COND_NE
, input_overflow
, t2
, t0
);
16348 tcg_gen_ext32s_tl(t3
, t1
);
16349 tcg_gen_setcond_tl(TCG_COND_NE
, t4
, t3
, t1
);
16350 tcg_gen_or_tl(input_overflow
, input_overflow
, t4
);
16352 tcg_gen_add_tl(t4
, t2
, t3
);
16353 tcg_gen_ext32s_tl(t4
, t4
);
16354 tcg_gen_xor_tl(t2
, t2
, t3
);
16355 tcg_gen_xor_tl(t3
, t4
, t3
);
16356 tcg_gen_andc_tl(t2
, t3
, t2
);
16357 tcg_gen_setcondi_tl(TCG_COND_LT
, t4
, t2
, 0);
16358 tcg_gen_or_tl(t4
, t4
, input_overflow
);
16359 if (opc
== OPC_BOVC
) {
16361 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE
), t4
, 0, fs
);
16364 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t4
, 0, fs
);
16366 tcg_temp_free(input_overflow
);
16370 } else if (rs
< rt
&& rs
== 0) {
16371 /* OPC_BEQZALC, OPC_BNEZALC */
16372 if (opc
== OPC_BEQZALC
) {
16374 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t1
, 0, fs
);
16377 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE
), t1
, 0, fs
);
16380 /* OPC_BEQC, OPC_BNEC */
16381 if (opc
== OPC_BEQC
) {
16383 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ
), t0
, t1
, fs
);
16386 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE
), t0
, t1
, fs
);
16391 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ
), t0
, 0, fs
);
16394 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE
), t0
, 0, fs
);
16397 MIPS_INVAL("Compact conditional branch/jump");
16398 generate_exception(ctx
, EXCP_RI
);
16402 /* Generating branch here as compact branches don't have delay slot */
16403 gen_goto_tb(ctx
, 1, ctx
->btarget
);
16406 ctx
->hflags
|= MIPS_HFLAG_FBNSLOT
;
16407 MIPS_DEBUG("Compact conditional branch");
16415 static void decode_opc_special_r6(CPUMIPSState
*env
, DisasContext
*ctx
)
16417 int rs
, rt
, rd
, sa
;
16420 rs
= (ctx
->opcode
>> 21) & 0x1f;
16421 rt
= (ctx
->opcode
>> 16) & 0x1f;
16422 rd
= (ctx
->opcode
>> 11) & 0x1f;
16423 sa
= (ctx
->opcode
>> 6) & 0x1f;
16425 op1
= MASK_SPECIAL(ctx
->opcode
);
16429 int imm2
= extract32(ctx
->opcode
, 6, 3);
16430 TCGv t0
= tcg_temp_new();
16431 TCGv t1
= tcg_temp_new();
16432 gen_load_gpr(t0
, rs
);
16433 gen_load_gpr(t1
, rt
);
16434 tcg_gen_shli_tl(t0
, t0
, imm2
+ 1);
16435 tcg_gen_add_tl(t0
, t0
, t1
);
16436 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
16441 case OPC_MULT
... OPC_DIVU
:
16442 op2
= MASK_R6_MULDIV(ctx
->opcode
);
16452 gen_r6_muldiv(ctx
, op2
, rd
, rs
, rt
);
16455 MIPS_INVAL("special_r6 muldiv");
16456 generate_exception(ctx
, EXCP_RI
);
16462 gen_cond_move(ctx
, op1
, rd
, rs
, rt
);
16466 if (rt
== 0 && sa
== 1) {
16467 /* Major opcode and function field is shared with preR6 MFHI/MTHI.
16468 We need additionally to check other fields */
16469 gen_cl(ctx
, op1
, rd
, rs
);
16471 generate_exception(ctx
, EXCP_RI
);
16475 if (ctx
->hflags
& MIPS_HFLAG_SBRI
) {
16476 generate_exception(ctx
, EXCP_RI
);
16478 generate_exception(ctx
, EXCP_DBp
);
16481 #if defined(TARGET_MIPS64)
16483 check_mips_64(ctx
);
16485 int imm2
= extract32(ctx
->opcode
, 6, 3);
16486 TCGv t0
= tcg_temp_new();
16487 TCGv t1
= tcg_temp_new();
16488 gen_load_gpr(t0
, rs
);
16489 gen_load_gpr(t1
, rt
);
16490 tcg_gen_shli_tl(t0
, t0
, imm2
+ 1);
16491 tcg_gen_add_tl(cpu_gpr
[rd
], t0
, t1
);
16498 if (rt
== 0 && sa
== 1) {
16499 /* Major opcode and function field is shared with preR6 MFHI/MTHI.
16500 We need additionally to check other fields */
16501 check_mips_64(ctx
);
16502 gen_cl(ctx
, op1
, rd
, rs
);
16504 generate_exception(ctx
, EXCP_RI
);
16507 case OPC_DMULT
... OPC_DDIVU
:
16508 op2
= MASK_R6_MULDIV(ctx
->opcode
);
16518 check_mips_64(ctx
);
16519 gen_r6_muldiv(ctx
, op2
, rd
, rs
, rt
);
16522 MIPS_INVAL("special_r6 muldiv");
16523 generate_exception(ctx
, EXCP_RI
);
16528 default: /* Invalid */
16529 MIPS_INVAL("special_r6");
16530 generate_exception(ctx
, EXCP_RI
);
16535 static void decode_opc_special_legacy(CPUMIPSState
*env
, DisasContext
*ctx
)
16537 int rs
, rt
, rd
, sa
;
16540 rs
= (ctx
->opcode
>> 21) & 0x1f;
16541 rt
= (ctx
->opcode
>> 16) & 0x1f;
16542 rd
= (ctx
->opcode
>> 11) & 0x1f;
16543 sa
= (ctx
->opcode
>> 6) & 0x1f;
16545 op1
= MASK_SPECIAL(ctx
->opcode
);
16547 case OPC_MOVN
: /* Conditional move */
16549 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
|
16550 INSN_LOONGSON2E
| INSN_LOONGSON2F
);
16551 gen_cond_move(ctx
, op1
, rd
, rs
, rt
);
16553 case OPC_MFHI
: /* Move from HI/LO */
16555 gen_HILO(ctx
, op1
, rs
& 3, rd
);
16558 case OPC_MTLO
: /* Move to HI/LO */
16559 gen_HILO(ctx
, op1
, rd
& 3, rs
);
16562 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
);
16563 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
16564 check_cp1_enabled(ctx
);
16565 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
16566 (ctx
->opcode
>> 16) & 1);
16568 generate_exception_err(ctx
, EXCP_CpU
, 1);
16574 check_insn(ctx
, INSN_VR54XX
);
16575 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
16576 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
16578 gen_muldiv(ctx
, op1
, rd
& 3, rs
, rt
);
16583 gen_muldiv(ctx
, op1
, 0, rs
, rt
);
16585 #if defined(TARGET_MIPS64)
16586 case OPC_DMULT
... OPC_DDIVU
:
16587 check_insn(ctx
, ISA_MIPS3
);
16588 check_mips_64(ctx
);
16589 gen_muldiv(ctx
, op1
, 0, rs
, rt
);
16593 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
, 4);
16596 #ifdef MIPS_STRICT_STANDARD
16597 MIPS_INVAL("SPIM");
16598 generate_exception(ctx
, EXCP_RI
);
16600 /* Implemented as RI exception for now. */
16601 MIPS_INVAL("spim (unofficial)");
16602 generate_exception(ctx
, EXCP_RI
);
16605 default: /* Invalid */
16606 MIPS_INVAL("special_legacy");
16607 generate_exception(ctx
, EXCP_RI
);
16612 static void decode_opc_special(CPUMIPSState
*env
, DisasContext
*ctx
)
16614 int rs
, rt
, rd
, sa
;
16617 rs
= (ctx
->opcode
>> 21) & 0x1f;
16618 rt
= (ctx
->opcode
>> 16) & 0x1f;
16619 rd
= (ctx
->opcode
>> 11) & 0x1f;
16620 sa
= (ctx
->opcode
>> 6) & 0x1f;
16622 op1
= MASK_SPECIAL(ctx
->opcode
);
16624 case OPC_SLL
: /* Shift with immediate */
16625 if (sa
== 5 && rd
== 0 &&
16626 rs
== 0 && rt
== 0) { /* PAUSE */
16627 if ((ctx
->insn_flags
& ISA_MIPS32R6
) &&
16628 (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
16629 MIPS_DEBUG("CTI in delay / forbidden slot");
16630 generate_exception(ctx
, EXCP_RI
);
16636 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
16639 switch ((ctx
->opcode
>> 21) & 0x1f) {
16641 /* rotr is decoded as srl on non-R2 CPUs */
16642 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
16647 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
16650 generate_exception(ctx
, EXCP_RI
);
16654 case OPC_ADD
... OPC_SUBU
:
16655 gen_arith(ctx
, op1
, rd
, rs
, rt
);
16657 case OPC_SLLV
: /* Shifts */
16659 gen_shift(ctx
, op1
, rd
, rs
, rt
);
16662 switch ((ctx
->opcode
>> 6) & 0x1f) {
16664 /* rotrv is decoded as srlv on non-R2 CPUs */
16665 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
16670 gen_shift(ctx
, op1
, rd
, rs
, rt
);
16673 generate_exception(ctx
, EXCP_RI
);
16677 case OPC_SLT
: /* Set on less than */
16679 gen_slt(ctx
, op1
, rd
, rs
, rt
);
16681 case OPC_AND
: /* Logic*/
16685 gen_logic(ctx
, op1
, rd
, rs
, rt
);
16688 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
, 4);
16690 case OPC_TGE
... OPC_TEQ
: /* Traps */
16692 check_insn(ctx
, ISA_MIPS2
);
16693 gen_trap(ctx
, op1
, rs
, rt
, -1);
16695 case OPC_LSA
: /* OPC_PMON */
16696 if ((ctx
->insn_flags
& ISA_MIPS32R6
) ||
16697 (env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
16698 decode_opc_special_r6(env
, ctx
);
16700 /* Pmon entry point, also R4010 selsl */
16701 #ifdef MIPS_STRICT_STANDARD
16702 MIPS_INVAL("PMON / selsl");
16703 generate_exception(ctx
, EXCP_RI
);
16705 gen_helper_0e0i(pmon
, sa
);
16710 generate_exception(ctx
, EXCP_SYSCALL
);
16711 ctx
->bstate
= BS_STOP
;
16714 generate_exception(ctx
, EXCP_BREAK
);
16717 check_insn(ctx
, ISA_MIPS2
);
16718 /* Treat as NOP. */
16721 #if defined(TARGET_MIPS64)
16722 /* MIPS64 specific opcodes */
16727 check_insn(ctx
, ISA_MIPS3
);
16728 check_mips_64(ctx
);
16729 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
16732 switch ((ctx
->opcode
>> 21) & 0x1f) {
16734 /* drotr is decoded as dsrl on non-R2 CPUs */
16735 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
16740 check_insn(ctx
, ISA_MIPS3
);
16741 check_mips_64(ctx
);
16742 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
16745 generate_exception(ctx
, EXCP_RI
);
16750 switch ((ctx
->opcode
>> 21) & 0x1f) {
16752 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
16753 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
16758 check_insn(ctx
, ISA_MIPS3
);
16759 check_mips_64(ctx
);
16760 gen_shift_imm(ctx
, op1
, rd
, rt
, sa
);
16763 generate_exception(ctx
, EXCP_RI
);
16767 case OPC_DADD
... OPC_DSUBU
:
16768 check_insn(ctx
, ISA_MIPS3
);
16769 check_mips_64(ctx
);
16770 gen_arith(ctx
, op1
, rd
, rs
, rt
);
16774 check_insn(ctx
, ISA_MIPS3
);
16775 check_mips_64(ctx
);
16776 gen_shift(ctx
, op1
, rd
, rs
, rt
);
16779 switch ((ctx
->opcode
>> 6) & 0x1f) {
16781 /* drotrv is decoded as dsrlv on non-R2 CPUs */
16782 if (ctx
->insn_flags
& ISA_MIPS32R2
) {
16787 check_insn(ctx
, ISA_MIPS3
);
16788 check_mips_64(ctx
);
16789 gen_shift(ctx
, op1
, rd
, rs
, rt
);
16792 generate_exception(ctx
, EXCP_RI
);
16797 if ((ctx
->insn_flags
& ISA_MIPS32R6
) ||
16798 (env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
16799 decode_opc_special_r6(env
, ctx
);
16804 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
16805 decode_opc_special_r6(env
, ctx
);
16807 decode_opc_special_legacy(env
, ctx
);
16812 static void decode_opc_special2_legacy(CPUMIPSState
*env
, DisasContext
*ctx
)
16817 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
16819 rs
= (ctx
->opcode
>> 21) & 0x1f;
16820 rt
= (ctx
->opcode
>> 16) & 0x1f;
16821 rd
= (ctx
->opcode
>> 11) & 0x1f;
16823 op1
= MASK_SPECIAL2(ctx
->opcode
);
16825 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
16826 case OPC_MSUB
... OPC_MSUBU
:
16827 check_insn(ctx
, ISA_MIPS32
);
16828 gen_muldiv(ctx
, op1
, rd
& 3, rs
, rt
);
16831 gen_arith(ctx
, op1
, rd
, rs
, rt
);
16834 case OPC_DIVU_G_2F
:
16835 case OPC_MULT_G_2F
:
16836 case OPC_MULTU_G_2F
:
16838 case OPC_MODU_G_2F
:
16839 check_insn(ctx
, INSN_LOONGSON2F
);
16840 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
16844 check_insn(ctx
, ISA_MIPS32
);
16845 gen_cl(ctx
, op1
, rd
, rs
);
16848 /* XXX: not clear which exception should be raised
16849 * when in debug mode...
16851 check_insn(ctx
, ISA_MIPS32
);
16852 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
16853 generate_exception(ctx
, EXCP_DBp
);
16855 generate_exception(ctx
, EXCP_DBp
);
16857 /* Treat as NOP. */
16859 #if defined(TARGET_MIPS64)
16862 check_insn(ctx
, ISA_MIPS64
);
16863 check_mips_64(ctx
);
16864 gen_cl(ctx
, op1
, rd
, rs
);
16866 case OPC_DMULT_G_2F
:
16867 case OPC_DMULTU_G_2F
:
16868 case OPC_DDIV_G_2F
:
16869 case OPC_DDIVU_G_2F
:
16870 case OPC_DMOD_G_2F
:
16871 case OPC_DMODU_G_2F
:
16872 check_insn(ctx
, INSN_LOONGSON2F
);
16873 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
16876 default: /* Invalid */
16877 MIPS_INVAL("special2_legacy");
16878 generate_exception(ctx
, EXCP_RI
);
16883 static void decode_opc_special3_r6(CPUMIPSState
*env
, DisasContext
*ctx
)
16885 int rs
, rt
, rd
, sa
;
16889 rs
= (ctx
->opcode
>> 21) & 0x1f;
16890 rt
= (ctx
->opcode
>> 16) & 0x1f;
16891 rd
= (ctx
->opcode
>> 11) & 0x1f;
16892 sa
= (ctx
->opcode
>> 6) & 0x1f;
16893 imm
= (int16_t)ctx
->opcode
>> 7;
16895 op1
= MASK_SPECIAL3(ctx
->opcode
);
16899 /* hint codes 24-31 are reserved and signal RI */
16900 generate_exception(ctx
, EXCP_RI
);
16902 /* Treat as NOP. */
16905 /* Treat as NOP. */
16908 gen_st_cond(ctx
, op1
, rt
, rs
, imm
);
16911 gen_ld(ctx
, op1
, rt
, rs
, imm
);
16916 /* Treat as NOP. */
16919 TCGv t0
= tcg_temp_new();
16920 gen_load_gpr(t0
, rt
);
16922 op2
= MASK_BSHFL(ctx
->opcode
);
16924 case OPC_ALIGN
... OPC_ALIGN_END
:
16927 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
16929 TCGv t1
= tcg_temp_new();
16930 TCGv_i64 t2
= tcg_temp_new_i64();
16931 gen_load_gpr(t1
, rs
);
16932 tcg_gen_concat_tl_i64(t2
, t1
, t0
);
16933 tcg_gen_shri_i64(t2
, t2
, 8 * (4 - sa
));
16934 #if defined(TARGET_MIPS64)
16935 tcg_gen_ext32s_i64(cpu_gpr
[rd
], t2
);
16937 tcg_gen_trunc_i64_i32(cpu_gpr
[rd
], t2
);
16939 tcg_temp_free_i64(t2
);
16944 gen_helper_bitswap(cpu_gpr
[rd
], t0
);
16950 #if defined(TARGET_MIPS64)
16952 gen_st_cond(ctx
, op1
, rt
, rs
, imm
);
16955 gen_ld(ctx
, op1
, rt
, rs
, imm
);
16958 check_mips_64(ctx
);
16961 /* Treat as NOP. */
16964 TCGv t0
= tcg_temp_new();
16965 gen_load_gpr(t0
, rt
);
16967 op2
= MASK_DBSHFL(ctx
->opcode
);
16969 case OPC_DALIGN
... OPC_DALIGN_END
:
16972 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
16974 TCGv t1
= tcg_temp_new();
16975 gen_load_gpr(t1
, rs
);
16976 tcg_gen_shli_tl(t0
, t0
, 8 * sa
);
16977 tcg_gen_shri_tl(t1
, t1
, 8 * (8 - sa
));
16978 tcg_gen_or_tl(cpu_gpr
[rd
], t1
, t0
);
16983 gen_helper_dbitswap(cpu_gpr
[rd
], t0
);
16990 default: /* Invalid */
16991 MIPS_INVAL("special3_r6");
16992 generate_exception(ctx
, EXCP_RI
);
16997 static void decode_opc_special3_legacy(CPUMIPSState
*env
, DisasContext
*ctx
)
17002 rs
= (ctx
->opcode
>> 21) & 0x1f;
17003 rt
= (ctx
->opcode
>> 16) & 0x1f;
17004 rd
= (ctx
->opcode
>> 11) & 0x1f;
17006 op1
= MASK_SPECIAL3(ctx
->opcode
);
17008 case OPC_DIV_G_2E
... OPC_DIVU_G_2E
:
17009 case OPC_MOD_G_2E
... OPC_MODU_G_2E
:
17010 case OPC_MULT_G_2E
... OPC_MULTU_G_2E
:
17011 /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
17012 * the same mask and op1. */
17013 if ((ctx
->insn_flags
& ASE_DSPR2
) && (op1
== OPC_MULT_G_2E
)) {
17014 op2
= MASK_ADDUH_QB(ctx
->opcode
);
17017 case OPC_ADDUH_R_QB
:
17019 case OPC_ADDQH_R_PH
:
17021 case OPC_ADDQH_R_W
:
17023 case OPC_SUBUH_R_QB
:
17025 case OPC_SUBQH_R_PH
:
17027 case OPC_SUBQH_R_W
:
17028 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17033 case OPC_MULQ_RS_W
:
17034 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
17037 MIPS_INVAL("MASK ADDUH.QB");
17038 generate_exception(ctx
, EXCP_RI
);
17041 } else if (ctx
->insn_flags
& INSN_LOONGSON2E
) {
17042 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
17044 generate_exception(ctx
, EXCP_RI
);
17048 op2
= MASK_LX(ctx
->opcode
);
17050 #if defined(TARGET_MIPS64)
17056 gen_mipsdsp_ld(ctx
, op2
, rd
, rs
, rt
);
17058 default: /* Invalid */
17059 MIPS_INVAL("MASK LX");
17060 generate_exception(ctx
, EXCP_RI
);
17064 case OPC_ABSQ_S_PH_DSP
:
17065 op2
= MASK_ABSQ_S_PH(ctx
->opcode
);
17067 case OPC_ABSQ_S_QB
:
17068 case OPC_ABSQ_S_PH
:
17070 case OPC_PRECEQ_W_PHL
:
17071 case OPC_PRECEQ_W_PHR
:
17072 case OPC_PRECEQU_PH_QBL
:
17073 case OPC_PRECEQU_PH_QBR
:
17074 case OPC_PRECEQU_PH_QBLA
:
17075 case OPC_PRECEQU_PH_QBRA
:
17076 case OPC_PRECEU_PH_QBL
:
17077 case OPC_PRECEU_PH_QBR
:
17078 case OPC_PRECEU_PH_QBLA
:
17079 case OPC_PRECEU_PH_QBRA
:
17080 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17087 gen_mipsdsp_bitinsn(ctx
, op1
, op2
, rd
, rt
);
17090 MIPS_INVAL("MASK ABSQ_S.PH");
17091 generate_exception(ctx
, EXCP_RI
);
17095 case OPC_ADDU_QB_DSP
:
17096 op2
= MASK_ADDU_QB(ctx
->opcode
);
17099 case OPC_ADDQ_S_PH
:
17102 case OPC_ADDU_S_QB
:
17104 case OPC_ADDU_S_PH
:
17106 case OPC_SUBQ_S_PH
:
17109 case OPC_SUBU_S_QB
:
17111 case OPC_SUBU_S_PH
:
17115 case OPC_RADDU_W_QB
:
17116 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17118 case OPC_MULEU_S_PH_QBL
:
17119 case OPC_MULEU_S_PH_QBR
:
17120 case OPC_MULQ_RS_PH
:
17121 case OPC_MULEQ_S_W_PHL
:
17122 case OPC_MULEQ_S_W_PHR
:
17123 case OPC_MULQ_S_PH
:
17124 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
17126 default: /* Invalid */
17127 MIPS_INVAL("MASK ADDU.QB");
17128 generate_exception(ctx
, EXCP_RI
);
17133 case OPC_CMPU_EQ_QB_DSP
:
17134 op2
= MASK_CMPU_EQ_QB(ctx
->opcode
);
17136 case OPC_PRECR_SRA_PH_W
:
17137 case OPC_PRECR_SRA_R_PH_W
:
17138 gen_mipsdsp_arith(ctx
, op1
, op2
, rt
, rs
, rd
);
17140 case OPC_PRECR_QB_PH
:
17141 case OPC_PRECRQ_QB_PH
:
17142 case OPC_PRECRQ_PH_W
:
17143 case OPC_PRECRQ_RS_PH_W
:
17144 case OPC_PRECRQU_S_QB_PH
:
17145 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17147 case OPC_CMPU_EQ_QB
:
17148 case OPC_CMPU_LT_QB
:
17149 case OPC_CMPU_LE_QB
:
17150 case OPC_CMP_EQ_PH
:
17151 case OPC_CMP_LT_PH
:
17152 case OPC_CMP_LE_PH
:
17153 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17155 case OPC_CMPGU_EQ_QB
:
17156 case OPC_CMPGU_LT_QB
:
17157 case OPC_CMPGU_LE_QB
:
17158 case OPC_CMPGDU_EQ_QB
:
17159 case OPC_CMPGDU_LT_QB
:
17160 case OPC_CMPGDU_LE_QB
:
17163 case OPC_PACKRL_PH
:
17164 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
17166 default: /* Invalid */
17167 MIPS_INVAL("MASK CMPU.EQ.QB");
17168 generate_exception(ctx
, EXCP_RI
);
17172 case OPC_SHLL_QB_DSP
:
17173 gen_mipsdsp_shift(ctx
, op1
, rd
, rs
, rt
);
17175 case OPC_DPA_W_PH_DSP
:
17176 op2
= MASK_DPA_W_PH(ctx
->opcode
);
17178 case OPC_DPAU_H_QBL
:
17179 case OPC_DPAU_H_QBR
:
17180 case OPC_DPSU_H_QBL
:
17181 case OPC_DPSU_H_QBR
:
17183 case OPC_DPAX_W_PH
:
17184 case OPC_DPAQ_S_W_PH
:
17185 case OPC_DPAQX_S_W_PH
:
17186 case OPC_DPAQX_SA_W_PH
:
17188 case OPC_DPSX_W_PH
:
17189 case OPC_DPSQ_S_W_PH
:
17190 case OPC_DPSQX_S_W_PH
:
17191 case OPC_DPSQX_SA_W_PH
:
17192 case OPC_MULSAQ_S_W_PH
:
17193 case OPC_DPAQ_SA_L_W
:
17194 case OPC_DPSQ_SA_L_W
:
17195 case OPC_MAQ_S_W_PHL
:
17196 case OPC_MAQ_S_W_PHR
:
17197 case OPC_MAQ_SA_W_PHL
:
17198 case OPC_MAQ_SA_W_PHR
:
17199 case OPC_MULSA_W_PH
:
17200 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17202 default: /* Invalid */
17203 MIPS_INVAL("MASK DPAW.PH");
17204 generate_exception(ctx
, EXCP_RI
);
17209 op2
= MASK_INSV(ctx
->opcode
);
17221 t0
= tcg_temp_new();
17222 t1
= tcg_temp_new();
17224 gen_load_gpr(t0
, rt
);
17225 gen_load_gpr(t1
, rs
);
17227 gen_helper_insv(cpu_gpr
[rt
], cpu_env
, t1
, t0
);
17233 default: /* Invalid */
17234 MIPS_INVAL("MASK INSV");
17235 generate_exception(ctx
, EXCP_RI
);
17239 case OPC_APPEND_DSP
:
17240 gen_mipsdsp_append(env
, ctx
, op1
, rt
, rs
, rd
);
17242 case OPC_EXTR_W_DSP
:
17243 op2
= MASK_EXTR_W(ctx
->opcode
);
17247 case OPC_EXTR_RS_W
:
17249 case OPC_EXTRV_S_H
:
17251 case OPC_EXTRV_R_W
:
17252 case OPC_EXTRV_RS_W
:
17257 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rt
, rs
, rd
, 1);
17260 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
17266 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17268 default: /* Invalid */
17269 MIPS_INVAL("MASK EXTR.W");
17270 generate_exception(ctx
, EXCP_RI
);
17274 #if defined(TARGET_MIPS64)
17275 case OPC_DDIV_G_2E
... OPC_DDIVU_G_2E
:
17276 case OPC_DMULT_G_2E
... OPC_DMULTU_G_2E
:
17277 case OPC_DMOD_G_2E
... OPC_DMODU_G_2E
:
17278 check_insn(ctx
, INSN_LOONGSON2E
);
17279 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
17281 case OPC_ABSQ_S_QH_DSP
:
17282 op2
= MASK_ABSQ_S_QH(ctx
->opcode
);
17284 case OPC_PRECEQ_L_PWL
:
17285 case OPC_PRECEQ_L_PWR
:
17286 case OPC_PRECEQ_PW_QHL
:
17287 case OPC_PRECEQ_PW_QHR
:
17288 case OPC_PRECEQ_PW_QHLA
:
17289 case OPC_PRECEQ_PW_QHRA
:
17290 case OPC_PRECEQU_QH_OBL
:
17291 case OPC_PRECEQU_QH_OBR
:
17292 case OPC_PRECEQU_QH_OBLA
:
17293 case OPC_PRECEQU_QH_OBRA
:
17294 case OPC_PRECEU_QH_OBL
:
17295 case OPC_PRECEU_QH_OBR
:
17296 case OPC_PRECEU_QH_OBLA
:
17297 case OPC_PRECEU_QH_OBRA
:
17298 case OPC_ABSQ_S_OB
:
17299 case OPC_ABSQ_S_PW
:
17300 case OPC_ABSQ_S_QH
:
17301 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17309 gen_mipsdsp_bitinsn(ctx
, op1
, op2
, rd
, rt
);
17311 default: /* Invalid */
17312 MIPS_INVAL("MASK ABSQ_S.QH");
17313 generate_exception(ctx
, EXCP_RI
);
17317 case OPC_ADDU_OB_DSP
:
17318 op2
= MASK_ADDU_OB(ctx
->opcode
);
17320 case OPC_RADDU_L_OB
:
17322 case OPC_SUBQ_S_PW
:
17324 case OPC_SUBQ_S_QH
:
17326 case OPC_SUBU_S_OB
:
17328 case OPC_SUBU_S_QH
:
17330 case OPC_SUBUH_R_OB
:
17332 case OPC_ADDQ_S_PW
:
17334 case OPC_ADDQ_S_QH
:
17336 case OPC_ADDU_S_OB
:
17338 case OPC_ADDU_S_QH
:
17340 case OPC_ADDUH_R_OB
:
17341 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17343 case OPC_MULEQ_S_PW_QHL
:
17344 case OPC_MULEQ_S_PW_QHR
:
17345 case OPC_MULEU_S_QH_OBL
:
17346 case OPC_MULEU_S_QH_OBR
:
17347 case OPC_MULQ_RS_QH
:
17348 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
17350 default: /* Invalid */
17351 MIPS_INVAL("MASK ADDU.OB");
17352 generate_exception(ctx
, EXCP_RI
);
17356 case OPC_CMPU_EQ_OB_DSP
:
17357 op2
= MASK_CMPU_EQ_OB(ctx
->opcode
);
17359 case OPC_PRECR_SRA_QH_PW
:
17360 case OPC_PRECR_SRA_R_QH_PW
:
17361 /* Return value is rt. */
17362 gen_mipsdsp_arith(ctx
, op1
, op2
, rt
, rs
, rd
);
17364 case OPC_PRECR_OB_QH
:
17365 case OPC_PRECRQ_OB_QH
:
17366 case OPC_PRECRQ_PW_L
:
17367 case OPC_PRECRQ_QH_PW
:
17368 case OPC_PRECRQ_RS_QH_PW
:
17369 case OPC_PRECRQU_S_OB_QH
:
17370 gen_mipsdsp_arith(ctx
, op1
, op2
, rd
, rs
, rt
);
17372 case OPC_CMPU_EQ_OB
:
17373 case OPC_CMPU_LT_OB
:
17374 case OPC_CMPU_LE_OB
:
17375 case OPC_CMP_EQ_QH
:
17376 case OPC_CMP_LT_QH
:
17377 case OPC_CMP_LE_QH
:
17378 case OPC_CMP_EQ_PW
:
17379 case OPC_CMP_LT_PW
:
17380 case OPC_CMP_LE_PW
:
17381 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17383 case OPC_CMPGDU_EQ_OB
:
17384 case OPC_CMPGDU_LT_OB
:
17385 case OPC_CMPGDU_LE_OB
:
17386 case OPC_CMPGU_EQ_OB
:
17387 case OPC_CMPGU_LT_OB
:
17388 case OPC_CMPGU_LE_OB
:
17389 case OPC_PACKRL_PW
:
17393 gen_mipsdsp_add_cmp_pick(ctx
, op1
, op2
, rd
, rs
, rt
, 1);
17395 default: /* Invalid */
17396 MIPS_INVAL("MASK CMPU_EQ.OB");
17397 generate_exception(ctx
, EXCP_RI
);
17401 case OPC_DAPPEND_DSP
:
17402 gen_mipsdsp_append(env
, ctx
, op1
, rt
, rs
, rd
);
17404 case OPC_DEXTR_W_DSP
:
17405 op2
= MASK_DEXTR_W(ctx
->opcode
);
17412 case OPC_DEXTR_R_L
:
17413 case OPC_DEXTR_RS_L
:
17415 case OPC_DEXTR_R_W
:
17416 case OPC_DEXTR_RS_W
:
17417 case OPC_DEXTR_S_H
:
17419 case OPC_DEXTRV_R_L
:
17420 case OPC_DEXTRV_RS_L
:
17421 case OPC_DEXTRV_S_H
:
17423 case OPC_DEXTRV_R_W
:
17424 case OPC_DEXTRV_RS_W
:
17425 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rt
, rs
, rd
, 1);
17430 gen_mipsdsp_accinsn(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17432 default: /* Invalid */
17433 MIPS_INVAL("MASK EXTR.W");
17434 generate_exception(ctx
, EXCP_RI
);
17438 case OPC_DPAQ_W_QH_DSP
:
17439 op2
= MASK_DPAQ_W_QH(ctx
->opcode
);
17441 case OPC_DPAU_H_OBL
:
17442 case OPC_DPAU_H_OBR
:
17443 case OPC_DPSU_H_OBL
:
17444 case OPC_DPSU_H_OBR
:
17446 case OPC_DPAQ_S_W_QH
:
17448 case OPC_DPSQ_S_W_QH
:
17449 case OPC_MULSAQ_S_W_QH
:
17450 case OPC_DPAQ_SA_L_PW
:
17451 case OPC_DPSQ_SA_L_PW
:
17452 case OPC_MULSAQ_S_L_PW
:
17453 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17455 case OPC_MAQ_S_W_QHLL
:
17456 case OPC_MAQ_S_W_QHLR
:
17457 case OPC_MAQ_S_W_QHRL
:
17458 case OPC_MAQ_S_W_QHRR
:
17459 case OPC_MAQ_SA_W_QHLL
:
17460 case OPC_MAQ_SA_W_QHLR
:
17461 case OPC_MAQ_SA_W_QHRL
:
17462 case OPC_MAQ_SA_W_QHRR
:
17463 case OPC_MAQ_S_L_PWL
:
17464 case OPC_MAQ_S_L_PWR
:
17469 gen_mipsdsp_multiply(ctx
, op1
, op2
, rd
, rs
, rt
, 0);
17471 default: /* Invalid */
17472 MIPS_INVAL("MASK DPAQ.W.QH");
17473 generate_exception(ctx
, EXCP_RI
);
17477 case OPC_DINSV_DSP
:
17478 op2
= MASK_INSV(ctx
->opcode
);
17490 t0
= tcg_temp_new();
17491 t1
= tcg_temp_new();
17493 gen_load_gpr(t0
, rt
);
17494 gen_load_gpr(t1
, rs
);
17496 gen_helper_dinsv(cpu_gpr
[rt
], cpu_env
, t1
, t0
);
17502 default: /* Invalid */
17503 MIPS_INVAL("MASK DINSV");
17504 generate_exception(ctx
, EXCP_RI
);
17508 case OPC_SHLL_OB_DSP
:
17509 gen_mipsdsp_shift(ctx
, op1
, rd
, rs
, rt
);
17512 default: /* Invalid */
17513 MIPS_INVAL("special3_legacy");
17514 generate_exception(ctx
, EXCP_RI
);
17519 static void decode_opc_special3(CPUMIPSState
*env
, DisasContext
*ctx
)
17521 int rs
, rt
, rd
, sa
;
17524 rs
= (ctx
->opcode
>> 21) & 0x1f;
17525 rt
= (ctx
->opcode
>> 16) & 0x1f;
17526 rd
= (ctx
->opcode
>> 11) & 0x1f;
17527 sa
= (ctx
->opcode
>> 6) & 0x1f;
17529 op1
= MASK_SPECIAL3(ctx
->opcode
);
17533 check_insn(ctx
, ISA_MIPS32R2
);
17534 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
17537 op2
= MASK_BSHFL(ctx
->opcode
);
17539 case OPC_ALIGN
... OPC_ALIGN_END
:
17541 check_insn(ctx
, ISA_MIPS32R6
);
17542 decode_opc_special3_r6(env
, ctx
);
17545 check_insn(ctx
, ISA_MIPS32R2
);
17546 gen_bshfl(ctx
, op2
, rt
, rd
);
17550 #if defined(TARGET_MIPS64)
17551 case OPC_DEXTM
... OPC_DEXT
:
17552 case OPC_DINSM
... OPC_DINS
:
17553 check_insn(ctx
, ISA_MIPS64R2
);
17554 check_mips_64(ctx
);
17555 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
17558 op2
= MASK_DBSHFL(ctx
->opcode
);
17560 case OPC_DALIGN
... OPC_DALIGN_END
:
17562 check_insn(ctx
, ISA_MIPS32R6
);
17563 decode_opc_special3_r6(env
, ctx
);
17566 check_insn(ctx
, ISA_MIPS64R2
);
17567 check_mips_64(ctx
);
17568 op2
= MASK_DBSHFL(ctx
->opcode
);
17569 gen_bshfl(ctx
, op2
, rt
, rd
);
17575 gen_rdhwr(ctx
, rt
, rd
);
17578 check_insn(ctx
, ASE_MT
);
17580 TCGv t0
= tcg_temp_new();
17581 TCGv t1
= tcg_temp_new();
17583 gen_load_gpr(t0
, rt
);
17584 gen_load_gpr(t1
, rs
);
17585 gen_helper_fork(t0
, t1
);
17591 check_insn(ctx
, ASE_MT
);
17593 TCGv t0
= tcg_temp_new();
17595 save_cpu_state(ctx
, 1);
17596 gen_load_gpr(t0
, rs
);
17597 gen_helper_yield(t0
, cpu_env
, t0
);
17598 gen_store_gpr(t0
, rd
);
17603 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
17604 decode_opc_special3_r6(env
, ctx
);
17606 decode_opc_special3_legacy(env
, ctx
);
17611 /* MIPS SIMD Architecture (MSA) */
17612 static inline int check_msa_access(DisasContext
*ctx
)
17614 if (unlikely((ctx
->hflags
& MIPS_HFLAG_FPU
) &&
17615 !(ctx
->hflags
& MIPS_HFLAG_F64
))) {
17616 generate_exception(ctx
, EXCP_RI
);
17620 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_MSA
))) {
17621 if (ctx
->insn_flags
& ASE_MSA
) {
17622 generate_exception(ctx
, EXCP_MSADIS
);
17625 generate_exception(ctx
, EXCP_RI
);
17632 static void gen_check_zero_element(TCGv tresult
, uint8_t df
, uint8_t wt
)
17634 /* generates tcg ops to check if any element is 0 */
17635 /* Note this function only works with MSA_WRLEN = 128 */
17636 uint64_t eval_zero_or_big
= 0;
17637 uint64_t eval_big
= 0;
17638 TCGv_i64 t0
= tcg_temp_new_i64();
17639 TCGv_i64 t1
= tcg_temp_new_i64();
17642 eval_zero_or_big
= 0x0101010101010101ULL
;
17643 eval_big
= 0x8080808080808080ULL
;
17646 eval_zero_or_big
= 0x0001000100010001ULL
;
17647 eval_big
= 0x8000800080008000ULL
;
17650 eval_zero_or_big
= 0x0000000100000001ULL
;
17651 eval_big
= 0x8000000080000000ULL
;
17654 eval_zero_or_big
= 0x0000000000000001ULL
;
17655 eval_big
= 0x8000000000000000ULL
;
17658 tcg_gen_subi_i64(t0
, msa_wr_d
[wt
<<1], eval_zero_or_big
);
17659 tcg_gen_andc_i64(t0
, t0
, msa_wr_d
[wt
<<1]);
17660 tcg_gen_andi_i64(t0
, t0
, eval_big
);
17661 tcg_gen_subi_i64(t1
, msa_wr_d
[(wt
<<1)+1], eval_zero_or_big
);
17662 tcg_gen_andc_i64(t1
, t1
, msa_wr_d
[(wt
<<1)+1]);
17663 tcg_gen_andi_i64(t1
, t1
, eval_big
);
17664 tcg_gen_or_i64(t0
, t0
, t1
);
17665 /* if all bits are zero then all elements are not zero */
17666 /* if some bit is non-zero then some element is zero */
17667 tcg_gen_setcondi_i64(TCG_COND_NE
, t0
, t0
, 0);
17668 tcg_gen_trunc_i64_tl(tresult
, t0
);
17669 tcg_temp_free_i64(t0
);
17670 tcg_temp_free_i64(t1
);
17673 static void gen_msa_branch(CPUMIPSState
*env
, DisasContext
*ctx
, uint32_t op1
)
17675 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
17676 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
17677 int64_t s16
= (int16_t)ctx
->opcode
;
17679 check_msa_access(ctx
);
17681 if (ctx
->insn_flags
& ISA_MIPS32R6
&& ctx
->hflags
& MIPS_HFLAG_BMASK
) {
17682 MIPS_DEBUG("CTI in delay / forbidden slot");
17683 generate_exception(ctx
, EXCP_RI
);
17690 TCGv_i64 t0
= tcg_temp_new_i64();
17691 tcg_gen_or_i64(t0
, msa_wr_d
[wt
<<1], msa_wr_d
[(wt
<<1)+1]);
17692 tcg_gen_setcondi_i64((op1
== OPC_BZ_V
) ?
17693 TCG_COND_EQ
: TCG_COND_NE
, t0
, t0
, 0);
17694 tcg_gen_trunc_i64_tl(bcond
, t0
);
17695 tcg_temp_free_i64(t0
);
17702 gen_check_zero_element(bcond
, df
, wt
);
17708 gen_check_zero_element(bcond
, df
, wt
);
17709 tcg_gen_setcondi_tl(TCG_COND_EQ
, bcond
, bcond
, 0);
17713 ctx
->btarget
= ctx
->pc
+ (s16
<< 2) + 4;
17715 ctx
->hflags
|= MIPS_HFLAG_BC
;
17716 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
17719 static void gen_msa_i8(CPUMIPSState
*env
, DisasContext
*ctx
)
17721 #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
17722 uint8_t i8
= (ctx
->opcode
>> 16) & 0xff;
17723 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
17724 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
17726 TCGv_i32 twd
= tcg_const_i32(wd
);
17727 TCGv_i32 tws
= tcg_const_i32(ws
);
17728 TCGv_i32 ti8
= tcg_const_i32(i8
);
17730 switch (MASK_MSA_I8(ctx
->opcode
)) {
17732 gen_helper_msa_andi_b(cpu_env
, twd
, tws
, ti8
);
17735 gen_helper_msa_ori_b(cpu_env
, twd
, tws
, ti8
);
17738 gen_helper_msa_nori_b(cpu_env
, twd
, tws
, ti8
);
17741 gen_helper_msa_xori_b(cpu_env
, twd
, tws
, ti8
);
17744 gen_helper_msa_bmnzi_b(cpu_env
, twd
, tws
, ti8
);
17747 gen_helper_msa_bmzi_b(cpu_env
, twd
, tws
, ti8
);
17750 gen_helper_msa_bseli_b(cpu_env
, twd
, tws
, ti8
);
17756 uint8_t df
= (ctx
->opcode
>> 24) & 0x3;
17757 if (df
== DF_DOUBLE
) {
17758 generate_exception(ctx
, EXCP_RI
);
17760 TCGv_i32 tdf
= tcg_const_i32(df
);
17761 gen_helper_msa_shf_df(cpu_env
, tdf
, twd
, tws
, ti8
);
17762 tcg_temp_free_i32(tdf
);
17767 MIPS_INVAL("MSA instruction");
17768 generate_exception(ctx
, EXCP_RI
);
17772 tcg_temp_free_i32(twd
);
17773 tcg_temp_free_i32(tws
);
17774 tcg_temp_free_i32(ti8
);
17777 static void gen_msa_i5(CPUMIPSState
*env
, DisasContext
*ctx
)
17779 #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
17780 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
17781 int8_t s5
= (int8_t) sextract32(ctx
->opcode
, 16, 5);
17782 uint8_t u5
= (ctx
->opcode
>> 16) & 0x1f;
17783 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
17784 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
17786 TCGv_i32 tdf
= tcg_const_i32(df
);
17787 TCGv_i32 twd
= tcg_const_i32(wd
);
17788 TCGv_i32 tws
= tcg_const_i32(ws
);
17789 TCGv_i32 timm
= tcg_temp_new_i32();
17790 tcg_gen_movi_i32(timm
, u5
);
17792 switch (MASK_MSA_I5(ctx
->opcode
)) {
17794 gen_helper_msa_addvi_df(cpu_env
, tdf
, twd
, tws
, timm
);
17797 gen_helper_msa_subvi_df(cpu_env
, tdf
, twd
, tws
, timm
);
17799 case OPC_MAXI_S_df
:
17800 tcg_gen_movi_i32(timm
, s5
);
17801 gen_helper_msa_maxi_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
17803 case OPC_MAXI_U_df
:
17804 gen_helper_msa_maxi_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
17806 case OPC_MINI_S_df
:
17807 tcg_gen_movi_i32(timm
, s5
);
17808 gen_helper_msa_mini_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
17810 case OPC_MINI_U_df
:
17811 gen_helper_msa_mini_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
17814 tcg_gen_movi_i32(timm
, s5
);
17815 gen_helper_msa_ceqi_df(cpu_env
, tdf
, twd
, tws
, timm
);
17817 case OPC_CLTI_S_df
:
17818 tcg_gen_movi_i32(timm
, s5
);
17819 gen_helper_msa_clti_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
17821 case OPC_CLTI_U_df
:
17822 gen_helper_msa_clti_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
17824 case OPC_CLEI_S_df
:
17825 tcg_gen_movi_i32(timm
, s5
);
17826 gen_helper_msa_clei_s_df(cpu_env
, tdf
, twd
, tws
, timm
);
17828 case OPC_CLEI_U_df
:
17829 gen_helper_msa_clei_u_df(cpu_env
, tdf
, twd
, tws
, timm
);
17833 int32_t s10
= sextract32(ctx
->opcode
, 11, 10);
17834 tcg_gen_movi_i32(timm
, s10
);
17835 gen_helper_msa_ldi_df(cpu_env
, tdf
, twd
, timm
);
17839 MIPS_INVAL("MSA instruction");
17840 generate_exception(ctx
, EXCP_RI
);
17844 tcg_temp_free_i32(tdf
);
17845 tcg_temp_free_i32(twd
);
17846 tcg_temp_free_i32(tws
);
17847 tcg_temp_free_i32(timm
);
17850 static void gen_msa_bit(CPUMIPSState
*env
, DisasContext
*ctx
)
17852 #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
17853 uint8_t dfm
= (ctx
->opcode
>> 16) & 0x7f;
17854 uint32_t df
= 0, m
= 0;
17855 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
17856 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
17863 if ((dfm
& 0x40) == 0x00) {
17866 } else if ((dfm
& 0x60) == 0x40) {
17869 } else if ((dfm
& 0x70) == 0x60) {
17872 } else if ((dfm
& 0x78) == 0x70) {
17876 generate_exception(ctx
, EXCP_RI
);
17880 tdf
= tcg_const_i32(df
);
17881 tm
= tcg_const_i32(m
);
17882 twd
= tcg_const_i32(wd
);
17883 tws
= tcg_const_i32(ws
);
17885 switch (MASK_MSA_BIT(ctx
->opcode
)) {
17887 gen_helper_msa_slli_df(cpu_env
, tdf
, twd
, tws
, tm
);
17890 gen_helper_msa_srai_df(cpu_env
, tdf
, twd
, tws
, tm
);
17893 gen_helper_msa_srli_df(cpu_env
, tdf
, twd
, tws
, tm
);
17896 gen_helper_msa_bclri_df(cpu_env
, tdf
, twd
, tws
, tm
);
17899 gen_helper_msa_bseti_df(cpu_env
, tdf
, twd
, tws
, tm
);
17902 gen_helper_msa_bnegi_df(cpu_env
, tdf
, twd
, tws
, tm
);
17904 case OPC_BINSLI_df
:
17905 gen_helper_msa_binsli_df(cpu_env
, tdf
, twd
, tws
, tm
);
17907 case OPC_BINSRI_df
:
17908 gen_helper_msa_binsri_df(cpu_env
, tdf
, twd
, tws
, tm
);
17911 gen_helper_msa_sat_s_df(cpu_env
, tdf
, twd
, tws
, tm
);
17914 gen_helper_msa_sat_u_df(cpu_env
, tdf
, twd
, tws
, tm
);
17917 gen_helper_msa_srari_df(cpu_env
, tdf
, twd
, tws
, tm
);
17920 gen_helper_msa_srlri_df(cpu_env
, tdf
, twd
, tws
, tm
);
17923 MIPS_INVAL("MSA instruction");
17924 generate_exception(ctx
, EXCP_RI
);
17928 tcg_temp_free_i32(tdf
);
17929 tcg_temp_free_i32(tm
);
17930 tcg_temp_free_i32(twd
);
17931 tcg_temp_free_i32(tws
);
17934 static void gen_msa_3r(CPUMIPSState
*env
, DisasContext
*ctx
)
17936 #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
17937 uint8_t df
= (ctx
->opcode
>> 21) & 0x3;
17938 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
17939 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
17940 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
17942 TCGv_i32 tdf
= tcg_const_i32(df
);
17943 TCGv_i32 twd
= tcg_const_i32(wd
);
17944 TCGv_i32 tws
= tcg_const_i32(ws
);
17945 TCGv_i32 twt
= tcg_const_i32(wt
);
17947 switch (MASK_MSA_3R(ctx
->opcode
)) {
17949 gen_helper_msa_sll_df(cpu_env
, tdf
, twd
, tws
, twt
);
17952 gen_helper_msa_addv_df(cpu_env
, tdf
, twd
, tws
, twt
);
17955 gen_helper_msa_ceq_df(cpu_env
, tdf
, twd
, tws
, twt
);
17958 gen_helper_msa_add_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
17960 case OPC_SUBS_S_df
:
17961 gen_helper_msa_subs_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
17964 gen_helper_msa_mulv_df(cpu_env
, tdf
, twd
, tws
, twt
);
17967 gen_helper_msa_sld_df(cpu_env
, tdf
, twd
, tws
, twt
);
17970 gen_helper_msa_vshf_df(cpu_env
, tdf
, twd
, tws
, twt
);
17973 gen_helper_msa_sra_df(cpu_env
, tdf
, twd
, tws
, twt
);
17976 gen_helper_msa_subv_df(cpu_env
, tdf
, twd
, tws
, twt
);
17978 case OPC_ADDS_A_df
:
17979 gen_helper_msa_adds_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
17981 case OPC_SUBS_U_df
:
17982 gen_helper_msa_subs_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
17985 gen_helper_msa_maddv_df(cpu_env
, tdf
, twd
, tws
, twt
);
17988 gen_helper_msa_splat_df(cpu_env
, tdf
, twd
, tws
, twt
);
17991 gen_helper_msa_srar_df(cpu_env
, tdf
, twd
, tws
, twt
);
17994 gen_helper_msa_srl_df(cpu_env
, tdf
, twd
, tws
, twt
);
17997 gen_helper_msa_max_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18000 gen_helper_msa_clt_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18002 case OPC_ADDS_S_df
:
18003 gen_helper_msa_adds_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18005 case OPC_SUBSUS_U_df
:
18006 gen_helper_msa_subsus_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18009 gen_helper_msa_msubv_df(cpu_env
, tdf
, twd
, tws
, twt
);
18012 gen_helper_msa_pckev_df(cpu_env
, tdf
, twd
, tws
, twt
);
18015 gen_helper_msa_srlr_df(cpu_env
, tdf
, twd
, tws
, twt
);
18018 gen_helper_msa_bclr_df(cpu_env
, tdf
, twd
, tws
, twt
);
18021 gen_helper_msa_max_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18024 gen_helper_msa_clt_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18026 case OPC_ADDS_U_df
:
18027 gen_helper_msa_adds_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18029 case OPC_SUBSUU_S_df
:
18030 gen_helper_msa_subsuu_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18033 gen_helper_msa_pckod_df(cpu_env
, tdf
, twd
, tws
, twt
);
18036 gen_helper_msa_bset_df(cpu_env
, tdf
, twd
, tws
, twt
);
18039 gen_helper_msa_min_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18042 gen_helper_msa_cle_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18045 gen_helper_msa_ave_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18047 case OPC_ASUB_S_df
:
18048 gen_helper_msa_asub_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18051 gen_helper_msa_div_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18054 gen_helper_msa_ilvl_df(cpu_env
, tdf
, twd
, tws
, twt
);
18057 gen_helper_msa_bneg_df(cpu_env
, tdf
, twd
, tws
, twt
);
18060 gen_helper_msa_min_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18063 gen_helper_msa_cle_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18066 gen_helper_msa_ave_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18068 case OPC_ASUB_U_df
:
18069 gen_helper_msa_asub_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18072 gen_helper_msa_div_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18075 gen_helper_msa_ilvr_df(cpu_env
, tdf
, twd
, tws
, twt
);
18078 gen_helper_msa_binsl_df(cpu_env
, tdf
, twd
, tws
, twt
);
18081 gen_helper_msa_max_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
18083 case OPC_AVER_S_df
:
18084 gen_helper_msa_aver_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18087 gen_helper_msa_mod_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18090 gen_helper_msa_ilvev_df(cpu_env
, tdf
, twd
, tws
, twt
);
18093 gen_helper_msa_binsr_df(cpu_env
, tdf
, twd
, tws
, twt
);
18096 gen_helper_msa_min_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
18098 case OPC_AVER_U_df
:
18099 gen_helper_msa_aver_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18102 gen_helper_msa_mod_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18105 gen_helper_msa_ilvod_df(cpu_env
, tdf
, twd
, tws
, twt
);
18108 case OPC_DOTP_S_df
:
18109 case OPC_DOTP_U_df
:
18110 case OPC_DPADD_S_df
:
18111 case OPC_DPADD_U_df
:
18112 case OPC_DPSUB_S_df
:
18113 case OPC_HADD_S_df
:
18114 case OPC_DPSUB_U_df
:
18115 case OPC_HADD_U_df
:
18116 case OPC_HSUB_S_df
:
18117 case OPC_HSUB_U_df
:
18118 if (df
== DF_BYTE
) {
18119 generate_exception(ctx
, EXCP_RI
);
18121 switch (MASK_MSA_3R(ctx
->opcode
)) {
18122 case OPC_DOTP_S_df
:
18123 gen_helper_msa_dotp_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18125 case OPC_DOTP_U_df
:
18126 gen_helper_msa_dotp_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18128 case OPC_DPADD_S_df
:
18129 gen_helper_msa_dpadd_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18131 case OPC_DPADD_U_df
:
18132 gen_helper_msa_dpadd_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18134 case OPC_DPSUB_S_df
:
18135 gen_helper_msa_dpsub_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18137 case OPC_HADD_S_df
:
18138 gen_helper_msa_hadd_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18140 case OPC_DPSUB_U_df
:
18141 gen_helper_msa_dpsub_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18143 case OPC_HADD_U_df
:
18144 gen_helper_msa_hadd_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18146 case OPC_HSUB_S_df
:
18147 gen_helper_msa_hsub_s_df(cpu_env
, tdf
, twd
, tws
, twt
);
18149 case OPC_HSUB_U_df
:
18150 gen_helper_msa_hsub_u_df(cpu_env
, tdf
, twd
, tws
, twt
);
18155 MIPS_INVAL("MSA instruction");
18156 generate_exception(ctx
, EXCP_RI
);
18159 tcg_temp_free_i32(twd
);
18160 tcg_temp_free_i32(tws
);
18161 tcg_temp_free_i32(twt
);
18162 tcg_temp_free_i32(tdf
);
18165 static void gen_msa_elm_3e(CPUMIPSState
*env
, DisasContext
*ctx
)
18167 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
18168 uint8_t source
= (ctx
->opcode
>> 11) & 0x1f;
18169 uint8_t dest
= (ctx
->opcode
>> 6) & 0x1f;
18170 TCGv telm
= tcg_temp_new();
18171 TCGv_i32 tsr
= tcg_const_i32(source
);
18172 TCGv_i32 tdt
= tcg_const_i32(dest
);
18174 switch (MASK_MSA_ELM_DF3E(ctx
->opcode
)) {
18176 gen_load_gpr(telm
, source
);
18177 gen_helper_msa_ctcmsa(cpu_env
, telm
, tdt
);
18180 gen_helper_msa_cfcmsa(telm
, cpu_env
, tsr
);
18181 gen_store_gpr(telm
, dest
);
18184 gen_helper_msa_move_v(cpu_env
, tdt
, tsr
);
18187 MIPS_INVAL("MSA instruction");
18188 generate_exception(ctx
, EXCP_RI
);
18192 tcg_temp_free(telm
);
18193 tcg_temp_free_i32(tdt
);
18194 tcg_temp_free_i32(tsr
);
18197 static void gen_msa_elm_df(CPUMIPSState
*env
, DisasContext
*ctx
, uint32_t df
,
18200 #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
18201 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
18202 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
18204 TCGv_i32 tws
= tcg_const_i32(ws
);
18205 TCGv_i32 twd
= tcg_const_i32(wd
);
18206 TCGv_i32 tn
= tcg_const_i32(n
);
18207 TCGv_i32 tdf
= tcg_const_i32(df
);
18209 switch (MASK_MSA_ELM(ctx
->opcode
)) {
18211 gen_helper_msa_sldi_df(cpu_env
, tdf
, twd
, tws
, tn
);
18213 case OPC_SPLATI_df
:
18214 gen_helper_msa_splati_df(cpu_env
, tdf
, twd
, tws
, tn
);
18217 gen_helper_msa_insve_df(cpu_env
, tdf
, twd
, tws
, tn
);
18219 case OPC_COPY_S_df
:
18220 case OPC_COPY_U_df
:
18221 case OPC_INSERT_df
:
18222 #if !defined(TARGET_MIPS64)
18223 /* Double format valid only for MIPS64 */
18224 if (df
== DF_DOUBLE
) {
18225 generate_exception(ctx
, EXCP_RI
);
18229 switch (MASK_MSA_ELM(ctx
->opcode
)) {
18230 case OPC_COPY_S_df
:
18231 gen_helper_msa_copy_s_df(cpu_env
, tdf
, twd
, tws
, tn
);
18233 case OPC_COPY_U_df
:
18234 gen_helper_msa_copy_u_df(cpu_env
, tdf
, twd
, tws
, tn
);
18236 case OPC_INSERT_df
:
18237 gen_helper_msa_insert_df(cpu_env
, tdf
, twd
, tws
, tn
);
18242 MIPS_INVAL("MSA instruction");
18243 generate_exception(ctx
, EXCP_RI
);
18245 tcg_temp_free_i32(twd
);
18246 tcg_temp_free_i32(tws
);
18247 tcg_temp_free_i32(tn
);
18248 tcg_temp_free_i32(tdf
);
18251 static void gen_msa_elm(CPUMIPSState
*env
, DisasContext
*ctx
)
18253 uint8_t dfn
= (ctx
->opcode
>> 16) & 0x3f;
18254 uint32_t df
= 0, n
= 0;
18256 if ((dfn
& 0x30) == 0x00) {
18259 } else if ((dfn
& 0x38) == 0x20) {
18262 } else if ((dfn
& 0x3c) == 0x30) {
18265 } else if ((dfn
& 0x3e) == 0x38) {
18268 } else if (dfn
== 0x3E) {
18269 /* CTCMSA, CFCMSA, MOVE.V */
18270 gen_msa_elm_3e(env
, ctx
);
18273 generate_exception(ctx
, EXCP_RI
);
18277 gen_msa_elm_df(env
, ctx
, df
, n
);
18280 static void gen_msa_3rf(CPUMIPSState
*env
, DisasContext
*ctx
)
18282 #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
18283 uint8_t df
= (ctx
->opcode
>> 21) & 0x1;
18284 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
18285 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
18286 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
18288 TCGv_i32 twd
= tcg_const_i32(wd
);
18289 TCGv_i32 tws
= tcg_const_i32(ws
);
18290 TCGv_i32 twt
= tcg_const_i32(wt
);
18291 TCGv_i32 tdf
= tcg_temp_new_i32();
18293 /* adjust df value for floating-point instruction */
18294 tcg_gen_movi_i32(tdf
, df
+ 2);
18296 switch (MASK_MSA_3RF(ctx
->opcode
)) {
18298 gen_helper_msa_fcaf_df(cpu_env
, tdf
, twd
, tws
, twt
);
18301 gen_helper_msa_fadd_df(cpu_env
, tdf
, twd
, tws
, twt
);
18304 gen_helper_msa_fcun_df(cpu_env
, tdf
, twd
, tws
, twt
);
18307 gen_helper_msa_fsub_df(cpu_env
, tdf
, twd
, tws
, twt
);
18310 gen_helper_msa_fcor_df(cpu_env
, tdf
, twd
, tws
, twt
);
18313 gen_helper_msa_fceq_df(cpu_env
, tdf
, twd
, tws
, twt
);
18316 gen_helper_msa_fmul_df(cpu_env
, tdf
, twd
, tws
, twt
);
18319 gen_helper_msa_fcune_df(cpu_env
, tdf
, twd
, tws
, twt
);
18322 gen_helper_msa_fcueq_df(cpu_env
, tdf
, twd
, tws
, twt
);
18325 gen_helper_msa_fdiv_df(cpu_env
, tdf
, twd
, tws
, twt
);
18328 gen_helper_msa_fcne_df(cpu_env
, tdf
, twd
, tws
, twt
);
18331 gen_helper_msa_fclt_df(cpu_env
, tdf
, twd
, tws
, twt
);
18334 gen_helper_msa_fmadd_df(cpu_env
, tdf
, twd
, tws
, twt
);
18337 tcg_gen_movi_i32(tdf
, df
+ 1);
18338 gen_helper_msa_mul_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
18341 gen_helper_msa_fcult_df(cpu_env
, tdf
, twd
, tws
, twt
);
18344 gen_helper_msa_fmsub_df(cpu_env
, tdf
, twd
, tws
, twt
);
18346 case OPC_MADD_Q_df
:
18347 tcg_gen_movi_i32(tdf
, df
+ 1);
18348 gen_helper_msa_madd_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
18351 gen_helper_msa_fcle_df(cpu_env
, tdf
, twd
, tws
, twt
);
18353 case OPC_MSUB_Q_df
:
18354 tcg_gen_movi_i32(tdf
, df
+ 1);
18355 gen_helper_msa_msub_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
18358 gen_helper_msa_fcule_df(cpu_env
, tdf
, twd
, tws
, twt
);
18361 gen_helper_msa_fexp2_df(cpu_env
, tdf
, twd
, tws
, twt
);
18364 gen_helper_msa_fsaf_df(cpu_env
, tdf
, twd
, tws
, twt
);
18367 gen_helper_msa_fexdo_df(cpu_env
, tdf
, twd
, tws
, twt
);
18370 gen_helper_msa_fsun_df(cpu_env
, tdf
, twd
, tws
, twt
);
18373 gen_helper_msa_fsor_df(cpu_env
, tdf
, twd
, tws
, twt
);
18376 gen_helper_msa_fseq_df(cpu_env
, tdf
, twd
, tws
, twt
);
18379 gen_helper_msa_ftq_df(cpu_env
, tdf
, twd
, tws
, twt
);
18382 gen_helper_msa_fsune_df(cpu_env
, tdf
, twd
, tws
, twt
);
18385 gen_helper_msa_fsueq_df(cpu_env
, tdf
, twd
, tws
, twt
);
18388 gen_helper_msa_fsne_df(cpu_env
, tdf
, twd
, tws
, twt
);
18391 gen_helper_msa_fslt_df(cpu_env
, tdf
, twd
, tws
, twt
);
18394 gen_helper_msa_fmin_df(cpu_env
, tdf
, twd
, tws
, twt
);
18396 case OPC_MULR_Q_df
:
18397 tcg_gen_movi_i32(tdf
, df
+ 1);
18398 gen_helper_msa_mulr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
18401 gen_helper_msa_fsult_df(cpu_env
, tdf
, twd
, tws
, twt
);
18403 case OPC_FMIN_A_df
:
18404 gen_helper_msa_fmin_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
18406 case OPC_MADDR_Q_df
:
18407 tcg_gen_movi_i32(tdf
, df
+ 1);
18408 gen_helper_msa_maddr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
18411 gen_helper_msa_fsle_df(cpu_env
, tdf
, twd
, tws
, twt
);
18414 gen_helper_msa_fmax_df(cpu_env
, tdf
, twd
, tws
, twt
);
18416 case OPC_MSUBR_Q_df
:
18417 tcg_gen_movi_i32(tdf
, df
+ 1);
18418 gen_helper_msa_msubr_q_df(cpu_env
, tdf
, twd
, tws
, twt
);
18421 gen_helper_msa_fsule_df(cpu_env
, tdf
, twd
, tws
, twt
);
18423 case OPC_FMAX_A_df
:
18424 gen_helper_msa_fmax_a_df(cpu_env
, tdf
, twd
, tws
, twt
);
18427 MIPS_INVAL("MSA instruction");
18428 generate_exception(ctx
, EXCP_RI
);
18432 tcg_temp_free_i32(twd
);
18433 tcg_temp_free_i32(tws
);
18434 tcg_temp_free_i32(twt
);
18435 tcg_temp_free_i32(tdf
);
18438 static void gen_msa_2r(CPUMIPSState
*env
, DisasContext
*ctx
)
18440 #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
18441 (op & (0x7 << 18)))
18442 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
18443 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
18444 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
18445 uint8_t df
= (ctx
->opcode
>> 16) & 0x3;
18446 TCGv_i32 twd
= tcg_const_i32(wd
);
18447 TCGv_i32 tws
= tcg_const_i32(ws
);
18448 TCGv_i32 twt
= tcg_const_i32(wt
);
18449 TCGv_i32 tdf
= tcg_const_i32(df
);
18451 switch (MASK_MSA_2R(ctx
->opcode
)) {
18453 #if !defined(TARGET_MIPS64)
18454 /* Double format valid only for MIPS64 */
18455 if (df
== DF_DOUBLE
) {
18456 generate_exception(ctx
, EXCP_RI
);
18460 gen_helper_msa_fill_df(cpu_env
, tdf
, twd
, tws
); /* trs */
18463 gen_helper_msa_pcnt_df(cpu_env
, tdf
, twd
, tws
);
18466 gen_helper_msa_nloc_df(cpu_env
, tdf
, twd
, tws
);
18469 gen_helper_msa_nlzc_df(cpu_env
, tdf
, twd
, tws
);
18472 MIPS_INVAL("MSA instruction");
18473 generate_exception(ctx
, EXCP_RI
);
18477 tcg_temp_free_i32(twd
);
18478 tcg_temp_free_i32(tws
);
18479 tcg_temp_free_i32(twt
);
18480 tcg_temp_free_i32(tdf
);
18483 static void gen_msa_2rf(CPUMIPSState
*env
, DisasContext
*ctx
)
18485 #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
18486 (op & (0xf << 17)))
18487 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
18488 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
18489 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
18490 uint8_t df
= (ctx
->opcode
>> 16) & 0x1;
18491 TCGv_i32 twd
= tcg_const_i32(wd
);
18492 TCGv_i32 tws
= tcg_const_i32(ws
);
18493 TCGv_i32 twt
= tcg_const_i32(wt
);
18494 /* adjust df value for floating-point instruction */
18495 TCGv_i32 tdf
= tcg_const_i32(df
+ 2);
18497 switch (MASK_MSA_2RF(ctx
->opcode
)) {
18498 case OPC_FCLASS_df
:
18499 gen_helper_msa_fclass_df(cpu_env
, tdf
, twd
, tws
);
18501 case OPC_FTRUNC_S_df
:
18502 gen_helper_msa_ftrunc_s_df(cpu_env
, tdf
, twd
, tws
);
18504 case OPC_FTRUNC_U_df
:
18505 gen_helper_msa_ftrunc_u_df(cpu_env
, tdf
, twd
, tws
);
18508 gen_helper_msa_fsqrt_df(cpu_env
, tdf
, twd
, tws
);
18510 case OPC_FRSQRT_df
:
18511 gen_helper_msa_frsqrt_df(cpu_env
, tdf
, twd
, tws
);
18514 gen_helper_msa_frcp_df(cpu_env
, tdf
, twd
, tws
);
18517 gen_helper_msa_frint_df(cpu_env
, tdf
, twd
, tws
);
18520 gen_helper_msa_flog2_df(cpu_env
, tdf
, twd
, tws
);
18522 case OPC_FEXUPL_df
:
18523 gen_helper_msa_fexupl_df(cpu_env
, tdf
, twd
, tws
);
18525 case OPC_FEXUPR_df
:
18526 gen_helper_msa_fexupr_df(cpu_env
, tdf
, twd
, tws
);
18529 gen_helper_msa_ffql_df(cpu_env
, tdf
, twd
, tws
);
18532 gen_helper_msa_ffqr_df(cpu_env
, tdf
, twd
, tws
);
18534 case OPC_FTINT_S_df
:
18535 gen_helper_msa_ftint_s_df(cpu_env
, tdf
, twd
, tws
);
18537 case OPC_FTINT_U_df
:
18538 gen_helper_msa_ftint_u_df(cpu_env
, tdf
, twd
, tws
);
18540 case OPC_FFINT_S_df
:
18541 gen_helper_msa_ffint_s_df(cpu_env
, tdf
, twd
, tws
);
18543 case OPC_FFINT_U_df
:
18544 gen_helper_msa_ffint_u_df(cpu_env
, tdf
, twd
, tws
);
18548 tcg_temp_free_i32(twd
);
18549 tcg_temp_free_i32(tws
);
18550 tcg_temp_free_i32(twt
);
18551 tcg_temp_free_i32(tdf
);
18554 static void gen_msa_vec_v(CPUMIPSState
*env
, DisasContext
*ctx
)
18556 #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
18557 uint8_t wt
= (ctx
->opcode
>> 16) & 0x1f;
18558 uint8_t ws
= (ctx
->opcode
>> 11) & 0x1f;
18559 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
18560 TCGv_i32 twd
= tcg_const_i32(wd
);
18561 TCGv_i32 tws
= tcg_const_i32(ws
);
18562 TCGv_i32 twt
= tcg_const_i32(wt
);
18564 switch (MASK_MSA_VEC(ctx
->opcode
)) {
18566 gen_helper_msa_and_v(cpu_env
, twd
, tws
, twt
);
18569 gen_helper_msa_or_v(cpu_env
, twd
, tws
, twt
);
18572 gen_helper_msa_nor_v(cpu_env
, twd
, tws
, twt
);
18575 gen_helper_msa_xor_v(cpu_env
, twd
, tws
, twt
);
18578 gen_helper_msa_bmnz_v(cpu_env
, twd
, tws
, twt
);
18581 gen_helper_msa_bmz_v(cpu_env
, twd
, tws
, twt
);
18584 gen_helper_msa_bsel_v(cpu_env
, twd
, tws
, twt
);
18587 MIPS_INVAL("MSA instruction");
18588 generate_exception(ctx
, EXCP_RI
);
18592 tcg_temp_free_i32(twd
);
18593 tcg_temp_free_i32(tws
);
18594 tcg_temp_free_i32(twt
);
18597 static void gen_msa_vec(CPUMIPSState
*env
, DisasContext
*ctx
)
18599 switch (MASK_MSA_VEC(ctx
->opcode
)) {
18607 gen_msa_vec_v(env
, ctx
);
18610 gen_msa_2r(env
, ctx
);
18613 gen_msa_2rf(env
, ctx
);
18616 MIPS_INVAL("MSA instruction");
18617 generate_exception(ctx
, EXCP_RI
);
18622 static void gen_msa(CPUMIPSState
*env
, DisasContext
*ctx
)
18624 uint32_t opcode
= ctx
->opcode
;
18625 check_insn(ctx
, ASE_MSA
);
18626 check_msa_access(ctx
);
18628 switch (MASK_MSA_MINOR(opcode
)) {
18629 case OPC_MSA_I8_00
:
18630 case OPC_MSA_I8_01
:
18631 case OPC_MSA_I8_02
:
18632 gen_msa_i8(env
, ctx
);
18634 case OPC_MSA_I5_06
:
18635 case OPC_MSA_I5_07
:
18636 gen_msa_i5(env
, ctx
);
18638 case OPC_MSA_BIT_09
:
18639 case OPC_MSA_BIT_0A
:
18640 gen_msa_bit(env
, ctx
);
18642 case OPC_MSA_3R_0D
:
18643 case OPC_MSA_3R_0E
:
18644 case OPC_MSA_3R_0F
:
18645 case OPC_MSA_3R_10
:
18646 case OPC_MSA_3R_11
:
18647 case OPC_MSA_3R_12
:
18648 case OPC_MSA_3R_13
:
18649 case OPC_MSA_3R_14
:
18650 case OPC_MSA_3R_15
:
18651 gen_msa_3r(env
, ctx
);
18654 gen_msa_elm(env
, ctx
);
18656 case OPC_MSA_3RF_1A
:
18657 case OPC_MSA_3RF_1B
:
18658 case OPC_MSA_3RF_1C
:
18659 gen_msa_3rf(env
, ctx
);
18662 gen_msa_vec(env
, ctx
);
18673 int32_t s10
= sextract32(ctx
->opcode
, 16, 10);
18674 uint8_t rs
= (ctx
->opcode
>> 11) & 0x1f;
18675 uint8_t wd
= (ctx
->opcode
>> 6) & 0x1f;
18676 uint8_t df
= (ctx
->opcode
>> 0) & 0x3;
18678 TCGv_i32 twd
= tcg_const_i32(wd
);
18679 TCGv taddr
= tcg_temp_new();
18680 gen_base_offset_addr(ctx
, taddr
, rs
, s10
<< df
);
18682 switch (MASK_MSA_MINOR(opcode
)) {
18684 gen_helper_msa_ld_b(cpu_env
, twd
, taddr
);
18687 gen_helper_msa_ld_h(cpu_env
, twd
, taddr
);
18690 gen_helper_msa_ld_w(cpu_env
, twd
, taddr
);
18693 gen_helper_msa_ld_d(cpu_env
, twd
, taddr
);
18696 gen_helper_msa_st_b(cpu_env
, twd
, taddr
);
18699 gen_helper_msa_st_h(cpu_env
, twd
, taddr
);
18702 gen_helper_msa_st_w(cpu_env
, twd
, taddr
);
18705 gen_helper_msa_st_d(cpu_env
, twd
, taddr
);
18709 tcg_temp_free_i32(twd
);
18710 tcg_temp_free(taddr
);
18714 MIPS_INVAL("MSA instruction");
18715 generate_exception(ctx
, EXCP_RI
);
18721 static void decode_opc(CPUMIPSState
*env
, DisasContext
*ctx
)
18724 int rs
, rt
, rd
, sa
;
18728 /* make sure instructions are on a word boundary */
18729 if (ctx
->pc
& 0x3) {
18730 env
->CP0_BadVAddr
= ctx
->pc
;
18731 generate_exception_err(ctx
, EXCP_AdEL
, EXCP_INST_NOTAVAIL
);
18732 ctx
->bstate
= BS_STOP
;
18736 /* Handle blikely not taken case */
18737 if ((ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) == MIPS_HFLAG_BL
) {
18738 TCGLabel
*l1
= gen_new_label();
18740 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
18741 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
18742 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
18743 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
18747 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
18748 tcg_gen_debug_insn_start(ctx
->pc
);
18751 op
= MASK_OP_MAJOR(ctx
->opcode
);
18752 rs
= (ctx
->opcode
>> 21) & 0x1f;
18753 rt
= (ctx
->opcode
>> 16) & 0x1f;
18754 rd
= (ctx
->opcode
>> 11) & 0x1f;
18755 sa
= (ctx
->opcode
>> 6) & 0x1f;
18756 imm
= (int16_t)ctx
->opcode
;
18759 decode_opc_special(env
, ctx
);
18762 decode_opc_special2_legacy(env
, ctx
);
18765 decode_opc_special3(env
, ctx
);
18768 op1
= MASK_REGIMM(ctx
->opcode
);
18770 case OPC_BLTZL
: /* REGIMM branches */
18774 check_insn(ctx
, ISA_MIPS2
);
18775 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
18779 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2, 4);
18783 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
18785 /* OPC_NAL, OPC_BAL */
18786 gen_compute_branch(ctx
, op1
, 4, 0, -1, imm
<< 2, 4);
18788 generate_exception(ctx
, EXCP_RI
);
18791 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2, 4);
18794 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
18796 check_insn(ctx
, ISA_MIPS2
);
18797 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
18798 gen_trap(ctx
, op1
, rs
, -1, imm
);
18801 check_insn(ctx
, ISA_MIPS32R2
);
18802 /* Break the TB to be able to sync copied instructions
18804 ctx
->bstate
= BS_STOP
;
18806 case OPC_BPOSGE32
: /* MIPS DSP branch */
18807 #if defined(TARGET_MIPS64)
18811 gen_compute_branch(ctx
, op1
, 4, -1, -2, (int32_t)imm
<< 2, 4);
18813 #if defined(TARGET_MIPS64)
18815 check_insn(ctx
, ISA_MIPS32R6
);
18816 check_mips_64(ctx
);
18818 tcg_gen_addi_tl(cpu_gpr
[rs
], cpu_gpr
[rs
], (int64_t)imm
<< 32);
18820 MIPS_DEBUG("dahi %s, %04x", regnames
[rs
], imm
);
18823 check_insn(ctx
, ISA_MIPS32R6
);
18824 check_mips_64(ctx
);
18826 tcg_gen_addi_tl(cpu_gpr
[rs
], cpu_gpr
[rs
], (int64_t)imm
<< 48);
18828 MIPS_DEBUG("dati %s, %04x", regnames
[rs
], imm
);
18831 default: /* Invalid */
18832 MIPS_INVAL("regimm");
18833 generate_exception(ctx
, EXCP_RI
);
18838 check_cp0_enabled(ctx
);
18839 op1
= MASK_CP0(ctx
->opcode
);
18847 #if defined(TARGET_MIPS64)
18851 #ifndef CONFIG_USER_ONLY
18852 gen_cp0(env
, ctx
, op1
, rt
, rd
);
18853 #endif /* !CONFIG_USER_ONLY */
18855 case OPC_C0_FIRST
... OPC_C0_LAST
:
18856 #ifndef CONFIG_USER_ONLY
18857 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
18858 #endif /* !CONFIG_USER_ONLY */
18861 #ifndef CONFIG_USER_ONLY
18864 TCGv t0
= tcg_temp_new();
18866 op2
= MASK_MFMC0(ctx
->opcode
);
18869 check_insn(ctx
, ASE_MT
);
18870 gen_helper_dmt(t0
);
18871 gen_store_gpr(t0
, rt
);
18874 check_insn(ctx
, ASE_MT
);
18875 gen_helper_emt(t0
);
18876 gen_store_gpr(t0
, rt
);
18879 check_insn(ctx
, ASE_MT
);
18880 gen_helper_dvpe(t0
, cpu_env
);
18881 gen_store_gpr(t0
, rt
);
18884 check_insn(ctx
, ASE_MT
);
18885 gen_helper_evpe(t0
, cpu_env
);
18886 gen_store_gpr(t0
, rt
);
18889 check_insn(ctx
, ISA_MIPS32R2
);
18890 save_cpu_state(ctx
, 1);
18891 gen_helper_di(t0
, cpu_env
);
18892 gen_store_gpr(t0
, rt
);
18893 /* Stop translation as we may have switched
18894 the execution mode. */
18895 ctx
->bstate
= BS_STOP
;
18898 check_insn(ctx
, ISA_MIPS32R2
);
18899 save_cpu_state(ctx
, 1);
18900 gen_helper_ei(t0
, cpu_env
);
18901 gen_store_gpr(t0
, rt
);
18902 /* Stop translation as we may have switched
18903 the execution mode. */
18904 ctx
->bstate
= BS_STOP
;
18906 default: /* Invalid */
18907 MIPS_INVAL("mfmc0");
18908 generate_exception(ctx
, EXCP_RI
);
18913 #endif /* !CONFIG_USER_ONLY */
18916 check_insn(ctx
, ISA_MIPS32R2
);
18917 gen_load_srsgpr(rt
, rd
);
18920 check_insn(ctx
, ISA_MIPS32R2
);
18921 gen_store_srsgpr(rt
, rd
);
18925 generate_exception(ctx
, EXCP_RI
);
18929 case OPC_BOVC
: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
18930 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
18931 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
18932 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
18935 /* Arithmetic with immediate opcode */
18936 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
18940 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
18942 case OPC_SLTI
: /* Set on less than with immediate opcode */
18944 gen_slt_imm(ctx
, op
, rt
, rs
, imm
);
18946 case OPC_ANDI
: /* Arithmetic with immediate opcode */
18947 case OPC_LUI
: /* OPC_AUI */
18950 gen_logic_imm(ctx
, op
, rt
, rs
, imm
);
18952 case OPC_J
... OPC_JAL
: /* Jump */
18953 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
18954 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
, 4);
18957 case OPC_BLEZC
: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
18958 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
18960 generate_exception(ctx
, EXCP_RI
);
18963 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
18964 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
18967 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
18970 case OPC_BGTZC
: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
18971 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
18973 generate_exception(ctx
, EXCP_RI
);
18976 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
18977 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
18980 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
18983 case OPC_BLEZALC
: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
18986 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
18988 check_insn(ctx
, ISA_MIPS32R6
);
18989 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
18990 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
18993 case OPC_BGTZALC
: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
18996 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
18998 check_insn(ctx
, ISA_MIPS32R6
);
18999 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
19000 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
19005 check_insn(ctx
, ISA_MIPS2
);
19006 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19010 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2, 4);
19012 case OPC_LL
: /* Load and stores */
19013 check_insn(ctx
, ISA_MIPS2
);
19017 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19019 case OPC_LB
... OPC_LH
:
19020 case OPC_LW
... OPC_LHU
:
19021 gen_ld(ctx
, op
, rt
, rs
, imm
);
19025 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19027 case OPC_SB
... OPC_SH
:
19029 gen_st(ctx
, op
, rt
, rs
, imm
);
19032 check_insn(ctx
, ISA_MIPS2
);
19033 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19034 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
19037 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19038 check_cp0_enabled(ctx
);
19039 check_insn(ctx
, ISA_MIPS3
| ISA_MIPS32
);
19040 /* Treat as NOP. */
19043 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19044 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32
);
19045 /* Treat as NOP. */
19048 /* Floating point (COP1). */
19053 gen_cop1_ldst(ctx
, op
, rt
, rs
, imm
);
19057 op1
= MASK_CP1(ctx
->opcode
);
19062 check_cp1_enabled(ctx
);
19063 check_insn(ctx
, ISA_MIPS32R2
);
19068 check_cp1_enabled(ctx
);
19069 gen_cp1(ctx
, op1
, rt
, rd
);
19071 #if defined(TARGET_MIPS64)
19074 check_cp1_enabled(ctx
);
19075 check_insn(ctx
, ISA_MIPS3
);
19076 check_mips_64(ctx
);
19077 gen_cp1(ctx
, op1
, rt
, rd
);
19080 case OPC_BC1EQZ
: /* OPC_BC1ANY2 */
19081 check_cp1_enabled(ctx
);
19082 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19084 gen_compute_branch1_r6(ctx
, MASK_CP1(ctx
->opcode
),
19089 check_insn(ctx
, ASE_MIPS3D
);
19090 gen_compute_branch1(ctx
, MASK_BC1(ctx
->opcode
),
19091 (rt
>> 2) & 0x7, imm
<< 2);
19095 check_cp1_enabled(ctx
);
19096 check_insn(ctx
, ISA_MIPS32R6
);
19097 gen_compute_branch1_r6(ctx
, MASK_CP1(ctx
->opcode
),
19101 check_cp1_enabled(ctx
);
19102 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19104 check_insn(ctx
, ASE_MIPS3D
);
19107 check_cp1_enabled(ctx
);
19108 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19109 gen_compute_branch1(ctx
, MASK_BC1(ctx
->opcode
),
19110 (rt
>> 2) & 0x7, imm
<< 2);
19113 check_cp1_enabled(ctx
);
19114 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19118 check_cp1_enabled(ctx
);
19119 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f), rt
, rd
, sa
,
19125 int r6_op
= ctx
->opcode
& FOP(0x3f, 0x1f);
19126 check_cp1_enabled(ctx
);
19127 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19129 case R6_OPC_CMP_AF_S
:
19130 case R6_OPC_CMP_UN_S
:
19131 case R6_OPC_CMP_EQ_S
:
19132 case R6_OPC_CMP_UEQ_S
:
19133 case R6_OPC_CMP_LT_S
:
19134 case R6_OPC_CMP_ULT_S
:
19135 case R6_OPC_CMP_LE_S
:
19136 case R6_OPC_CMP_ULE_S
:
19137 case R6_OPC_CMP_SAF_S
:
19138 case R6_OPC_CMP_SUN_S
:
19139 case R6_OPC_CMP_SEQ_S
:
19140 case R6_OPC_CMP_SEUQ_S
:
19141 case R6_OPC_CMP_SLT_S
:
19142 case R6_OPC_CMP_SULT_S
:
19143 case R6_OPC_CMP_SLE_S
:
19144 case R6_OPC_CMP_SULE_S
:
19145 case R6_OPC_CMP_OR_S
:
19146 case R6_OPC_CMP_UNE_S
:
19147 case R6_OPC_CMP_NE_S
:
19148 case R6_OPC_CMP_SOR_S
:
19149 case R6_OPC_CMP_SUNE_S
:
19150 case R6_OPC_CMP_SNE_S
:
19151 gen_r6_cmp_s(ctx
, ctx
->opcode
& 0x1f, rt
, rd
, sa
);
19153 case R6_OPC_CMP_AF_D
:
19154 case R6_OPC_CMP_UN_D
:
19155 case R6_OPC_CMP_EQ_D
:
19156 case R6_OPC_CMP_UEQ_D
:
19157 case R6_OPC_CMP_LT_D
:
19158 case R6_OPC_CMP_ULT_D
:
19159 case R6_OPC_CMP_LE_D
:
19160 case R6_OPC_CMP_ULE_D
:
19161 case R6_OPC_CMP_SAF_D
:
19162 case R6_OPC_CMP_SUN_D
:
19163 case R6_OPC_CMP_SEQ_D
:
19164 case R6_OPC_CMP_SEUQ_D
:
19165 case R6_OPC_CMP_SLT_D
:
19166 case R6_OPC_CMP_SULT_D
:
19167 case R6_OPC_CMP_SLE_D
:
19168 case R6_OPC_CMP_SULE_D
:
19169 case R6_OPC_CMP_OR_D
:
19170 case R6_OPC_CMP_UNE_D
:
19171 case R6_OPC_CMP_NE_D
:
19172 case R6_OPC_CMP_SOR_D
:
19173 case R6_OPC_CMP_SUNE_D
:
19174 case R6_OPC_CMP_SNE_D
:
19175 gen_r6_cmp_d(ctx
, ctx
->opcode
& 0x1f, rt
, rd
, sa
);
19178 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f),
19179 rt
, rd
, sa
, (imm
>> 8) & 0x7);
19184 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f), rt
, rd
, sa
,
19199 check_insn(ctx
, ASE_MSA
);
19200 gen_msa_branch(env
, ctx
, op1
);
19204 generate_exception(ctx
, EXCP_RI
);
19209 /* Compact branches [R6] and COP2 [non-R6] */
19210 case OPC_BC
: /* OPC_LWC2 */
19211 case OPC_BALC
: /* OPC_SWC2 */
19212 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19213 /* OPC_BC, OPC_BALC */
19214 gen_compute_compact_branch(ctx
, op
, 0, 0,
19215 sextract32(ctx
->opcode
<< 2, 0, 28));
19217 /* OPC_LWC2, OPC_SWC2 */
19218 /* COP2: Not implemented. */
19219 generate_exception_err(ctx
, EXCP_CpU
, 2);
19222 case OPC_BEQZC
: /* OPC_JIC, OPC_LDC2 */
19223 case OPC_BNEZC
: /* OPC_JIALC, OPC_SDC2 */
19224 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19226 /* OPC_BEQZC, OPC_BNEZC */
19227 gen_compute_compact_branch(ctx
, op
, rs
, 0,
19228 sextract32(ctx
->opcode
<< 2, 0, 23));
19230 /* OPC_JIC, OPC_JIALC */
19231 gen_compute_compact_branch(ctx
, op
, 0, rt
, imm
);
19234 /* OPC_LWC2, OPC_SWC2 */
19235 /* COP2: Not implemented. */
19236 generate_exception_err(ctx
, EXCP_CpU
, 2);
19240 check_insn(ctx
, INSN_LOONGSON2F
);
19241 /* Note that these instructions use different fields. */
19242 gen_loongson_multimedia(ctx
, sa
, rd
, rt
);
19246 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19247 if (ctx
->CP0_Config1
& (1 << CP0C1_FP
)) {
19248 check_cp1_enabled(ctx
);
19249 op1
= MASK_CP3(ctx
->opcode
);
19253 check_insn(ctx
, ISA_MIPS5
| ISA_MIPS32R2
);
19259 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32R2
);
19260 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
19263 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32R2
);
19264 /* Treat as NOP. */
19267 check_insn(ctx
, ISA_MIPS5
| ISA_MIPS32R2
);
19281 check_insn(ctx
, ISA_MIPS4
| ISA_MIPS32R2
);
19282 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
19286 generate_exception (ctx
, EXCP_RI
);
19290 generate_exception_err(ctx
, EXCP_CpU
, 1);
19294 #if defined(TARGET_MIPS64)
19295 /* MIPS64 opcodes */
19296 case OPC_LDL
... OPC_LDR
:
19298 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19302 check_insn(ctx
, ISA_MIPS3
);
19303 check_mips_64(ctx
);
19304 gen_ld(ctx
, op
, rt
, rs
, imm
);
19306 case OPC_SDL
... OPC_SDR
:
19307 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19310 check_insn(ctx
, ISA_MIPS3
);
19311 check_mips_64(ctx
);
19312 gen_st(ctx
, op
, rt
, rs
, imm
);
19315 check_insn_opc_removed(ctx
, ISA_MIPS32R6
);
19316 check_insn(ctx
, ISA_MIPS3
);
19317 check_mips_64(ctx
);
19318 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
19320 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
19321 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19322 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
19323 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
19326 check_insn(ctx
, ISA_MIPS3
);
19327 check_mips_64(ctx
);
19328 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
19332 check_insn(ctx
, ISA_MIPS3
);
19333 check_mips_64(ctx
);
19334 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
19337 case OPC_BNVC
: /* OPC_BNEZALC, OPC_BNEC */
19338 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19339 gen_compute_compact_branch(ctx
, op
, rs
, rt
, imm
<< 2);
19341 MIPS_INVAL("major opcode");
19342 generate_exception(ctx
, EXCP_RI
);
19346 case OPC_DAUI
: /* OPC_JALX */
19347 if (ctx
->insn_flags
& ISA_MIPS32R6
) {
19348 #if defined(TARGET_MIPS64)
19350 check_mips_64(ctx
);
19352 TCGv t0
= tcg_temp_new();
19353 gen_load_gpr(t0
, rs
);
19354 tcg_gen_addi_tl(cpu_gpr
[rt
], t0
, imm
<< 16);
19357 MIPS_DEBUG("daui %s, %s, %04x", regnames
[rt
], regnames
[rs
], imm
);
19359 generate_exception(ctx
, EXCP_RI
);
19360 MIPS_INVAL("major opcode");
19364 check_insn(ctx
, ASE_MIPS16
| ASE_MICROMIPS
);
19365 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
19366 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
, 4);
19369 case OPC_MSA
: /* OPC_MDMX */
19370 /* MDMX: Not implemented. */
19374 check_insn(ctx
, ISA_MIPS32R6
);
19375 gen_pcrel(ctx
, rs
, imm
);
19377 default: /* Invalid */
19378 MIPS_INVAL("major opcode");
19379 generate_exception(ctx
, EXCP_RI
);
19385 gen_intermediate_code_internal(MIPSCPU
*cpu
, TranslationBlock
*tb
,
19388 CPUState
*cs
= CPU(cpu
);
19389 CPUMIPSState
*env
= &cpu
->env
;
19391 target_ulong pc_start
;
19392 target_ulong next_page_start
;
19401 qemu_log("search pc %d\n", search_pc
);
19404 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
19407 ctx
.singlestep_enabled
= cs
->singlestep_enabled
;
19408 ctx
.insn_flags
= env
->insn_flags
;
19409 ctx
.CP0_Config1
= env
->CP0_Config1
;
19411 ctx
.bstate
= BS_NONE
;
19412 ctx
.kscrexist
= (env
->CP0_Config4
>> CP0C4_KScrExist
) & 0xff;
19413 ctx
.rxi
= (env
->CP0_Config3
>> CP0C3_RXI
) & 1;
19414 ctx
.ie
= (env
->CP0_Config4
>> CP0C4_IE
) & 3;
19415 ctx
.bi
= (env
->CP0_Config3
>> CP0C3_BI
) & 1;
19416 ctx
.bp
= (env
->CP0_Config3
>> CP0C3_BP
) & 1;
19417 ctx
.PAMask
= env
->PAMask
;
19418 ctx
.mvh
= (env
->CP0_Config5
>> CP0C5_MVH
) & 1;
19419 ctx
.CP0_LLAddr_shift
= env
->CP0_LLAddr_shift
;
19420 /* Restore delay slot state from the tb context. */
19421 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
19422 ctx
.ulri
= (env
->CP0_Config3
>> CP0C3_ULRI
) & 1;
19423 restore_cpu_state(env
, &ctx
);
19424 #ifdef CONFIG_USER_ONLY
19425 ctx
.mem_idx
= MIPS_HFLAG_UM
;
19427 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
19429 ctx
.default_tcg_memop_mask
= (ctx
.insn_flags
& ISA_MIPS32R6
) ?
19430 MO_UNALN
: MO_ALIGN
;
19432 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
19433 if (max_insns
== 0)
19434 max_insns
= CF_COUNT_MASK
;
19435 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
19437 while (ctx
.bstate
== BS_NONE
) {
19438 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
19439 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
19440 if (bp
->pc
== ctx
.pc
) {
19441 save_cpu_state(&ctx
, 1);
19442 ctx
.bstate
= BS_BRANCH
;
19443 gen_helper_0e0i(raise_exception
, EXCP_DEBUG
);
19444 /* Include the breakpoint location or the tb won't
19445 * be flushed when it must be. */
19447 goto done_generating
;
19453 j
= tcg_op_buf_count();
19457 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
19459 tcg_ctx
.gen_opc_pc
[lj
] = ctx
.pc
;
19460 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
19461 gen_opc_btarget
[lj
] = ctx
.btarget
;
19462 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
19463 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
19465 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
19468 is_slot
= ctx
.hflags
& MIPS_HFLAG_BMASK
;
19469 if (!(ctx
.hflags
& MIPS_HFLAG_M16
)) {
19470 ctx
.opcode
= cpu_ldl_code(env
, ctx
.pc
);
19472 decode_opc(env
, &ctx
);
19473 } else if (ctx
.insn_flags
& ASE_MICROMIPS
) {
19474 ctx
.opcode
= cpu_lduw_code(env
, ctx
.pc
);
19475 insn_bytes
= decode_micromips_opc(env
, &ctx
);
19476 } else if (ctx
.insn_flags
& ASE_MIPS16
) {
19477 ctx
.opcode
= cpu_lduw_code(env
, ctx
.pc
);
19478 insn_bytes
= decode_mips16_opc(env
, &ctx
);
19480 generate_exception(&ctx
, EXCP_RI
);
19481 ctx
.bstate
= BS_STOP
;
19485 if (ctx
.hflags
& MIPS_HFLAG_BMASK
) {
19486 if (!(ctx
.hflags
& (MIPS_HFLAG_BDS16
| MIPS_HFLAG_BDS32
|
19487 MIPS_HFLAG_FBNSLOT
))) {
19488 /* force to generate branch as there is neither delay nor
19494 gen_branch(&ctx
, insn_bytes
);
19496 ctx
.pc
+= insn_bytes
;
19500 /* Execute a branch and its delay slot as a single instruction.
19501 This is what GDB expects and is consistent with what the
19502 hardware does (e.g. if a delay slot instruction faults, the
19503 reported PC is the PC of the branch). */
19504 if (cs
->singlestep_enabled
&& (ctx
.hflags
& MIPS_HFLAG_BMASK
) == 0) {
19508 if (ctx
.pc
>= next_page_start
) {
19512 if (tcg_op_buf_full()) {
19516 if (num_insns
>= max_insns
)
19522 if (tb
->cflags
& CF_LAST_IO
) {
19525 if (cs
->singlestep_enabled
&& ctx
.bstate
!= BS_BRANCH
) {
19526 save_cpu_state(&ctx
, ctx
.bstate
!= BS_EXCP
);
19527 gen_helper_0e0i(raise_exception
, EXCP_DEBUG
);
19529 switch (ctx
.bstate
) {
19531 gen_goto_tb(&ctx
, 0, ctx
.pc
);
19534 save_cpu_state(&ctx
, 0);
19535 gen_goto_tb(&ctx
, 0, ctx
.pc
);
19538 tcg_gen_exit_tb(0);
19546 gen_tb_end(tb
, num_insns
);
19549 j
= tcg_op_buf_count();
19552 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
19554 tb
->size
= ctx
.pc
- pc_start
;
19555 tb
->icount
= num_insns
;
19559 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
19560 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
19561 log_target_disas(env
, pc_start
, ctx
.pc
- pc_start
, 0);
19567 void gen_intermediate_code (CPUMIPSState
*env
, struct TranslationBlock
*tb
)
19569 gen_intermediate_code_internal(mips_env_get_cpu(env
), tb
, false);
19572 void gen_intermediate_code_pc (CPUMIPSState
*env
, struct TranslationBlock
*tb
)
19574 gen_intermediate_code_internal(mips_env_get_cpu(env
), tb
, true);
19577 static void fpu_dump_state(CPUMIPSState
*env
, FILE *f
, fprintf_function fpu_fprintf
,
19581 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
19583 #define printfpr(fp) \
19586 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
19587 " fd:%13g fs:%13g psu: %13g\n", \
19588 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
19589 (double)(fp)->fd, \
19590 (double)(fp)->fs[FP_ENDIAN_IDX], \
19591 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
19594 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
19595 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
19596 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
19597 " fd:%13g fs:%13g psu:%13g\n", \
19598 tmp.w[FP_ENDIAN_IDX], tmp.d, \
19600 (double)tmp.fs[FP_ENDIAN_IDX], \
19601 (double)tmp.fs[!FP_ENDIAN_IDX]); \
19606 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
19607 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
,
19608 get_float_exception_flags(&env
->active_fpu
.fp_status
));
19609 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
19610 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
19611 printfpr(&env
->active_fpu
.fpr
[i
]);
19617 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
19618 /* Debug help: The architecture requires 32bit code to maintain proper
19619 sign-extended values on 64bit machines. */
19621 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
19624 cpu_mips_check_sign_extensions (CPUMIPSState
*env
, FILE *f
,
19625 fprintf_function cpu_fprintf
,
19630 if (!SIGN_EXT_P(env
->active_tc
.PC
))
19631 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
19632 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
19633 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
19634 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
19635 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
19636 if (!SIGN_EXT_P(env
->btarget
))
19637 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
19639 for (i
= 0; i
< 32; i
++) {
19640 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
19641 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
19644 if (!SIGN_EXT_P(env
->CP0_EPC
))
19645 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
19646 if (!SIGN_EXT_P(env
->lladdr
))
19647 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->lladdr
);
19651 void mips_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
19654 MIPSCPU
*cpu
= MIPS_CPU(cs
);
19655 CPUMIPSState
*env
= &cpu
->env
;
19658 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
19659 " LO=0x" TARGET_FMT_lx
" ds %04x "
19660 TARGET_FMT_lx
" " TARGET_FMT_ld
"\n",
19661 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
19662 env
->hflags
, env
->btarget
, env
->bcond
);
19663 for (i
= 0; i
< 32; i
++) {
19665 cpu_fprintf(f
, "GPR%02d:", i
);
19666 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
19668 cpu_fprintf(f
, "\n");
19671 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
19672 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
19673 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
19675 env
->CP0_Config0
, env
->CP0_Config1
, env
->lladdr
);
19676 cpu_fprintf(f
, " Config2 0x%08x Config3 0x%08x\n",
19677 env
->CP0_Config2
, env
->CP0_Config3
);
19678 cpu_fprintf(f
, " Config4 0x%08x Config5 0x%08x\n",
19679 env
->CP0_Config4
, env
->CP0_Config5
);
19680 if (env
->hflags
& MIPS_HFLAG_FPU
)
19681 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
19682 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
19683 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
19687 void mips_tcg_init(void)
19692 /* Initialize various static tables. */
19696 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
19697 TCGV_UNUSED(cpu_gpr
[0]);
19698 for (i
= 1; i
< 32; i
++)
19699 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
19700 offsetof(CPUMIPSState
, active_tc
.gpr
[i
]),
19703 for (i
= 0; i
< 32; i
++) {
19704 int off
= offsetof(CPUMIPSState
, active_fpu
.fpr
[i
].wr
.d
[0]);
19706 tcg_global_mem_new_i64(TCG_AREG0
, off
, msaregnames
[i
* 2]);
19707 /* The scalar floating-point unit (FPU) registers are mapped on
19708 * the MSA vector registers. */
19709 fpu_f64
[i
] = msa_wr_d
[i
* 2];
19710 off
= offsetof(CPUMIPSState
, active_fpu
.fpr
[i
].wr
.d
[1]);
19711 msa_wr_d
[i
* 2 + 1] =
19712 tcg_global_mem_new_i64(TCG_AREG0
, off
, msaregnames
[i
* 2 + 1]);
19715 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
19716 offsetof(CPUMIPSState
, active_tc
.PC
), "PC");
19717 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
19718 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
19719 offsetof(CPUMIPSState
, active_tc
.HI
[i
]),
19721 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
19722 offsetof(CPUMIPSState
, active_tc
.LO
[i
]),
19725 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
19726 offsetof(CPUMIPSState
, active_tc
.DSPControl
),
19728 bcond
= tcg_global_mem_new(TCG_AREG0
,
19729 offsetof(CPUMIPSState
, bcond
), "bcond");
19730 btarget
= tcg_global_mem_new(TCG_AREG0
,
19731 offsetof(CPUMIPSState
, btarget
), "btarget");
19732 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
19733 offsetof(CPUMIPSState
, hflags
), "hflags");
19735 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
19736 offsetof(CPUMIPSState
, active_fpu
.fcr0
),
19738 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
19739 offsetof(CPUMIPSState
, active_fpu
.fcr31
),
19745 #include "translate_init.c"
19747 MIPSCPU
*cpu_mips_init(const char *cpu_model
)
19751 const mips_def_t
*def
;
19753 def
= cpu_mips_find_by_name(cpu_model
);
19756 cpu
= MIPS_CPU(object_new(TYPE_MIPS_CPU
));
19758 env
->cpu_model
= def
;
19760 #ifndef CONFIG_USER_ONLY
19761 mmu_init(env
, def
);
19763 fpu_init(env
, def
);
19764 mvp_init(env
, def
);
19766 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
19771 void cpu_state_reset(CPUMIPSState
*env
)
19773 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
19774 CPUState
*cs
= CPU(cpu
);
19776 /* Reset registers to their default values */
19777 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
19778 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
19779 #ifdef TARGET_WORDS_BIGENDIAN
19780 env
->CP0_Config0
|= (1 << CP0C0_BE
);
19782 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
19783 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
19784 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
19785 env
->CP0_Config4
= env
->cpu_model
->CP0_Config4
;
19786 env
->CP0_Config4_rw_bitmask
= env
->cpu_model
->CP0_Config4_rw_bitmask
;
19787 env
->CP0_Config5
= env
->cpu_model
->CP0_Config5
;
19788 env
->CP0_Config5_rw_bitmask
= env
->cpu_model
->CP0_Config5_rw_bitmask
;
19789 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
19790 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
19791 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
19792 << env
->cpu_model
->CP0_LLAddr_shift
;
19793 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
19794 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
19795 env
->CCRes
= env
->cpu_model
->CCRes
;
19796 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
19797 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
19798 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
19799 env
->current_tc
= 0;
19800 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
19801 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
19802 #if defined(TARGET_MIPS64)
19803 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
19804 env
->SEGMask
|= 3ULL << 62;
19807 env
->PABITS
= env
->cpu_model
->PABITS
;
19808 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
19809 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
19810 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
19811 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
19812 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
19813 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
19814 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
19815 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
19816 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
19817 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
19818 env
->CP0_PageGrain_rw_bitmask
= env
->cpu_model
->CP0_PageGrain_rw_bitmask
;
19819 env
->CP0_PageGrain
= env
->cpu_model
->CP0_PageGrain
;
19820 env
->active_fpu
.fcr0
= env
->cpu_model
->CP1_fcr0
;
19821 env
->msair
= env
->cpu_model
->MSAIR
;
19822 env
->insn_flags
= env
->cpu_model
->insn_flags
;
19824 #if defined(CONFIG_USER_ONLY)
19825 env
->CP0_Status
= (MIPS_HFLAG_UM
<< CP0St_KSU
);
19826 # ifdef TARGET_MIPS64
19827 /* Enable 64-bit register mode. */
19828 env
->CP0_Status
|= (1 << CP0St_PX
);
19830 # ifdef TARGET_ABI_MIPSN64
19831 /* Enable 64-bit address mode. */
19832 env
->CP0_Status
|= (1 << CP0St_UX
);
19834 /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
19835 hardware registers. */
19836 env
->CP0_HWREna
|= 0x0000000F;
19837 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
19838 env
->CP0_Status
|= (1 << CP0St_CU1
);
19840 if (env
->CP0_Config3
& (1 << CP0C3_DSPP
)) {
19841 env
->CP0_Status
|= (1 << CP0St_MX
);
19843 # if defined(TARGET_MIPS64)
19844 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
19845 if ((env
->CP0_Config1
& (1 << CP0C1_FP
)) &&
19846 (env
->CP0_Status_rw_bitmask
& (1 << CP0St_FR
))) {
19847 env
->CP0_Status
|= (1 << CP0St_FR
);
19851 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
19852 /* If the exception was raised from a delay slot,
19853 come back to the jump. */
19854 env
->CP0_ErrorEPC
= (env
->active_tc
.PC
19855 - (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4));
19857 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
19859 env
->active_tc
.PC
= (int32_t)0xBFC00000;
19860 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
19861 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
19862 env
->CP0_Wired
= 0;
19863 env
->CP0_EBase
= (cs
->cpu_index
& 0x3FF);
19864 if (kvm_enabled()) {
19865 env
->CP0_EBase
|= 0x40000000;
19867 env
->CP0_EBase
|= 0x80000000;
19869 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
19870 /* vectored interrupts not implemented, timer on int 7,
19871 no performance counters. */
19872 env
->CP0_IntCtl
= 0xe0000000;
19876 for (i
= 0; i
< 7; i
++) {
19877 env
->CP0_WatchLo
[i
] = 0;
19878 env
->CP0_WatchHi
[i
] = 0x80000000;
19880 env
->CP0_WatchLo
[7] = 0;
19881 env
->CP0_WatchHi
[7] = 0;
19883 /* Count register increments in debug mode, EJTAG version 1 */
19884 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
19886 cpu_mips_store_count(env
, 1);
19888 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
19891 /* Only TC0 on VPE 0 starts as active. */
19892 for (i
= 0; i
< ARRAY_SIZE(env
->tcs
); i
++) {
19893 env
->tcs
[i
].CP0_TCBind
= cs
->cpu_index
<< CP0TCBd_CurVPE
;
19894 env
->tcs
[i
].CP0_TCHalt
= 1;
19896 env
->active_tc
.CP0_TCHalt
= 1;
19899 if (cs
->cpu_index
== 0) {
19900 /* VPE0 starts up enabled. */
19901 env
->mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
19902 env
->CP0_VPEConf0
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
19904 /* TC0 starts up unhalted. */
19906 env
->active_tc
.CP0_TCHalt
= 0;
19907 env
->tcs
[0].CP0_TCHalt
= 0;
19908 /* With thread 0 active. */
19909 env
->active_tc
.CP0_TCStatus
= (1 << CP0TCSt_A
);
19910 env
->tcs
[0].CP0_TCStatus
= (1 << CP0TCSt_A
);
19914 if ((env
->insn_flags
& ISA_MIPS32R6
) &&
19915 (env
->active_fpu
.fcr0
& (1 << FCR0_F64
))) {
19916 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
19917 env
->CP0_Status
|= (1 << CP0St_FR
);
19921 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
19925 compute_hflags(env
);
19926 restore_rounding_mode(env
);
19927 restore_flush_mode(env
);
19928 restore_pamask(env
);
19929 cs
->exception_index
= EXCP_NONE
;
19932 void restore_state_to_opc(CPUMIPSState
*env
, TranslationBlock
*tb
, int pc_pos
)
19934 env
->active_tc
.PC
= tcg_ctx
.gen_opc_pc
[pc_pos
];
19935 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
19936 env
->hflags
|= gen_opc_hflags
[pc_pos
];
19937 switch (env
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
19938 case MIPS_HFLAG_BR
:
19940 case MIPS_HFLAG_BC
:
19941 case MIPS_HFLAG_BL
:
19943 env
->btarget
= gen_opc_btarget
[pc_pos
];