hw/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "ptimer.h"
  27
  28 #define D(x)
  29
  30 #define R_TCSR     0
  31 #define R_TLR      1
  32 #define R_TCR      2
  33 #define R_MAX      4
  34
  35 #define TCSR_MDT        (1<<0)
  36 #define TCSR_UDT        (1<<1)
  37 #define TCSR_GENT       (1<<2)
  38 #define TCSR_CAPT       (1<<3)
  39 #define TCSR_ARHT       (1<<4)
  40 #define TCSR_LOAD       (1<<5)
  41 #define TCSR_ENIT       (1<<6)
  42 #define TCSR_ENT        (1<<7)
  43 #define TCSR_TINT       (1<<8)
  44 #define TCSR_PWMA       (1<<9)
  45 #define TCSR_ENALL      (1<<10)
  46
  47 struct xlx_timer
  48 {
  49     QEMUBH *bh;
  50     ptimer_state *ptimer;
  51     void *parent;
  52     int nr; /* for debug.  */
  53
  54     unsigned long timer_div;
  55
  56     uint32_t regs[R_MAX];
  57 };
  58
  59 struct timerblock
  60 {
  61     SysBusDevice busdev;
  62     MemoryRegion mmio;
  63     qemu_irq irq;
  64     uint8_t one_timer_only;
  65     uint32_t freq_hz;
  66     struct xlx_timer *timers;
  67 };
  68
  69 static inline unsigned int num_timers(struct timerblock *t)
  70 {
  71     return 2 - t->one_timer_only;
  72 }
  73
  74 static inline unsigned int timer_from_addr(target_phys_addr_t addr)
  75 {
  76     /* Timers get a 4x32bit control reg area each.  */
  77     return addr >> 2;
  78 }
  79
  80 static void timer_update_irq(struct timerblock *t)
  81 {
  82     unsigned int i, irq = 0;
  83     uint32_t csr;
  84
  85     for (i = 0; i < num_timers(t); i++) {
  86         csr = t->timers[i].regs[R_TCSR];
  87         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  88     }
  89
  90     /* All timers within the same slave share a single IRQ line.  */
  91     qemu_set_irq(t->irq, !!irq);
  92 }
  93
  94 static uint64_t
  95 timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
  96 {
  97     struct timerblock *t = opaque;
  98     struct xlx_timer *xt;
  99     uint32_t r = 0;
 100     unsigned int timer;
 101
 102     addr >>= 2;
 103     timer = timer_from_addr(addr);
 104     xt = &t->timers[timer];
 105     /* Further decoding to address a specific timers reg.  */
 106     addr &= 0x3;
 107     switch (addr)
 108     {
 109         case R_TCR:
 110                 r = ptimer_get_count(xt->ptimer);
 111                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 112                     r = ~r;
 113                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 114                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 115             break;
 116         default:
 117             if (addr < ARRAY_SIZE(xt->regs))
 118                 r = xt->regs[addr];
 119             break;
 120
 121     }
 122     D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 123     return r;
 124 }
 125
 126 static void timer_enable(struct xlx_timer *xt)
 127 {
 128     uint64_t count;
 129
 130     D(printf("%s timer=%d down=%d\n", __func__,
 131               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 132
 133     ptimer_stop(xt->ptimer);
 134
 135     if (xt->regs[R_TCSR] & TCSR_UDT)
 136         count = xt->regs[R_TLR];
 137     else
 138         count = ~0 - xt->regs[R_TLR];
 139     ptimer_set_limit(xt->ptimer, count, 1);
 140     ptimer_run(xt->ptimer, 1);
 141 }
 142
 143 static void
 144 timer_write(void *opaque, target_phys_addr_t addr,
 145             uint64_t val64, unsigned int size)
 146 {
 147     struct timerblock *t = opaque;
 148     struct xlx_timer *xt;
 149     unsigned int timer;
 150     uint32_t value = val64;
 151
 152     addr >>= 2;
 153     timer = timer_from_addr(addr);
 154     xt = &t->timers[timer];
 155     D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
 156              __func__, addr * 4, value, timer, addr & 3));
 157     /* Further decoding to address a specific timers reg.  */
 158     addr &= 3;
 159     switch (addr)
 160     {
 161         case R_TCSR:
 162             if (value & TCSR_TINT)
 163                 value &= ~TCSR_TINT;
 164
 165             xt->regs[addr] = value;
 166             if (value & TCSR_ENT)
 167                 timer_enable(xt);
 168             break;
 169
 170         default:
 171             if (addr < ARRAY_SIZE(xt->regs))
 172                 xt->regs[addr] = value;
 173             break;
 174     }
 175     timer_update_irq(t);
 176 }
 177
 178 static const MemoryRegionOps timer_ops = {
 179     .read = timer_read,
 180     .write = timer_write,
 181     .endianness = DEVICE_NATIVE_ENDIAN,
 182     .valid = {
 183         .min_access_size = 4,
 184         .max_access_size = 4
 185     }
 186 };
 187
 188 static void timer_hit(void *opaque)
 189 {
 190     struct xlx_timer *xt = opaque;
 191     struct timerblock *t = xt->parent;
 192     D(printf("%s %d\n", __func__, timer));
 193     xt->regs[R_TCSR] |= TCSR_TINT;
 194
 195     if (xt->regs[R_TCSR] & TCSR_ARHT)
 196         timer_enable(xt);
 197     timer_update_irq(t);
 198 }
 199
 200 static int xilinx_timer_init(SysBusDevice *dev)
 201 {
 202     struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
 203     unsigned int i;
 204
 205     /* All timers share a single irq line.  */
 206     sysbus_init_irq(dev, &t->irq);
 207
 208     /* Init all the ptimers.  */
 209     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
 210     for (i = 0; i < num_timers(t); i++) {
 211         struct xlx_timer *xt = &t->timers[i];
 212
 213         xt->parent = t;
 214         xt->nr = i;
 215         xt->bh = qemu_bh_new(timer_hit, xt);
 216         xt->ptimer = ptimer_init(xt->bh);
 217         ptimer_set_freq(xt->ptimer, t->freq_hz);
 218     }
 219
 220     memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx,xps-timer",
 221                           R_MAX * 4 * num_timers(t));
 222     sysbus_init_mmio(dev, &t->mmio);
 223     return 0;
 224 }
 225
 226 static Property xilinx_timer_properties[] = {
 227     DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   62 * 1000000),
 228     DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
 229     DEFINE_PROP_END_OF_LIST(),
 230 };
 231
 232 static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 233 {
 234     DeviceClass *dc = DEVICE_CLASS(klass);
 235     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 236
 237     k->init = xilinx_timer_init;
 238     dc->props = xilinx_timer_properties;
 239 }
 240
 241 static TypeInfo xilinx_timer_info = {
 242     .name          = "xlnx,xps-timer",
 243     .parent        = TYPE_SYS_BUS_DEVICE,
 244     .instance_size = sizeof(struct timerblock),
 245     .class_init    = xilinx_timer_class_init,
 246 };
 247
 248 static void xilinx_timer_register_types(void)
 249 {
 250     type_register_static(&xilinx_timer_info);
 251 }
 252
 253 type_init(xilinx_timer_register_types)