?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
xen: use uint64_t instead of target_ulong in cpu_ioreq_move
[qemu/ar7.git] / hw / nseries.c
blobaf287dd6dc7380e5bba0d00cfee9865b0e00d345
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "sysemu.h"
23 #include "omap.h"
24 #include "arm-misc.h"
25 #include "irq.h"
26 #include "console.h"
27 #include "boards.h"
28 #include "i2c.h"
29 #include "devices.h"
30 #include "flash.h"
31 #include "hw.h"
32 #include "bt.h"
33 #include "loader.h"
34 #include "blockdev.h"
35 #include "sysbus.h"
36
37 /* Nokia N8x0 support */
38 struct n800_s {
39 struct omap_mpu_state_s *cpu;
40
41 struct rfbi_chip_s blizzard;
42 struct {
43 void *opaque;
44 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
45 uWireSlave *chip;
46 } ts;
47 i2c_bus *i2c;
48
49 int keymap[0x80];
50 DeviceState *kbd;
51
52 DeviceState *usb;
53 void *retu;
54 void *tahvo;
55 DeviceState *nand;
56 };
57
58 /* GPIO pins */
59 #define N8X0_TUSB_ENABLE_GPIO 0
60 #define N800_MMC2_WP_GPIO 8
61 #define N800_UNKNOWN_GPIO0 9 /* out */
62 #define N810_MMC2_VIOSD_GPIO 9
63 #define N810_HEADSET_AMP_GPIO 10
64 #define N800_CAM_TURN_GPIO 12
65 #define N810_GPS_RESET_GPIO 12
66 #define N800_BLIZZARD_POWERDOWN_GPIO 15
67 #define N800_MMC1_WP_GPIO 23
68 #define N810_MMC2_VSD_GPIO 23
69 #define N8X0_ONENAND_GPIO 26
70 #define N810_BLIZZARD_RESET_GPIO 30
71 #define N800_UNKNOWN_GPIO2 53 /* out */
72 #define N8X0_TUSB_INT_GPIO 58
73 #define N8X0_BT_WKUP_GPIO 61
74 #define N8X0_STI_GPIO 62
75 #define N8X0_CBUS_SEL_GPIO 64
76 #define N8X0_CBUS_DAT_GPIO 65
77 #define N8X0_CBUS_CLK_GPIO 66
78 #define N8X0_WLAN_IRQ_GPIO 87
79 #define N8X0_BT_RESET_GPIO 92
80 #define N8X0_TEA5761_CS_GPIO 93
81 #define N800_UNKNOWN_GPIO 94
82 #define N810_TSC_RESET_GPIO 94
83 #define N800_CAM_ACT_GPIO 95
84 #define N810_GPS_WAKEUP_GPIO 95
85 #define N8X0_MMC_CS_GPIO 96
86 #define N8X0_WLAN_PWR_GPIO 97
87 #define N8X0_BT_HOST_WKUP_GPIO 98
88 #define N810_SPEAKER_AMP_GPIO 101
89 #define N810_KB_LOCK_GPIO 102
90 #define N800_TSC_TS_GPIO 103
91 #define N810_TSC_TS_GPIO 106
92 #define N8X0_HEADPHONE_GPIO 107
93 #define N8X0_RETU_GPIO 108
94 #define N800_TSC_KP_IRQ_GPIO 109
95 #define N810_KEYBOARD_GPIO 109
96 #define N800_BAT_COVER_GPIO 110
97 #define N810_SLIDE_GPIO 110
98 #define N8X0_TAHVO_GPIO 111
99 #define N800_UNKNOWN_GPIO4 112 /* out */
100 #define N810_SLEEPX_LED_GPIO 112
101 #define N800_TSC_RESET_GPIO 118 /* ? */
102 #define N810_AIC33_RESET_GPIO 118
103 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
104 #define N8X0_TMP105_GPIO 125
105
106 /* Config */
107 #define BT_UART 0
108 #define XLDR_LL_UART 1
109
110 /* Addresses on the I2C bus 0 */
111 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
112 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
113 #define N810_LP5521_ADDR 0x32 /* LEDs */
114 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
115 #define N810_LM8323_ADDR 0x45 /* Keyboard */
116 /* Addresses on the I2C bus 1 */
117 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
118 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
119
120 /* Chipselects on GPMC NOR interface */
121 #define N8X0_ONENAND_CS 0
122 #define N8X0_USB_ASYNC_CS 1
123 #define N8X0_USB_SYNC_CS 4
124
125 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
126
127 static void n800_mmc_cs_cb(void *opaque, int line, int level)
128 {
129 /* TODO: this seems to actually be connected to the menelaus, to
130 * which also both MMC slots connect. */
131 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
132
133 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
134 }
135
136 static void n8x0_gpio_setup(struct n800_s *s)
137 {
138 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
139 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
140
141 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
142 }
143
144 #define MAEMO_CAL_HEADER(...) \
145 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
146 __VA_ARGS__, \
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
148
149 static const uint8_t n8x0_cal_wlan_mac[] = {
150 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
151 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
152 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
153 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
154 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
155 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
156 };
157
158 static const uint8_t n8x0_cal_bt_id[] = {
159 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
160 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
161 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
162 N8X0_BD_ADDR,
163 };
164
165 static void n8x0_nand_setup(struct n800_s *s)
166 {
167 char *otp_region;
168 DriveInfo *dinfo;
169
170 s->nand = qdev_create(NULL, "onenand");
171 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
172 /* Either 0x40 or 0x48 are OK for the device ID */
173 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
174 qdev_prop_set_uint16(s->nand, "version_id", 0);
175 qdev_prop_set_int32(s->nand, "shift", 1);
176 dinfo = drive_get(IF_MTD, 0, 0);
177 if (dinfo && dinfo->bdrv) {
178 qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
179 }
180 qdev_init_nofail(s->nand);
181 sysbus_connect_irq(sysbus_from_qdev(s->nand), 0,
182 qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
183 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS,
184 sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0));
185 otp_region = onenand_raw_otp(s->nand);
186
187 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
188 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
189 /* XXX: in theory should also update the OOB for both pages */
190 }
191
192 static void n8x0_i2c_setup(struct n800_s *s)
193 {
194 DeviceState *dev;
195 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
196
197 /* Attach the CPU on one end of our I2C bus. */
198 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
199
200 /* Attach a menelaus PM chip */
201 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
202 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
203
204 /* Attach a TMP105 PM chip (A0 wired to ground) */
205 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
206 qdev_connect_gpio_out(dev, 0, tmp_irq);
207 }
208
209 /* Touchscreen and keypad controller */
210 static MouseTransformInfo n800_pointercal = {
211 .x = 800,
212 .y = 480,
213 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
214 };
215
216 static MouseTransformInfo n810_pointercal = {
217 .x = 800,
218 .y = 480,
219 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
220 };
221
222 #define RETU_KEYCODE 61 /* F3 */
223
224 static void n800_key_event(void *opaque, int keycode)
225 {
226 struct n800_s *s = (struct n800_s *) opaque;
227 int code = s->keymap[keycode & 0x7f];
228
229 if (code == -1) {
230 if ((keycode & 0x7f) == RETU_KEYCODE)
231 retu_key_event(s->retu, !(keycode & 0x80));
232 return;
233 }
234
235 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
236 }
237
238 static const int n800_keys[16] = {
239 -1,
240 72, /* Up */
241 63, /* Home (F5) */
242 -1,
243 75, /* Left */
244 28, /* Enter */
245 77, /* Right */
246 -1,
247 1, /* Cycle (ESC) */
248 80, /* Down */
249 62, /* Menu (F4) */
250 -1,
251 66, /* Zoom- (F8) */
252 64, /* FullScreen (F6) */
253 65, /* Zoom+ (F7) */
254 -1,
255 };
256
257 static void n800_tsc_kbd_setup(struct n800_s *s)
258 {
259 int i;
260
261 /* XXX: are the three pins inverted inside the chip between the
262 * tsc and the cpu (N4111)? */
263 qemu_irq penirq = NULL; /* NC */
264 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
265 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
266
267 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
268 s->ts.opaque = s->ts.chip->opaque;
269 s->ts.txrx = tsc210x_txrx;
270
271 for (i = 0; i < 0x80; i ++)
272 s->keymap[i] = -1;
273 for (i = 0; i < 0x10; i ++)
274 if (n800_keys[i] >= 0)
275 s->keymap[n800_keys[i]] = i;
276
277 qemu_add_kbd_event_handler(n800_key_event, s);
278
279 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
280 }
281
282 static void n810_tsc_setup(struct n800_s *s)
283 {
284 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
285
286 s->ts.opaque = tsc2005_init(pintdav);
287 s->ts.txrx = tsc2005_txrx;
288
289 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
290 }
291
292 /* N810 Keyboard controller */
293 static void n810_key_event(void *opaque, int keycode)
294 {
295 struct n800_s *s = (struct n800_s *) opaque;
296 int code = s->keymap[keycode & 0x7f];
297
298 if (code == -1) {
299 if ((keycode & 0x7f) == RETU_KEYCODE)
300 retu_key_event(s->retu, !(keycode & 0x80));
301 return;
302 }
303
304 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
305 }
306
307 #define M 0
308
309 static int n810_keys[0x80] = {
310 [0x01] = 16, /* Q */
311 [0x02] = 37, /* K */
312 [0x03] = 24, /* O */
313 [0x04] = 25, /* P */
314 [0x05] = 14, /* Backspace */
315 [0x06] = 30, /* A */
316 [0x07] = 31, /* S */
317 [0x08] = 32, /* D */
318 [0x09] = 33, /* F */
319 [0x0a] = 34, /* G */
320 [0x0b] = 35, /* H */
321 [0x0c] = 36, /* J */
322
323 [0x11] = 17, /* W */
324 [0x12] = 62, /* Menu (F4) */
325 [0x13] = 38, /* L */
326 [0x14] = 40, /* ' (Apostrophe) */
327 [0x16] = 44, /* Z */
328 [0x17] = 45, /* X */
329 [0x18] = 46, /* C */
330 [0x19] = 47, /* V */
331 [0x1a] = 48, /* B */
332 [0x1b] = 49, /* N */
333 [0x1c] = 42, /* Shift (Left shift) */
334 [0x1f] = 65, /* Zoom+ (F7) */
335
336 [0x21] = 18, /* E */
337 [0x22] = 39, /* ; (Semicolon) */
338 [0x23] = 12, /* - (Minus) */
339 [0x24] = 13, /* = (Equal) */
340 [0x2b] = 56, /* Fn (Left Alt) */
341 [0x2c] = 50, /* M */
342 [0x2f] = 66, /* Zoom- (F8) */
343
344 [0x31] = 19, /* R */
345 [0x32] = 29 | M, /* Right Ctrl */
346 [0x34] = 57, /* Space */
347 [0x35] = 51, /* , (Comma) */
348 [0x37] = 72 | M, /* Up */
349 [0x3c] = 82 | M, /* Compose (Insert) */
350 [0x3f] = 64, /* FullScreen (F6) */
351
352 [0x41] = 20, /* T */
353 [0x44] = 52, /* . (Dot) */
354 [0x46] = 77 | M, /* Right */
355 [0x4f] = 63, /* Home (F5) */
356 [0x51] = 21, /* Y */
357 [0x53] = 80 | M, /* Down */
358 [0x55] = 28, /* Enter */
359 [0x5f] = 1, /* Cycle (ESC) */
360
361 [0x61] = 22, /* U */
362 [0x64] = 75 | M, /* Left */
363
364 [0x71] = 23, /* I */
365 #if 0
366 [0x75] = 28 | M, /* KP Enter (KP Enter) */
367 #else
368 [0x75] = 15, /* KP Enter (Tab) */
369 #endif
370 };
371
372 #undef M
373
374 static void n810_kbd_setup(struct n800_s *s)
375 {
376 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
377 int i;
378
379 for (i = 0; i < 0x80; i ++)
380 s->keymap[i] = -1;
381 for (i = 0; i < 0x80; i ++)
382 if (n810_keys[i] > 0)
383 s->keymap[n810_keys[i]] = i;
384
385 qemu_add_kbd_event_handler(n810_key_event, s);
386
387 /* Attach the LM8322 keyboard to the I2C bus,
388 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
389 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
390 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
391 }
392
393 /* LCD MIPI DBI-C controller (URAL) */
394 struct mipid_s {
395 int resp[4];
396 int param[4];
397 int p;
398 int pm;
399 int cmd;
400
401 int sleep;
402 int booster;
403 int te;
404 int selfcheck;
405 int partial;
406 int normal;
407 int vscr;
408 int invert;
409 int onoff;
410 int gamma;
411 uint32_t id;
412 };
413
414 static void mipid_reset(struct mipid_s *s)
415 {
416 if (!s->sleep)
417 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
418
419 s->pm = 0;
420 s->cmd = 0;
421
422 s->sleep = 1;
423 s->booster = 0;
424 s->selfcheck =
425 (1 << 7) | /* Register loading OK. */
426 (1 << 5) | /* The chip is attached. */
427 (1 << 4); /* Display glass still in one piece. */
428 s->te = 0;
429 s->partial = 0;
430 s->normal = 1;
431 s->vscr = 0;
432 s->invert = 0;
433 s->onoff = 1;
434 s->gamma = 0;
435 }
436
437 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
438 {
439 struct mipid_s *s = (struct mipid_s *) opaque;
440 uint8_t ret;
441
442 if (len > 9)
443 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
444
445 if (s->p >= ARRAY_SIZE(s->resp))
446 ret = 0;
447 else
448 ret = s->resp[s->p ++];
449 if (s->pm --> 0)
450 s->param[s->pm] = cmd;
451 else
452 s->cmd = cmd;
453
454 switch (s->cmd) {
455 case 0x00: /* NOP */
456 break;
457
458 case 0x01: /* SWRESET */
459 mipid_reset(s);
460 break;
461
462 case 0x02: /* BSTROFF */
463 s->booster = 0;
464 break;
465 case 0x03: /* BSTRON */
466 s->booster = 1;
467 break;
468
469 case 0x04: /* RDDID */
470 s->p = 0;
471 s->resp[0] = (s->id >> 16) & 0xff;
472 s->resp[1] = (s->id >> 8) & 0xff;
473 s->resp[2] = (s->id >> 0) & 0xff;
474 break;
475
476 case 0x06: /* RD_RED */
477 case 0x07: /* RD_GREEN */
478 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
479 * for the bootloader one needs to change this. */
480 case 0x08: /* RD_BLUE */
481 s->p = 0;
482 /* TODO: return first pixel components */
483 s->resp[0] = 0x01;
484 break;
485
486 case 0x09: /* RDDST */
487 s->p = 0;
488 s->resp[0] = s->booster << 7;
489 s->resp[1] = (5 << 4) | (s->partial << 2) |
490 (s->sleep << 1) | s->normal;
491 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
492 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
493 s->resp[3] = s->gamma << 6;
494 break;
495
496 case 0x0a: /* RDDPM */
497 s->p = 0;
498 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
499 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
500 break;
501 case 0x0b: /* RDDMADCTR */
502 s->p = 0;
503 s->resp[0] = 0;
504 break;
505 case 0x0c: /* RDDCOLMOD */
506 s->p = 0;
507 s->resp[0] = 5; /* 65K colours */
508 break;
509 case 0x0d: /* RDDIM */
510 s->p = 0;
511 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
512 break;
513 case 0x0e: /* RDDSM */
514 s->p = 0;
515 s->resp[0] = s->te << 7;
516 break;
517 case 0x0f: /* RDDSDR */
518 s->p = 0;
519 s->resp[0] = s->selfcheck;
520 break;
521
522 case 0x10: /* SLPIN */
523 s->sleep = 1;
524 break;
525 case 0x11: /* SLPOUT */
526 s->sleep = 0;
527 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
528 break;
529
530 case 0x12: /* PTLON */
531 s->partial = 1;
532 s->normal = 0;
533 s->vscr = 0;
534 break;
535 case 0x13: /* NORON */
536 s->partial = 0;
537 s->normal = 1;
538 s->vscr = 0;
539 break;
540
541 case 0x20: /* INVOFF */
542 s->invert = 0;
543 break;
544 case 0x21: /* INVON */
545 s->invert = 1;
546 break;
547
548 case 0x22: /* APOFF */
549 case 0x23: /* APON */
550 goto bad_cmd;
551
552 case 0x25: /* WRCNTR */
553 if (s->pm < 0)
554 s->pm = 1;
555 goto bad_cmd;
556
557 case 0x26: /* GAMSET */
558 if (!s->pm)
559 s->gamma = ffs(s->param[0] & 0xf) - 1;
560 else if (s->pm < 0)
561 s->pm = 1;
562 break;
563
564 case 0x28: /* DISPOFF */
565 s->onoff = 0;
566 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
567 break;
568 case 0x29: /* DISPON */
569 s->onoff = 1;
570 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
571 break;
572
573 case 0x2a: /* CASET */
574 case 0x2b: /* RASET */
575 case 0x2c: /* RAMWR */
576 case 0x2d: /* RGBSET */
577 case 0x2e: /* RAMRD */
578 case 0x30: /* PTLAR */
579 case 0x33: /* SCRLAR */
580 goto bad_cmd;
581
582 case 0x34: /* TEOFF */
583 s->te = 0;
584 break;
585 case 0x35: /* TEON */
586 if (!s->pm)
587 s->te = 1;
588 else if (s->pm < 0)
589 s->pm = 1;
590 break;
591
592 case 0x36: /* MADCTR */
593 goto bad_cmd;
594
595 case 0x37: /* VSCSAD */
596 s->partial = 0;
597 s->normal = 0;
598 s->vscr = 1;
599 break;
600
601 case 0x38: /* IDMOFF */
602 case 0x39: /* IDMON */
603 case 0x3a: /* COLMOD */
604 goto bad_cmd;
605
606 case 0xb0: /* CLKINT / DISCTL */
607 case 0xb1: /* CLKEXT */
608 if (s->pm < 0)
609 s->pm = 2;
610 break;
611
612 case 0xb4: /* FRMSEL */
613 break;
614
615 case 0xb5: /* FRM8SEL */
616 case 0xb6: /* TMPRNG / INIESC */
617 case 0xb7: /* TMPHIS / NOP2 */
618 case 0xb8: /* TMPREAD / MADCTL */
619 case 0xba: /* DISTCTR */
620 case 0xbb: /* EPVOL */
621 goto bad_cmd;
622
623 case 0xbd: /* Unknown */
624 s->p = 0;
625 s->resp[0] = 0;
626 s->resp[1] = 1;
627 break;
628
629 case 0xc2: /* IFMOD */
630 if (s->pm < 0)
631 s->pm = 2;
632 break;
633
634 case 0xc6: /* PWRCTL */
635 case 0xc7: /* PPWRCTL */
636 case 0xd0: /* EPWROUT */
637 case 0xd1: /* EPWRIN */
638 case 0xd4: /* RDEV */
639 case 0xd5: /* RDRR */
640 goto bad_cmd;
641
642 case 0xda: /* RDID1 */
643 s->p = 0;
644 s->resp[0] = (s->id >> 16) & 0xff;
645 break;
646 case 0xdb: /* RDID2 */
647 s->p = 0;
648 s->resp[0] = (s->id >> 8) & 0xff;
649 break;
650 case 0xdc: /* RDID3 */
651 s->p = 0;
652 s->resp[0] = (s->id >> 0) & 0xff;
653 break;
654
655 default:
656 bad_cmd:
657 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
658 break;
659 }
660
661 return ret;
662 }
663
664 static void *mipid_init(void)
665 {
666 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
667
668 s->id = 0x838f03;
669 mipid_reset(s);
670
671 return s;
672 }
673
674 static void n8x0_spi_setup(struct n800_s *s)
675 {
676 void *tsc = s->ts.opaque;
677 void *mipid = mipid_init();
678
679 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
680 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
681 }
682
683 /* This task is normally performed by the bootloader. If we're loading
684 * a kernel directly, we need to enable the Blizzard ourselves. */
685 static void n800_dss_init(struct rfbi_chip_s *chip)
686 {
687 uint8_t *fb_blank;
688
689 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
690 chip->write(chip->opaque, 1, 0x64);
691 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
692 chip->write(chip->opaque, 1, 0x1e);
693 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
694 chip->write(chip->opaque, 1, 0xe0);
695 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
696 chip->write(chip->opaque, 1, 0x01);
697 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
698 chip->write(chip->opaque, 1, 0x06);
699 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
700 chip->write(chip->opaque, 1, 1); /* Enable bit */
701
702 chip->write(chip->opaque, 0, 0x6c);
703 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
704 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
705 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
706 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
707 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
708 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
709 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
710 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
711 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
712 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
713 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
714 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
715 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
716 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
717 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
718 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
719 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
720 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
721
722 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
723 /* Display Memory Data Port */
724 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
725 g_free(fb_blank);
726 }
727
728 static void n8x0_dss_setup(struct n800_s *s)
729 {
730 s->blizzard.opaque = s1d13745_init(NULL);
731 s->blizzard.block = s1d13745_write_block;
732 s->blizzard.write = s1d13745_write;
733 s->blizzard.read = s1d13745_read;
734
735 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
736 }
737
738 static void n8x0_cbus_setup(struct n800_s *s)
739 {
740 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
741 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
742 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
743
744 CBus *cbus = cbus_init(dat_out);
745
746 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
747 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
748 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
749
750 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
751 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
752 }
753
754 static void n8x0_uart_setup(struct n800_s *s)
755 {
756 CharDriverState *radio = uart_hci_init(
757 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
758
759 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
760 csrhci_pins_get(radio)[csrhci_pin_reset]);
761 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
762 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
763
764 omap_uart_attach(s->cpu->uart[BT_UART], radio);
765 }
766
767 static void n8x0_usb_setup(struct n800_s *s)
768 {
769 SysBusDevice *dev;
770 s->usb = qdev_create(NULL, "tusb6010");
771 dev = sysbus_from_qdev(s->usb);
772 qdev_init_nofail(s->usb);
773 sysbus_connect_irq(dev, 0,
774 qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO));
775 /* Using the NOR interface */
776 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
777 sysbus_mmio_get_region(dev, 0));
778 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
779 sysbus_mmio_get_region(dev, 1));
780 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO,
781 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
782 }
783
784 /* Setup done before the main bootloader starts by some early setup code
785 * - used when we want to run the main bootloader in emulation. This
786 * isn't documented. */
787 static uint32_t n800_pinout[104] = {
788 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
789 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
790 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
791 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
792 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
793 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
794 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
795 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
796 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
797 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
798 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
799 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
800 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
801 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
802 0x00000000, 0x00000038, 0x00340000, 0x00000000,
803 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
804 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
805 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
806 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
807 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
808 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
809 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
810 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
811 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
812 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
813 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
814 };
815
816 static void n800_setup_nolo_tags(void *sram_base)
817 {
818 int i;
819 uint32_t *p = sram_base + 0x8000;
820 uint32_t *v = sram_base + 0xa000;
821
822 memset(p, 0, 0x3000);
823
824 strcpy((void *) (p + 0), "QEMU N800");
825
826 strcpy((void *) (p + 8), "F5");
827
828 stl_raw(p + 10, 0x04f70000);
829 strcpy((void *) (p + 9), "RX-34");
830
831 /* RAM size in MB? */
832 stl_raw(p + 12, 0x80);
833
834 /* Pointer to the list of tags */
835 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
836
837 /* The NOLO tags start here */
838 p = sram_base + 0x9000;
839 #define ADD_TAG(tag, len) \
840 stw_raw((uint16_t *) p + 0, tag); \
841 stw_raw((uint16_t *) p + 1, len); p ++; \
842 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
843
844 /* OMAP STI console? Pin out settings? */
845 ADD_TAG(0x6e01, 414);
846 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
847 stl_raw(v ++, n800_pinout[i]);
848
849 /* Kernel memsize? */
850 ADD_TAG(0x6e05, 1);
851 stl_raw(v ++, 2);
852
853 /* NOLO serial console */
854 ADD_TAG(0x6e02, 4);
855 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
856
857 #if 0
858 /* CBUS settings (Retu/AVilma) */
859 ADD_TAG(0x6e03, 6);
860 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
861 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
862 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
863 v += 2;
864 #endif
865
866 /* Nokia ASIC BB5 (Retu/Tahvo) */
867 ADD_TAG(0x6e0a, 4);
868 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
869 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
870 v ++;
871
872 /* LCD console? */
873 ADD_TAG(0x6e04, 4);
874 stw_raw((uint16_t *) v + 0, 30); /* ??? */
875 stw_raw((uint16_t *) v + 1, 24); /* ??? */
876 v ++;
877
878 #if 0
879 /* LCD settings */
880 ADD_TAG(0x6e06, 2);
881 stw_raw((uint16_t *) (v ++), 15); /* ??? */
882 #endif
883
884 /* I^2C (Menelaus) */
885 ADD_TAG(0x6e07, 4);
886 stl_raw(v ++, 0x00720000); /* ??? */
887
888 /* Unknown */
889 ADD_TAG(0x6e0b, 6);
890 stw_raw((uint16_t *) v + 0, 94); /* ??? */
891 stw_raw((uint16_t *) v + 1, 23); /* ??? */
892 stw_raw((uint16_t *) v + 2, 0); /* ??? */
893 v += 2;
894
895 /* OMAP gpio switch info */
896 ADD_TAG(0x6e0c, 80);
897 strcpy((void *) v, "bat_cover"); v += 3;
898 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
899 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
900 v += 2;
901 strcpy((void *) v, "cam_act"); v += 3;
902 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
903 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
904 v += 2;
905 strcpy((void *) v, "cam_turn"); v += 3;
906 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
907 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
908 v += 2;
909 strcpy((void *) v, "headphone"); v += 3;
910 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
911 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
912 v += 2;
913
914 /* Bluetooth */
915 ADD_TAG(0x6e0e, 12);
916 stl_raw(v ++, 0x5c623d01); /* ??? */
917 stl_raw(v ++, 0x00000201); /* ??? */
918 stl_raw(v ++, 0x00000000); /* ??? */
919
920 /* CX3110x WLAN settings */
921 ADD_TAG(0x6e0f, 8);
922 stl_raw(v ++, 0x00610025); /* ??? */
923 stl_raw(v ++, 0xffff0057); /* ??? */
924
925 /* MMC host settings */
926 ADD_TAG(0x6e10, 12);
927 stl_raw(v ++, 0xffff000f); /* ??? */
928 stl_raw(v ++, 0xffffffff); /* ??? */
929 stl_raw(v ++, 0x00000060); /* ??? */
930
931 /* OneNAND chip select */
932 ADD_TAG(0x6e11, 10);
933 stl_raw(v ++, 0x00000401); /* ??? */
934 stl_raw(v ++, 0x0002003a); /* ??? */
935 stl_raw(v ++, 0x00000002); /* ??? */
936
937 /* TEA5761 sensor settings */
938 ADD_TAG(0x6e12, 2);
939 stl_raw(v ++, 93); /* GPIO num ??? */
940
941 #if 0
942 /* Unknown tag */
943 ADD_TAG(6e09, 0);
944
945 /* Kernel UART / console */
946 ADD_TAG(6e12, 0);
947 #endif
948
949 /* End of the list */
950 stl_raw(p ++, 0x00000000);
951 stl_raw(p ++, 0x00000000);
952 }
953
954 /* This task is normally performed by the bootloader. If we're loading
955 * a kernel directly, we need to set up GPMC mappings ourselves. */
956 static void n800_gpmc_init(struct n800_s *s)
957 {
958 uint32_t config7 =
959 (0xf << 8) | /* MASKADDRESS */
960 (1 << 6) | /* CSVALID */
961 (4 << 0); /* BASEADDRESS */
962
963 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
964 (void *) &config7, sizeof(config7));
965 }
966
967 /* Setup sequence done by the bootloader */
968 static void n8x0_boot_init(void *opaque)
969 {
970 struct n800_s *s = (struct n800_s *) opaque;
971 uint32_t buf;
972
973 /* PRCM setup */
974 #define omap_writel(addr, val) \
975 buf = (val); \
976 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
977
978 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
979 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
980 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
981 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
982 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
983 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
984 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
985 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
986 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
987 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
988 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
989 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
990 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
991 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
992 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
993 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
994 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
995 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
996 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
997 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
998 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
999 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1000 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1001 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1002 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1003 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1004 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1005 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1006 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1007 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1008 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1009 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1010 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1011 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1012 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1013 (0x78 << 12) | (6 << 8));
1014 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1015
1016 /* GPMC setup */
1017 n800_gpmc_init(s);
1018
1019 /* Video setup */
1020 n800_dss_init(&s->blizzard);
1021
1022 /* CPU setup */
1023 s->cpu->env->GE = 0x5;
1024
1025 /* If the machine has a slided keyboard, open it */
1026 if (s->kbd)
1027 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
1028 }
1029
1030 #define OMAP_TAG_NOKIA_BT 0x4e01
1031 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1032 #define OMAP_TAG_CBUS 0x4e03
1033 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1034
1035 static struct omap_gpiosw_info_s {
1036 const char *name;
1037 int line;
1038 int type;
1039 } n800_gpiosw_info[] = {
1040 {
1041 "bat_cover", N800_BAT_COVER_GPIO,
1042 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1043 }, {
1044 "cam_act", N800_CAM_ACT_GPIO,
1045 OMAP_GPIOSW_TYPE_ACTIVITY,
1046 }, {
1047 "cam_turn", N800_CAM_TURN_GPIO,
1048 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1049 }, {
1050 "headphone", N8X0_HEADPHONE_GPIO,
1051 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1052 },
1053 { NULL }
1054 }, n810_gpiosw_info[] = {
1055 {
1056 "gps_reset", N810_GPS_RESET_GPIO,
1057 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1058 }, {
1059 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1060 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1061 }, {
1062 "headphone", N8X0_HEADPHONE_GPIO,
1063 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1064 }, {
1065 "kb_lock", N810_KB_LOCK_GPIO,
1066 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1067 }, {
1068 "sleepx_led", N810_SLEEPX_LED_GPIO,
1069 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1070 }, {
1071 "slide", N810_SLIDE_GPIO,
1072 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1073 },
1074 { NULL }
1075 };
1076
1077 static struct omap_partition_info_s {
1078 uint32_t offset;
1079 uint32_t size;
1080 int mask;
1081 const char *name;
1082 } n800_part_info[] = {
1083 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1084 { 0x00020000, 0x00060000, 0x0, "config" },
1085 { 0x00080000, 0x00200000, 0x0, "kernel" },
1086 { 0x00280000, 0x00200000, 0x3, "initfs" },
1087 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1088
1089 { 0, 0, 0, NULL }
1090 }, n810_part_info[] = {
1091 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1092 { 0x00020000, 0x00060000, 0x0, "config" },
1093 { 0x00080000, 0x00220000, 0x0, "kernel" },
1094 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1095 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1096
1097 { 0, 0, 0, NULL }
1098 };
1099
1100 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1101
1102 static int n8x0_atag_setup(void *p, int model)
1103 {
1104 uint8_t *b;
1105 uint16_t *w;
1106 uint32_t *l;
1107 struct omap_gpiosw_info_s *gpiosw;
1108 struct omap_partition_info_s *partition;
1109 const char *tag;
1110
1111 w = p;
1112
1113 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1114 stw_raw(w ++, 4); /* u16 len */
1115 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1116 w ++;
1117
1118 #if 0
1119 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1120 stw_raw(w ++, 4); /* u16 len */
1121 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1122 stw_raw(w ++, 115200); /* u32 console_speed */
1123 #endif
1124
1125 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1126 stw_raw(w ++, 36); /* u16 len */
1127 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1128 w += 8;
1129 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1130 w += 8;
1131 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1132 stw_raw(w ++, 24); /* u8 data_lines */
1133
1134 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1135 stw_raw(w ++, 8); /* u16 len */
1136 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1137 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1138 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1139 w ++;
1140
1141 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1142 stw_raw(w ++, 4); /* u16 len */
1143 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1144 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1145
1146 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1147 for (; gpiosw->name; gpiosw ++) {
1148 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1149 stw_raw(w ++, 20); /* u16 len */
1150 strcpy((void *) w, gpiosw->name); /* char name[12] */
1151 w += 6;
1152 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1153 stw_raw(w ++, gpiosw->type);
1154 stw_raw(w ++, 0);
1155 stw_raw(w ++, 0);
1156 }
1157
1158 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1159 stw_raw(w ++, 12); /* u16 len */
1160 b = (void *) w;
1161 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1162 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1163 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1164 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1165 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1166 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1167 b += 6;
1168 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1169 w = (void *) b;
1170
1171 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1172 stw_raw(w ++, 8); /* u16 len */
1173 stw_raw(w ++, 0x25); /* u8 chip_type */
1174 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1175 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1176 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1177
1178 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1179 stw_raw(w ++, 16); /* u16 len */
1180 if (model == 810) {
1181 stw_raw(w ++, 0x23f); /* unsigned flags */
1182 stw_raw(w ++, -1); /* s16 power_pin */
1183 stw_raw(w ++, -1); /* s16 switch_pin */
1184 stw_raw(w ++, -1); /* s16 wp_pin */
1185 stw_raw(w ++, 0x240); /* unsigned flags */
1186 stw_raw(w ++, 0xc000); /* s16 power_pin */
1187 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1188 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1189 } else {
1190 stw_raw(w ++, 0xf); /* unsigned flags */
1191 stw_raw(w ++, -1); /* s16 power_pin */
1192 stw_raw(w ++, -1); /* s16 switch_pin */
1193 stw_raw(w ++, -1); /* s16 wp_pin */
1194 stw_raw(w ++, 0); /* unsigned flags */
1195 stw_raw(w ++, 0); /* s16 power_pin */
1196 stw_raw(w ++, 0); /* s16 switch_pin */
1197 stw_raw(w ++, 0); /* s16 wp_pin */
1198 }
1199
1200 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1201 stw_raw(w ++, 4); /* u16 len */
1202 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1203 w ++;
1204
1205 partition = (model == 810) ? n810_part_info : n800_part_info;
1206 for (; partition->name; partition ++) {
1207 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1208 stw_raw(w ++, 28); /* u16 len */
1209 strcpy((void *) w, partition->name); /* char name[16] */
1210 l = (void *) (w + 8);
1211 stl_raw(l ++, partition->size); /* unsigned int size */
1212 stl_raw(l ++, partition->offset); /* unsigned int offset */
1213 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1214 w = (void *) l;
1215 }
1216
1217 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1218 stw_raw(w ++, 12); /* u16 len */
1219 #if 0
1220 strcpy((void *) w, "por"); /* char reason_str[12] */
1221 strcpy((void *) w, "charger"); /* char reason_str[12] */
1222 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1223 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1224 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1225 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1226 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1227 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1228 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1229 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1230 #else
1231 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1232 #endif
1233 w += 6;
1234
1235 tag = (model == 810) ? "RX-44" : "RX-34";
1236 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1237 stw_raw(w ++, 24); /* u16 len */
1238 strcpy((void *) w, "product"); /* char component[12] */
1239 w += 6;
1240 strcpy((void *) w, tag); /* char version[12] */
1241 w += 6;
1242
1243 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1244 stw_raw(w ++, 24); /* u16 len */
1245 strcpy((void *) w, "hw-build"); /* char component[12] */
1246 w += 6;
1247 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1248 w += 6;
1249
1250 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1251 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1252 stw_raw(w ++, 24); /* u16 len */
1253 strcpy((void *) w, "nolo"); /* char component[12] */
1254 w += 6;
1255 strcpy((void *) w, tag); /* char version[12] */
1256 w += 6;
1257
1258 return (void *) w - p;
1259 }
1260
1261 static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1262 {
1263 return n8x0_atag_setup(p, 800);
1264 }
1265
1266 static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1267 {
1268 return n8x0_atag_setup(p, 810);
1269 }
1270
1271 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1272 const char *kernel_filename,
1273 const char *kernel_cmdline, const char *initrd_filename,
1274 const char *cpu_model, struct arm_boot_info *binfo, int model)
1275 {
1276 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1277 int sdram_size = binfo->ram_size;
1278 DisplayState *ds;
1279
1280 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
1281
1282 /* Setup peripherals
1283 *
1284 * Believed external peripherals layout in the N810:
1285 * (spi bus 1)
1286 * tsc2005
1287 * lcd_mipid
1288 * (spi bus 2)
1289 * Conexant cx3110x (WLAN)
1290 * optional: pc2400m (WiMAX)
1291 * (i2c bus 0)
1292 * TLV320AIC33 (audio codec)
1293 * TCM825x (camera by Toshiba)
1294 * lp5521 (clever LEDs)
1295 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1296 * lm8323 (keypad, manf 00, rev 04)
1297 * (i2c bus 1)
1298 * tmp105 (temperature sensor, hwmon)
1299 * menelaus (pm)
1300 * (somewhere on i2c - maybe N800-only)
1301 * tea5761 (FM tuner)
1302 * (serial 0)
1303 * GPS
1304 * (some serial port)
1305 * csr41814 (Bluetooth)
1306 */
1307 n8x0_gpio_setup(s);
1308 n8x0_nand_setup(s);
1309 n8x0_i2c_setup(s);
1310 if (model == 800)
1311 n800_tsc_kbd_setup(s);
1312 else if (model == 810) {
1313 n810_tsc_setup(s);
1314 n810_kbd_setup(s);
1315 }
1316 n8x0_spi_setup(s);
1317 n8x0_dss_setup(s);
1318 n8x0_cbus_setup(s);
1319 n8x0_uart_setup(s);
1320 if (usb_enabled)
1321 n8x0_usb_setup(s);
1322
1323 if (kernel_filename) {
1324 /* Or at the linux loader. */
1325 binfo->kernel_filename = kernel_filename;
1326 binfo->kernel_cmdline = kernel_cmdline;
1327 binfo->initrd_filename = initrd_filename;
1328 arm_load_kernel(s->cpu->env, binfo);
1329
1330 qemu_register_reset(n8x0_boot_init, s);
1331 }
1332
1333 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
1334 int rom_size;
1335 uint8_t nolo_tags[0x10000];
1336 /* No, wait, better start at the ROM. */
1337 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1338
1339 /* This is intended for loading the `secondary.bin' program from
1340 * Nokia images (the NOLO bootloader). The entry point seems
1341 * to be at OMAP2_Q2_BASE + 0x400000.
1342 *
1343 * The `2nd.bin' files contain some kind of earlier boot code and
1344 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1345 *
1346 * The code above is for loading the `zImage' file from Nokia
1347 * images. */
1348 rom_size = load_image_targphys(option_rom[0].name,
1349 OMAP2_Q2_BASE + 0x400000,
1350 sdram_size - 0x400000);
1351 printf("%i bytes of image loaded\n", rom_size);
1352
1353 n800_setup_nolo_tags(nolo_tags);
1354 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1355 }
1356 /* FIXME: We shouldn't really be doing this here. The LCD controller
1357 will set the size once configured, so this just sets an initial
1358 size until the guest activates the display. */
1359 ds = get_displaystate();
1360 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
1361 dpy_resize(ds);
1362 }
1363
1364 static struct arm_boot_info n800_binfo = {
1365 .loader_start = OMAP2_Q2_BASE,
1366 /* Actually two chips of 0x4000000 bytes each */
1367 .ram_size = 0x08000000,
1368 .board_id = 0x4f7,
1369 .atag_board = n800_atag_setup,
1370 };
1371
1372 static struct arm_boot_info n810_binfo = {
1373 .loader_start = OMAP2_Q2_BASE,
1374 /* Actually two chips of 0x4000000 bytes each */
1375 .ram_size = 0x08000000,
1376 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1377 * used by some older versions of the bootloader and 5555 is used
1378 * instead (including versions that shipped with many devices). */
1379 .board_id = 0x60c,
1380 .atag_board = n810_atag_setup,
1381 };
1382
1383 static void n800_init(ram_addr_t ram_size,
1384 const char *boot_device,
1385 const char *kernel_filename, const char *kernel_cmdline,
1386 const char *initrd_filename, const char *cpu_model)
1387 {
1388 return n8x0_init(ram_size, boot_device,
1389 kernel_filename, kernel_cmdline, initrd_filename,
1390 cpu_model, &n800_binfo, 800);
1391 }
1392
1393 static void n810_init(ram_addr_t ram_size,
1394 const char *boot_device,
1395 const char *kernel_filename, const char *kernel_cmdline,
1396 const char *initrd_filename, const char *cpu_model)
1397 {
1398 return n8x0_init(ram_size, boot_device,
1399 kernel_filename, kernel_cmdline, initrd_filename,
1400 cpu_model, &n810_binfo, 810);
1401 }
1402
1403 static QEMUMachine n800_machine = {
1404 .name = "n800",
1405 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1406 .init = n800_init,
1407 };
1408
1409 static QEMUMachine n810_machine = {
1410 .name = "n810",
1411 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1412 .init = n810_init,
1413 };
1414
1415 static void nseries_machine_init(void)
1416 {
1417 qemu_register_machine(&n800_machine);
1418 qemu_register_machine(&n810_machine);
1419 }
1420
1421 machine_init(nseries_machine_init);
AR7 emulation for QEMU