2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
15 #include <linux/kvm.h>
17 #include "qemu-common.h"
20 #include "qemu/error-report.h"
21 #include "qemu/timer.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/kvm.h"
24 #include "sysemu/cpus.h"
26 #include "exec/memattrs.h"
30 #define DPRINTF(fmt, ...) \
31 do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
33 static int kvm_mips_fpu_cap
;
34 static int kvm_mips_msa_cap
;
36 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
40 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
);
42 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
47 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
49 /* MIPS has 128 signals */
50 kvm_set_sigmask_len(s
, 16);
52 kvm_mips_fpu_cap
= kvm_check_extension(s
, KVM_CAP_MIPS_FPU
);
53 kvm_mips_msa_cap
= kvm_check_extension(s
, KVM_CAP_MIPS_MSA
);
55 DPRINTF("%s\n", __func__
);
59 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
64 int kvm_arch_init_vcpu(CPUState
*cs
)
66 MIPSCPU
*cpu
= MIPS_CPU(cs
);
67 CPUMIPSState
*env
= &cpu
->env
;
70 qemu_add_vm_change_state_handler(kvm_mips_update_state
, cs
);
72 if (kvm_mips_fpu_cap
&& env
->CP0_Config1
& (1 << CP0C1_FP
)) {
73 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_MIPS_FPU
, 0, 0);
75 /* mark unsupported so it gets disabled on reset */
81 if (kvm_mips_msa_cap
&& env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
82 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_MIPS_MSA
, 0, 0);
84 /* mark unsupported so it gets disabled on reset */
90 DPRINTF("%s\n", __func__
);
94 int kvm_arch_destroy_vcpu(CPUState
*cs
)
99 void kvm_mips_reset_vcpu(MIPSCPU
*cpu
)
101 CPUMIPSState
*env
= &cpu
->env
;
103 if (!kvm_mips_fpu_cap
&& env
->CP0_Config1
& (1 << CP0C1_FP
)) {
104 warn_report("KVM does not support FPU, disabling");
105 env
->CP0_Config1
&= ~(1 << CP0C1_FP
);
107 if (!kvm_mips_msa_cap
&& env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
108 warn_report("KVM does not support MSA, disabling");
109 env
->CP0_Config3
&= ~(1 << CP0C3_MSAP
);
112 DPRINTF("%s\n", __func__
);
115 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
117 DPRINTF("%s\n", __func__
);
121 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
123 DPRINTF("%s\n", __func__
);
127 static inline int cpu_mips_io_interrupts_pending(MIPSCPU
*cpu
)
129 CPUMIPSState
*env
= &cpu
->env
;
131 return env
->CP0_Cause
& (0x1 << (2 + CP0Ca_IP
));
135 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
137 MIPSCPU
*cpu
= MIPS_CPU(cs
);
139 struct kvm_mips_interrupt intr
;
141 qemu_mutex_lock_iothread();
143 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
144 cpu_mips_io_interrupts_pending(cpu
)) {
147 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
149 error_report("%s: cpu %d: failed to inject IRQ %x",
150 __func__
, cs
->cpu_index
, intr
.irq
);
154 qemu_mutex_unlock_iothread();
157 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
159 return MEMTXATTRS_UNSPECIFIED
;
162 int kvm_arch_process_async_events(CPUState
*cs
)
167 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
171 DPRINTF("%s\n", __func__
);
172 switch (run
->exit_reason
) {
174 error_report("%s: unknown exit reason %d",
175 __func__
, run
->exit_reason
);
183 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
185 DPRINTF("%s\n", __func__
);
189 void kvm_arch_init_irq_routing(KVMState
*s
)
193 int kvm_mips_set_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
195 CPUState
*cs
= CPU(cpu
);
196 struct kvm_mips_interrupt intr
;
198 if (!kvm_enabled()) {
210 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
215 int kvm_mips_set_ipi_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
217 CPUState
*cs
= current_cpu
;
218 CPUState
*dest_cs
= CPU(cpu
);
219 struct kvm_mips_interrupt intr
;
221 if (!kvm_enabled()) {
225 intr
.cpu
= dest_cs
->cpu_index
;
233 DPRINTF("%s: CPU %d, IRQ: %d\n", __func__
, intr
.cpu
, intr
.irq
);
235 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
240 #define MIPS_CP0_32(_R, _S) \
241 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
243 #define MIPS_CP0_64(_R, _S) \
244 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
246 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
247 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
248 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
249 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
250 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
251 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
252 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
253 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
254 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
255 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
256 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
257 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
258 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
259 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
260 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
261 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
262 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
263 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
264 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
265 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
266 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
268 static inline int kvm_mips_put_one_reg(CPUState
*cs
, uint64_t reg_id
,
271 struct kvm_one_reg cp0reg
= {
273 .addr
= (uintptr_t)addr
276 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
279 static inline int kvm_mips_put_one_ureg(CPUState
*cs
, uint64_t reg_id
,
282 struct kvm_one_reg cp0reg
= {
284 .addr
= (uintptr_t)addr
287 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
290 static inline int kvm_mips_put_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
293 uint64_t val64
= *addr
;
294 struct kvm_one_reg cp0reg
= {
296 .addr
= (uintptr_t)&val64
299 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
302 static inline int kvm_mips_put_one_reg64(CPUState
*cs
, uint64_t reg_id
,
305 struct kvm_one_reg cp0reg
= {
307 .addr
= (uintptr_t)addr
310 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
313 static inline int kvm_mips_put_one_ureg64(CPUState
*cs
, uint64_t reg_id
,
316 struct kvm_one_reg cp0reg
= {
318 .addr
= (uintptr_t)addr
321 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
324 static inline int kvm_mips_get_one_reg(CPUState
*cs
, uint64_t reg_id
,
327 struct kvm_one_reg cp0reg
= {
329 .addr
= (uintptr_t)addr
332 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
335 static inline int kvm_mips_get_one_ureg(CPUState
*cs
, uint64_t reg_id
,
338 struct kvm_one_reg cp0reg
= {
340 .addr
= (uintptr_t)addr
343 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
346 static inline int kvm_mips_get_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
351 struct kvm_one_reg cp0reg
= {
353 .addr
= (uintptr_t)&val64
356 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
363 static inline int kvm_mips_get_one_reg64(CPUState
*cs
, uint64_t reg_id
,
366 struct kvm_one_reg cp0reg
= {
368 .addr
= (uintptr_t)addr
371 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
374 static inline int kvm_mips_get_one_ureg64(CPUState
*cs
, uint64_t reg_id
,
377 struct kvm_one_reg cp0reg
= {
379 .addr
= (uintptr_t)addr
382 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
385 #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M)
386 #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \
388 #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M)
389 #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \
391 #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M)
392 #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \
393 (1U << CP0C5_UFE) | \
394 (1U << CP0C5_FRE) | \
397 static inline int kvm_mips_change_one_reg(CPUState
*cs
, uint64_t reg_id
,
398 int32_t *addr
, int32_t mask
)
403 err
= kvm_mips_get_one_reg(cs
, reg_id
, &tmp
);
408 /* only change bits in mask */
409 change
= (*addr
^ tmp
) & mask
;
415 return kvm_mips_put_one_reg(cs
, reg_id
, &tmp
);
419 * We freeze the KVM timer when either the VM clock is stopped or the state is
420 * saved (the state is dirty).
424 * Save the state of the KVM timer when VM clock is stopped or state is synced
427 static int kvm_mips_save_count(CPUState
*cs
)
429 MIPSCPU
*cpu
= MIPS_CPU(cs
);
430 CPUMIPSState
*env
= &cpu
->env
;
434 /* freeze KVM timer */
435 err
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
437 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err
);
439 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
440 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
441 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
443 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
449 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
451 DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__
, err
);
456 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
458 DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__
, err
);
466 * Restore the state of the KVM timer when VM clock is restarted or state is
469 static int kvm_mips_restore_count(CPUState
*cs
)
471 MIPSCPU
*cpu
= MIPS_CPU(cs
);
472 CPUMIPSState
*env
= &cpu
->env
;
474 int err_dc
, err
, ret
= 0;
476 /* check the timer is frozen */
477 err_dc
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
479 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err_dc
);
481 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
482 /* freeze timer (sets COUNT_RESUME for us) */
483 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
484 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
486 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
492 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
494 DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__
, err
);
499 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
501 DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__
, err
);
505 /* resume KVM timer */
507 count_ctl
&= ~KVM_REG_MIPS_COUNT_CTL_DC
;
508 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
510 DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__
, err
);
519 * Handle the VM clock being started or stopped
521 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
)
523 CPUState
*cs
= opaque
;
525 uint64_t count_resume
;
528 * If state is already dirty (synced to QEMU) then the KVM timer state is
529 * already saved and can be restored when it is synced back to KVM.
532 if (!cs
->vcpu_dirty
) {
533 ret
= kvm_mips_save_count(cs
);
535 warn_report("Failed saving count");
539 /* Set clock restore time to now */
540 count_resume
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
541 ret
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_COUNT_RESUME
,
544 warn_report("Failed setting COUNT_RESUME");
548 if (!cs
->vcpu_dirty
) {
549 ret
= kvm_mips_restore_count(cs
);
551 warn_report("Failed restoring count");
557 static int kvm_mips_put_fpu_registers(CPUState
*cs
, int level
)
559 MIPSCPU
*cpu
= MIPS_CPU(cs
);
560 CPUMIPSState
*env
= &cpu
->env
;
564 /* Only put FPU state if we're emulating a CPU with an FPU */
565 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
566 /* FPU Control Registers */
567 if (level
== KVM_PUT_FULL_STATE
) {
568 err
= kvm_mips_put_one_ureg(cs
, KVM_REG_MIPS_FCR_IR
,
569 &env
->active_fpu
.fcr0
);
571 DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__
, err
);
575 err
= kvm_mips_put_one_ureg(cs
, KVM_REG_MIPS_FCR_CSR
,
576 &env
->active_fpu
.fcr31
);
578 DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__
, err
);
583 * FPU register state is a subset of MSA vector state, so don't put FPU
584 * registers if we're emulating a CPU with MSA.
586 if (!(env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
587 /* Floating point registers */
588 for (i
= 0; i
< 32; ++i
) {
589 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
590 err
= kvm_mips_put_one_ureg64(cs
, KVM_REG_MIPS_FPR_64(i
),
591 &env
->active_fpu
.fpr
[i
].d
);
593 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FPR_32(i
),
594 &env
->active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]);
597 DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__
, i
, err
);
604 /* Only put MSA state if we're emulating a CPU with MSA */
605 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
606 /* MSA Control Registers */
607 if (level
== KVM_PUT_FULL_STATE
) {
608 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_MSA_IR
,
611 DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__
, err
);
615 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_MSA_CSR
,
616 &env
->active_tc
.msacsr
);
618 DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__
, err
);
622 /* Vector registers (includes FP registers) */
623 for (i
= 0; i
< 32; ++i
) {
624 /* Big endian MSA not supported by QEMU yet anyway */
625 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_VEC_128(i
),
626 env
->active_fpu
.fpr
[i
].wr
.d
);
628 DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__
, i
, err
);
637 static int kvm_mips_get_fpu_registers(CPUState
*cs
)
639 MIPSCPU
*cpu
= MIPS_CPU(cs
);
640 CPUMIPSState
*env
= &cpu
->env
;
644 /* Only get FPU state if we're emulating a CPU with an FPU */
645 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
646 /* FPU Control Registers */
647 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FCR_IR
,
648 &env
->active_fpu
.fcr0
);
650 DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__
, err
);
653 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FCR_CSR
,
654 &env
->active_fpu
.fcr31
);
656 DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__
, err
);
659 restore_fp_status(env
);
663 * FPU register state is a subset of MSA vector state, so don't save FPU
664 * registers if we're emulating a CPU with MSA.
666 if (!(env
->CP0_Config3
& (1 << CP0C3_MSAP
))) {
667 /* Floating point registers */
668 for (i
= 0; i
< 32; ++i
) {
669 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
670 err
= kvm_mips_get_one_ureg64(cs
, KVM_REG_MIPS_FPR_64(i
),
671 &env
->active_fpu
.fpr
[i
].d
);
673 err
= kvm_mips_get_one_ureg(cs
, KVM_REG_MIPS_FPR_32(i
),
674 &env
->active_fpu
.fpr
[i
].w
[FP_ENDIAN_IDX
]);
677 DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__
, i
, err
);
684 /* Only get MSA state if we're emulating a CPU with MSA */
685 if (env
->CP0_Config3
& (1 << CP0C3_MSAP
)) {
686 /* MSA Control Registers */
687 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_MSA_IR
,
690 DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__
, err
);
693 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_MSA_CSR
,
694 &env
->active_tc
.msacsr
);
696 DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__
, err
);
699 restore_msa_fp_status(env
);
702 /* Vector registers (includes FP registers) */
703 for (i
= 0; i
< 32; ++i
) {
704 /* Big endian MSA not supported by QEMU yet anyway */
705 err
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_VEC_128(i
),
706 env
->active_fpu
.fpr
[i
].wr
.d
);
708 DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__
, i
, err
);
718 static int kvm_mips_put_cp0_registers(CPUState
*cs
, int level
)
720 MIPSCPU
*cpu
= MIPS_CPU(cs
);
721 CPUMIPSState
*env
= &cpu
->env
;
726 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
728 DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__
, err
);
731 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
734 DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__
, err
);
737 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
738 &env
->active_tc
.CP0_UserLocal
);
740 DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__
, err
);
743 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
746 DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__
, err
);
749 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
751 DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__
, err
);
754 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
756 DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__
, err
);
759 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
762 DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__
, err
);
766 /* If VM clock stopped then state will be restored when it is restarted */
767 if (runstate_is_running()) {
768 err
= kvm_mips_restore_count(cs
);
774 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
777 DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__
, err
);
780 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
783 DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__
, err
);
786 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
788 DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__
, err
);
791 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
793 DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__
, err
);
796 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PRID
, &env
->CP0_PRid
);
798 DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__
, err
);
801 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG
,
803 KVM_REG_MIPS_CP0_CONFIG_MASK
);
805 DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__
, err
);
808 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG1
,
810 KVM_REG_MIPS_CP0_CONFIG1_MASK
);
812 DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__
, err
);
815 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG2
,
817 KVM_REG_MIPS_CP0_CONFIG2_MASK
);
819 DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__
, err
);
822 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG3
,
824 KVM_REG_MIPS_CP0_CONFIG3_MASK
);
826 DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__
, err
);
829 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG4
,
831 KVM_REG_MIPS_CP0_CONFIG4_MASK
);
833 DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__
, err
);
836 err
= kvm_mips_change_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG5
,
838 KVM_REG_MIPS_CP0_CONFIG5_MASK
);
840 DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__
, err
);
843 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
846 DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__
, err
);
853 static int kvm_mips_get_cp0_registers(CPUState
*cs
)
855 MIPSCPU
*cpu
= MIPS_CPU(cs
);
856 CPUMIPSState
*env
= &cpu
->env
;
859 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
861 DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__
, err
);
864 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
867 DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__
, err
);
870 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
871 &env
->active_tc
.CP0_UserLocal
);
873 DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__
, err
);
876 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
879 DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__
, err
);
882 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
884 DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__
, err
);
887 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
889 DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__
, err
);
892 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
895 DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__
, err
);
898 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
901 DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__
, err
);
904 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
907 DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__
, err
);
910 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
912 DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__
, err
);
916 /* If VM clock stopped then state was already saved when it was stopped */
917 if (runstate_is_running()) {
918 err
= kvm_mips_save_count(cs
);
924 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
926 DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__
, err
);
929 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PRID
, &env
->CP0_PRid
);
931 DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__
, err
);
934 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG
, &env
->CP0_Config0
);
936 DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__
, err
);
939 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG1
, &env
->CP0_Config1
);
941 DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__
, err
);
944 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG2
, &env
->CP0_Config2
);
946 DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__
, err
);
949 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG3
, &env
->CP0_Config3
);
951 DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__
, err
);
954 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG4
, &env
->CP0_Config4
);
956 DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__
, err
);
959 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CONFIG5
, &env
->CP0_Config5
);
961 DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__
, err
);
964 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
967 DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__
, err
);
974 int kvm_arch_put_registers(CPUState
*cs
, int level
)
976 MIPSCPU
*cpu
= MIPS_CPU(cs
);
977 CPUMIPSState
*env
= &cpu
->env
;
978 struct kvm_regs regs
;
982 /* Set the registers based on QEMU's view of things */
983 for (i
= 0; i
< 32; i
++) {
984 regs
.gpr
[i
] = (int64_t)(target_long
)env
->active_tc
.gpr
[i
];
987 regs
.hi
= (int64_t)(target_long
)env
->active_tc
.HI
[0];
988 regs
.lo
= (int64_t)(target_long
)env
->active_tc
.LO
[0];
989 regs
.pc
= (int64_t)(target_long
)env
->active_tc
.PC
;
991 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
997 ret
= kvm_mips_put_cp0_registers(cs
, level
);
1002 ret
= kvm_mips_put_fpu_registers(cs
, level
);
1010 int kvm_arch_get_registers(CPUState
*cs
)
1012 MIPSCPU
*cpu
= MIPS_CPU(cs
);
1013 CPUMIPSState
*env
= &cpu
->env
;
1015 struct kvm_regs regs
;
1018 /* Get the current register set as KVM seems it */
1019 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1025 for (i
= 0; i
< 32; i
++) {
1026 env
->active_tc
.gpr
[i
] = regs
.gpr
[i
];
1029 env
->active_tc
.HI
[0] = regs
.hi
;
1030 env
->active_tc
.LO
[0] = regs
.lo
;
1031 env
->active_tc
.PC
= regs
.pc
;
1033 kvm_mips_get_cp0_registers(cs
);
1034 kvm_mips_get_fpu_registers(cs
);
1039 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
1040 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
1045 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
1046 int vector
, PCIDevice
*dev
)
1051 int kvm_arch_release_virq_post(int virq
)
1056 int kvm_arch_msi_data_to_gsi(uint32_t data
)